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simple whitespace fixes

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commit a8c9e9e4b1c2c3fc836eddeeb7b63f4d4d6dc64d 1 parent 9850ed3
@stevej authored
Showing with 273 additions and 275 deletions.
  1. +27 −28 LPC214x.h
  2. +169 −170 Startup.S
  3. +1 −1  main_memory_block.ld
  4. +76 −76 syscalls.c
View
55 LPC214x.h
@@ -1,6 +1,6 @@
/******************************************************************************
* LPC214X.h: Header file for Philips LPC214x Family Microprocessors
- * The header file is the super set of all hardware definition of the
+ * The header file is the super set of all hardware definition of the
* peripherals for the LPC214x family microprocessor.
*
* Copyright(C) 2006, Philips Semiconductor
@@ -11,14 +11,14 @@
* 2005.10.13 ver 1.01 Removed CSPR and DC_REVISION register.
* CSPR can not be accessed at the user level,
* DC_REVISION is no long available.
- * All registers use "volatile unsigned long".
+ * All registers use "volatile unsigned long".
******************************************************************************/
#ifndef __LPC214x_H
#define __LPC214x_H
/* Vectored Interrupt Controller (VIC) */
-#define VIC_BASE_ADDR 0xFFFFF000
+#define VIC_BASE_ADDR 0xFFFFF000
#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004))
@@ -65,13 +65,13 @@
#define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C))
/* Pin Connect Block */
-#define PINSEL_BASE_ADDR 0xE002C000
+#define PINSEL_BASE_ADDR 0xE002C000
#define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00))
#define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04))
#define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14))
/* General Purpose Input/Output (GPIO) */
-#define GPIO_BASE_ADDR 0xE0028000
+#define GPIO_BASE_ADDR 0xE0028000
#define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
#define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
#define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
@@ -82,23 +82,23 @@
#define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
/* Fast I/O setup */
-#define FIO_BASE_ADDR 0x3FFFC000
-#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00))
+#define FIO_BASE_ADDR 0x3FFFC000
+#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00))
#define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))
#define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))
#define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))
#define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))
-#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20))
+#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20))
#define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30))
#define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34))
#define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
#define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C))
/* System Control Block(SCB) modules include Memory Accelerator Module,
-Phase Locked Loop, VPB divider, Power Control, External Interrupt,
+Phase Locked Loop, VPB divider, Power Control, External Interrupt,
Reset, and Code Security/Debugging */
-#define SCB_BASE_ADDR 0xE01FC000
+#define SCB_BASE_ADDR 0xE01FC000
/* Memory Accelerator Module (MAM) */
#define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))
@@ -134,10 +134,10 @@ Reset, and Code Security/Debugging */
#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))
/* System Controls and Status */
-#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
+#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
/* Timer 0 */
-#define TMR0_BASE_ADDR 0xE0004000
+#define TMR0_BASE_ADDR 0xE0004000
#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
@@ -157,7 +157,7 @@ Reset, and Code Security/Debugging */
#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
/* Timer 1 */
-#define TMR1_BASE_ADDR 0xE0008000
+#define TMR1_BASE_ADDR 0xE0008000
#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
@@ -177,7 +177,7 @@ Reset, and Code Security/Debugging */
#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))
/* Pulse Width Modulator (PWM) */
-#define PWM_BASE_ADDR 0xE0014000
+#define PWM_BASE_ADDR 0xE0014000
#define PWMIR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x00))
#define PWMTCR (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x04))
#define PWMTC (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x08))
@@ -196,7 +196,7 @@ Reset, and Code Security/Debugging */
#define PWMLER (*(volatile unsigned long *)(PWM_BASE_ADDR + 0x50))
/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
-#define UART0_BASE_ADDR 0xE000C000
+#define UART0_BASE_ADDR 0xE000C000
#define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
#define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
#define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
@@ -214,7 +214,7 @@ Reset, and Code Security/Debugging */
#define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))
/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
-#define UART1_BASE_ADDR 0xE0010000
+#define UART1_BASE_ADDR 0xE0010000
#define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
#define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
#define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
@@ -232,7 +232,7 @@ Reset, and Code Security/Debugging */
#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))
/* I2C Interface 0 */
-#define I2C0_BASE_ADDR 0xE001C000
+#define I2C0_BASE_ADDR 0xE001C000
#define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
#define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
#define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
@@ -242,7 +242,7 @@ Reset, and Code Security/Debugging */
#define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))
/* I2C Interface 1 */
-#define I2C1_BASE_ADDR 0xE005C000
+#define I2C1_BASE_ADDR 0xE005C000
#define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
#define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
#define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
@@ -252,7 +252,7 @@ Reset, and Code Security/Debugging */
#define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))
/* SPI0 (Serial Peripheral Interface 0) */
-#define SPI0_BASE_ADDR 0xE0020000
+#define SPI0_BASE_ADDR 0xE0020000
#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))
#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))
#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))
@@ -260,7 +260,7 @@ Reset, and Code Security/Debugging */
#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))
/* SSP Controller */
-#define SSP_BASE_ADDR 0xE0068000
+#define SSP_BASE_ADDR 0xE0068000
#define SSPCR0 (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x00))
#define SSPCR1 (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x04))
#define SSPDR (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x08))
@@ -272,7 +272,7 @@ Reset, and Code Security/Debugging */
#define SSPICR (*(volatile unsigned long * )(SSP_BASE_ADDR + 0x20))
/* Real Time Clock */
-#define RTC_BASE_ADDR 0xE0024000
+#define RTC_BASE_ADDR 0xE0024000
#define ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
#define CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))
#define CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
@@ -301,7 +301,7 @@ Reset, and Code Security/Debugging */
#define PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84))
/* A/D Converter 0 (AD0) */
-#define AD0_BASE_ADDR 0xE0034000
+#define AD0_BASE_ADDR 0xE0034000
#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))
@@ -317,7 +317,7 @@ Reset, and Code Security/Debugging */
#define ADGSR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x08))
/* A/D Converter 1 (AD1) */
-#define AD1_BASE_ADDR 0xE0060000
+#define AD1_BASE_ADDR 0xE0060000
#define AD1CR (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x00))
#define AD1GDR (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x04))
#define AD1STAT (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x30))
@@ -332,18 +332,18 @@ Reset, and Code Security/Debugging */
#define AD1DR7 (*(volatile unsigned long *)(AD1_BASE_ADDR + 0x2C))
/* D/A Converter */
-#define DAC_BASE_ADDR 0xE006C000
+#define DAC_BASE_ADDR 0xE006C000
#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))
/* Watchdog */
-#define WDG_BASE_ADDR 0xE0000000
+#define WDG_BASE_ADDR 0xE0000000
#define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00))
#define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04))
#define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08))
#define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C))
/* USB Controller */
-#define USB_BASE_ADDR 0xE0090000 /* USB Base Address */
+#define USB_BASE_ADDR 0xE0090000 /* USB Base Address */
/* Device Interrupt Registers */
#define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00))
#define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04))
@@ -392,8 +392,7 @@ Reset, and Code Security/Debugging */
#define NDD_REQ_INT_SET (*((volatile unsigned long *)USB_BASE_ADDR + 0xB4))
#define SYS_ERR_INT_STAT (*((volatile unsigned long *)USB_BASE_ADDR + 0xB8))
#define SYS_ERR_INT_CLR (*((volatile unsigned long *)USB_BASE_ADDR + 0xBC))
-#define SYS_ERR_INT_SET (*((volatile unsigned long *)USB_BASE_ADDR + 0xC0))
+#define SYS_ERR_INT_SET (*((volatile unsigned long *)USB_BASE_ADDR + 0xC0))
#define MODULE_ID (*((volatile unsigned long *)USB_BASE_ADDR + 0xFC))
#endif // __LPC214x_H
-
View
339 Startup.S
@@ -7,27 +7,27 @@
/* */
/***********************************************************************/
-/*
+/*
This file has been heavily modified for the GNU-Toolchain by:
Martin Thomas, Kaiserslautern, Germany
<mthomas@rhrk.uni-kl.de>
http://www.siwawi.arubi.uni-kl.de/avr_projects
-
- If it does not work for you: don't blame Keil or Philips.
+
+ If it does not work for you: don't blame Keil or Philips.
*/
-/*
-//*** <<< Use Configuration Wizard in Context Menu >>> ***
+/*
+//*** <<< Use Configuration Wizard in Context Menu >>> ***
*/
/*
- * The STARTUP.S code is executed after CPU Reset. This file may be
- * translated with the following SET symbols. In uVision these SET
+ * The STARTUP.S code is executed after CPU Reset. This file may be
+ * translated with the following SET symbols. In uVision these SET
* symbols are entered under Options - ASM - Set.
*
- * REMAP: when set the startup code initializes the register MEMMAP
- * which overwrites the settings of the CPU configuration pins. The
+ * REMAP: when set the startup code initializes the register MEMMAP
+ * which overwrites the settings of the CPU configuration pins. The
* startup and interrupt vectors are remapped from:
* 0x00000000 default setting (not remapped)
* 0x80000000 when EXTMEM_MODE is used
@@ -84,16 +84,16 @@
// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
- .set Mode_USR, 0x10
- .set Mode_FIQ, 0x11
- .set Mode_IRQ, 0x12
- .set Mode_SVC, 0x13
- .set Mode_ABT, 0x17
- .set Mode_UND, 0x1B
- .set Mode_SYS, 0x1F
+ .set Mode_USR, 0x10
+ .set Mode_FIQ, 0x11
+ .set Mode_IRQ, 0x12
+ .set Mode_SVC, 0x13
+ .set Mode_ABT, 0x17
+ .set Mode_UND, 0x1B
+ .set Mode_SYS, 0x1F
- .set I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
- .set F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
+ .set I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
+ .set F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
/*
@@ -106,37 +106,37 @@
// <o5> User/System Mode <0x0-0xFFFFFFFF:4>
// </h>
*/
- .set UND_Stack_Size, 0x00000080
- .set SVC_Stack_Size, 0x00000080
- .set ABT_Stack_Size, 0x00000080
- .set FIQ_Stack_Size, 0x00000080
- .set IRQ_Stack_Size, 0x00000200
- .set USR_Stack_Size, 0x00000800
+ .set UND_Stack_Size, 0x00000080
+ .set SVC_Stack_Size, 0x00000080
+ .set ABT_Stack_Size, 0x00000080
+ .set FIQ_Stack_Size, 0x00000080
+ .set IRQ_Stack_Size, 0x00000200
+ .set USR_Stack_Size, 0x00000800
#if 0
-AREA STACK, DATA, READWRITE, ALIGN=2
- DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode
- DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode
- DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode
- DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode
- DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode
- DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode
+AREA STACK, DATA, READWRITE, ALIGN=2
+ DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode
+ DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode
+ DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode
+ DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode
+ DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode
+ DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode
#endif
.arm
.section .stack, "w"
.align 4
- .space (USR_Stack_Size+3)&~3 // Stack for User/System Mode
- .space (SVC_Stack_Size+3)&~3 // Stack for Supervisor Mode
- .space (IRQ_Stack_Size+3)&~3 // Stack for Interrupt Mode
- .space (FIQ_Stack_Size+3)&~3 // Stack for Fast Interrupt Mode
- .space (ABT_Stack_Size+3)&~3 // Stack for Abort Mode
- .space (UND_Stack_Size+3)&~3 // Stack for Undefined Mode
+ .space (USR_Stack_Size+3)&~3 // Stack for User/System Mode
+ .space (SVC_Stack_Size+3)&~3 // Stack for Supervisor Mode
+ .space (IRQ_Stack_Size+3)&~3 // Stack for Interrupt Mode
+ .space (FIQ_Stack_Size+3)&~3 // Stack for Fast Interrupt Mode
+ .space (ABT_Stack_Size+3)&~3 // Stack for Abort Mode
+ .space (UND_Stack_Size+3)&~3 // Stack for Undefined Mode
Top_Stack:
// VPBDIV definitions
- .set VPBDIV, 0xE01FC100 /* VPBDIV Address */
+ .set VPBDIV, 0xE01FC100 /* VPBDIV Address */
/*
// <e> VPBDIV Setup
@@ -151,21 +151,21 @@ Top_Stack:
// <2=> XCLK Pin = CPU Clock / 2
// </e>
*/
- .set VPBDIV_SETUP, 1
- .set VPBDIV_Val, 0x00000000
+ .set VPBDIV_SETUP, 1
+ .set VPBDIV_Val, 0x00000000
// Phase Locked Loop (PLL) definitions
- .set PLL_BASE, 0xE01FC080 /* PLL Base Address */
- .set PLLCON_OFS, 0x00 /* PLL Control Offset*/
- .set PLLCFG_OFS, 0x04 /* PLL Configuration Offset */
- .set PLLSTAT_OFS, 0x08 /* PLL Status Offset */
- .set PLLFEED_OFS, 0x0C /* PLL Feed Offset */
- .set PLLCON_PLLE, (1<<0) /* PLL Enable */
- .set PLLCON_PLLC, (1<<1) /* PLL Connect */
- .set PLLCFG_MSEL, (0x1F<<0) /* PLL Multiplier */
- .set PLLCFG_PSEL, (0x03<<5) /* PLL Divider */
- .set PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */
+ .set PLL_BASE, 0xE01FC080 /* PLL Base Address */
+ .set PLLCON_OFS, 0x00 /* PLL Control Offset*/
+ .set PLLCFG_OFS, 0x04 /* PLL Configuration Offset */
+ .set PLLSTAT_OFS, 0x08 /* PLL Status Offset */
+ .set PLLFEED_OFS, 0x0C /* PLL Feed Offset */
+ .set PLLCON_PLLE, (1<<0) /* PLL Enable */
+ .set PLLCON_PLLC, (1<<1) /* PLL Connect */
+ .set PLLCFG_MSEL, (0x1F<<0) /* PLL Multiplier */
+ .set PLLCFG_PSEL, (0x03<<5) /* PLL Divider */
+ .set PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */
/*
// <e> PLL Setup
@@ -184,13 +184,13 @@ Top_Stack:
// </e>
*/
// .set PLL_SETUP, 1
- .set PLLCFG_Val, 0x00000024
+ .set PLLCFG_Val, 0x00000024
// Memory Accelerator Module (MAM) definitions
- .set MAM_BASE, 0xE01FC000 /* MAM Base Address */
- .set MAMCR_OFS, 0x00 /* MAM Control Offset*/
- .set MAMTIM_OFS, 0x04 /* MAM Timing Offset */
+ .set MAM_BASE, 0xE01FC000 /* MAM Base Address */
+ .set MAMCR_OFS, 0x00 /* MAM Control Offset*/
+ .set MAMTIM_OFS, 0x04 /* MAM Timing Offset */
/*
// <e> MAM Setup
@@ -207,18 +207,18 @@ Top_Stack:
// </e>
*/
// .set MAM_SETUP, 1
- .set MAMCR_Val, 0x00000002
- .set MAMTIM_Val, 0x00000004
+ .set MAMCR_Val, 0x00000002
+ .set MAMTIM_Val, 0x00000004
// Starupt Code must be linked first at Address at which it expects to run.
.if (EXTMEM_MODE)
- .set CODE_BASE, 0x80000000
+ .set CODE_BASE, 0x80000000
.elseif (RAM_MODE)
- .set CODE_BASE, 0x40000000
+ .set CODE_BASE, 0x40000000
.else
- .set CODE_BASE, 0x00000000
+ .set CODE_BASE, 0x00000000
.endif
#if 0
@@ -229,7 +229,7 @@ AREA STARTUPCODE, CODE, AT CODE_BASE // READONLY, ALIGN=4
__startup PROC CODE32
-// Pre-defined interrupt handlers that may be directly
+// Pre-defined interrupt handlers that may be directly
// overwritten by C interrupt functions
EXTERN CODE32 (Undef_Handler?A)
EXTERN CODE32 (SWI_Handler?A)
@@ -250,7 +250,7 @@ EXTERN CODE32 (FIQ_Handler?A)
.section .vectorg, "ax"
.endif
-// Pre-defined interrupt handlers that may be directly
+// Pre-defined interrupt handlers that may be directly
// overwritten by C interrupt functions
.extern Undef_Handler
.extern SWI_Handler
@@ -264,16 +264,16 @@ EXTERN CODE32 (FIQ_Handler?A)
// Mapped to Address 0.
// Absolute addressing mode must be used.
-__Vectors: LDR PC,Reset_Addr
- LDR PC,Undef_Addr
- LDR PC,SWI_Addr
- LDR PC,PAbt_Addr
- LDR PC,DAbt_Addr
- NOP /* Reserved Vector */
+__Vectors: LDR PC,Reset_Addr
+ LDR PC,Undef_Addr
+ LDR PC,SWI_Addr
+ LDR PC,PAbt_Addr
+ LDR PC,DAbt_Addr
+ NOP /* Reserved Vector */
// LDR PC,IRQ_Addr
// LDR PC,[PC, #-0x0FF0] /* Vector from VicVectAddr */
- LDR PC,IRQ_Wrapper_Addr
- LDR PC,FIQ_Addr
+ LDR PC,IRQ_Wrapper_Addr
+ LDR PC,FIQ_Addr
Reset_Addr: .word Reset_Handler
Undef_Addr: .word Undef_Handler
@@ -282,7 +282,7 @@ Undef_Addr: .word Undef_Handler
SWI_Addr: .word 0 /* in swi_handler.S */
PAbt_Addr: .word PAbt_Handler
DAbt_Addr: .word DAbt_Handler
- .word 0 /* Reserved Address */
+ .word 0 /* Reserved Address */
// IRQ_Addr: .word __IRQ_Handler
IRQ_Wrapper_Addr: .word __IRQ_Wrapper
FIQ_Addr: .word FIQ_Handler
@@ -302,7 +302,7 @@ FIQ_Handler: B FIQ_Handler
.section .init, "ax"
.if (VECTREMAPPED)
-/* mthomas: Dummy used during startup - mind the nops since the
+/* mthomas: Dummy used during startup - mind the nops since the
flash-utility will overwrite the "reserved vector"-address
with the checksum */
B Reset_Handler
@@ -321,82 +321,82 @@ FIQ_Handler: B FIQ_Handler
.func __startup
__startup:
-Reset_Handler:
+Reset_Handler:
// Memory Mapping
- .set MEMMAP, 0xE01FC040 /* Memory Mapping Control */
+ .set MEMMAP, 0xE01FC040 /* Memory Mapping Control */
.if (REMAP)
- LDR R0, =MEMMAP
-.if (EXTMEM_MODE)
- MOV R1, #3
+ LDR R0, =MEMMAP
+.if (EXTMEM_MODE)
+ MOV R1, #3
.elseif (RAM_MODE) || (VECTREMAPPED)
.print "MEMMAP to 2 on init"
- MOV R1, #2
+ MOV R1, #2
.else
- MOV R1, #1
+ MOV R1, #1
.endif
- STR R1, [R0]
+ STR R1, [R0]
.endif
// Setup Stack for each mode
- LDR R0, =Top_Stack
+ LDR R0, =Top_Stack
// Enter Undefined Instruction Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
- MOV SP, R0
- SUB R0, R0, #UND_Stack_Size
+ MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
+ MOV SP, R0
+ SUB R0, R0, #UND_Stack_Size
// Enter Abort Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
- MOV SP, R0
- SUB R0, R0, #ABT_Stack_Size
+ MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
+ MOV SP, R0
+ SUB R0, R0, #ABT_Stack_Size
// Enter FIQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
- MOV SP, R0
- SUB R0, R0, #FIQ_Stack_Size
+ MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
+ MOV SP, R0
+ SUB R0, R0, #FIQ_Stack_Size
// Enter IRQ Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
- MOV SP, R0
- SUB R0, R0, #IRQ_Stack_Size
+ MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
+ MOV SP, R0
+ SUB R0, R0, #IRQ_Stack_Size
// Enter Supervisor Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
- MOV SP, R0
- SUB R0, R0, #SVC_Stack_Size
+ MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
+ MOV SP, R0
+ SUB R0, R0, #SVC_Stack_Size
// Enter User Mode and set its Stack Pointer
- MSR CPSR_c, #Mode_SYS /* Interrupts enabled */
+ MSR CPSR_c, #Mode_SYS /* Interrupts enabled */
// MSR CPSR_c, #Mode_USR|I_Bit|F_Bit /* Interrupts disabled */
- MOV SP, R0
+ MOV SP, R0
.if (RAM_MODE==0)
/* Relocate .data section (Copy from ROM to RAM) */
- LDR R1, =_etext
- LDR R2, =_data
- LDR R3, =_edata
- CMP R2, R3
- BEQ DataIsEmpty
-LoopRel: CMP R2, R3
- LDRLO R0, [R1], #4
- STRLO R0, [R2], #4
- BLO LoopRel
+ LDR R1, =_etext
+ LDR R2, =_data
+ LDR R3, =_edata
+ CMP R2, R3
+ BEQ DataIsEmpty
+LoopRel: CMP R2, R3
+ LDRLO R0, [R1], #4
+ STRLO R0, [R2], #4
+ BLO LoopRel
DataIsEmpty:
.endif
-
+
/* Clear .bss section (Zero init) */
- MOV R0, #0
- LDR R1, =__bss_start__
- LDR R2, =__bss_end__
- CMP R1,R2
- BEQ BSSIsEmpty
-LoopZI: CMP R1, R2
- STRLO R0, [R1], #4
- BLO LoopZI
+ MOV R0, #0
+ LDR R1, =__bss_start__
+ LDR R2, =__bss_end__
+ CMP R1,R2
+ BEQ BSSIsEmpty
+LoopZI: CMP R1, R2
+ STRLO R0, [R1], #4
+ BLO LoopZI
BSSIsEmpty:
@@ -415,12 +415,12 @@ ctor_loop:
ctor_end:
// Enter the C code
- //LDR R0,=INIT
- LDR R0,=main
- TST R0,#1 // Bit-0 set: main is Thumb
- LDREQ LR,=__exit_ARM // ARM Mode
- LDRNE LR,=__exit_THUMB // Thumb Mode
- BX R0
+ //LDR R0,=INIT
+ LDR R0,=main
+ TST R0,#1 // Bit-0 set: main is Thumb
+ LDREQ LR,=__exit_ARM // ARM Mode
+ LDRNE LR,=__exit_THUMB // Thumb Mode
+ BX R0
.size __startup, . - __startup
.endfunc
@@ -429,7 +429,7 @@ ctor_end:
.global __exit_ARM
.func __exit_ARM
__exit_ARM:
- B __exit_ARM
+ B __exit_ARM
.size __exit_ARM, . - __exit_ARM
.endfunc
@@ -437,7 +437,7 @@ __exit_ARM:
.global __exit_THUMB
.func __exit_THUMB
__exit_THUMB:
- B __exit_THUMB
+ B __exit_THUMB
.size __exit_THUMB, . - __exit_THUMB
.endfunc
@@ -460,64 +460,64 @@ __exit_THUMB:
.set VIC_base_addr, 0xFFFFF000
.set VIC_vect_offs, 0x30
- .arm
- .global __IRQ_Wrapper
- .func __IRQ_Wrapper
+ .arm
+ .global __IRQ_Wrapper
+ .func __IRQ_Wrapper
__IRQ_Wrapper:
/*- Manage Exception Entry */
/*- Adjust and save LR_irq in IRQ stack */
- sub lr, lr, #4
- stmfd sp!, {lr}
+ sub lr, lr, #4
+ stmfd sp!, {lr}
/*- Save SPSR need to be saved for nested interrupt */
- mrs r14, SPSR
- stmfd sp!, {r14}
+ mrs r14, SPSR
+ stmfd sp!, {r14}
/*- Save and r0 in IRQ stack */
- stmfd sp!, {r0}
+ stmfd sp!, {r0}
/*- Write in the IVR to support Protect Mode */
/*- No effect in Normal Mode */
/*- De-assert the NIRQ and clear the source in Protect Mode */
/* R14 = LR */
- ldr r14, =VIC_base_addr
- ldr r0 , [r14, #VIC_vect_offs]
- /*str r14, [r14, #VIC_vect_offs]*/
+ ldr r14, =VIC_base_addr
+ ldr r0 , [r14, #VIC_vect_offs]
+ /*str r14, [r14, #VIC_vect_offs]*/
/*- Enable Interrupt and Switch in Supervisor Mode */
- msr CPSR_c, #Mode_SVC
+ msr CPSR_c, #Mode_SVC
/*- Save scratch/used registers and LR in User Stack */
- /*stmfd sp!, { r1-r3, r12, r14}*/
- stmfd sp!, { r1-r12, r14 }
+ /*stmfd sp!, { r1-r3, r12, r14}*/
+ stmfd sp!, { r1-r12, r14 }
/*- Branch to the routine pointed by the VIC-Vector-Address */
- mov r14, pc
- bx r0
+ mov r14, pc
+ bx r0
/*- Restore scratch/used registers and LR from User Stack*/
- /* ldmia sp!, { r1-r3, r12, r14} */
- ldmia sp!, { r1-r12, r14 }
+ /* ldmia sp!, { r1-r3, r12, r14} */
+ ldmia sp!, { r1-r12, r14 }
/*- Disable Interrupt and switch back in IRQ mode */
- msr CPSR_c, #I_Bit | Mode_IRQ
+ msr CPSR_c, #I_Bit | Mode_IRQ
#if 0
-/* VICVectAddr=0 is already done in the ISRs of the Philips-Examples
+/* VICVectAddr=0 is already done in the ISRs of the Philips-Examples
so commented out here */
/*- Mark the End of Interrupt on the VIC */
- ldr r14, =VIC_base_addr
- str r14, [r14, #VIC_vect_offs]
+ ldr r14, =VIC_base_addr
+ str r14, [r14, #VIC_vect_offs]
#endif
/*- Restore SPSR_irq and r0 from IRQ stack */
- ldmia sp!, {r0}
+ ldmia sp!, {r0}
/*- Restore SPSR_irq and r0 from IRQ stack */
- ldmia sp!, {r14}
- msr SPSR_cxsf, r14
+ ldmia sp!, {r14}
+ msr SPSR_cxsf, r14
/*- Restore adjusted LR_irq from IRQ stack directly in the PC */
- ldmia sp!, {pc}^
+ ldmia sp!, {pc}^
.size __IRQ_Wrapper, . - __IRQ_Wrapper
.endfunc
@@ -525,29 +525,29 @@ __IRQ_Wrapper:
#if 0
/* mthomas:
- Wrapper to call a C swi-Function declared with
+ Wrapper to call a C swi-Function declared with
void SWI_Handler(int swi_num, int *regs)
- Inspired by Anglia Designs example
+ Inspired by Anglia Designs example
-- not used here - see swi_handler.S
*/
- .arm
- .global __SWI_Wrapper
- .func __SWI_Wrapper
+ .arm
+ .global __SWI_Wrapper
+ .func __SWI_Wrapper
__SWI_Wrapper: /* r0 holds swi number */
- STMFD sp!,{r0-r12,lr} /* Save The workspace plus the current return */
- /* address lr_ mode into the stack */
- MRS r1, spsr /* Save the spsr_mode into r1 */
- STMFD sp!, {r1} /* Save spsr */
- MOV r1, sp /* load regs */
- LDR r0,=SWI_Handler
- MOV lr, pc
- BX r0 /* call the C-funcktion */
- LDMFD sp!, {r1} /* Restore the saved spsr_mode into r1 */
- MSR spsr_cxsf, r1 /* Restore spsr_mode */
- LDMFD sp!, {r0-r12,pc} /* Return to the instruction following */
- /* the exception interrupt */
- .size __SWI_Wrapper, . - __SWI_Wrapper
- .endfunc
+ STMFD sp!,{r0-r12,lr} /* Save The workspace plus the current return */
+ /* address lr_ mode into the stack */
+ MRS r1, spsr /* Save the spsr_mode into r1 */
+ STMFD sp!, {r1} /* Save spsr */
+ MOV r1, sp /* load regs */
+ LDR r0,=SWI_Handler
+ MOV lr, pc
+ BX r0 /* call the C-funcktion */
+ LDMFD sp!, {r1} /* Restore the saved spsr_mode into r1 */
+ MSR spsr_cxsf, r1 /* Restore spsr_mode */
+ LDMFD sp!, {r0-r12,pc} /* Return to the instruction following */
+ /* the exception interrupt */
+ .size __SWI_Wrapper, . - __SWI_Wrapper
+ .endfunc
#endif
#if 0
@@ -557,7 +557,7 @@ __SWI_Wrapper: /* r0 holds swi number */
.func __IRQ_Wrapper
__IRQ_Wrapper:
SUB lr, lr, #4 /* Update the link register */
- STMFD sp!,{r0-r12,lr} /* Save The workspace plus the current return */
+ STMFD sp!,{r0-r12,lr} /* Save The workspace plus the current return */
/* address lr_ mode into the stack */
MRS r1, spsr /* Save the spsr_mode into r1 */
STMFD sp!, {r1} /* Save spsr */
@@ -578,4 +578,3 @@ ReturnAddress:
#endif
.end
-
View
2  main_memory_block.ld
@@ -18,7 +18,7 @@ MEMORY
{
/*ROM set to 0x20000 where the USB bootloader ends and main code begins*/
/*Reduction to 0x10000 on 11-6-07 to incorporate new user settings and serial number*/
- ROM (rx) : ORIGIN = 0x00010000, LENGTH = 380k
+ ROM (rx) : ORIGIN = 0x00010000, LENGTH = 380k
RAM (rw) : ORIGIN = 0x40000000, LENGTH = 32k
}
View
152 syscalls.c
@@ -15,129 +15,129 @@
//#include "uart.h"
_ssize_t _read_r(
- struct _reent *r,
- int file,
- void *ptr,
+ struct _reent *r,
+ int file,
+ void *ptr,
size_t len)
{
-/*
- char c;
- int i;
- unsigned char *p;
-
- p = (unsigned char*)ptr;
-
- for (i = 0; i < len; i++) {
- // c = uart0Getch();
- c = uart0GetchW();
- if (c == 0x0D) {
- *p='\0';
- break;
- }
- *p++ = c;
- uart0Putch(c);
- }
+/*
+ char c;
+ int i;
+ unsigned char *p;
+
+ p = (unsigned char*)ptr;
+
+ for (i = 0; i < len; i++) {
+ // c = uart0Getch();
+ c = uart0GetchW();
+ if (c == 0x0D) {
+ *p='\0';
+ break;
+ }
+ *p++ = c;
+ uart0Putch(c);
+ }
*/
-// return len - i;
- return 0;
+// return len - i;
+ return 0;
}
_ssize_t _write_r (
- struct _reent *r,
- int file,
- const void *ptr,
+ struct _reent *r,
+ int file,
+ const void *ptr,
size_t len)
{
/*
- int i;
- const unsigned char *p;
-
- p = (const unsigned char*) ptr;
-
- for (i = 0; i < len; i++) {
- if (*p == '\n' ) uart0Putch('\r');
- uart0Putch(*p++);
- }
+ int i;
+ const unsigned char *p;
+
+ p = (const unsigned char*) ptr;
+
+ for (i = 0; i < len; i++) {
+ if (*p == '\n' ) uart0Putch('\r');
+ uart0Putch(*p++);
+ }
*/
- return len;
+ return len;
}
int _close_r(
- struct _reent *r,
+ struct _reent *r,
int file)
{
- return 0;
+ return 0;
}
_off_t _lseek_r(
- struct _reent *r,
- int file,
- _off_t ptr,
+ struct _reent *r,
+ int file,
+ _off_t ptr,
int dir)
{
- return (_off_t)0; /* Always indicate we are at file beginning. */
+ return (_off_t)0; /* Always indicate we are at file beginning. */
}
int _fstat_r(
- struct _reent *r,
- int file,
+ struct _reent *r,
+ int file,
struct stat *st)
{
- /* Always set as character device. */
- st->st_mode = S_IFCHR;
- /* assigned to strong type with implicit */
- /* signed/unsigned conversion. Required by */
- /* newlib. */
+ /* Always set as character device. */
+ st->st_mode = S_IFCHR;
+ /* assigned to strong type with implicit */
+ /* signed/unsigned conversion. Required by */
+ /* newlib. */
- return 0;
+ return 0;
}
int isatty(int file); /* avoid warning */
int isatty(int file)
{
- return 1;
+ return 1;
}
#if 0
static void _exit (int n) {
label: goto label; /* endless loop */
}
-#endif
+#endif
/* "malloc clue function" */
- /**** Locally used variables. ****/
-extern char end[]; /* end is set in the linker command */
- /* file and is the end of statically */
- /* allocated data (thus start of heap). */
+ /**** Locally used variables. ****/
+extern char end[]; /* end is set in the linker command */
+ /* file and is the end of statically */
+ /* allocated data (thus start of heap). */
-static char *heap_ptr; /* Points to current end of the heap. */
+static char *heap_ptr; /* Points to current end of the heap. */
/************************** _sbrk_r *************************************/
-/* Support function. Adjusts end of heap to provide more memory to */
-/* memory allocator. Simple and dumb with no sanity checks. */
-/* struct _reent *r -- re-entrancy structure, used by newlib to */
-/* support multiple threads of operation. */
-/* ptrdiff_t nbytes -- number of bytes to add. */
-/* Returns pointer to start of new heap area. */
-/* Note: This implementation is not thread safe (despite taking a */
-/* _reent structure as a parameter). */
-/* Since _s_r is not used in the current implementation, the following */
-/* messages must be suppressed. */
+/* Support function. Adjusts end of heap to provide more memory to */
+/* memory allocator. Simple and dumb with no sanity checks. */
+/* struct _reent *r -- re-entrancy structure, used by newlib to */
+/* support multiple threads of operation. */
+/* ptrdiff_t nbytes -- number of bytes to add. */
+/* Returns pointer to start of new heap area. */
+/* Note: This implementation is not thread safe (despite taking a */
+/* _reent structure as a parameter). */
+/* Since _s_r is not used in the current implementation, the following */
+/* messages must be suppressed. */
void * _sbrk_r(
- struct _reent *_s_r,
+ struct _reent *_s_r,
ptrdiff_t nbytes)
{
- char *base; /* errno should be set to ENOMEM on error */
-
- if (!heap_ptr) { /* Initialize if first time through. */
- heap_ptr = end;
- }
- base = heap_ptr; /* Point to end of heap. */
- heap_ptr += nbytes; /* Increase heap. */
-
- return base; /* Return pointer to start of new heap area. */
+ char *base; /* errno should be set to ENOMEM on error */
+
+ if (!heap_ptr) { /* Initialize if first time through. */
+ heap_ptr = end;
+ }
+ base = heap_ptr; /* Point to end of heap. */
+ heap_ptr += nbytes; /* Increase heap. */
+
+ return base; /* Return pointer to start of new heap area. */
}
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