diff --git a/arch/arm/mach-omap2/smartreflex-class1p5.c b/arch/arm/mach-omap2/smartreflex-class1p5.c
index b8f63c21923..a15da0fb1a5 100644
--- a/arch/arm/mach-omap2/smartreflex-class1p5.c
+++ b/arch/arm/mach-omap2/smartreflex-class1p5.c
@@ -291,7 +291,14 @@ static void sr_class1p5_calib_work(struct work_struct *work)
 			u_volt_margin = volt_data->volt_margin;
 		}
 
-		u_volt_safe += u_volt_margin;
+		if (u_volt_margin & SR1P5_MARGIN_DISABLE_SR) {
+			/* XXX This should be impossible! */
+			pr_err("%s: SR calibration ran for %s OPP with vnom %d"
+				"for which SR was disabled??!\n", __func__,
+				voltdm->name, volt_data->volt_nominal);
+		} else {
+			u_volt_safe += u_volt_margin;
+		}
 	}
 
 	if (u_volt_safe > volt_data->volt_nominal) {
@@ -420,6 +427,13 @@ static int sr_class1p5_enable(struct voltagedomain *voltdm,
 		return -EINVAL;
 	}
 
+	/* SR is disabled for this OPP, don't calibrate */
+	if (volt_data->volt_margin == SR1P5_MARGIN_DISABLE_SR) {
+		pr_info_once("%s: %s: SR is disabled for this OPP, volt_nominal=%d\n",
+			__func__, voltdm->name, volt_data->volt_nominal);
+		return 0;
+	}
+
 	/* If already calibrated, nothing to do here.. */
 	if (volt_data->volt_calibrated)
 		return 0;
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 1be2beed3b4..8b81fb3bc55 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -161,6 +161,13 @@ struct omap_volt_data {
 	int	abb_type;
 };
 
+/*
+ * XXX HACK
+ * Special volt_margin value to set to disable SmartReflex class 1.5
+ * calibration entirely for a particular voltage.
+ */
+#define SR1P5_MARGIN_DISABLE_SR (1 << 31)
+
 /*
  * Introduced in OMAP4, is a concept of a default channel - in OMAP4, this
  * channel is MPU, all other domains such as IVA/CORE, could optionally