forked from openrisc/orpsoc-cores
/
wb_intercon.conf
74 lines (63 loc) · 840 Bytes
/
wb_intercon.conf
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; or1k instruction bus master
[master or1k_i]
slaves =
sdram_ibus
rom0
; or1k data bus master
[master dbus]
slaves =
sdram_dbus
uart0
gpio0
gpio1
i2c0
i2c1
spi0
spi1
spi2
; SDRAM
; Have several ports with buffering features,
; so we split each port into a seperate slave
[slave sdram_dbus]
offset=0
; 32 MB
size=0x2000000
[slave sdram_ibus]
offset=0
; 32 MB
size=0x2000000
[slave uart0]
datawidth=8
offset=0x90000000
size=32
[slave gpio0]
datawidth=8
offset=0x91000000
size=2
[slave gpio1]
datawidth=8
offset=0x92000000
size=2
[slave i2c0]
datawidth=8
offset=0xa0000000
size=8
[slave i2c1]
datawidth=8
offset=0xa1000000
size=8
[slave spi0]
datawidth=8
offset=0xb0000000
size=8
[slave spi1]
datawidth=8
offset=0xb1000000
size=8
[slave spi2]
datawidth=8
offset=0xb2000000
size=8
[slave rom0]
offset=0xf0000000
size=1024