From 4003ada417fca9c32ed23617b40552a722195450 Mon Sep 17 00:00:00 2001
From: Frederic Pillon <frederic.pillon@st.com>
Date: Thu, 27 Nov 2025 09:37:26 +0100
Subject: [PATCH 1/3] system(wba) update STM32WBAxx HAL Drivers to v1.8.0

Included in STM32CubeWBA FW v1.8.0

Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
---
 .../Inc/Legacy/stm32_hal_legacy.h             |  16 +-
 .../Inc/stm32wbaxx_hal.h                      |   2 +-
 .../Inc/stm32wbaxx_hal_conf_template.h        |   6 -
 .../Inc/stm32wbaxx_hal_gpio_ex.h              |  10 +-
 .../Inc/stm32wbaxx_hal_gtzc.h                 |   2 +-
 .../Inc/stm32wbaxx_hal_hash.h                 |  12 +-
 .../Inc/stm32wbaxx_hal_i2c_ex.h               |  49 ++++
 .../Inc/stm32wbaxx_hal_pwr_ex.h               |   3 +
 .../Inc/stm32wbaxx_hal_rtc_ex.h               |  10 +-
 .../Inc/stm32wbaxx_hal_smbus_ex.h             |  49 ++++
 .../Inc/stm32wbaxx_ll_i2c.h                   |  24 ++
 .../Inc/stm32wbaxx_ll_lptim.h                 |   6 +
 .../Inc/stm32wbaxx_ll_pwr.h                   |   2 +
 .../Inc/stm32wbaxx_ll_usb.h                   |  30 +-
 .../STM32WBAxx_HAL_Driver/Release_Notes.html  | 277 ++++++++++++------
 .../Src/stm32wbaxx_hal_hash.c                 |  60 ++--
 .../Src/stm32wbaxx_hal_hcd.c                  |  21 +-
 .../Src/stm32wbaxx_hal_pcd.c                  |   4 +-
 .../Src/stm32wbaxx_hal_pwr_ex.c               |   6 +-
 .../Src/stm32wbaxx_hal_ramcfg.c               |   2 +-
 .../Src/stm32wbaxx_hal_rtc_ex.c               |   6 +-
 .../Src/stm32wbaxx_hal_uart.c                 |  66 ++---
 .../Src/stm32wbaxx_ll_usb.c                   |  59 ++--
 .../Drivers/STM32YYxx_HAL_Driver_version.md   |   2 +-
 24 files changed, 464 insertions(+), 260 deletions(-)

diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
index da4d4112ab..397845a1d8 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -361,7 +361,10 @@ extern "C" {
 #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
     defined(STM32L4S7xx) || defined(STM32L4S9xx)
 #define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
-#endif
+#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx)
+#define DMA_REQUEST_PSSI                    DMA_REQUEST_DCMI_PSSI
+#define LL_DMAMUX_REQ_PSSI                  LL_DMAMUX_REQ_DCMI_PSSI
+#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
 
 #endif /* STM32L4 */
 
@@ -2149,6 +2152,13 @@ extern "C" {
 #define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
 #define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
 
+#if defined(STM32H7RS) || defined(STM32N6)
+#define FMC_SWAPBMAP_DISABLE                  FMC_SWAPBANK_MODE0
+#define FMC_SWAPBMAP_SDRAM_SRAM               FMC_SWAPBANK_MODE1
+#define HAL_SetFMCMemorySwappingConfig        HAL_FMC_SetBankSwapConfig
+#define HAL_GetFMCMemorySwappingConfig        HAL_FMC_GetBankSwapConfig
+#endif /* STM32H7RS || STM32N6 */
+
 /**
   * @}
   */
@@ -3953,8 +3963,8 @@ extern "C" {
   */
 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
     defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
-    defined (STM32WBA) || defined (STM32H5) ||  defined (STM32C0) || defined (STM32N6) || \
-    defined (STM32H7RS) ||  defined (STM32U0) || defined (STM32U3)
+    defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \
+    defined (STM32U0) || defined (STM32U3)
 #else
 #define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
 #endif
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h
index f7d84b9398..4bce2f7e98 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h
@@ -79,7 +79,7 @@ extern HAL_TickFreqTypeDef      uwTickFreq;
   * @brief STM32WBAxx HAL Driver version number
   */
 #define __STM32WBAxx_HAL_VERSION_MAIN   (0x01UL) /*!< [31:24] main version */
-#define __STM32WBAxx_HAL_VERSION_SUB1   (0x07UL) /*!< [23:16] sub1 version */
+#define __STM32WBAxx_HAL_VERSION_SUB1   (0x08UL) /*!< [23:16] sub1 version */
 #define __STM32WBAxx_HAL_VERSION_SUB2   (0x00UL) /*!< [15:8]  sub2 version */
 #define __STM32WBAxx_HAL_VERSION_RC     (0x00UL) /*!< [7:0]  release candidate */
 #define __STM32WBAxx_HAL_VERSION    ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h
index 33429676bb..3601befa86 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h
@@ -68,7 +68,6 @@ extern "C" {
 #define HAL_UART_MODULE_ENABLED
 #define HAL_USART_MODULE_ENABLED
 #define HAL_WWDG_MODULE_ENABLED
-#define HAL_XSPI_MODULE_ENABLED
 
 /* ########################## Oscillator Values adaptation ####################*/
 /**
@@ -181,7 +180,6 @@ extern "C" {
 #define  USE_HAL_UART_REGISTER_CALLBACKS       0U /* UART register callback disabled      */
 #define  USE_HAL_USART_REGISTER_CALLBACKS      0U /* USART register callback disabled     */
 #define  USE_HAL_WWDG_REGISTER_CALLBACKS       0U /* WWDG register callback disabled      */
-#define  USE_HAL_XSPI_REGISTER_CALLBACKS       0U /* XSPI register callback disabled      */
 
 /* ################## SPI peripheral configuration ########################## */
 
@@ -339,10 +337,6 @@ extern "C" {
 #include "stm32wbaxx_hal_wwdg.h"
 #endif /* HAL_WWDG_MODULE_ENABLED */
 
-#ifdef HAL_XSPI_MODULE_ENABLED
-#include "stm32wbaxx_hal_xspi.h"
-#endif /* HAL_XSPI_MODULE_ENABLED */
-
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 /**
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h
index 1d580d31a2..6efbcc0f66 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h
@@ -367,11 +367,11 @@ extern "C" {
 /**
   * @brief   AF 4 selection
   */
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /*!< I2C1 Alternate Function mapping   */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /*!< I2C2 Alternate Function mapping   */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /*!< I2C3 Alternate Function mapping   */
-#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /*!< I2C4 Alternate Function mapping   */
-#define GPIO_AF4_OTG_HS        ((uint8_t)0x04)  /*!< OTG-HS Alternate Function mapping */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /*!< I2C1 Alternate Function mapping       */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /*!< I2C2 Alternate Function mapping       */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /*!< I2C3 Alternate Function mapping       */
+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /*!< I2C4 Alternate Function mapping       */
+#define GPIO_AF4_USB_OTG_HS    ((uint8_t)0x04)  /*!< USB OTG-HS Alternate Function mapping */
 
 /**
   * @brief   AF 5 selection
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h
index e49e1fe210..f49e61b584 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h
@@ -43,7 +43,7 @@ extern "C" {
   */
 
 /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */
-#if  defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) || defined (STM32WBA5Mxx)
+#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) || defined (STM32WBA5Mxx)
 #define GTZC_MPCBB_NB_VCTR_REG_MAX      4U  /*!< Maximum number of superblocks */
 #elif defined (STM32WBA62xx) || defined (STM32WBA63xx) || defined (STM32WBA64xx) || defined (STM32WBA65xx) || defined (STM32WBA6Mxx)
 #define GTZC_MPCBB_NB_VCTR_REG_MAX      28U /*!< Maximum number of superblocks */
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hash.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hash.h
index 7ee602ab7f..f927537a84 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hash.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hash.h
@@ -291,11 +291,13 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash);  /*!< pointer
   *            @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
   *            @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
   *            @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  * @retval The new state of __FLAG__ (SET or RESET).
   */
-#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__)  (((__FLAG__) > 8U)  ?                    \
-                                                    (((__HANDLE__)->Instance->CR & (__FLAG__)) == (__FLAG__)) :\
-                                                    (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) )
+#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__)  (((__FLAG__) > 8U)  ?                           \
+                                                    ((((__HANDLE__)->Instance->CR & (__FLAG__)) == \
+                                                      (__FLAG__)) ? SET : RESET) :                     \
+                                                    ((((__HANDLE__)->Instance->SR & (__FLAG__)) == \
+                                                      (__FLAG__)) ? SET : RESET) )
 
 /** @brief  Clear the specified HASH flag.
   * @param  __HANDLE__ specifies the HASH handle.
@@ -389,7 +391,7 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
 void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
 void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
 HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf);
-HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, const HASH_ConfigTypeDef *pConf);
 
 /* Callbacks Register/UnRegister functions  ***********************************/
 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h
index 90f2f25058..f72a2e8e09 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h
@@ -105,6 +105,7 @@ typedef struct
 #define I2C_TRIG_GRP2                   (0x20000000U)         /*!< Trigger Group for I2C3 */
 
 #if defined(I2C_TRIG_GRP1)
+#if defined(GPDMA1)
 #define I2C_GRP1_GPDMA_CH0_TCF_TRG      (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U))
 /*!< HW Trigger signal is GPDMA_CH0_TRG     */
 #define I2C_GRP1_GPDMA_CH1_TCF_TRG      (uint32_t)(I2C_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
@@ -113,6 +114,17 @@ typedef struct
 /*!< HW Trigger signal is GPDMA_CH2_TRG     */
 #define I2C_GRP1_GPDMA_CH3_TCF_TRG      (uint32_t)(I2C_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
 /*!< HW Trigger signal is GPDMA_CH3_TRG     */
+#endif /* GPDMA1 */
+#if defined(LPDMA1)
+#define I2C_GRP1_LPDMA_CH0_TCF_TRG      (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U))
+/*!< HW Trigger signal is LPDMA_CH0_TRG     */
+#define I2C_GRP1_LPDMA_CH1_TCF_TRG      (uint32_t)(I2C_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH1_TRG     */
+#define I2C_GRP1_LPDMA_CH2_TCF_TRG      (uint32_t)(I2C_TRIG_GRP1 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH2_TRG     */
+#define I2C_GRP1_LPDMA_CH3_TCF_TRG      (uint32_t)(I2C_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH3_TRG     */
+#endif /* LPDMA1 */
 #define I2C_GRP1_EXTI5_TRG              (uint32_t)(I2C_TRIG_GRP1 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos))
 /*!< HW Trigger signal is EXTI5_TRG         */
 #define I2C_GRP1_EXTI9_TRG              (uint32_t)(I2C_TRIG_GRP1 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos))
@@ -135,6 +147,7 @@ typedef struct
 /*!< HW Trigger signal is RTC_WUT_TRG       */
 #endif /* I2C_TRIG_GRP1 */
 
+#if defined(GPDMA1)
 #define I2C_GRP2_GPDMA_CH0_TCF_TRG      (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U))
 /*!< HW Trigger signal is GPDMA_CH0_TRG     */
 #define I2C_GRP2_GPDMA_CH1_TCF_TRG      (uint32_t)(I2C_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
@@ -143,6 +156,17 @@ typedef struct
 /*!< HW Trigger signal is GPDMA_CH2_TRG     */
 #define I2C_GRP2_GPDMA_CH3_TCF_TRG      (uint32_t)(I2C_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
 /*!< HW Trigger signal is GPDMA_CH3_TRG     */
+#endif /* GPDMA1 */
+#if defined(LPDMA1)
+#define I2C_GRP2_LPDMA_CH0_TCF_TRG      (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U))
+/*!< HW Trigger signal is LPDMA_CH0_TRG     */
+#define I2C_GRP2_LPDMA_CH1_TCF_TRG      (uint32_t)(I2C_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH1_TRG     */
+#define I2C_GRP2_LPDMA_CH2_TCF_TRG      (uint32_t)(I2C_TRIG_GRP2 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH2_TRG     */
+#define I2C_GRP2_LPDMA_CH3_TCF_TRG      (uint32_t)(I2C_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH3_TRG     */
+#endif /* LPDMA1 */
 #define I2C_GRP2_EXTI5_TRG              (uint32_t)(I2C_TRIG_GRP2 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos))
 /*!< HW Trigger signal is EXTI5_TRG         */
 #define I2C_GRP2_EXTI8_TRG              (uint32_t)(I2C_TRIG_GRP2 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos))
@@ -297,6 +321,7 @@ HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c);
 
 #else
 
+#if defined(GPDMA1)
 #define IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__)  (((__SOURCE__) == I2C_GRP1_GPDMA_CH0_TCF_TRG  ) || \
                                               ((__SOURCE__) == I2C_GRP1_GPDMA_CH1_TCF_TRG  ) || \
                                               ((__SOURCE__) == I2C_GRP1_GPDMA_CH2_TCF_TRG  ) || \
@@ -317,6 +342,30 @@ HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c);
                                               ((__SOURCE__) == I2C_GRP2_LPTIM1_CH1_TRG     ) || \
                                               ((__SOURCE__) == I2C_GRP2_RTC_ALRA_TRG       ) || \
                                               ((__SOURCE__) == I2C_GRP2_RTC_WUT_TRG        ))
+#endif /* GPDMA1 */
+
+#if defined(LPDMA1)
+#define IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__)  (((__SOURCE__) == I2C_GRP1_LPDMA_CH0_TCF_TRG  ) || \
+                                              ((__SOURCE__) == I2C_GRP1_LPDMA_CH1_TCF_TRG  ) || \
+                                              ((__SOURCE__) == I2C_GRP1_LPDMA_CH2_TCF_TRG  ) || \
+                                              ((__SOURCE__) == I2C_GRP1_LPDMA_CH3_TCF_TRG  ) || \
+                                              ((__SOURCE__) == I2C_GRP1_EXTI5_TRG          ) || \
+                                              ((__SOURCE__) == I2C_GRP1_EXTI9_TRG          ) || \
+                                              ((__SOURCE__) == I2C_GRP1_LPTIM1_CH1_TRG     ) || \
+                                              ((__SOURCE__) == I2C_GRP1_LPTIM2_CH1_TRG     ) || \
+                                              ((__SOURCE__) == I2C_GRP1_RTC_ALRA_TRG       ) || \
+                                              ((__SOURCE__) == I2C_GRP1_RTC_WUT_TRG        ))
+
+#define IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__)  (((__SOURCE__) == I2C_GRP2_LPDMA_CH0_TCF_TRG  ) || \
+                                              ((__SOURCE__) == I2C_GRP2_LPDMA_CH1_TCF_TRG  ) || \
+                                              ((__SOURCE__) == I2C_GRP2_LPDMA_CH2_TCF_TRG  ) || \
+                                              ((__SOURCE__) == I2C_GRP2_LPDMA_CH3_TCF_TRG  ) || \
+                                              ((__SOURCE__) == I2C_GRP2_EXTI5_TRG          ) || \
+                                              ((__SOURCE__) == I2C_GRP2_EXTI8_TRG          ) || \
+                                              ((__SOURCE__) == I2C_GRP2_LPTIM1_CH1_TRG     ) || \
+                                              ((__SOURCE__) == I2C_GRP2_RTC_ALRA_TRG       ) || \
+                                              ((__SOURCE__) == I2C_GRP2_RTC_WUT_TRG        ))
+#endif /* LPDMA1 */
 #endif /* COMP1 && COMP2 */
 
 #if defined(I2C_TRIG_GRP1)
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h
index 63ffd0d005..fc8d059356 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h
@@ -73,8 +73,11 @@ extern "C" {
 #define PWR_SRAM2_FULL_STOP_RETENTION        PWR_CR2_SRAM2PDS1     /*!< SRAM2 full retention in Stop modes */
 #endif /* !defined(PWR_STOP3_SUPPORT) */
 
+#if defined (PWR_CR2_ICRAMPDS)
 /* Cache RAMs retention defines */
 #define PWR_ICACHE_FULL_STOP_RETENTION       PWR_CR2_ICRAMPDS      /*!< ICACHE SRAM retention in Stop modes */
+#endif /* PWR_CR2_ICRAMPDS */
+
 #if defined(PWR_STOP2_SUPPORT)
 #if defined(USB_OTG_HS)
 /* USB_OTG_HS SRAM power-down in Stop modes */
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h
index 66a8fffc38..087123fae3 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h
@@ -854,12 +854,20 @@ typedef struct
   * @{
   */
 #define TAMP_DEVICESECRETS_ERASE_NONE          0U                   /*! < No Erase          */
+#ifdef TAMP_RPCFGR_RPCFG
 #define TAMP_DEVICESECRETS_ERASE_SRAM2         TAMP_RPCFGR_RPCFG_1  /*!< SRAM2              */
 #define TAMP_DEVICESECRETS_ERASE_RHUK          TAMP_RPCFGR_RPCFG_2  /*!< RHUK               */
 #define TAMP_DEVICESECRETS_ERASE_ICACHE        TAMP_RPCFGR_RPCFG_3  /*!< ICACHE             */
 #define TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH TAMP_RPCFGR_RPCFG_4  /*!< SAES, AES and HASH */
 #define TAMP_DEVICESECRETS_ERASE_PKA_SRAM      TAMP_RPCFGR_RPCFG_5  /*!< Initialization     */
 #define TAMP_DEVICESECRETS_ERASE_ALL           TAMP_RPCFGR_RPCFG    /*!< All                */
+#elif defined(TAMP_ERCFGR_ERCFG)
+#define TAMP_DEVICESECRETS_ERASE_SRAM2           TAMP_ERCFGR_ERCFG_1  /*!< SRAM2                */
+#define TAMP_DEVICESECRETS_ERASE_ICACHE          TAMP_ERCFGR_ERCFG_3  /*!< ICACHE               */
+#define TAMP_DEVICESECRETS_ERASE_AES_HASH_OTFDEC TAMP_ERCFGR_ERCFG_4  /*!< AES, HASH and OTFDEC */
+#define TAMP_DEVICESECRETS_ERASE_PKA_SRAM        TAMP_ERCFGR_ERCFG_5  /*!< PKA SRAM             */
+#define TAMP_DEVICESECRETS_ERASE_ALL             TAMP_ERCFGR_ERCFG    /*!< All                  */
+#endif
 /**
   * @}
   */
@@ -1609,7 +1617,7 @@ uint32_t          HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef *hrtc, uint32_t Bac
 void              HAL_RTCEx_BKUPErase(const RTC_HandleTypeDef *hrtc);
 void              HAL_RTCEx_BKUPBlock(const RTC_HandleTypeDef *hrtc);
 void              HAL_RTCEx_BKUPUnblock(const RTC_HandleTypeDef *hrtc);
-#ifdef TAMP_RPCFGR_RPCFG
+#if defined (TAMP_RPCFGR_RPCFG) || defined(TAMP_ERCFGR_ERCFG)
 void              HAL_RTCEx_ConfigEraseDeviceSecrets(const RTC_HandleTypeDef *hrtc, uint32_t DeviceSecretConf);
 #endif /* TAMP_RPCFGR_RPCFG */
 /**
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h
index 76150a8200..44e3b80331 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h
@@ -97,6 +97,7 @@ typedef struct
 #define SMBUS_TRIG_GRP2                   (0x20000000U)         /*!< Trigger Group for I2C3 */
 
 #if defined(SMBUS_TRIG_GRP1)
+#if defined(GPDMA1)
 #define SMBUS_GRP1_GPDMA_CH0_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000U))
 /*!< HW Trigger signal is GPDMA_CH0_TRG     */
 #define SMBUS_GRP1_GPDMA_CH1_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
@@ -105,6 +106,17 @@ typedef struct
 /*!< HW Trigger signal is GPDMA_CH2_TRG     */
 #define SMBUS_GRP1_GPDMA_CH3_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
 /*!< HW Trigger signal is GPDMA_CH3_TRG     */
+#endif /* GPDMA1 */
+#if defined(LPDMA1)
+#define SMBUS_GRP1_LPDMA_CH0_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000U))
+/*!< HW Trigger signal is LPDMA_CH0_TRG     */
+#define SMBUS_GRP1_LPDMA_CH1_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH1_TRG     */
+#define SMBUS_GRP1_LPDMA_CH2_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP1 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH2_TRG     */
+#define SMBUS_GRP1_LPDMA_CH3_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH3_TRG     */
+#endif /* LPDMA1 */
 #define SMBUS_GRP1_EXTI5_TRG              (uint32_t)(SMBUS_TRIG_GRP1 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos))
 /*!< HW Trigger signal is EXTI5_TRG         */
 #define SMBUS_GRP1_EXTI9_TRG              (uint32_t)(SMBUS_TRIG_GRP1 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos))
@@ -127,6 +139,7 @@ typedef struct
 /*!< HW Trigger signal is RTC_WUT_TRG       */
 #endif /* SMBUS_TRIG_GRP1 */
 
+#if defined(GPDMA1)
 #define SMBUS_GRP2_GPDMA_CH0_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP2 | (0x00000000U))
 /*!< HW Trigger signal is GPDMA_CH0_TRG     */
 #define SMBUS_GRP2_GPDMA_CH1_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
@@ -135,6 +148,17 @@ typedef struct
 /*!< HW Trigger signal is GPDMA_CH2_TRG     */
 #define SMBUS_GRP2_GPDMA_CH3_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
 /*!< HW Trigger signal is GPDMA_CH3_TRG     */
+#endif /* GPDMA1 */
+#if defined(LPDMA1)
+#define SMBUS_GRP2_LPDMA_CH0_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP2 | (0x00000000U))
+/*!< HW Trigger signal is LPDMA_CH0_TRG     */
+#define SMBUS_GRP2_LPDMA_CH1_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH1_TRG     */
+#define SMBUS_GRP2_LPDMA_CH2_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP2 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH2_TRG     */
+#define SMBUS_GRP2_LPDMA_CH3_TCF_TRG      (uint32_t)(SMBUS_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH3_TRG     */
+#endif /* LPDMA1 */
 #define SMBUS_GRP2_EXTI5_TRG              (uint32_t)(SMBUS_TRIG_GRP2 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos))
 /*!< HW Trigger signal is EXTI5_TRG         */
 #define SMBUS_GRP2_EXTI8_TRG              (uint32_t)(SMBUS_TRIG_GRP2 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos))
@@ -275,6 +299,7 @@ HAL_StatusTypeDef HAL_SMBUSEx_ClearConfigAutonomousMode(SMBUS_HandleTypeDef *hsm
 
 #else
 
+#if defined(GPDMA1)
 #define IS_SMBUS_GRP1_TRIG_SOURCE(__SOURCE__)  (((__SOURCE__) == SMBUS_GRP1_GPDMA_CH0_TCF_TRG  ) || \
                                                 ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH1_TCF_TRG  ) || \
                                                 ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH2_TCF_TRG  ) || \
@@ -295,6 +320,30 @@ HAL_StatusTypeDef HAL_SMBUSEx_ClearConfigAutonomousMode(SMBUS_HandleTypeDef *hsm
                                                 ((__SOURCE__) == SMBUS_GRP2_LPTIM1_CH1_TRG     ) || \
                                                 ((__SOURCE__) == SMBUS_GRP2_RTC_ALRA_TRG       ) || \
                                                 ((__SOURCE__) == SMBUS_GRP2_RTC_WUT_TRG        ))
+#endif /* GPDMA1 */
+
+#if defined(LPDMA1)
+#define IS_SMBUS_GRP1_TRIG_SOURCE(__SOURCE__)  (((__SOURCE__) == SMBUS_GRP1_LPDMA_CH0_TCF_TRG  ) || \
+                                                ((__SOURCE__) == SMBUS_GRP1_LPDMA_CH1_TCF_TRG  ) || \
+                                                ((__SOURCE__) == SMBUS_GRP1_LPDMA_CH2_TCF_TRG  ) || \
+                                                ((__SOURCE__) == SMBUS_GRP1_LPDMA_CH3_TCF_TRG  ) || \
+                                                ((__SOURCE__) == SMBUS_GRP1_EXTI5_TRG          ) || \
+                                                ((__SOURCE__) == SMBUS_GRP1_EXTI9_TRG          ) || \
+                                                ((__SOURCE__) == SMBUS_GRP1_LPTIM1_CH1_TRG     ) || \
+                                                ((__SOURCE__) == SMBUS_GRP1_LPTIM2_CH1_TRG     ) || \
+                                                ((__SOURCE__) == SMBUS_GRP1_RTC_ALRA_TRG       ) || \
+                                                ((__SOURCE__) == SMBUS_GRP1_RTC_WUT_TRG        ))
+
+#define IS_SMBUS_GRP2_TRIG_SOURCE(__SOURCE__)  (((__SOURCE__) == SMBUS_GRP2_LPDMA_CH0_TCF_TRG  ) || \
+                                                ((__SOURCE__) == SMBUS_GRP2_LPDMA_CH1_TCF_TRG  ) || \
+                                                ((__SOURCE__) == SMBUS_GRP2_LPDMA_CH2_TCF_TRG  ) || \
+                                                ((__SOURCE__) == SMBUS_GRP2_LPDMA_CH3_TCF_TRG  ) || \
+                                                ((__SOURCE__) == SMBUS_GRP2_EXTI5_TRG          ) || \
+                                                ((__SOURCE__) == SMBUS_GRP2_EXTI8_TRG          ) || \
+                                                ((__SOURCE__) == SMBUS_GRP2_LPTIM1_CH1_TRG     ) || \
+                                                ((__SOURCE__) == SMBUS_GRP2_RTC_ALRA_TRG       ) || \
+                                                ((__SOURCE__) == SMBUS_GRP2_RTC_WUT_TRG        ))
+#endif /* LPDMA1 */
 #endif /* COMP1 && COMP2 */
 
 #if defined(SMBUS_TRIG_GRP1)
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h
index 61fc8b43bb..d6486f8b9a 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h
@@ -361,6 +361,7 @@ typedef struct
 #define LL_I2C_TRIG_GRP2                   (0x20000000U)         /*!< Trigger Group for I2C3 */
 
 #if defined(LL_I2C_TRIG_GRP1)
+#if defined(GPDMA1)
 #define LL_I2C_GRP1_GPDMA_CH0_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U))
 /*!< HW Trigger signal is GPDMA_CH0_TRG     */
 #define LL_I2C_GRP1_GPDMA_CH1_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
@@ -369,6 +370,17 @@ typedef struct
 /*!< HW Trigger signal is GPDMA_CH2_TRG     */
 #define LL_I2C_GRP1_GPDMA_CH3_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
 /*!< HW Trigger signal is GPDMA_CH3_TRG     */
+#endif /* GPDMA1 */
+#if defined(LPDMA1)
+#define LL_I2C_GRP1_LPDMA_CH0_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U))
+/*!< HW Trigger signal is LPDMA_CH0_TRG     */
+#define LL_I2C_GRP1_LPDMA_CH1_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH1_TRG     */
+#define LL_I2C_GRP1_LPDMA_CH2_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH2_TRG     */
+#define LL_I2C_GRP1_LPDMA_CH3_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH3_TRG     */
+#endif /* LPDMA1 */
 #define LL_I2C_GRP1_EXTI5_TRG              (uint32_t)(LL_I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
 /*!< HW Trigger signal is EXTI5_TRG         */
 #define LL_I2C_GRP1_EXTI9_TRG              (uint32_t)(LL_I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
@@ -391,6 +403,7 @@ typedef struct
 /*!< HW Trigger signal is RTC_WUT_TRG       */
 #endif /* I2C_TRIG_GRP1 */
 
+#if defined(GPDMA1)
 #define LL_I2C_GRP2_GPDMA_CH0_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP2 | (0x00000000U))
 /*!< HW Trigger signal is GPDMA_CH0_TRG     */
 #define LL_I2C_GRP2_GPDMA_CH1_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
@@ -399,6 +412,17 @@ typedef struct
 /*!< HW Trigger signal is GPDMA_CH2_TRG     */
 #define LL_I2C_GRP2_GPDMA_CH3_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
 /*!< HW Trigger signal is GPDMA_CH3_TRG     */
+#endif /* GPDMA1 */
+#if defined(LPDMA1)
+#define LL_I2C_GRP2_LPDMA_CH0_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP2 | (0x00000000U))
+/*!< HW Trigger signal is LPDMA_CH0_TRG     */
+#define LL_I2C_GRP2_LPDMA_CH1_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH1_TRG     */
+#define LL_I2C_GRP2_LPDMA_CH2_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH2_TRG     */
+#define LL_I2C_GRP2_LPDMA_CH3_TCF_TRG      (uint32_t)(LL_I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
+/*!< HW Trigger signal is LPDMA_CH3_TRG     */
+#endif /* LPDMA1 */
 #define LL_I2C_GRP2_EXTI5_TRG              (uint32_t)(LL_I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
 /*!< HW Trigger signal is EXTI5_TRG         */
 #define LL_I2C_GRP2_EXTI8_TRG              (uint32_t)(LL_I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h
index 45334f6127..7907d2118f 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h
@@ -308,8 +308,14 @@ typedef struct
 #if defined(COMP2)
 #define LL_LPTIM_TRIG_SOURCE_COMP2            LPTIM_CFGR_TRIGSEL                                                   /*!<External input trigger is connected to COMP2 output*/
 #endif /* COMP2 */
+#if defined(GPDMA1)
 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF    LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to GPDMA CH0 transfer complete */
 #define LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF    (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to GPDMA CH4 transfer complete */
+#endif /* GPDMA1 */
+#if defined(LPDMA1)
+#define LL_LPTIM_TRIG_SOURCE_LPDMA_CH0_TCF    LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to LPDMA CH0 transfer complete */
+#define LL_LPTIM_TRIG_SOURCE_LPDMA_CH4_TCF    (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to LPDMA CH4 transfer complete */
+#endif /* LPDMA1 */
 /**
   * @}
   */
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h
index bb1626a472..34f6f97767 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h
@@ -202,6 +202,7 @@ extern "C" {
   * @}
   */
 
+#if defined (PWR_CR2_ICRAMPDS)
 /** @defgroup PWR_LL_EC_ICACHERAM_STOP_RETENTION PWR ICACHE SRAM Retention in Stop Mode
   * @{
   */
@@ -210,6 +211,7 @@ extern "C" {
 /**
   * @}
   */
+#endif /* PWR_CR2_ICRAMPDS */
 
 #if defined(PWR_STOP2_SUPPORT)
 #if defined(USB_OTG_HS)
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usb.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usb.h
index 34385bb1ea..8d431171e0 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usb.h
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usb.h
@@ -399,9 +399,9 @@ typedef USB_HCTypeDef       USB_DRD_HCTypeDef;
 /** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
   * @{
   */
-#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1)
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1)
-#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1)
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0UL << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1UL << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3UL << 1)
 /**
   * @}
   */
@@ -509,9 +509,9 @@ typedef USB_HCTypeDef       USB_DRD_HCTypeDef;
 /** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
   * @{
   */
-#define HPRT0_PRTSPD_HIGH_SPEED                0U
-#define HPRT0_PRTSPD_FULL_SPEED                1U
-#define HPRT0_PRTSPD_LOW_SPEED                 2U
+#define HPRT0_PRTSPD_HIGH_SPEED                0UL
+#define HPRT0_PRTSPD_FULL_SPEED                1UL
+#define HPRT0_PRTSPD_LOW_SPEED                 2UL
 /**
   * @}
   */
@@ -542,6 +542,12 @@ typedef USB_HCTypeDef       USB_DRD_HCTypeDef;
 #define TEST_PACKET                            4U
 #define TEST_FORCE_EN                          5U
 
+#define USB_OTG_GAHBCFG_HBSTLEN_SINGLE         (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
+#define USB_OTG_GAHBCFG_HBSTLEN_INCR           (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
+#define USB_OTG_GAHBCFG_HBSTLEN_INCR4          (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
+#define USB_OTG_GAHBCFG_HBSTLEN_INCR8          (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
+#define USB_OTG_GAHBCFG_HBSTLEN_INCR16         (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
+
 #define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
 #define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
 
@@ -641,8 +647,8 @@ typedef USB_HCTypeDef       USB_DRD_HCTypeDef;
   * @}
   */
 /********************  Bit definition for USB_COUNTn_RX register  *************/
-#define USB_CNTRX_NBLK_MSK                    (0x1FU << 26)
-#define USB_CNTRX_BLSIZE                      (0x1U << 31)
+#define USB_CNTRX_NBLK_MSK                    (0x1FUL << 26)
+#define USB_CNTRX_BLSIZE                      (0x1UL << 31)
 
 
 /*Set Channel/Endpoint to the USB Register */
@@ -1213,7 +1219,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
 
 uint32_t          USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx);
 HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
-HAL_StatusTypeDef USB_HC_Activate(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir);
+HAL_StatusTypeDef USB_HC_Activate(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir);
 #endif /* defined (HAL_HCD_MODULE_ENABLED) */
 
 HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
@@ -1249,14 +1255,14 @@ HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx);
 HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg);
 
 #if defined (HAL_HCD_MODULE_ENABLED)
-HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch);
-HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch);
+HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num);
+HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num);
 HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc);
 HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state);
 HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum,
                               uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps);
 
-HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t ch_num, uint8_t ch_dir);
+HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t ch_dir);
 #endif /* defined (HAL_HCD_MODULE_ENABLED) */
 
 uint32_t          USB_GetHostSpeed(USB_DRD_TypeDef const *USBx);
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html
index fcb8816140..8e6d335a28 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html
@@ -65,9 +65,9 @@ <h1 id="purpose">Purpose</h1>
 <section id="update-history" class="col-sm-12 col-lg-8">
 <h1>Update History</h1>
 <div class="collapse">
-<input type="checkbox" id="collapse-section12" checked aria-hidden="true">
-<label for="collapse-section12" aria-hidden="true"><strong>V1.7.0 /
-23-May-2025</strong></label>
+<input type="checkbox" id="collapse-section13" checked aria-hidden="true">
+<label for="collapse-section13" aria-hidden="true"><strong>V1.8.0 /
+07-October-2025</strong></label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <h3
@@ -89,12 +89,110 @@ <h3 id="official-release-of-halll-drivers-for-stm32wbaxx-serie">Official
 HSEM, I2C, ICACHE, IWDG, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI,
 SYSTEM, TIM, USART, USB, UTILS, WWDG</li>
 </ul></li>
+</ul>
+<p><br />
+</p>
+<h2 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h2>
+<ul>
+<li><strong>HAL GPIO</strong> driver
+<ul>
+<li>Update the naming of the USB OTG-HS alternate function</li>
+</ul></li>
+<li><strong>HAL HASH</strong> driver
+<ul>
+<li>Optimization of waiting flag function</li>
+<li>Correction of MISRA warnings</li>
+<li>Correction of compilation warnings in customer environment</li>
+<li>Update related to error callbacks generation with the correct
+computed digest</li>
+</ul></li>
+<li><strong>HAL HCD</strong> driver
+<ul>
+<li>Correction of MISRA warnings</li>
+<li>Adding data toggle support for control EP</li>
+</ul></li>
+<li><strong>HAL PCD</strong> driver
+<ul>
+<li>Correction of MISRA warnings</li>
+</ul></li>
+<li><strong>HAL UART</strong> driver
+<ul>
+<li>Fix transfer count underflow when using polling mode</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h2 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h2>
+<ul>
+<li><strong>LL USB</strong> driver
+<ul>
+<li>Use phy_ch_num instead ch_num for DRD IP</li>
+<li>Correct used value of GAHBCFG[HBSTLEN] field</li>
+<li>Correction of MISRA warnings</li>
+<li>Ensure to enable NYET/NAK ITs</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<ul>
+<li>STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and
+STM32WBA5Mxx devices</li>
+<li>STM32WBA62xx, STM32WBA63xx, STM32WBA64xx, STM32WBA65xx and
+STM32WBA6Mxx devices</li>
+<li>NUCLEO-WBA55CG, STM32WBA55G-DK1 and B-WBA5M-WPAN boards</li>
+<li>NUCLEO-WBA65RI, STM32WBA65I-DK1 and B-WBA6M-WPAN board</li>
+</ul>
+<h2 id="backward-compatibility">Backward compatibility</h2>
+<ul>
+<li>Not applicable</li>
+</ul>
+<h2 id="known-limitations">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="dependencies">Dependencies</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="notes">Notes</h2>
+<ul>
+<li>None</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section12" aria-hidden="true">
+<label for="collapse-section12" aria-hidden="true"><strong>V1.7.0 /
+23-May-2025</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3
+id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba5x-and-stm32wba6x-devices-1">Official
+Release of <strong>STM32CubeWBA</strong> Firmware package supporting
+<strong>STM32WBA5x</strong> and <strong>STM32WBA6x</strong> devices</h3>
+<h2 id="contents-1">Contents</h2>
+<h3
+id="official-release-of-halll-drivers-for-stm32wbaxx-serie-1">Official
+Release of <strong>HAL/LL Drivers</strong> for
+<strong>STM32WBAxx</strong> serie</h3>
+<ul>
+<li><strong>HAL/LL Drivers</strong> are available for all peripherals:
+<ul>
+<li><strong>HAL</strong>: ADC, COMP, CORTEX, CRC, CRYP, DMA, EXTI,
+FLASH, GPIO, GTZC, HASH, HCD, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PCD,
+PKA, PWR, RAMCFG, RCC, RNG, RTC, SAI, SMARTCARD, SMBUS, SPI, TIM, TSC,
+UART, USART, WWDG</li>
+<li><strong>LL</strong>: ADC, BUS, COMP, CORTEX, CRC, DMA, EXTI, GPIO,
+HSEM, I2C, ICACHE, IWDG, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI,
+SYSTEM, TIM, USART, USB, UTILS, WWDG</li>
+</ul></li>
 <li>Update HAL/LL drivers to support of <strong>STM32WBA6Mxx</strong>
 devices</li>
 </ul>
 <p><br />
 </p>
-<h2 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h2>
+<h2 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h2>
 <ul>
 <li><strong>HAL CORTEX</strong> driver
 <ul>
@@ -186,7 +284,7 @@ <h2 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h2>
+<h2 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h2>
 <ul>
 <li><strong>LL ADC</strong> driver
 <ul>
@@ -224,7 +322,8 @@ <h2 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-1">Supported Devices and
+boards</h2>
 <ul>
 <li>STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and
 STM32WBA5Mxx devices</li>
@@ -233,19 +332,19 @@ <h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
 <li>NUCLEO-WBA55CG, STM32WBA55G-DK1 and B-WBA5M-WPAN boards</li>
 <li>NUCLEO-WBA65RI and STM32WBA65I-DK1 board</li>
 </ul>
-<h2 id="backward-compatibility">Backward compatibility</h2>
+<h2 id="backward-compatibility-1">Backward compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
-<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="known-limitations-1">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies">Dependencies</h2>
+<h2 id="dependencies-1">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes">Notes</h2>
+<h2 id="notes-1">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -256,14 +355,14 @@ <h2 id="notes">Notes</h2>
 <label for="collapse-section11" aria-hidden="true"><strong>V1.6.1 /
 02-April-2025</strong></label>
 <div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
 <h3
-id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba5x-and-stm32wba6x-devices-1">Official
+id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba5x-and-stm32wba6x-devices-2">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA5x</strong> and <strong>STM32WBA6x</strong> devices</h3>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
 <h3
-id="official-release-of-halll-drivers-for-stm32wbaxx-serie-1">Official
+id="official-release-of-halll-drivers-for-stm32wbaxx-serie-2">Official
 Release of <strong>HAL/LL Drivers</strong> for
 <strong>STM32WBAxx</strong> serie</h3>
 <ul>
@@ -281,7 +380,7 @@ <h2 id="contents-1">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h2>
+<h2 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h2>
 <ul>
 <li><strong>HAL CRYP</strong> driver
 <ul>
@@ -304,13 +403,13 @@ <h2 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h2>
+<h2 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h2>
 <ul>
 <li>None</li>
 </ul>
 <p><br />
 </p>
-<h2 id="supported-devices-and-boards-1">Supported Devices and
+<h2 id="supported-devices-and-boards-2">Supported Devices and
 boards</h2>
 <ul>
 <li>STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and
@@ -320,19 +419,19 @@ <h2 id="supported-devices-and-boards-1">Supported Devices and
 <li>NUCLEO-WBA55CG, STM32WBA55G-DK1 and B-WBA5M-WPAN boards</li>
 <li>NUCLEO-WBA65RI and STM32WBA65I-DK1 board</li>
 </ul>
-<h2 id="backward-compatibility-1">Backward compatibility</h2>
+<h2 id="backward-compatibility-2">Backward compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-1">Dependencies</h2>
+<h2 id="dependencies-2">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-1">Notes</h2>
+<h2 id="notes-2">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -343,14 +442,14 @@ <h2 id="notes-1">Notes</h2>
 <label for="collapse-section10" aria-hidden="true"><strong>V1.6.0 /
 07-February-2025</strong></label>
 <div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
 <h3
-id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba5x-and-stm32wba6x-devices-2">Official
+id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba5x-and-stm32wba6x-devices-3">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA5x</strong> and <strong>STM32WBA6x</strong> devices</h3>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-3">Contents</h2>
 <h3
-id="official-release-of-halll-drivers-for-stm32wbaxx-serie-2">Official
+id="official-release-of-halll-drivers-for-stm32wbaxx-serie-3">Official
 Release of <strong>HAL/LL Drivers</strong> for
 <strong>STM32WBAxx</strong> serie</h3>
 <ul>
@@ -369,7 +468,7 @@ <h2 id="contents-2">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h2>
+<h2 id="hal-drivers-updates-3"><strong>HAL Drivers</strong> updates</h2>
 <ul>
 <li><strong>HAL ADC</strong> driver
 <ul>
@@ -398,7 +497,7 @@ <h2 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h2>
+<h2 id="ll-drivers-updates-3"><strong>LL Drivers</strong> updates</h2>
 <ul>
 <li><strong>LL LPTIM</strong> driver
 <ul>
@@ -408,7 +507,7 @@ <h2 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="supported-devices-and-boards-2">Supported Devices and
+<h2 id="supported-devices-and-boards-3">Supported Devices and
 boards</h2>
 <ul>
 <li>STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and
@@ -418,19 +517,19 @@ <h2 id="supported-devices-and-boards-2">Supported Devices and
 <li>NUCLEO-WBA55CG, STM32WBA55G-DK1 and B-WBA5M-WPAN boards</li>
 <li>NUCLEO-WBA65RI and STM32WBA65I-DK1 board</li>
 </ul>
-<h2 id="backward-compatibility-2">Backward compatibility</h2>
+<h2 id="backward-compatibility-3">Backward compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
-<h2 id="known-limitations-2">Known Limitations</h2>
+<h2 id="known-limitations-3">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-2">Dependencies</h2>
+<h2 id="dependencies-3">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-2">Notes</h2>
+<h2 id="notes-3">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -441,16 +540,16 @@ <h2 id="notes-2">Notes</h2>
 <label for="collapse-section9" aria-hidden="true"><strong>V1.5.0 /
 22-October-2024</strong></label>
 <div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
 <h3
 id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba50xx-stm32wba52xx-stm32wba54xx-stm32wba55xx-and-stm32wba5mxx-devices">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA50xx</strong>, <strong>STM32WBA52xx</strong>,
 <strong>STM32WBA54xx</strong>, <strong>STM32WBA55xx</strong> and
 <strong>STM32WBA5Mxx</strong> devices</h3>
-<h2 id="contents-3">Contents</h2>
+<h2 id="contents-4">Contents</h2>
 <h3
-id="official-release-of-halll-drivers-for-stm32wbaxx-serie-3">Official
+id="official-release-of-halll-drivers-for-stm32wbaxx-serie-4">Official
 Release of <strong>HAL/LL Drivers</strong> for
 <strong>STM32WBAxx</strong> serie</h3>
 <ul>
@@ -468,7 +567,7 @@ <h2 id="contents-3">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="hal-drivers-updates-3"><strong>HAL Drivers</strong> updates</h2>
+<h2 id="hal-drivers-updates-4"><strong>HAL Drivers</strong> updates</h2>
 <ul>
 <li><strong>HAL COMP</strong> driver
 <ul>
@@ -541,7 +640,7 @@ <h2 id="hal-drivers-updates-3"><strong>HAL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="ll-drivers-updates-3"><strong>LL Drivers</strong> updates</h2>
+<h2 id="ll-drivers-updates-4"><strong>LL Drivers</strong> updates</h2>
 <ul>
 <li><strong>LL ADC</strong> driver
 <ul>
@@ -574,26 +673,26 @@ <h2 id="ll-drivers-updates-3"><strong>LL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="supported-devices-and-boards-3">Supported Devices and
+<h2 id="supported-devices-and-boards-4">Supported Devices and
 boards</h2>
 <ul>
 <li>STM32WBA50xx, STM32WBA52xx, STM32WBA54xx, STM32WBA55xx and
 STM32WBA5Mxx devices</li>
 <li>NUCLEO-WBA55CG, STM32WBA55G-DK1 and b-WBA5M-WPAN boards</li>
 </ul>
-<h2 id="backward-compatibility-3">Backward compatibility</h2>
+<h2 id="backward-compatibility-4">Backward compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
-<h2 id="known-limitations-3">Known Limitations</h2>
+<h2 id="known-limitations-4">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-3">Dependencies</h2>
+<h2 id="dependencies-4">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-3">Notes</h2>
+<h2 id="notes-4">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -604,16 +703,16 @@ <h2 id="notes-3">Notes</h2>
 <label for="collapse-section8" aria-hidden="true"><strong>V1.4.0 /
 05-June-2024</strong></label>
 <div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
 <h3
 id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba50xx-stm32wba52xx-stm32wba54xx-and-stm32wba55xx-devices">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA50xx</strong>, <strong>STM32WBA52xx</strong>,
 <strong>STM32WBA54xx</strong> and <strong>STM32WBA55xx</strong>
 devices</h3>
-<h2 id="contents-4">Contents</h2>
+<h2 id="contents-5">Contents</h2>
 <h3
-id="official-release-of-halll-drivers-for-stm32wbaxx-serie-4">Official
+id="official-release-of-halll-drivers-for-stm32wbaxx-serie-5">Official
 Release of <strong>HAL/LL Drivers</strong> for
 <strong>STM32WBAxx</strong> serie</h3>
 <ul>
@@ -630,7 +729,7 @@ <h2 id="contents-4">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="hal-drivers-updates-4"><strong>HAL Drivers</strong> updates</h2>
+<h2 id="hal-drivers-updates-5"><strong>HAL Drivers</strong> updates</h2>
 <ul>
 <li><strong>HAL CORTEX</strong> driver
 <ul>
@@ -675,7 +774,7 @@ <h2 id="hal-drivers-updates-4"><strong>HAL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="ll-drivers-updates-4"><strong>LL Drivers</strong> updates</h2>
+<h2 id="ll-drivers-updates-5"><strong>LL Drivers</strong> updates</h2>
 <ul>
 <li><strong>LL CORTEX</strong> driver
 <ul>
@@ -705,26 +804,26 @@ <h2 id="ll-drivers-updates-4"><strong>LL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="supported-devices-and-boards-4">Supported Devices and
+<h2 id="supported-devices-and-boards-5">Supported Devices and
 boards</h2>
 <ul>
 <li>STM32WBA50xx, STM32WBA52xx, STM32WBA54xx and STM32WBA55xx
 devices</li>
 <li>NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards</li>
 </ul>
-<h2 id="backward-compatibility-4">Backward compatibility</h2>
+<h2 id="backward-compatibility-5">Backward compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
-<h2 id="known-limitations-4">Known Limitations</h2>
+<h2 id="known-limitations-5">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-4">Dependencies</h2>
+<h2 id="dependencies-5">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-4">Notes</h2>
+<h2 id="notes-5">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -735,15 +834,15 @@ <h2 id="notes-4">Notes</h2>
 <label for="collapse-section7" aria-hidden="true"><strong>V1.3.0 /
 07-February-2024</strong></label>
 <div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
 <h3
 id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba52xx-and-stm32wba55xx-devices">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA52xx</strong> and <strong>STM32WBA55xx</strong>
 devices</h3>
-<h2 id="contents-5">Contents</h2>
+<h2 id="contents-6">Contents</h2>
 <h3
-id="official-release-of-halll-drivers-for-stm32wbaxx-serie-5">Official
+id="official-release-of-halll-drivers-for-stm32wbaxx-serie-6">Official
 Release of <strong>HAL/LL Drivers</strong> for
 <strong>STM32WBAxx</strong> serie</h3>
 <ul>
@@ -760,7 +859,7 @@ <h2 id="contents-5">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="hal-drivers-updates-5"><strong>HAL Drivers</strong> updates</h2>
+<h2 id="hal-drivers-updates-6"><strong>HAL Drivers</strong> updates</h2>
 <ul>
 <li><strong>HAL CORTEX</strong> driver
 <ul>
@@ -798,7 +897,7 @@ <h2 id="hal-drivers-updates-5"><strong>HAL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="ll-drivers-updates-5"><strong>LL Drivers</strong> updates</h2>
+<h2 id="ll-drivers-updates-6"><strong>LL Drivers</strong> updates</h2>
 <ul>
 <li><strong>LL LPUART</strong> driver
 <ul>
@@ -807,25 +906,25 @@ <h2 id="ll-drivers-updates-5"><strong>LL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="supported-devices-and-boards-5">Supported Devices and
+<h2 id="supported-devices-and-boards-6">Supported Devices and
 boards</h2>
 <ul>
 <li>STM32WBA52xx and STM32WBA55xx devices</li>
 <li>NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards</li>
 </ul>
-<h2 id="backward-compatibility-5">Backward compatibility</h2>
+<h2 id="backward-compatibility-6">Backward compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
-<h2 id="known-limitations-5">Known Limitations</h2>
+<h2 id="known-limitations-6">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-5">Dependencies</h2>
+<h2 id="dependencies-6">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-5">Notes</h2>
+<h2 id="notes-6">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -836,15 +935,15 @@ <h2 id="notes-5">Notes</h2>
 <label for="collapse-section6" aria-hidden="true"><strong>V1.2.0 /
 02-November-2023</strong></label>
 <div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
 <h3
 id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba52xx-and-stm32wba55xx-devices-1">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA52xx</strong> and <strong>STM32WBA55xx</strong>
 devices</h3>
-<h2 id="contents-6">Contents</h2>
+<h2 id="contents-7">Contents</h2>
 <h3
-id="official-release-of-halll-drivers-for-stm32wbaxx-serie-6">Official
+id="official-release-of-halll-drivers-for-stm32wbaxx-serie-7">Official
 Release of <strong>HAL/LL Drivers</strong> for
 <strong>STM32WBAxx</strong> serie</h3>
 <ul>
@@ -871,7 +970,7 @@ <h2 id="contents-6">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="hal-drivers-updates-6"><strong>HAL Drivers</strong> updates</h2>
+<h2 id="hal-drivers-updates-7"><strong>HAL Drivers</strong> updates</h2>
 <ul>
 <li><strong>HAL CORTEX</strong> driver
 <ul>
@@ -984,7 +1083,7 @@ <h2 id="hal-drivers-updates-6"><strong>HAL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="ll-drivers-updates-6"><strong>LL Drivers</strong> updates</h2>
+<h2 id="ll-drivers-updates-7"><strong>LL Drivers</strong> updates</h2>
 <ul>
 <li><strong>LL GPIO</strong> driver
 <ul>
@@ -1011,25 +1110,25 @@ <h2 id="ll-drivers-updates-6"><strong>LL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="supported-devices-and-boards-6">Supported Devices and
+<h2 id="supported-devices-and-boards-7">Supported Devices and
 boards</h2>
 <ul>
 <li>STM32WBA52xx and STM32WBA55xx devices</li>
 <li>NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards</li>
 </ul>
-<h2 id="backward-compatibility-6">Backward compatibility</h2>
+<h2 id="backward-compatibility-7">Backward compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
-<h2 id="known-limitations-6">Known Limitations</h2>
+<h2 id="known-limitations-7">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-6">Dependencies</h2>
+<h2 id="dependencies-7">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-6">Notes</h2>
+<h2 id="notes-7">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -1040,14 +1139,14 @@ <h2 id="notes-6">Notes</h2>
 <label for="collapse-section5" aria-hidden="true"><strong>V1.1.0 /
 06-June-2023</strong></label>
 <div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
 <h3
 id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba52xx-devices">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA52xx</strong> devices</h3>
-<h2 id="contents-7">Contents</h2>
+<h2 id="contents-8">Contents</h2>
 <h3
-id="official-release-of-halll-drivers-for-stm32wbaxx-serie-7">Official
+id="official-release-of-halll-drivers-for-stm32wbaxx-serie-8">Official
 Release of <strong>HAL/LL Drivers</strong> for
 <strong>STM32WBAxx</strong> serie</h3>
 <ul>
@@ -1063,7 +1162,7 @@ <h2 id="contents-7">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="hal-drivers-updates-7"><strong>HAL Drivers</strong> updates</h2>
+<h2 id="hal-drivers-updates-8"><strong>HAL Drivers</strong> updates</h2>
 <ul>
 <li><strong>HAL CORTEX</strong> driver
 <ul>
@@ -1141,7 +1240,7 @@ <h2 id="hal-drivers-updates-7"><strong>HAL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="ll-drivers-updates-7"><strong>LL Drivers</strong> updates</h2>
+<h2 id="ll-drivers-updates-8"><strong>LL Drivers</strong> updates</h2>
 <ul>
 <li><strong>LL DMA</strong> driver
 <ul>
@@ -1167,25 +1266,25 @@ <h2 id="ll-drivers-updates-7"><strong>LL Drivers</strong> updates</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="supported-devices-and-boards-7">Supported Devices and
+<h2 id="supported-devices-and-boards-8">Supported Devices and
 boards</h2>
 <ul>
 <li>STM32WBA52xx devices</li>
 <li>NUCLEO-WBA52CG board</li>
 </ul>
-<h2 id="backward-compatibility-7">Backward compatibility</h2>
+<h2 id="backward-compatibility-8">Backward compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
-<h2 id="known-limitations-7">Known Limitations</h2>
+<h2 id="known-limitations-8">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-7">Dependencies</h2>
+<h2 id="dependencies-8">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-7">Notes</h2>
+<h2 id="notes-8">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -1196,12 +1295,12 @@ <h2 id="notes-7">Notes</h2>
 <label for="collapse-section4" checked aria-hidden="true"><strong>V1.0.0
 / 08-February-2023</strong></label>
 <div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
 <h3
 id="first-official-release-of-stm32cubewba-firmware-package-supporting-stm32wba52xx-devices">First
 Official Release of <strong>STM32CubeWBA</strong> Firmware package
 supporting <strong>STM32WBA52xx</strong> devices</h3>
-<h2 id="contents-8">Contents</h2>
+<h2 id="contents-9">Contents</h2>
 <h3
 id="first-official-release-of-halll-drivers-for-stm32wbaxx-serie">First
 Official Release of <strong>HAL/LL Drivers</strong> for
@@ -1219,25 +1318,25 @@ <h2 id="contents-8">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="supported-devices-and-boards-8">Supported Devices and
+<h2 id="supported-devices-and-boards-9">Supported Devices and
 boards</h2>
 <ul>
 <li>STM32WBA52xx devices</li>
 <li>NUCLEO-WBA52CG board</li>
 </ul>
-<h2 id="backward-compatibility-8">Backward compatibility</h2>
+<h2 id="backward-compatibility-9">Backward compatibility</h2>
 <ul>
 <li>Not applicable</li>
 </ul>
-<h2 id="known-limitations-8">Known Limitations</h2>
+<h2 id="known-limitations-9">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-8">Dependencies</h2>
+<h2 id="dependencies-9">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-8">Notes</h2>
+<h2 id="notes-9">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hash.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hash.c
index 8ee08b2aeb..05eafdb6d5 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hash.c
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hash.c
@@ -301,7 +301,7 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
   *         the configuration information for HASH module
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf)
+HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, const HASH_ConfigTypeDef *pConf)
 {
   uint32_t cr_value;
 
@@ -751,11 +751,11 @@ HAL_StatusTypeDef HAL_HASH_ProcessSuspend(HASH_HandleTypeDef *hhash)
       /* DMA3 used, DMA_CBR1_BNDT in bytes, DMA_CSR_FIFOL in words */
       remainingwords = ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CBR1) \
                         & DMA_CBR1_BNDT) / 4U;
-#if defined(GPDMA1)
+#if  defined(DMA_CSR_FIFOL)
       remainingwords += ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CSR) \
                          & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos;
-#endif /* GPDMA1 */
 
+#endif /* DMA_CSR_FIFOL */
       if (remainingwords <= nbbytePartialHash)
       {
         /* No suspension attempted since almost to the end of the transferred data. */
@@ -1837,11 +1837,10 @@ HAL_StatusTypeDef HAL_HASH_HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_
   {
     return HAL_BUSY;
   }
-
+  status = HASH_WriteData_IT(hhash);
   /* Enable the specified HASH interrupt*/
   __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
 
-  status = HASH_WriteData_IT(hhash);
 
   /* Return function status */
   return status;
@@ -1909,10 +1908,10 @@ HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate_IT(HASH_HandleTypeDef *hhash, const u
       /* Set the phase */
       hhash->Phase = HAL_HASH_PHASE_PROCESS;
     }
+    status = HASH_WriteData_IT(hhash);
     /* Enable the specified HASH interrupt*/
     __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
 
-    status = HASH_WriteData_IT(hhash);
   }
   else
   {
@@ -1959,10 +1958,10 @@ HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast_IT(HASH_HandleTypeDef *hhash, con
     hhash->Size = Size;
     /* Set multi buffers accumulation flag */
     hhash->Accumulation = 0U;
+    status = HASH_WriteData_IT(hhash);
     /* Enable the specified HASH interrupt*/
     __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI);
 
-    status = HASH_WriteData_IT(hhash);
   }
   else
   {
@@ -2203,7 +2202,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
 
   }
   /* If Peripheral ready to accept new data */
-  if ((itflag & HASH_FLAG_DINIS) == HASH_FLAG_DINIS)
+  if (((itflag & HASH_FLAG_DINIS) == HASH_FLAG_DINIS) && ((itflag & HASH_FLAG_DCIS) != HASH_FLAG_DCIS))
   {
     if ((itsource & HASH_IT_DINI) == HASH_IT_DINI)
     {
@@ -2909,7 +2908,7 @@ static HAL_StatusTypeDef HASH_WriteData_IT(HASH_HandleTypeDef *hhash)
       }
     }
   }
-  else if ((hhash->State == HAL_HASH_STATE_SUSPENDED))
+  else if (hhash->State == HAL_HASH_STATE_SUSPENDED)
   {
     return HAL_OK;
   }
@@ -3015,43 +3014,20 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash,
 {
   uint32_t tickstart = HAL_GetTick();
 
-  /* Wait until flag is set */
-  if (Status == RESET)
-  {
-    while (__HAL_HASH_GET_FLAG(hhash, Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if (Timeout != HAL_MAX_DELAY)
-      {
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-        {
-          /* Set State to Ready to be able to restart later on */
-          hhash->State  = HAL_HASH_STATE_READY;
-          hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
-          /* Process Unlocked */
-          __HAL_UNLOCK(hhash);
-          return HAL_ERROR;
-        }
-      }
-    }
-  }
-  else
+  while (__HAL_HASH_GET_FLAG(hhash, Flag) == Status)
   {
-    while (__HAL_HASH_GET_FLAG(hhash, Flag) != RESET)
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
     {
-      /* Check for the Timeout */
-      if (Timeout != HAL_MAX_DELAY)
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
       {
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-        {
-          /* Set State to Ready to be able to restart later on */
-          hhash->State  = HAL_HASH_STATE_READY;
-          hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
-          /* Process Unlocked */
-          __HAL_UNLOCK(hhash);
+        /* Set State to Ready to be able to restart later on */
+        hhash->State  = HAL_HASH_STATE_READY;
+        hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhash);
 
-          return HAL_ERROR;
-        }
+        return HAL_ERROR;
       }
     }
   }
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hcd.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hcd.c
index 9528b4cbf9..306d23f0bb 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hcd.c
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hcd.c
@@ -1777,8 +1777,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
       hhcd->hc[chnum].state = HC_HALTED;
       hhcd->hc[chnum].urb_state = URB_DONE;
 
-      if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) ||
-          (hhcd->hc[chnum].ep_type == EP_TYPE_INTR))
+      if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC)
       {
         if (hhcd->Init.dma_enable == 0U)
         {
@@ -2284,7 +2283,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
           else
           {
             /* This is a dual EP0 PMA allocation */
-            hhcd->ep0_PmaAllocState |= (0x1U << 12);
+            hhcd->ep0_PmaAllocState |= (0x1UL << 12);
 
             /* PMA Dynamic Allocation for EP0 OUT direction */
             hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR;
@@ -4520,7 +4519,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps)
     while ((j <= 31U) && (FreeBlocks != NbrReqBlocks))
     {
       /* check if block j is free */
-      if ((Entry & ((uint32_t)1U << j)) == 0U)
+      if ((Entry & ((uint32_t)1UL << j)) == 0U)
       {
         if (FreeBlocks == 0U)
         {
@@ -4531,7 +4530,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps)
         j++;
 
         /* Parse Column PMALockTable */
-        while ((j <= 31U) && ((Entry & ((uint32_t)1U << j)) == 0U) && (FreeBlocks < NbrReqBlocks))
+        while ((j <= 31U) && ((Entry & ((uint32_t)1UL << j)) == 0U) && (FreeBlocks < NbrReqBlocks))
         {
           FreeBlocks++;
           j++;
@@ -4539,7 +4538,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps)
 
         /* Free contiguous Blocks not found */
         if (((FreeBlocks < NbrReqBlocks) && (j < 31U)) ||
-            ((j == 31U) && ((Entry & ((uint32_t)1U << j)) != 0U)))
+            ((j == 31U) && ((Entry & ((uint32_t)1UL << j)) != 0U)))
         {
           FreeBlocks = 0U;
         }
@@ -4557,7 +4556,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps)
     {
       for (uint8_t j = ColIndex; j <= 31U; j++)
       {
-        hhcd->PMALookupTable[i] |= ((uint32_t)1U << j);
+        hhcd->PMALookupTable[i] |= ((uint32_t)1UL << j);
         if (--FreeBlocks == 0U)
         {
           break;
@@ -4616,7 +4615,7 @@ HAL_StatusTypeDef  HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
       {
         hhcd->ep0_PmaAllocState &= 0xFFF0U;
         hhcd->ep0_PmaAllocState |= ch_num;
-        hhcd->ep0_PmaAllocState |= (1U << 8);
+        hhcd->ep0_PmaAllocState |= (1UL << 8);
       }
 
       /* Configure the PMA */
@@ -4749,7 +4748,7 @@ HAL_StatusTypeDef  HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd)
   /* Allocate a Space for buffer descriptor table depending on the Host channel number */
   for (uint8_t i = 0U; i < hhcd->Init.Host_channels; i++)
   {
-    hhcd->PMALookupTable[0] |= ((uint32_t)1U << i);
+    hhcd->PMALookupTable[0] |= ((uint32_t)1UL << i);
   }
 
   return HAL_OK;
@@ -4811,12 +4810,12 @@ static HAL_StatusTypeDef  HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_
     for (uint8_t j = ColIndex; j <= 31U; j++)
     {
       /* Check if the block is not already reserved or it was already closed */
-      if ((hhcd->PMALookupTable[i] & ((uint32_t)1U << j)) == 0U)
+      if ((hhcd->PMALookupTable[i] & ((uint32_t)1UL << j)) == 0U)
       {
         return HAL_ERROR;
       }
       /* Free the reserved block by resetting the corresponding bit */
-      hhcd->PMALookupTable[i] &= ~(1U << j);
+      hhcd->PMALookupTable[i] &= ~(1UL << j);
 
       if (--block_nbr == 0U)
       {
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pcd.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pcd.c
index 2e169f908d..209990fe9e 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pcd.c
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pcd.c
@@ -1451,7 +1451,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
 
         if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
             ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
-            (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U)))
+            (((RegVal & (0x1UL << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U)))
         {
           hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
 
@@ -2241,7 +2241,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t tes
     case TEST_SE0_NAK:
     case TEST_PACKET:
     case TEST_FORCE_EN:
-      USBx_DEVICE->DCTL &= ~(0x7U << 4);
+      USBx_DEVICE->DCTL &= ~(0x7UL << 4);
       USBx_DEVICE->DCTL |= (uint32_t)testmode << 4;
       break;
 
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr_ex.c
index 92bc2f411e..2c77a89f3f 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr_ex.c
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr_ex.c
@@ -409,7 +409,7 @@ void HAL_PWREx_DisableFastSoftStart(void)
 }
 
 #if defined(PWR_STOP2_SUPPORT)
-#if defined(USB_OTG_HS)
+#if defined(PWR_VOSR_USBPWREN)
 /**
   * @brief  Configure the clocked delay between VDD11USBDIS and VDD11USBRDY.
   * @param  Delay : Specifies the delay in system clock cycles.
@@ -520,7 +520,9 @@ void HAL_PWREx_DisableUSBPWR(void)
 {
   CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBPWREN);
 }
+#endif /* defined(PWR_VOSR_USBPWREN) */
 
+#if defined(PWR_SVMCR_USV)
 /**
   * @brief  Enable VDDUSB supply.
   * @note   Remove VDDUSB electrical and logical isolation, once VDDUSB supply
@@ -540,7 +542,7 @@ void HAL_PWREx_DisableVddUSB(void)
 {
   CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV);
 }
-#endif /* defined(USB_OTG_HS) */
+#endif /* defined(PWR_SVMCR_USV) */
 
 #if defined(PWR_SVMCR_IO2SV)
 /**
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_ramcfg.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_ramcfg.c
index 5c186f8fd1..dd3944dd89 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_ramcfg.c
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_ramcfg.c
@@ -676,7 +676,7 @@ HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg
 
   /* Check the parameters */
   assert_param(IS_RAMCFG_WP_INSTANCE(hramcfg->Instance));
-  assert_param(IS_RAMCFG_WRITEPROTECTION_PAGE(StartPage + NbPage));
+  assert_param(IS_RAMCFG_WRITEPROTECTION_PAGE(StartPage + NbPage - 1U));
 
   /* Check RAMCFG state */
   if (hramcfg->State == HAL_RAMCFG_STATE_READY)
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc_ex.c
index 7801b24235..ff2a51f743 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc_ex.c
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc_ex.c
@@ -2648,7 +2648,7 @@ void  HAL_RTCEx_BKUPUnblock(const RTC_HandleTypeDef *hrtc)
   CLEAR_BIT(TAMP->CR2, TAMP_CR2_BKBLOCK);
 }
 
-#ifdef TAMP_RPCFGR_RPCFG
+#if defined (TAMP_RPCFGR_RPCFG) || defined(TAMP_ERCFGR_ERCFG)
 /**
   * @brief  Enable and Disable the erase of the configurable Device Secrets
   * @note   This API must be called before enabling the Tamper.
@@ -2670,7 +2670,11 @@ void  HAL_RTCEx_ConfigEraseDeviceSecrets(const RTC_HandleTypeDef *hrtc, uint32_t
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hrtc);
 
+#if defined (TAMP_RPCFGR_RPCFG)
   MODIFY_REG(TAMP->RPCFGR, TAMP_RPCFGR_RPCFG, DeviceSecretConf);
+#elif defined (TAMP_ERCFGR_ERCFG)
+  MODIFY_REG(TAMP->ERCFGR, TAMP_ERCFGR_ERCFG, DeviceSecretConf);
+#endif
 }
 #endif /* TAMP_RPCFGR_RPCFG */
 
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c
index 1887f6c60d..9d3d21bb56 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c
@@ -1161,7 +1161,15 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD
         huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
         pdata8bits++;
       }
-      huart->TxXferCount--;
+      if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX)
+      {
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Process was aborted during the transmission */
+        return HAL_ERROR;
+      }
     }
 
     if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
@@ -1257,7 +1265,15 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
         *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
         pdata8bits++;
       }
-      huart->RxXferCount--;
+      if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+      {
+        huart->RxXferCount--;
+      }
+      else
+      {
+        /* Process was aborted during the reception */
+        return HAL_ERROR;
+      }
     }
 
     /* At end of Rx process, restore huart->RxState to Ready */
@@ -1790,10 +1806,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
   }
 #endif /* HAL_DMA_MODULE_ENABLED */
 
-  /* Reset Tx and Rx transfer counters */
-  huart->TxXferCount = 0U;
-  huart->RxXferCount = 0U;
-
   /* Clear the Error flags in the ICR register */
   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
 
@@ -1862,9 +1874,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
   }
 #endif /* HAL_DMA_MODULE_ENABLED */
 
-  /* Reset Tx transfer counter */
-  huart->TxXferCount = 0U;
-
   /* Flush the whole TX FIFO (if needed) */
   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
   {
@@ -1929,9 +1938,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
   }
 #endif /* HAL_DMA_MODULE_ENABLED */
 
-  /* Reset Rx transfer counter */
-  huart->RxXferCount = 0U;
-
   /* Clear the Error flags in the ICR register */
   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
 
@@ -2059,10 +2065,6 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
   if (abortcplt == 1U)
   {
-    /* Reset Tx and Rx transfer counters */
-    huart->TxXferCount = 0U;
-    huart->RxXferCount = 0U;
-
     /* Clear ISR function pointers */
     huart->RxISR = NULL;
     huart->TxISR = NULL;
@@ -2143,8 +2145,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
     }
     else
     {
-      /* Reset Tx transfer counter */
-      huart->TxXferCount = 0U;
 
       /* Clear TxISR function pointers */
       huart->TxISR = NULL;
@@ -2165,9 +2165,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
   else
 #endif /* HAL_DMA_MODULE_ENABLED */
   {
-    /* Reset Tx transfer counter */
-    huart->TxXferCount = 0U;
-
     /* Clear TxISR function pointers */
     huart->TxISR = NULL;
 
@@ -2242,9 +2239,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
     }
     else
     {
-      /* Reset Rx transfer counter */
-      huart->RxXferCount = 0U;
-
       /* Clear RxISR function pointer */
       huart->pRxBuffPtr = NULL;
 
@@ -2271,9 +2265,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
   else
 #endif /* HAL_DMA_MODULE_ENABLED */
   {
-    /* Reset Rx transfer counter */
-    huart->RxXferCount = 0U;
-
     /* Clear RxISR function pointer */
     huart->pRxBuffPtr = NULL;
 
@@ -3760,8 +3751,6 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
   /* Check if DMA in circular mode */
   if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
   {
-    huart->TxXferCount = 0U;
-
     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
        in the UART CR3 register */
     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
@@ -3812,8 +3801,6 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
   /* Check if DMA in circular mode */
   if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
   {
-    huart->RxXferCount = 0U;
-
     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
     ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
     ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
@@ -3840,8 +3827,6 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
      If Reception till IDLE event has been selected : use Rx Event callback */
   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
   {
-    huart->RxXferCount = 0;
-
     /* Check current nb of data still to be received on DMA side.
        DMA Normal mode, remaining nb of data will be 0
        DMA Circular mode, remaining nb of data is reset to RxXferSize */
@@ -3937,7 +3922,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
       (gstate == HAL_UART_STATE_BUSY_TX))
   {
-    huart->TxXferCount = 0U;
     UART_EndTxTransfer(huart);
   }
 
@@ -3945,7 +3929,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
       (rxstate == HAL_UART_STATE_BUSY_RX))
   {
-    huart->RxXferCount = 0U;
     UART_EndRxTransfer(huart);
   }
 
@@ -3969,7 +3952,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma)
 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
 {
   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
-  huart->RxXferCount = 0U;
 
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
   /*Call registered error callback*/
@@ -4003,10 +3985,6 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
     }
   }
 
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  huart->TxXferCount = 0U;
-  huart->RxXferCount = 0U;
-
   /* Reset errorCode */
   huart->ErrorCode = HAL_UART_ERROR_NONE;
 
@@ -4058,10 +4036,6 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
     }
   }
 
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  huart->TxXferCount = 0U;
-  huart->RxXferCount = 0U;
-
   /* Reset errorCode */
   huart->ErrorCode = HAL_UART_ERROR_NONE;
 
@@ -4099,8 +4073,6 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
 {
   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
 
-  huart->TxXferCount = 0U;
-
   /* Flush the whole TX FIFO (if needed) */
   if (huart->FifoMode == UART_FIFOMODE_ENABLE)
   {
@@ -4132,8 +4104,6 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
 {
   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
-  huart->RxXferCount = 0U;
-
   /* Clear the Error flags in the ICR register */
   __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
 
diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_usb.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_usb.c
index 47a92d9f97..7a17904212 100644
--- a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_usb.c
+++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_usb.c
@@ -103,7 +103,8 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
 
   if (cfg.dma_enable == 1U)
   {
-    USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
+    USBx->GAHBCFG &= ~(USB_OTG_GAHBCFG_HBSTLEN);
+    USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_INCR4;
     USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
   }
 
@@ -734,7 +735,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
     if (ep->xfer_len == 0U)
     {
       USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1UL << 19));
       USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
     }
     else
@@ -754,7 +755,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
           ep->xfer_len = ep->maxpacket;
         }
 
-        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1UL << 19));
       }
       else
       {
@@ -780,7 +781,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
 
       if (ep->type == EP_TYPE_ISOC)
       {
-        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+        if ((USBx_DEVICE->DSTS & (1UL << 8)) == 0U)
         {
           USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
         }
@@ -808,7 +809,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
       }
       else
       {
-        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+        if ((USBx_DEVICE->DSTS & (1UL << 8)) == 0U)
         {
           USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
         }
@@ -841,14 +842,14 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
       ep->xfer_size = ep->maxpacket;
 
       USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
-      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19));
     }
     else
     {
       if (ep->xfer_len == 0U)
       {
         USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
-        USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+        USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19));
       }
       else
       {
@@ -870,7 +871,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
 
     if (ep->type == EP_TYPE_ISOC)
     {
-      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)
+      if ((USBx_DEVICE->DSTS & (1UL << 8)) == 0U)
       {
         USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
       }
@@ -896,10 +897,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
 HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
 {
   __IO uint32_t count = 0U;
+  __IO uint32_t RegVal;
   HAL_StatusTypeDef ret = HAL_OK;
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t dma_enable = (USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) >> 0x5U;
-  uint32_t RegVal;
 
   /* IN endpoint */
   if (ep->is_in == 1U)
@@ -1393,7 +1394,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dm
   }
 
   USBx_OUTEP(0U)->DOEPTSIZ = 0U;
-  USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+  USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19));
   USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
   USBx_OUTEP(0U)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;
 
@@ -1525,8 +1526,8 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
   USBx->GINTSTS = CLEAR_INTERRUPT_MASK;
   /* set Rx FIFO size */
   USBx->GRXFSIZ  = 0x200U;
-  USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
-  USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
+  USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100UL << 16) & USB_OTG_NPTXFD) | 0x200U);
+  USBx->HPTXFSIZ = (uint32_t)(((0xE0UL << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
 
   /* Enable the common interrupts */
   if (cfg.dma_enable == 0U)
@@ -1769,7 +1770,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
   /* Program the HCCHAR register */
   if ((epnum & 0x80U) == 0x80U)
   {
-    HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
+    HCcharEpDir = (0x1UL << 15) & USB_OTG_HCCHAR_EPDIR;
   }
   else
   {
@@ -1781,7 +1782,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
   /* LS device plugged to HUB */
   if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED))
   {
-    HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
+    HCcharLowSpeed = (0x1UL << 17) & USB_OTG_HCCHAR_LSDEV;
   }
   else
   {
@@ -1825,7 +1826,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
   /* in DMA mode host Core automatically issues ping in case of NYET/NAK */
   if (dma == 1U)
   {
-    if ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK))
+    if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U))
     {
 
       USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET |
@@ -2110,7 +2111,7 @@ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
 
     if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
     {
-      if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
+      if ((USBx->HNPTXSTS & (0xFFUL << 16)) == 0U)
       {
         USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
         USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
@@ -2138,7 +2139,7 @@ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
   {
     USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
 
-    if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
+    if ((USBx_HOST->HPTXSTS & (0xFFUL << 16)) == 0U)
     {
       USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
       USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
@@ -2169,7 +2170,7 @@ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
   * @param  ch_dir Host Channel direction
   * @retval HAL state
   */
-HAL_StatusTypeDef USB_HC_Activate(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir)
+HAL_StatusTypeDef USB_HC_Activate(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir)
 {
   UNUSED(ch_dir);
 
@@ -3390,7 +3391,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num,
                  USB_CHEP_KIND |
                  USB_CHEP_ERRTX |
                  USB_CHEP_ERRRX |
-                 (0xFU << 27));
+                 (0xFUL << 27));
 
   /* Set device address and Endpoint number associated to the channel */
   wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) |
@@ -3678,13 +3679,13 @@ static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx,
 /**
   * @brief  Halt a host channel in
   * @param  USBx Selected device
-  * @param  hc_num Host Channel number
+  * @param  phy_ch_num Host Channel number
   * @retval HAL state
   */
-HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch)
+HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num)
 {
   /* Set disable to Channel */
-  USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch, USB_CH_RX_DIS);
+  USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_DIS);
 
   return HAL_OK;
 }
@@ -3693,13 +3694,13 @@ HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch)
 /**
   * @brief  Halt a host channel out
   * @param  USBx Selected device
-  * @param  hc_num Host Channel number
+  * @param  phy_ch_num Host Channel number
   * @retval HAL state
   */
-HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch)
+HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num)
 {
   /* Set disable to Channel */
-  USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch, USB_CH_TX_DIS);
+  USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch_num, USB_CH_TX_DIS);
 
   return HAL_OK;
 }
@@ -3707,21 +3708,21 @@ HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch)
 /**
   * @brief  Activate a host channel
   * @param  USBx  Selected device
-  * @param  ch_num  Host Channel number
+  * @param  phy_ch_num  Host Channel number
   * @param  ch_dir  Host Channel direction
   * @retval HAL state
   */
-HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch, uint8_t ch_dir)
+HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t ch_dir)
 {
   if (ch_dir == CH_IN_DIR)
   {
     /* Enable TX host Channel */
-    USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch, USB_CH_TX_VALID);
+    USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch_num, USB_CH_TX_VALID);
   }
   else
   {
     /* Enable RX host Channel */
-    USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch, USB_CH_RX_VALID);
+    USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_VALID);
   }
 
   return HAL_OK;
diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md
index 71c0cd92cc..02aa7cf49b 100644
--- a/system/Drivers/STM32YYxx_HAL_Driver_version.md
+++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md
@@ -21,7 +21,7 @@
   * STM32U5: 1.6.2
   * STM32WB: 1.14.6
   * STM32WB0: 1.4.0
-  * STM32WBA: 1.7.0
+  * STM32WBA: 1.8.0
   * STM32WL: 1.4.0
   * STM32WL3: 1.2.0
 

From 5b3eb9028374e79e4d9062e53370c308bfdc395e Mon Sep 17 00:00:00 2001
From: Frederic Pillon <frederic.pillon@st.com>
Date: Thu, 27 Nov 2025 09:37:27 +0100
Subject: [PATCH 2/3] system(wba): update STM32WBAxx CMSIS Drivers to v1.8.0

Included in STM32CubeWBA FW v1.8.0

Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
---
 .../ST/STM32WBAxx/Include/stm32wba62xx.h      |   2 +-
 .../ST/STM32WBAxx/Include/stm32wba63xx.h      |   2 +-
 .../ST/STM32WBAxx/Include/stm32wba64xx.h      |   2 +-
 .../ST/STM32WBAxx/Include/stm32wba65xx.h      |   2 +-
 .../ST/STM32WBAxx/Include/stm32wba6mxx.h      |   2 +-
 .../Device/ST/STM32WBAxx/Include/stm32wbaxx.h |   2 +-
 .../Device/ST/STM32WBAxx/Release_Notes.html   | 125 ++++++++++++------
 .../gcc/linker/STM32WBA50xx_FLASH.ld          |   7 +-
 .../Device/ST/STM32YYxx_CMSIS_version.md      |   2 +-
 9 files changed, 93 insertions(+), 53 deletions(-)

diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba62xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba62xx.h
index 02efbfa1ea..5c7fc760cf 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba62xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba62xx.h
@@ -3332,7 +3332,7 @@ typedef struct
 
 /******************  Bit definition for DMA_CTR2 register  *******************/
 #define DMA_CTR2_REQSEL_Pos                 (0UL)
-#define DMA_CTR2_REQSEL_Msk                 (0x3FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000003F */
+#define DMA_CTR2_REQSEL_Msk                 (0x7FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000007F */
 #define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
 #define DMA_CTR2_SWREQ_Pos                  (9UL)
 #define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000100 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba63xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba63xx.h
index 36a2d5bdce..3a2607309e 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba63xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba63xx.h
@@ -3101,7 +3101,7 @@ typedef struct
 
 /******************  Bit definition for DMA_CTR2 register  *******************/
 #define DMA_CTR2_REQSEL_Pos                 (0UL)
-#define DMA_CTR2_REQSEL_Msk                 (0x3FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000003F */
+#define DMA_CTR2_REQSEL_Msk                 (0x7FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000007F */
 #define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
 #define DMA_CTR2_SWREQ_Pos                  (9UL)
 #define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000100 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba64xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba64xx.h
index e03650e815..a89e868fd1 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba64xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba64xx.h
@@ -3294,7 +3294,7 @@ typedef struct
 
 /******************  Bit definition for DMA_CTR2 register  *******************/
 #define DMA_CTR2_REQSEL_Pos                 (0UL)
-#define DMA_CTR2_REQSEL_Msk                 (0x3FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000003F */
+#define DMA_CTR2_REQSEL_Msk                 (0x7FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000007F */
 #define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
 #define DMA_CTR2_SWREQ_Pos                  (9UL)
 #define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000100 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba65xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba65xx.h
index f9c2555c93..78710ac2fc 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba65xx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba65xx.h
@@ -3332,7 +3332,7 @@ typedef struct
 
 /******************  Bit definition for DMA_CTR2 register  *******************/
 #define DMA_CTR2_REQSEL_Pos                 (0UL)
-#define DMA_CTR2_REQSEL_Msk                 (0x3FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000003F */
+#define DMA_CTR2_REQSEL_Msk                 (0x7FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000007F */
 #define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
 #define DMA_CTR2_SWREQ_Pos                  (9UL)
 #define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000100 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba6mxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba6mxx.h
index 306a1a285c..2179edae7c 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba6mxx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba6mxx.h
@@ -3332,7 +3332,7 @@ typedef struct
 
 /******************  Bit definition for DMA_CTR2 register  *******************/
 #define DMA_CTR2_REQSEL_Pos                 (0UL)
-#define DMA_CTR2_REQSEL_Msk                 (0x3FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000003F */
+#define DMA_CTR2_REQSEL_Msk                 (0x7FUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x0000007F */
 #define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
 #define DMA_CTR2_SWREQ_Pos                  (9UL)
 #define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000100 */
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h
index 8a2e14c9a7..c404f60473 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h
+++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h
@@ -87,7 +87,7 @@
   * @brief CMSIS Device version number
   */
 #define __STM32WBA_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32WBA_CMSIS_VERSION_SUB1   (0x07U) /*!< [23:16] sub1 version */
+#define __STM32WBA_CMSIS_VERSION_SUB1   (0x08U) /*!< [23:16] sub1 version */
 #define __STM32WBA_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32WBA_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32WBA_CMSIS_VERSION       ((__STM32WBA_CMSIS_VERSION_MAIN << 24U)\
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html
index 165939a6b5..cc310382df 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html
+++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html
@@ -67,9 +67,9 @@ <h1 id="purpose">Purpose</h1>
 <section id="update-history" class="col-sm-12 col-lg-8">
 <h1>Update History</h1>
 <div class="collapse">
-<input type="checkbox" id="collapse-section11" checked aria-hidden="true">
-<label for="collapse-section11" aria-hidden="true"><strong>V1.7.0 /
-23-May-2025</strong></label>
+<input type="checkbox" id="collapse-section12" checked aria-hidden="true">
+<label for="collapse-section12" aria-hidden="true"><strong>V1.8.0 /
+7-October-2025</strong></label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <h3
@@ -82,6 +82,45 @@ <h2 id="contents">Contents</h2>
 Release of <strong>CMSIS devices</strong> drivers supporting
 <strong>STM32WBA5x</strong> and <strong>STM32WBA6x</strong> devices</h3>
 <ul>
+<li>Update CMSIS devices drivers to include latest corrections
+<ul>
+<li>Update DMA request field to cover all possible requests</li>
+<li>For WBA50, map only heap and stack in SRAM1, remaining data in
+SRAM2</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h2 id="known-limitations">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="dependencies">Dependencies</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="notes">Notes</h2>
+<ul>
+<li>None</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section11" aria-hidden="true">
+<label for="collapse-section11" aria-hidden="true"><strong>V1.7.0 /
+23-May-2025</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3
+id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba5x-and-stm32wba6x-devices-1">Official
+Release of <strong>STM32CubeWBA</strong> Firmware package supporting
+<strong>STM32WBA5x</strong> and <strong>STM32WBA6x</strong> devices</h3>
+<h2 id="contents-1">Contents</h2>
+<h3
+id="official-release-of-cmsis-devices-drivers-supporting-stm32wba5x-and-stm32wba6x-devices-1">Official
+Release of <strong>CMSIS devices</strong> drivers supporting
+<strong>STM32WBA5x</strong> and <strong>STM32WBA6x</strong> devices</h3>
+<ul>
 <li>Update CMSIS devices drivers to add STM32WBA6M</li>
 <li>Update CMSIS devices drivers to include latest corrections
 <ul>
@@ -95,15 +134,15 @@ <h2 id="contents">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="known-limitations-1">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies">Dependencies</h2>
+<h2 id="dependencies-1">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes">Notes</h2>
+<h2 id="notes-1">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -114,14 +153,14 @@ <h2 id="notes">Notes</h2>
 <label for="collapse-section10" aria-hidden="true"><strong>V1.6.0 /
 07-February-2025</strong></label>
 <div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
 <h3
-id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba5x-and-stm32wba6x-devices-1">Official
+id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba5x-and-stm32wba6x-devices-2">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA5x</strong> and <strong>STM32WBA6x</strong> devices</h3>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
 <h3
-id="official-release-of-cmsis-devices-drivers-supporting-stm32wba5x-and-stm32wba6x-devices-1">Official
+id="official-release-of-cmsis-devices-drivers-supporting-stm32wba5x-and-stm32wba6x-devices-2">Official
 Release of <strong>CMSIS devices</strong> drivers supporting
 <strong>STM32WBA5x</strong> and <strong>STM32WBA6x</strong> devices</h3>
 <ul>
@@ -134,15 +173,15 @@ <h2 id="contents-1">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-1">Dependencies</h2>
+<h2 id="dependencies-2">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-1">Notes</h2>
+<h2 id="notes-2">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -153,14 +192,14 @@ <h2 id="notes-1">Notes</h2>
 <label for="collapse-section9" aria-hidden="true"><strong>V1.5.0 /
 22-October-2024</strong></label>
 <div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
 <h3
 id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba50xx-stm32wba52xx-stm32wba54xx-stm32wba55xx-and-stm32wba5mxx-devices">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA50xx</strong>, <strong>STM32WBA52xx</strong>,
 <strong>STM32WBA54xx</strong>, <strong>STM32WBA55xx</strong> and
 <strong>STM32WBA5Mxx</strong> devices</h3>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-3">Contents</h2>
 <h3
 id="official-release-of-cmsis-devices-drivers-supporting-stm32wba50xx-stm32wba52xx-stm32wba54xx-stm32wba55xx-and-stm32wba5mxx-devices">Official
 Release of <strong>CMSIS devices</strong> drivers supporting
@@ -180,15 +219,15 @@ <h2 id="contents-2">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="known-limitations-2">Known Limitations</h2>
+<h2 id="known-limitations-3">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-2">Dependencies</h2>
+<h2 id="dependencies-3">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-2">Notes</h2>
+<h2 id="notes-3">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -199,14 +238,14 @@ <h2 id="notes-2">Notes</h2>
 <label for="collapse-section8" aria-hidden="true"><strong>V1.4.0 /
 05-June-2024</strong></label>
 <div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
 <h3
 id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba50xx-stm32wba52xx-stm32wba54xx-and-stm32wba55xx-devices">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA50xx</strong>, <strong>STM32WBA52xx</strong>,
 <strong>STM32WBA54xx</strong> and <strong>STM32WBA55xx</strong>
 devices</h3>
-<h2 id="contents-3">Contents</h2>
+<h2 id="contents-4">Contents</h2>
 <h3
 id="official-release-of-cmsis-devices-drivers-supporting-stm32wba50xx-stm32wba52xx-stm32wba54xx-and-stm32wba55xx-devices">Official
 Release of <strong>CMSIS devices</strong> drivers supporting
@@ -224,15 +263,15 @@ <h2 id="contents-3">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="known-limitations-3">Known Limitations</h2>
+<h2 id="known-limitations-4">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-3">Dependencies</h2>
+<h2 id="dependencies-4">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-3">Notes</h2>
+<h2 id="notes-4">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -243,13 +282,13 @@ <h2 id="notes-3">Notes</h2>
 <label for="collapse-section7" aria-hidden="true"><strong>V1.3.0 /
 07-February-2024</strong></label>
 <div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
 <h3
 id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba52xx-and-stm32wba55xx-devices">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA52xx</strong> and <strong>STM32WBA55xx</strong>
 devices</h3>
-<h2 id="contents-4">Contents</h2>
+<h2 id="contents-5">Contents</h2>
 <h3
 id="official-release-of-cmsis-devices-drivers-supporting-stm32wba52xx-and-stm32wba55xx-devices">Official
 Release of <strong>CMSIS devices</strong> drivers supporting
@@ -267,15 +306,15 @@ <h2 id="contents-4">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="known-limitations-4">Known Limitations</h2>
+<h2 id="known-limitations-5">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-4">Dependencies</h2>
+<h2 id="dependencies-5">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-4">Notes</h2>
+<h2 id="notes-5">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -286,13 +325,13 @@ <h2 id="notes-4">Notes</h2>
 <label for="collapse-section6" aria-hidden="true"><strong>V1.2.0 /
 02-November-2023</strong></label>
 <div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
 <h3
 id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba52xx-and-stm32wba55xx-devices-1">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA52xx</strong> and <strong>STM32WBA55xx</strong>
 devices</h3>
-<h2 id="contents-5">Contents</h2>
+<h2 id="contents-6">Contents</h2>
 <h3
 id="official-release-of-cmsis-devices-drivers-supporting-stm32wba52xx-and-stm32wba55xx-devices-1">Official
 Release of <strong>CMSIS devices</strong> drivers supporting
@@ -312,15 +351,15 @@ <h2 id="contents-5">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="known-limitations-5">Known Limitations</h2>
+<h2 id="known-limitations-6">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-5">Dependencies</h2>
+<h2 id="dependencies-6">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-5">Notes</h2>
+<h2 id="notes-6">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -331,12 +370,12 @@ <h2 id="notes-5">Notes</h2>
 <label for="collapse-section5" aria-hidden="true"><strong>V1.1.0 /
 06-June-2023</strong></label>
 <div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
 <h3
 id="official-release-of-stm32cubewba-firmware-package-supporting-stm32wba52xx-devices">Official
 Release of <strong>STM32CubeWBA</strong> Firmware package supporting
 <strong>STM32WBA52xx</strong> devices</h3>
-<h2 id="contents-6">Contents</h2>
+<h2 id="contents-7">Contents</h2>
 <h3
 id="official-release-of-cmsis-devices-drivers-supporting-stm32wba52xx-devices">Official
 Release of <strong>CMSIS devices</strong> drivers supporting
@@ -349,15 +388,15 @@ <h2 id="contents-6">Contents</h2>
 </ul>
 <p><br />
 </p>
-<h2 id="known-limitations-6">Known Limitations</h2>
+<h2 id="known-limitations-7">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-6">Dependencies</h2>
+<h2 id="dependencies-7">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-6">Notes</h2>
+<h2 id="notes-7">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
@@ -368,27 +407,27 @@ <h2 id="notes-6">Notes</h2>
 <label for="collapse-section4" aria-hidden="true"><strong>V1.0.0 /
 08-February-2023</strong></label>
 <div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
 <h3
 id="first-official-release-of-stm32cubewba-firmware-package-supporting-stm32wba52xx-devices">First
 Official Release of <strong>STM32CubeWBA</strong> Firmware package
 supporting <strong>STM32WBA52xx</strong> devices</h3>
-<h2 id="contents-7">Contents</h2>
+<h2 id="contents-8">Contents</h2>
 <ul>
 <li>First official release of CMSIS devices drivers
 <ul>
 <li>Support of STM32WBA52xx devices</li>
 </ul></li>
 </ul>
-<h2 id="known-limitations-7">Known Limitations</h2>
+<h2 id="known-limitations-8">Known Limitations</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="dependencies-7">Dependencies</h2>
+<h2 id="dependencies-8">Dependencies</h2>
 <ul>
 <li>None</li>
 </ul>
-<h2 id="notes-7">Notes</h2>
+<h2 id="notes-8">Notes</h2>
 <ul>
 <li>None</li>
 </ul>
diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA50xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA50xx_FLASH.ld
index 801082fb8f..d686c6a125 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA50xx_FLASH.ld
+++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA50xx_FLASH.ld
@@ -7,7 +7,7 @@
 **
 **  Abstract    : Linker script for STM32WBA50xx Device from STM32WBA series
 **                      512Kbytes FLASH
-**                      16Kbytes RAM
+**                      16Kbytes + 48Kbytes RAM
 **
 **                Set heap size, stack size and stack location according
 **                to application requirements.
@@ -45,6 +45,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
 MEMORY
 {
   RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 16K
+  SRAM2  (xrw)    : ORIGIN = 0x20010000,   LENGTH = 48K
   FLASH  (rx)     : ORIGIN = 0x08000000,   LENGTH = 512K
 }
 
@@ -146,7 +147,7 @@ SECTIONS
     . = ALIGN(4);
     _edata = .;        /* define a global symbol at data end */
 
-  } >RAM AT> FLASH
+  } >SRAM2 AT> FLASH
 
   /* Uninitialized data section into "RAM" Ram type memory */
   . = ALIGN(4);
@@ -162,7 +163,7 @@ SECTIONS
     . = ALIGN(4);
     _ebss = .;         /* define a global symbol at bss end */
     __bss_end__ = _ebss;
-  } >RAM
+  } >SRAM2
 
   /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
   ._user_heap_stack :
diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
index eb3e7f27b1..2dee36ee2b 100644
--- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
+++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md
@@ -21,7 +21,7 @@
   * STM32U5: 1.4.2
   * STM32WB: 1.12.3
   * STM32WB0: 1.4.0
-  * STM32WBA: 1.7.0
+  * STM32WBA: 1.8.0
   * STM32WL: 1.3.0
   * STM32WL3: 1.2.0
 

From 5618b84b7b01340d81d1024039add083098f3d11 Mon Sep 17 00:00:00 2001
From: Frederic Pillon <frederic.pillon@st.com>
Date: Thu, 27 Nov 2025 10:02:12 +0100
Subject: [PATCH 3/3] system(wba): update STM32WBAx hal default config

Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
---
 system/STM32WBAxx/stm32wbaxx_hal_conf_default.h | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h b/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h
index aa14075a16..e357caff31 100644
--- a/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h
+++ b/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h
@@ -73,7 +73,6 @@ extern "C" {
 #define HAL_UART_MODULE_ENABLED
 #define HAL_USART_MODULE_ENABLED
 #define HAL_WWDG_MODULE_ENABLED
-#define HAL_XSPI_MODULE_ENABLED
 #endif
 
 /* ########################## Oscillator Values adaptation ####################*/
@@ -195,7 +194,6 @@ extern "C" {
 #define  USE_HAL_UART_REGISTER_CALLBACKS       0U /* UART register callback disabled      */
 #define  USE_HAL_USART_REGISTER_CALLBACKS      0U /* USART register callback disabled     */
 #define  USE_HAL_WWDG_REGISTER_CALLBACKS       0U /* WWDG register callback disabled      */
-#define  USE_HAL_XSPI_REGISTER_CALLBACKS       0U /* XSPI register callback disabled      */
 
 /* ################## SPI peripheral configuration ########################## */
 
@@ -353,10 +351,6 @@ extern "C" {
 #include "stm32wbaxx_hal_wwdg.h"
 #endif /* HAL_WWDG_MODULE_ENABLED */
 
-#ifdef HAL_XSPI_MODULE_ENABLED
-#include "stm32wbaxx_hal_xspi.h"
-#endif /* HAL_XSPI_MODULE_ENABLED */
-
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 /**