From 72aedb0041e69600dd3f4bfc80934871060d11ed Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 27 Nov 2025 10:16:52 +0100 Subject: [PATCH 01/10] chore(wl3): update hal patch Signed-off-by: Frederic Pillon --- .../WL3/0001-fix-wl3-HAL-and-LL-warnings.patch | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/CI/update/patch/HAL/WL3/0001-fix-wl3-HAL-and-LL-warnings.patch b/CI/update/patch/HAL/WL3/0001-fix-wl3-HAL-and-LL-warnings.patch index 9c4c0d7601..6df419dbe5 100644 --- a/CI/update/patch/HAL/WL3/0001-fix-wl3-HAL-and-LL-warnings.patch +++ b/CI/update/patch/HAL/WL3/0001-fix-wl3-HAL-and-LL-warnings.patch @@ -1,4 +1,4 @@ -From 6d24d07674b242544e2f24a26dd9785efb178650 Mon Sep 17 00:00:00 2001 +From cf9d51a1f1763f3452c8ce2312b79357ac9766fc Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 23 Sep 2025 14:48:50 +0200 Subject: [PATCH 1/1] fix(wl3): HAL and LL warnings @@ -7,8 +7,7 @@ Signed-off-by: Frederic Pillon --- .../Inc/stm32wl3x_ll_dma.h | 104 ++++++++++++++++++ .../Src/stm32wl3x_hal_flash_ex.c | 2 +- - .../Src/stm32wl3x_ll_adc.c | 2 +- - 3 files changed, 106 insertions(+), 2 deletions(-) + 2 files changed, 105 insertions(+), 1 deletion(-) diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h index b94790b32..e49d7c53f 100644 @@ -859,19 +858,6 @@ index 9cd95caf3..d1b9f3dd0 100644 uint32_t index; /* Check the parameters */ -diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_adc.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_adc.c -index 5455a5343..4a88375ed 100644 ---- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_adc.c -+++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_adc.c -@@ -24,7 +24,7 @@ - #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" - #else --#define assert_param(expr) ((void)0UL) -+#define assert_param(expr) ((void)0U) - #endif /* USE_FULL_ASSERT */ - - /** @addtogroup STM32WL3x_LL_Driver -- 2.34.1 From 19f8e10177a0e3ac5d872002da9aae63823ca39b Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 27 Nov 2025 15:57:08 +0100 Subject: [PATCH 02/10] fix(ci): naming exception WL3 does not have the same naming convention than other series. product_line definition are not the same convention nor case. Signed-off-by: Frederic Pillon --- CI/update/stm32variant.py | 54 +++++++++++++++++++++++++++++++-------- CI/update/stm32wrapper.py | 8 ++++-- 2 files changed, 49 insertions(+), 13 deletions(-) diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index 5cea6cd56f..b33f0c3a76 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -1647,12 +1647,36 @@ def print_variant(generic_list, alt_syswkup_list): def search_product_line(valueline: str, extra: str) -> str: product_line = "" product_line_list = product_line_dict[mcu_family] - if not valueline.startswith("STM32MP1"): + if valueline.startswith("STM32MP1"): + # previous + # Unfortunately, MP1 does not follows the same naming rules + for pline in product_line_dict[mcu_family]: + vline = valueline + product_line = pline + # Remove the 'x' character from pline and + # the one at same index in the vline + while 1: + idx = pline.find("x") + if idx > 0: + pline = pline.replace("x", "", 1) + if "STM32MP15xx" != vline: + vline = vline[:idx] + vline[idx + 1 :] + else: + break + if pline >= vline and pline[:10] == vline[:10]: + break + else: + # In case of CMSIS device does not exist + product_line = "STM32MP15xx" + elif valueline.startswith("STM32WL3"): for idx_pline, pline in enumerate(product_line_list): vline = valueline + # Add an 'x' at the end to match the length + # as startup file contains only one 'x' at the end + # STM32WL3xx -> STM32WL30K8 + # STM32WL3Rx -> STM32WL3RK8 product_line = pline - if vline.startswith("STM32WB0") or vline.startswith("STM32WL3"): - pline = pline + "xx" + pline = pline + "x" # Remove the 'x' character from pline and # the one at same index in the vline while 1: @@ -1662,7 +1686,8 @@ def search_product_line(valueline: str, extra: str) -> str: vline = vline[:idx] + vline[idx + 1 :] else: break - if pline >= vline: + # Exact match or generic name + if pline == vline or product_line == "STM32WL3xx": if ( extra and len(product_line_list) > idx_pline + 1 @@ -1674,27 +1699,34 @@ def search_product_line(valueline: str, extra: str) -> str: else: # In case of CMSIS device does not exist product_line = "" + product_line = product_line.upper() else: - # previous - # Unfortunately, MP1 does not follows the same naming rules - for pline in product_line_dict[mcu_family]: + for idx_pline, pline in enumerate(product_line_list): vline = valueline product_line = pline + if vline.startswith("STM32WB0"): + pline = pline + "xx" # Remove the 'x' character from pline and # the one at same index in the vline while 1: idx = pline.find("x") if idx > 0: pline = pline.replace("x", "", 1) - if "STM32MP15xx" != vline: - vline = vline[:idx] + vline[idx + 1 :] + vline = vline[:idx] + vline[idx + 1 :] else: break - if pline >= vline and pline[:10] == vline[:10]: + if pline >= vline: + if ( + extra + and len(product_line_list) > idx_pline + 1 + and product_line_list[idx_pline + 1] == (product_line + extra) + ): + # Look for the next product line if contains the extra + product_line = product_line_list[idx_pline + 1] break else: # In case of CMSIS device does not exist - product_line = "STM32MP15xx" + product_line = "" return product_line diff --git a/CI/update/stm32wrapper.py b/CI/update/stm32wrapper.py index 7c85db0cb1..b9849c8a3c 100644 --- a/CI/update/stm32wrapper.py +++ b/CI/update/stm32wrapper.py @@ -123,12 +123,16 @@ def printCMSISStartup(log): for fn_list in group_startup_list: if len(fn_list) == 1: valueline = re.split("_|\\.", fn_list[0]) - vline = valueline[1].upper().replace("X", "x") + vline = valueline[1].upper() + if not valueline[1].startswith("stm32wl3"): + vline = vline.replace("X", "x") cmsis_list.append({"vline": vline, "fn": fn_list[0], "cm": ""}) else: for fn in fn_list: valueline = re.split("_|\\.", fn) - vline = valueline[1].upper().replace("X", "x") + vline = valueline[1].upper() + if not valueline[1].startswith("stm32wl3"): + vline = vline.replace("X", "x") cm = valueline[2].upper() cmsis_list.append({"vline": vline, "fn": fn, "cm": cm}) with open(CMSIS_Startupfile, "w", newline="\n") as out_file: From bf96377d83cbab285caef1795afbcbb7f9fcca22 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 27 Nov 2025 16:01:46 +0100 Subject: [PATCH 03/10] system(wl3) update STM32WL3x HAL Drivers to v1.3.0 Included in STM32CubeWL3 FW v1.3.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 15 +- .../STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h | 2 +- .../Inc/stm32wl3x_hal_adc.h | 12 +- .../Inc/stm32wl3x_hal_gpio_ex.h | 2 +- .../Inc/stm32wl3x_hal_i2c_ex.h | 25 +- .../Inc/stm32wl3x_hal_i2s.h | 2 + .../Inc/stm32wl3x_hal_lpawur.h | 4 +- .../Inc/stm32wl3x_hal_mrsubg.h | 405 ++--- .../Inc/stm32wl3x_hal_mrsubg_timer.h | 154 +- .../Inc/stm32wl3x_hal_pwr.h | 331 ++++- .../Inc/stm32wl3x_hal_rcc.h | 20 +- .../Inc/stm32wl3x_hal_smbus_ex.h | 24 +- .../Inc/stm32wl3x_ll_adc.h | 39 +- .../Inc/stm32wl3x_ll_bus.h | 20 +- .../Inc/stm32wl3x_ll_dma.h | 104 -- .../Inc/stm32wl3x_ll_dmamux.h | 5 + .../Inc/stm32wl3x_ll_lcsc.h | 101 +- .../Inc/stm32wl3x_ll_lpawur.h | 5 +- .../Inc/stm32wl3x_ll_mrsubg.h | 1305 ++++++++++------- .../Inc/stm32wl3x_ll_mrsubg_timer.h | 22 +- .../Inc/stm32wl3x_ll_pwr.h | 64 +- .../Inc/stm32wl3x_ll_spi.h | 2 + .../Inc/stm32wl3x_ll_utils.h | 4 +- .../STM32WL3x_HAL_Driver/Release_Notes.html | 147 +- .../Src/stm32wl3x_hal_flash_ex.c | 2 +- .../Src/stm32wl3x_hal_gpio.c | 6 + .../Src/stm32wl3x_hal_i2s.c | 2 + .../Src/stm32wl3x_hal_lpawur.c | 4 +- .../Src/stm32wl3x_hal_mrsubg.c | 1040 ++++++++----- .../Src/stm32wl3x_hal_mrsubg_timer.c | 518 ++++--- .../Src/stm32wl3x_hal_pwr.c | 71 +- .../Src/stm32wl3x_hal_pwr_ex.c | 7 + .../Src/stm32wl3x_hal_rcc_ex.c | 10 +- .../Src/stm32wl3x_hal_timebase_tim_template.c | 5 + .../Src/stm32wl3x_hal_uart.c | 66 +- .../Src/stm32wl3x_ll_i2c.c | 5 +- .../Src/stm32wl3x_ll_pwr.c | 9 + .../Src/stm32wl3x_ll_spi.c | 4 + .../Src/stm32wl3x_ll_utils.c | 4 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 40 files changed, 2781 insertions(+), 1788 deletions(-) diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 7d18636efb..836d610016 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -361,7 +361,10 @@ extern "C" { #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI -#endif +#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) +#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI +#define LL_DMAMUX_REQ_PSSI LL_DMAMUX_REQ_DCMI_PSSI +#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4 */ @@ -564,6 +567,9 @@ extern "C" { #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET #endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ /** * @} @@ -2146,6 +2152,13 @@ extern "C" { #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER +#if defined(STM32H7RS) || defined(STM32N6) +#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0 +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1 +#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig +#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig +#endif /* STM32H7RS || STM32N6 */ + /** * @} */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h index a85484fdfa..a91747987f 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal.h @@ -48,7 +48,7 @@ extern "C" { * @brief HAL Driver version number */ #define __STM32WL3X_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WL3X_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32WL3X_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ #define __STM32WL3X_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WL3X_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WL3X_HAL_VERSION ((__STM32WL3X_HAL_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_adc.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_adc.h index bf1e9e68bb..77aef7cf62 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_adc.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_adc.h @@ -300,10 +300,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ -#define ADC_SAMPLING_AT_START (LL_ADC_SAMPLING_AT_START) /*!< Sampling only at conversion start (default) */ -#define ADC_SAMPLING_AT_END (LL_ADC_SAMPLING_AT_END) /*!< Sampling sampling phase starts after end of - conversion, and stops upon trigger event - (Also known as Bulb sampling mode). */ +#define ADC_SAMPLING_AT_START (LL_ADC_SAMPLING_AT_START) /*!< Sampling phase starts only at conversion start and + sampling time is 125ns regardless of the sampling + period (default). */ +#define ADC_SAMPLING_AT_END (LL_ADC_SAMPLING_AT_END) /*!< Sampling phase starts after end of + conversion, and stops upon trigger event (Also known + as Bulb sampling mode). + Sampling time is a function of the sampling period + (Sample rate). */ /** * @} diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_gpio_ex.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_gpio_ex.h index b3517a8ef2..2584b85655 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_gpio_ex.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_gpio_ex.h @@ -52,7 +52,7 @@ extern "C" { * */ -#if defined(STM32WL3XX) +#if defined(STM32WL3XX) || defined(STM32WL3RX) /** * @brief AF 0 selection */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h index 06c8d452ea..e3ad8763eb 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2c_ex.h @@ -53,6 +53,7 @@ extern "C" { /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus * @{ */ +#if defined (I2C1) || defined (I2C2) #define I2C_FASTMODEPLUS_PA0 SYSCFG_I2C_FMP_CTRL_I2C1_PA0_FMP /*!< Enable Fast Mode Plus on PA0 */ #define I2C_FASTMODEPLUS_PA1 SYSCFG_I2C_FMP_CTRL_I2C1_PA1_FMP /*!< Enable Fast Mode Plus on PA1 */ #define I2C_FASTMODEPLUS_PB6 SYSCFG_I2C_FMP_CTRL_I2C1_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ @@ -63,6 +64,7 @@ extern "C" { #define I2C_FASTMODEPLUS_PA7 SYSCFG_I2C_FMP_CTRL_I2C2_PA7_FMP /*!< Enable Fast Mode Plus on PA7 */ #define I2C_FASTMODEPLUS_PA13 SYSCFG_I2C_FMP_CTRL_I2C2_PA13_FMP /*!< Enable Fast Mode Plus on PA13 */ #define I2C_FASTMODEPLUS_PA14 SYSCFG_I2C_FMP_CTRL_I2C2_PA14_FMP /*!< Enable Fast Mode Plus on PA14 */ +#endif /* I2C1 || I2C2 */ /** * @} */ @@ -126,16 +128,19 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA0)) == I2C_FASTMODEPLUS_PA0) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA1)) == I2C_FASTMODEPLUS_PA1) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB10)) == I2C_FASTMODEPLUS_PB10) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB11)) == I2C_FASTMODEPLUS_PB11) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA6)) == I2C_FASTMODEPLUS_PA6) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA7)) == I2C_FASTMODEPLUS_PA7) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA13)) == I2C_FASTMODEPLUS_PA13) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PA14)) == I2C_FASTMODEPLUS_PA14)) +#if defined(I2C1) || defined(I2C2) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ( \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA0)) == I2C_FASTMODEPLUS_PA0) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA1)) == I2C_FASTMODEPLUS_PA1) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB10)) == I2C_FASTMODEPLUS_PB10) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB11)) == I2C_FASTMODEPLUS_PB11) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA6)) == I2C_FASTMODEPLUS_PA6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA7)) == I2C_FASTMODEPLUS_PA7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA13)) == I2C_FASTMODEPLUS_PA13) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA14)) == I2C_FASTMODEPLUS_PA14)) +#endif /* I2C1 || I2C2 */ + /** * @} */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2s.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2s.h index a46521f3b1..0e7ccecc5e 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2s.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_i2s.h @@ -27,6 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32wl3x_hal_def.h" +#if defined(SPI_I2S_SUPPORT) /** @addtogroup STM32WL3x_HAL_Driver * @{ */ @@ -543,6 +544,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); /** * @} */ +#endif /* SPI_I2S_SUPPORT */ #ifdef __cplusplus } diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_lpawur.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_lpawur.h index 3cb6b2cb9d..9b5426551e 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_lpawur.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_lpawur.h @@ -30,7 +30,7 @@ extern "C" { /** @addtogroup STM32WL3x_HAL_Driver * @{ */ - +#if defined (LPAWUR) /** @addtogroup LPAWUR * @{ */ @@ -179,7 +179,7 @@ void HAL_LPAWUR_MspDeInit(void); /** * @} */ - +#endif /* LPAWUR */ /** * @} */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg.h index 0d5652f46d..ecc12acad2 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2024-2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -16,7 +16,7 @@ ****************************************************************************** */ - /* Define to prevent recursive inclusion -------------------------------------*/ +/* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32WL3x_HAL_MRSUBG_H #define STM32WL3x_HAL_MRSUBG_H @@ -41,6 +41,11 @@ extern "C" { */ #define GAIN_RX_CHAIN 64 +#define CHANNEL_FILTER_THRESHOLD 400000U +#define IF_FREQ_HIGH 600U +#define IF_FREQ_LOW 300U +#define SLOW_CLOCK_FREQ_DEFAULT 32000U + #define WMBUS_PREAMBLE_LEN_S1S2LONGHEADER (uint16_t)279 #define WMBUS_PREAMBLE_LEN_S1MS2T2OTHERTOMETER (uint16_t)15 #define WMBUS_PREAMBLE_LEN_T1T2METERTOOTHER (uint16_t)19 @@ -72,7 +77,7 @@ extern "C" { */ /** - * @brief Send a specific command to the STM32WL3. + * @brief Send a specific command to the STM32WL3x. * @param __CMD_NAME__ code of the command to send. * @retval None. */ @@ -82,12 +87,17 @@ extern "C" { * @brief Sets the RX_MODE for the MRSUBG. * @param __MODE__ the rx mode * This parameter can be any of the following values: - * @arg @ref RX_NORMAL Only payload is stored into the RAM buffers. CRC and packet length are readable in dedicated status registers - * @arg @ref RX_DIRECT_BUFFERS Full bit stream is stored into the RAM buffers. - * @arg @ref RX_DIRECT_GPIO Full bit stream is provided serially through the RX DATA GPIO. - * @arg @ref RX_IQ_SAMPLING Raw I/Q sampling taken at the output of the Channel filter inside the demodulator are stored in RAM. - * @arg @ref RX_FREQDETEC_SAMPLING Raw data taken at the output of the frequency detector inside the demodulator (detection of the instantaneous frequency changes) are stored in RAM. - * @arg @ref RX_SOFTBIT_SAMPLING Raw data taken at the output of the post-filter inside the demodulator (soft bits before the 0/1 detection) are stored in RAM. + * @arg @ref RX_NORMAL Only payload is stored into the RAM buffers. CRC and packet length + * are readable in dedicated status registers + * @arg @ref RX_DIRECT_BUFFERS Full bit stream is stored into the RAM buffers. + * @arg @ref RX_DIRECT_GPIO Full bit stream is provided serially through the RX DATA GPIO. + * @arg @ref RX_IQ_SAMPLING Raw I/Q sampling taken at the output of the Channel filter inside + * the demodulator are stored in RAM. + * @arg @ref RX_FREQDETEC_SAMPLING Raw data taken at the output of the frequency detector inside + * the demodulator (detection of the instantaneous frequency changes) + * are stored in RAM. + * @arg @ref RX_SOFTBIT_SAMPLING Raw data taken at the output of the post-filter inside the + * demodulator (soft bits before the 0/1 detection) are stored in RAM. * @retval None. */ #define __HAL_MRSUBG_SET_RX_MODE(__MODE__) LL_MRSubG_SetRXMode(__MODE__) @@ -96,10 +106,13 @@ extern "C" { * @brief Sets the TX_MODE for the MRSUBG. * @param __MODE__ the tx mode * This parameter can be any of the following values: - * @arg @ref TX_NORMAL Only payload is provided through RAM buffers Rest of the frame built from configuration registers (PREAMBLE, SYNC, CRC...). - * @arg @ref TX_DIRECT_BUFFERS Full bit stream (including PREAMBLE, SYNC, CRC...) to be provided through RAM buffers. - * @arg @ref TX_DIRECT_GPIO Full bit stream (including PREAMBLE, SYNC, CRC...) to be provided serially through the TX DATA GPIO. - * @arg @ref TX_PN Internal PN generator send a polynomial bit stream on the antenna. + * @arg @ref TX_NORMAL Only payload is provided through RAM buffers. Rest of the frame + * built from configuration registers (PREAMBLE, SYNC, CRC...). + * @arg @ref TX_DIRECT_BUFFERS Full bit stream (including PREAMBLE, SYNC, CRC...) to be provided + * through RAM buffers. + * @arg @ref TX_DIRECT_GPIO Full bit stream (including PREAMBLE, SYNC, CRC...) to be provided + * serially through the TX DATA GPIO. + * @arg @ref TX_PN Internal PN generator sends a polynomial bit stream on the antenna. * @retval None. */ #define __HAL_MRSUBG_SET_TX_MODE(__MODE__) LL_MRSubG_SetTXMode(__MODE__) @@ -129,132 +142,158 @@ extern "C" { * @param __SIZE__ the size of the data buffer. * @retval None. */ -#define __HAL_MRSUBG_SET_DATABUFFER_SIZE(__SIZE__) MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->DATABUFFER_SIZE, MR_SUBG_GLOB_STATIC_DATABUFFER_SIZE_DATABUFFER_SIZE, __SIZE__) +#define __HAL_MRSUBG_SET_DATABUFFER_SIZE(__SIZE__) \ + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->DATABUFFER_SIZE, MR_SUBG_GLOB_STATIC_DATABUFFER_SIZE_DATABUFFER_SIZE, __SIZE__) /** - * @brief Get the size of the data buffer. - * @retval The size of the data buffer. - */ + * @brief Get the size of the data buffer. + * @retval The size of the data buffer. + */ #define __HAL_MRSUBG_GET_DATABUFFER_SIZE() READ_REG(MR_SUBG_GLOB_STATIC->DATABUFFER_SIZE) /** - * @brief Get the number of bytes used in the last used DATA BUFFER. - * @retval The number of bytes used in the last used DATA BUFFER. - */ -#define __HAL_MRSUBG_GET_DATABUFFER_COUNT() READ_REG_FIELD(MR_SUBG_GLOB_STATUS->DATABUFFER_INFO, MR_SUBG_GLOB_STATUS_DATABUFFER_INFO_CURRENT_DATABUFFER_COUNT); + * @brief Get the number of bytes used in the last used DATA BUFFER. + * @retval The number of bytes used in the last used DATA BUFFER. + */ +#define __HAL_MRSUBG_GET_DATABUFFER_COUNT() \ + READ_REG_FIELD(MR_SUBG_GLOB_STATUS->DATABUFFER_INFO, MR_SUBG_GLOB_STATUS_DATABUFFER_INFO_CURRENT_DATABUFFER_COUNT) /** - * @brief Set the pointer for data buffer 0. - * @param __ARG__ Pointer to be set for data buffer 0. - * @retval None. - */ + * @brief Set the pointer for data buffer 0. + * @param __ARG__ Pointer to be set for data buffer 0. + * @retval None. + */ #define __HAL_MRSUBG_SET_DATABUFFER0_POINTER(__ARG__) WRITE_REG(MR_SUBG_GLOB_STATIC->DATABUFFER0_PTR, __ARG__) /** - * @brief Set the pointer for data buffer 1. - * @param __ARG__ Pointer to be set for data buffer 1. - * @retval None. - */ + * @brief Set the pointer for data buffer 1. + * @param __ARG__ Pointer to be set for data buffer 1. + * @retval None. + */ #define __HAL_MRSUBG_SET_DATABUFFER1_POINTER(__ARG__) WRITE_REG(MR_SUBG_GLOB_STATIC->DATABUFFER1_PTR, __ARG__) /** - * @brief Get the RX indicator status. - * @retval The RX indicator status. - */ + * @brief Get the RX indicator status. + * @retval The RX indicator status. + */ #define __HAL_MRSUBG_GET_RX_INDICATOR() READ_REG(MR_SUBG_GLOB_STATUS->RX_INDICATOR) /** - * @brief Enable RF sequence IRQ with a given flag. - * @param __FLAG__ Flag to enable RF sequence IRQ. - * @retval None. - */ + * @brief Enable RF sequence IRQ with a given flag. + * @param __FLAG__ Flag to enable RF sequence IRQ. + * @retval None. + */ #define __HAL_MRSUBG_SET_RFSEQ_IRQ_ENABLE(__FLAG__) WRITE_REG(MR_SUBG_GLOB_DYNAMIC->RFSEQ_IRQ_ENABLE, __FLAG__) /** - * @brief Get the RF sequence IRQ status. - * @retval The RF sequence IRQ status. - */ + * @brief Get the RF sequence IRQ status. + * @retval The RF sequence IRQ status. + */ #define __HAL_MRSUBG_GET_RFSEQ_IRQ_STATUS() READ_REG(MR_SUBG_GLOB_STATUS->RFSEQ_IRQ_STATUS) /** - * @brief Clear the RF sequence IRQ flag with a given flag. - * @param __FLAG__ Flag to clear RF sequence IRQ. - * @retval None. - */ + * @brief Clear the RF sequence IRQ flag with a given flag. + * @param __FLAG__ Flag to clear RF sequence IRQ. + * @retval None. + */ #define __HAL_MRSUBG_CLEAR_RFSEQ_IRQ_FLAG(__FLAG__) WRITE_REG(MR_SUBG_GLOB_STATUS->RFSEQ_IRQ_STATUS, __FLAG__) /** - * @brief Get detailed RF sequence status. - * @retval The detailed RF sequence status. - */ + * @brief Get detailed RF sequence status. + * @retval The detailed RF sequence status. + */ #define __HAL_MRSUBG_GET_RFSEQ_STATUS_DETAIL() READ_REG(MR_SUBG_GLOB_STATUS->RFSEQ_STATUS_DETAIL) /** - * @brief Set detailed RF sequence status with a given argument. - * @param __ARG__ Argument to set detailed RF sequence status. - * @retval None. - */ + * @brief Set detailed RF sequence status with a given argument. + * @param __ARG__ Argument to set detailed RF sequence status. + * @retval None. + */ #define __HAL_MRSUBG_SET_RFSEQ_STATUS_DETAIL(__ARG__) WRITE_REG(MR_SUBG_GLOB_STATUS->RFSEQ_STATUS_DETAIL, __ARG__) /** - * @brief Set the RX timeout with a given timeout value. - * @param __TIMEOUT__ Timeout value to set for RX. - * @retval None. - */ -#define __HAL_MRSUBG_SET_RX_TIMEOUT(__TIMEOUT__) MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_TIMEOUT, __TIMEOUT__) + * @brief Set the RX timeout with a given timeout value. + * @param __TIMEOUT__ Timeout value to set for RX. + * @retval None. + */ +#define __HAL_MRSUBG_SET_RX_TIMEOUT(__TIMEOUT__) \ + MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_TIMEOUT, __TIMEOUT__) /** - * @brief Set the fast RX timeout with a given timeout value. - * @param __TIMEOUT__ Timeout value to set for fast RX. - * @retval None. - */ -#define __HAL_MRSUBG_SET_FAST_RX_TIMEOUT(__TIMEOUT__) MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->FAST_RX_TIMER, MR_SUBG_GLOB_DYNAMIC_FAST_RX_TIMER_FAST_RX_TIMEOUT, __TIMEOUT__) + * @brief Set the fast RX timeout with a given timeout value. + * @param __TIMEOUT__ Timeout value to set for fast RX. + * @retval None. + */ +#define __HAL_MRSUBG_SET_FAST_RX_TIMEOUT(__TIMEOUT__) \ + MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->FAST_RX_TIMER, MR_SUBG_GLOB_DYNAMIC_FAST_RX_TIMER_FAST_RX_TIMEOUT, __TIMEOUT__) /** - * @brief Set the wakeup offset with a given offset value. - * @param __OFFSET__ Offset value to set for wakeup. - * @retval None. - */ -#define __HAL_MRSUBG_SET_WAKEUP_OFFSET(__OFFSET__) MODIFY_REG_FIELD(MR_SUBG_GLOB_RETAINED->WAKEUP_CTRL, MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_SOC_WAKEUP_OFFSET, __OFFSET__) + * @brief Set the wakeup offset with a given offset value. + * @param __OFFSET__ Offset value to set for wakeup. + * @retval None. + */ +#define __HAL_MRSUBG_SET_WAKEUP_OFFSET(__OFFSET__) \ + MODIFY_REG_FIELD(MR_SUBG_GLOB_RETAINED->WAKEUP_CTRL, MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_SOC_WAKEUP_OFFSET, __OFFSET__) /** - * @brief Enable CS blanking. - * @retval None. - */ -#define __HAL_MRSUBG_SET_CS_BLANKING() SET_BIT(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_AS_CS_BLANKING) + * @brief Enable CS blanking. + * @retval None. + */ +#define __HAL_MRSUBG_SET_CS_BLANKING() \ + SET_BIT(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_AS_CS_BLANKING) /** - * @brief Clear CS blanking. - * @retval None. - */ -#define __HAL_MRSUBG_CLEAR_CS_BLANKING() CLEAR_BIT(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_AS_CS_BLANKING) + * @brief Clear CS blanking. + * @retval None. + */ +#define __HAL_MRSUBG_CLEAR_CS_BLANKING() \ + CLEAR_BIT(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_AS_CS_BLANKING) /** - * @brief Set the PQI threshold with a given threshold value. - * @param __THRVAL__ The threshold level. - * @retval None. - */ -#define __HAL_MRSUBG_SET_PQI_THRESHOLD(__THRVAL__) MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_PQI_THR, __THRVAL__) + * @brief Set the PQI threshold with a given threshold value. + * @param __THRVAL__ The threshold level. + * @retval None. + */ +#define __HAL_MRSUBG_SET_PQI_THRESHOLD(__THRVAL__) \ + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_PQI_THR, __THRVAL__) /** - * @brief Enable WMBUS and SQI mask. - * @retval None. - */ -#define __HAL_MRSUBG_WMBUS_ENABLE_AND_SQI_MASK() {CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_nAND_SELECT); SET_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_SQI_TIMEOUT_MASK);} + * @brief Set the SQI threshold with a given threshold value. + * @param __THRVAL__ Threshold value of type @ref SQI_Threshold. + * @retval None + */ +#define __HAL_MRSUBG_SET_SQI_THRESHOLD(__THRVAL__) LL_MRSubG_SetSQIThreshold(__THRVAL__) /** - * @brief Get the IF offset digital value. - * @retval The IF offset digital value. - */ -#define __HAL_MRSUBG_GET_IF_OFFSET_DIG() READ_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_DIG) + * @brief Get the SQI threshold value. + * @retval Threshold value of type @ref SQI_Threshold. + */ +#define __HAL_MRSUBG_GET_SQI_THRESHOLD() LL_MRSubG_GetSQIThreshold() + +/** + * @brief Enable WMBUS and SQI mask. + * @retval None. + */ +#define __HAL_MRSUBG_WMBUS_ENABLE_AND_SQI_MASK() \ + { \ + CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_nAND_SELECT); \ + SET_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_SQI_TIMEOUT_MASK); \ + } /** -* @brief Get the RSSI level in dBm. -* @retval The RSSI level to convert. -*/ + * @brief Get the IF offset digital value. + * @retval The IF offset digital value. + */ +#define __HAL_MRSUBG_GET_IF_OFFSET_DIG() \ + READ_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_DIG) + +/** + * @brief Get the RSSI level in dBm. + * @retval The RSSI level to convert. + */ #define __HAL_MRSUBG_CONVERT_RSSI_TO_DBM(__VALUE__) (__VALUE__/2)-(96+GAIN_RX_CHAIN) - /** +/** * @} */ @@ -264,63 +303,71 @@ extern "C" { */ /** - * @brief STM32WL3 Modulation enumeration - */ -typedef enum { + * @brief STM32WL3x Modulation enumeration + */ +typedef enum +{ MOD_2FSK = 0x00, /*!< 2-FSK modulation selected */ MOD_4FSK = 0x01, /*!< 4-FSK modulation selected */ MOD_2GFSK05 = 0x12, /*!< 2GFSK modulation selected with BT = 0.5 */ MOD_2GFSK1 = 0x02, /*!< 2GFSK modulation selected with BT = 1 */ - MOD_4GFSK05 = 0x13, /*!< 4GFSK modulation selected with BT = 0.5 */ - MOD_4GFSK1 = 0x03, /*!< 4GFSK modulation selected with BT = 1 */ - MOD_ASK = 0x05, /*!< ASK modulation selected. */ - MOD_OOK = 0x05, /*!< OOK modulation selected. */ + MOD_4GFSK05 = 0x13, /*!< 4GFSK modulation selected with BT = 0.5 */ + MOD_4GFSK1 = 0x03, /*!< 4GFSK modulation selected with BT = 1 */ + MOD_ASK = 0x05, /*!< ASK modulation selected. */ + MOD_OOK = 0x05, /*!< OOK modulation selected. */ MOD_POLAR = 0x06, /*!< Polar modulation selected. */ MOD_CW = 0x07, /*!< CW modulation selected */ } MRSubGModSelect; /** - * @brief STM32WL3 selection of the PRBS polynomial - */ -typedef enum{ + * @brief STM32WL3x selection of the PRBS polynomial + */ +typedef enum +{ PN9 = 0x00, /* x^9 +x^5 + 1 with the initial state equal to 0x1FF. */ PN15 = 0x01, /* x^15 +x^14 + 1 with the initial state equal to 0x7FFF. */ } MRSubG_PN_SEL; /** - * @brief STM32WL3 Time Capture selection trigger - */ -typedef enum{ - TC_SEL_DISABLE = 0x00, /* The feature is disabled, no time capture will occur. */ - TC_SEL_END_OF_TX = 0x01, /* The interpolated absolute time is latched on end of transmission information. */ - TC_SEL_END_OF_RX = 0x02, /* The interpolated absolute time is latched on end of reception information whatever the CRC result (RX OK or CRC error). */ - TC_SEL_SYNC_DETECT = 0x03, /* The interpolated absolute time is latched on the SYNC word detection event. */ + * @brief STM32WL3x Time Capture selection trigger + */ +typedef enum +{ + TC_SEL_DISABLE = 0x00, /*!< The feature is disabled, no time capture will occur. */ + TC_SEL_END_OF_TX = 0x01, /*!< The interpolated absolute time is latched on end of transmission information. */ + TC_SEL_END_OF_RX = 0x02, /*!< The interpolated absolute time is latched on end of reception information + whatever the CRC result (RX OK or CRC error). */ + TC_SEL_SYNC_DETECT = 0x03, /*!< The interpolated absolute time is latched on the SYNC word detection event. */ } MRSubG_TimeCaptureSel; /** - * @brief STM32WL3 AFC reinitialization option to improve the AFC behavior on frames with PREAMBLE smaller than 64 bits - */ -typedef enum{ - AFC_REINIT_NONE = 0x00, /* No reinitialization allowed. */ - AFC_REINIT_RSSI = 0x01, /* Reinitialization based on RSSI ramping. */ - AFC_REINIT_FDEV = 0x02, /* Reinitialization based on abnormal Fdev. */ - AFC_REINIT_RSSI_FDEV = 0x03, /* Reinitialization based on both RSSI and abnormal Fdev. <- DEFAULT */ + * @brief STM32WL3x AFC reinitialization option to improve the AFC behavior on frames + * with PREAMBLE smaller than 64 bits + */ +typedef enum +{ + AFC_REINIT_NONE = 0x00, /*!< No reinitialization allowed. */ + AFC_REINIT_RSSI = 0x01, /*!< Reinitialization based on RSSI ramping. */ + AFC_REINIT_FDEV = 0x02, /*!< Reinitialization based on abnormal Fdev. */ + AFC_REINIT_RSSI_FDEV = 0x03, /*!< Reinitialization based on both RSSI and abnormal Fdev. <- DEFAULT */ } MRSubG_AFCReinit; /** - * @brief STM32WL3 Basic Packet Init structure definition. - */ -typedef enum { - PKT_BASIC = 0, - PKT_802_15_4 = 1 + * @brief STM32WL3x Basic Packet Init structure definition. + */ +typedef enum +{ + PKT_BASIC = 0, + PKT_802_15_4 = 1 } MRSubG_PcktType; /** - * @brief WMbus submode enumeration. - */ -typedef enum { + * @brief WMbus submode enumeration. + */ +typedef enum +{ WMBUS_SUBMODE_NOT_CONFIGURED = 0, /*!< WMBUS submode S1, S2 (long header) - Header length = WMBUS_prmbl_ctrl + 279 (in "01" bit pairs) , Sync word = 0x7696 (length 18 bits) */ WMBUS_SUBMODE_S1_S2_LONG_HEADER, /*!< WMBUS submode S1, S2 (long header) - Header length = WMBUS_prmbl_ctrl + 279 (in "01" bit pairs) , Sync word = 0x7696 (length 18 bits) */ WMBUS_SUBMODE_S1_M_S2_T2_OTHER_TO_METER, /*!< WMBUS submode S1-m, S2, T2 (other to meter) - Header length = WMBUS_prmbl_ctrl + 15 (in "01" bit pairs) , Sync word = 0x7696 (length 18 bits)*/ @@ -329,9 +376,10 @@ typedef enum { } WMbusSubmode; /** - * @brief STM32WL3 MRSUBG Radio Config structure definition - */ -typedef struct { + * @brief STM32WL3x MRSUBG Radio Config structure definition + */ +typedef struct +{ uint32_t lFrequencyBase; /*!< Specifies the base carrier frequency (in Hz) */ MRSubGModSelect xModulationSelect; /*!< Specifies the modulation @ref MRSubGModSelect */ uint32_t lDatarate; /*!< Specifies the datarate expressed in sps.*/ @@ -340,59 +388,64 @@ typedef struct { uint8_t dsssExp; /*!< Specifies the DSSS spreading exponent. Use 0 to disable DSSS. */ int8_t outputPower; /*!< PA value to write expressed in dBm. */ MRSubG_PA_DRVMode PADrvMode; /*!< PA drive mode. */ -} SMRSubGConfig; +} SMRSubGConfig_t; /** - * @brief STM32WL3 MRSUBG RF version structure definition - */ -typedef struct { + * @brief STM32WL3x MRSUBG RF version structure definition + */ +typedef struct +{ uint8_t revision; /*!< Revision of the RFIP (to be used for metal fixes)*/ uint8_t version; /*!< Version of the RFIP (to be used for cut upgrades)*/ uint8_t product; /*!< Used for major upgrades (new protocols support / new features)*/ -} SMRSubGVersion; - -/** - * @brief STM32WL3 Basic Packet Init structure definition. - */ -typedef struct { - uint16_t PreambleLength; /*!< Set the preamble length of packet in pairs of bits (0 to 2046) */ - uint16_t PostambleLength; /*!< Set the postable length of packet. The number of POSTAMBLE pairs of bits can be set from 0 to 63. */ - uint8_t SyncLength; /*!< Set the sync word length of packet in bits. From 1 to 64 bits. */ - uint32_t SyncWord; /*!< Set the sync words in MSB. */ - MRSubG_LengthMode FixVarLength; /*!< Enable the variable length mode. */ - MRSubG_PreambleSeq PreambleSequence; /*!< Select the PREAMBLE pattern to be applied. */ - MRSubG_PostambleSeq PostambleSequence; /*!< Packet postamble control: postamble bit sequence selection. */ - MRSubG_PcktCrcMode CrcMode; /*!< Set the CRC type. @ref MRSubG_PcktCrcMode */ - MRSubG_PcktCoding Coding; /*!< Enable the FEC/Viterbi. */ - FunctionalState DataWhitening; /*!< Enable the data whitening. */ - MRSubG_LenWidthhMode LengthWidth; /*!< Set the length width. this bit field is considered/relevant only if FIX_VAR_LEN=1 */ - FunctionalState SyncPresent; /*!< ndicate if a SYNC word is present on the frame or not (null length) */ -} MRSubG_PcktBasicFields; - -/** - * @brief STM32WL3 WMBUS Packet Init structure definition. - */ -typedef struct { +} SMRSubGVersion_t; + +/** + * @brief STM32WL3x Basic Packet Init structure definition. + */ +typedef struct +{ + uint16_t PreambleLength; /*!< Set the preamble length of packet in pairs of bits (0 to 2046) */ + uint16_t PostambleLength; /*!< Set the postable length of packet. The number of POSTAMBLE pairs of bits can be set from 0 to 63. */ + uint8_t SyncLength; /*!< Set the sync word length of packet in bits. From 1 to 64 bits. */ + uint32_t SyncWord; /*!< Set the sync words in MSB. */ + MRSubG_LengthMode FixVarLength; /*!< Enable the variable length mode. */ + MRSubG_PreambleSeq PreambleSequence; /*!< Select the PREAMBLE pattern to be applied. */ + MRSubG_PostambleSeq PostambleSequence; /*!< Packet postamble control: postamble bit sequence selection. */ + MRSubG_PcktCrcMode CrcMode; /*!< Set the CRC type. @ref MRSubG_PcktCrcMode */ + MRSubG_PcktCoding Coding; /*!< Enable the FEC/Viterbi. */ + FunctionalState DataWhitening; /*!< Enable the data whitening. */ + MRSubG_LenWidthhMode LengthWidth; /*!< Set the length width. this bit field is considered/relevant only if FIX_VAR_LEN=1 */ + FunctionalState SyncPresent; /*!< ndicate if a SYNC word is present on the frame or not (null length) */ +} MRSubG_PcktBasicFields_t; + +/** + * @brief STM32WL3x WMBUS Packet Init structure definition. + */ +typedef struct +{ WMbusSubmode xWMbusSubmode; /*!< Set the WMBUS submode. @ref WMbusSubmode */ uint16_t PreambleLength; /*!< Set the preamble length of packet. From 1 to 2046 bit. */ - uint16_t PostambleLength; /*!< Set the postable length of packet. From 1 to 126 bit. */ -} MRSubG_WMBUS_PcktFields; + uint16_t PostambleLength; /*!< Set the postable length of packet. From 1 to 126 bit. */ +} MRSubG_WMBUS_PcktFields_t; /** - * @brief STM32WL3 802.15.4 FEC encoding types. - */ -typedef enum { - FEC_15_4_G_NONE = 0, - FEC_15_4_G_NRNSC = 1, - FEC_15_4_G_RSC = 2, - FEC_15_4_G_RSC_Interleaving = 3 + * @brief STM32WL3x 802.15.4 FEC encoding types. + */ +typedef enum +{ + FEC_15_4_G_NONE = 0, + FEC_15_4_G_NRNSC = 1, + FEC_15_4_G_RSC = 2, + FEC_15_4_G_RSC_Interleaving = 3 } MRSubG_FEC15_4gType; /** - * @brief STM32WL3 802.15.4 Packet Init structure definition. - */ -typedef struct { + * @brief STM32WL3x 802.15.4 Packet Init structure definition. + */ +typedef struct +{ MRSubGModSelect Modulation; /*!< Enumerated value as follow: - 0: MOD_2FSK - 1: MOD_4FSK */ @@ -403,9 +456,9 @@ typedef struct { - 0: FCS_32BIT CRC mode5 - 1: FCS_16BIT CRC mode3 */ FunctionalState Whitening; /*!< Enable the data whitening. */ - MRSubG_FEC15_4gType FecType; /*!< FEC type for 802.15.4g */ - uint16_t FrameLength; /*!< size of payload + FCS, in bytes */ -} MRSubG_802_15_4_PcktFields; + MRSubG_FEC15_4gType FecType; /*!< FEC type for 802.15.4g */ + uint16_t FrameLength; /*!< size of payload + FCS, in bytes */ +} MRSubG_802_15_4_PcktFields_t; /** @@ -427,9 +480,9 @@ void HAL_MRSubG_BUSY_IRQHandler(void); void HAL_MRSubG_TX_RX_SEQUENCE_IRQHandler(void); void HAL_MRSubG_WKUP_IRQHandler(void); -SMRSubGVersion HAL_MRSubGGetVersion(void); -uint8_t HAL_MRSubG_Init(SMRSubGConfig* pxSRadioInitStruct); -void HAL_MRSubG_GetInfo(SMRSubGConfig* pxSRadioInitStruct); +SMRSubGVersion_t HAL_MRSubGGetVersion(void); +uint8_t HAL_MRSubG_Init(SMRSubGConfig_t *pxSRadioInitStruct); +void HAL_MRSubG_GetInfo(SMRSubGConfig_t *pxSRadioInitStruct); void HAL_MRSubG_SetFrequencyBase(uint32_t lFBase); uint32_t HAL_MRSubG_GetFrequencyBase(void); void HAL_MRSubG_SetDatarate(uint32_t lDatarate); @@ -449,12 +502,12 @@ uint32_t HAL_MRSubG_GetBytesOfTransaction(void); uint32_t HAL_MRSubG_Sequencer_Microseconds(uint32_t microseconds); uint32_t HAL_MRSubG_Sequencer_Milliseconds(uint32_t milliseconds); uint32_t HAL_MRSubG_Sequencer_Seconds(uint32_t seconds); -ErrorStatus HAL_MRSubG_Sequencer_ApplyStaticConfig(MRSubG_Sequencer_GlobalConfiguration *cfg); -ErrorStatus HAL_MRSubG_Sequencer_ApplyDynamicConfig(MRSubG_Sequencer_ActionConfiguration *cfg, MRSubGCmd cmd); +ErrorStatus HAL_MRSubG_Sequencer_ApplyStaticConfig(MRSubG_Sequencer_GlobalConfiguration_t *cfg); +ErrorStatus HAL_MRSubG_Sequencer_ApplyDynamicConfig(MRSubG_Sequencer_ActionConfiguration_t *cfg, MRSubGCmd cmd); void HAL_MRSubG_PktBasicSetPayloadLength(uint16_t nPayloadLength); -void HAL_MRSubG_PacketBasicInit(MRSubG_PcktBasicFields* pxPktBasicInit); -void HAL_MRSubG_WMBus_PacketInit(MRSubG_WMBUS_PcktFields* pxPktWMbusInit); -void HAL_MRSubG_802_15_4_PacketInit(MRSubG_802_15_4_PcktFields* px802_15_4PktInit); +void HAL_MRSubG_PacketBasicInit(MRSubG_PcktBasicFields_t *pxPktBasicInit); +void HAL_MRSubG_WMBus_PacketInit(MRSubG_WMBUS_PcktFields_t *pxPktWMbusInit); +void HAL_MRSubG_802_15_4_PacketInit(MRSubG_802_15_4_PcktFields_t *px802_15_4PktInit); /** * @} diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg_timer.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg_timer.h index 00240651ff..b34fb5db33 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg_timer.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_mrsubg_timer.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2024-2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -47,12 +47,13 @@ extern "C" { /** * @brief MRSUBG TIMER Init Structure definition */ -typedef struct { +typedef struct +{ uint32_t HSE_XTAL_freq; /*!< HSE XTAL frequency */ uint16_t XTAL_StartupTime; /*!< XTAL startup in us unit */ BOOL enableInitialCalibration; /*!< Enable initial estimation of the frequency of the - * Low Speed Oscillator, otherwise it will be assumed - * fixed at 32.768 kHz. */ + * Low Speed Oscillator, otherwise it will be assumed + * fixed at 32.768 kHz. */ uint32_t periodicCalibrationInterval; /*!< Periodic calibration interval in ms, to disable set to 0 */ } MRSUBG_TIMER_InitTypeDef; @@ -64,18 +65,20 @@ typedef void (*VTIMER_CallbackType)(void *); /** * @brief VIRTUAL TIMER handle Structure definition */ -typedef struct VTIMER_HandleTypeS { - uint64_t expiryTime; /*!< Managed internally when the timer is started */ - VTIMER_CallbackType callback; /*!< Pointer to the user callback */ - BOOL active; /*!< Managed internally when the timer is started */ - struct VTIMER_HandleTypeS *next; /*!< Managed internally when the timer is started */ - void *userData; /*!< Pointer to user data */ -} VTIMER_HandleType; +typedef struct VTIMER_HandleTypeS +{ + uint64_t expiryTime; /*!< Managed internally when the timer is started */ + VTIMER_CallbackType callback; /*!< Pointer to the user callback */ + BOOL active; /*!< Managed internally when the timer is started */ + struct VTIMER_HandleTypeS *next; /*!< Managed internally when the timer is started */ + void *userData; /*!< Pointer to user data */ +} VTIMER_HandleType_t; /** * @brief MRSUBG TIMER status enumeration definition */ -typedef enum { +typedef enum +{ MRSUBG_TIMER_OFF = 0, MRSUBG_TIMER_PENDING = 1, } MRSUBG_TIMER_Status; @@ -96,6 +99,9 @@ typedef enum { * @brief MRSUBG TIMER Status */ #define WAKEUP_MRSUBG_TIMER_BUSY (0x01U) + +#define TIME_MAX_VALUE 255 + /** * @} */ @@ -117,19 +123,19 @@ void HAL_MRSUBG_TIMER_CPU_WKUP_IRQHandler(void); */ /** - * @brief Initialize the MRSUBG timer module. It must be placed in the initialization - * section of the application. - * @param MRSUBG_TIMER_InitStruct MRSUBG Timer Initialization parameters - * @retval None - */ - void HAL_MRSUBG_TIMER_Init(MRSUBG_TIMER_InitTypeDef *MRSUBG_TIMER_InitStruct); + * @brief Initialize the MRSUBG timer module. It must be placed in the initialization + * section of the application. + * @param MRSUBG_TIMER_InitStruct MRSUBG Timer Initialization parameters + * @retval None + */ +void HAL_MRSUBG_TIMER_Init(MRSUBG_TIMER_InitTypeDef *MRSUBG_TIMER_InitStruct); /** - * @brief Timer module state machine. Check and schedule the calibration. - * Check expired timers and execute user callback. - * It must be placed inside the infinite loop. - * @retval None - */ + * @brief Timer module state machine. Check and schedule the calibration. + * Check expired timers and execute user callback. + * It must be placed inside the infinite loop. + * @retval None + */ void HAL_MRSUBG_TIMER_Tick(void); /** @@ -141,17 +147,17 @@ void HAL_MRSUBG_TIMER_Tick(void); */ /** - * @brief Return the status of the RFIP Wakeup timer and the last value programmed in the register. - * @param time: return the RFIP Wakeup time. - * @retval 0 if no timer has been programmed. - * @retval 1 if RFIP Wakeup Timer has been programmed. - */ + * @brief Return the status of the RFIP Wakeup timer and the last value programmed in the register. + * @param time: return the RFIP Wakeup time. + * @retval 0 if no timer has been programmed. + * @retval 1 if RFIP Wakeup Timer has been programmed. + */ uint8_t HAL_MRSUBG_TIMER_GetRadioTimerValue(uint32_t *time); /** - * @brief Returns the admitted low power mode according to the next timer activity. - * @return Low Power mode - */ + * @brief Returns the admitted low power mode according to the next timer activity. + * @return Low Power mode + */ PowerSaveLevels HAL_MRSUBG_TIMER_PowerSaveLevelCheck(void); /** @@ -163,25 +169,25 @@ PowerSaveLevels HAL_MRSUBG_TIMER_PowerSaveLevelCheck(void); */ /** - * @brief Translates time in microseconds into machine time units. - * @param time: Microseconds to be converted in MTU - * @return Machine time value - */ + * @brief Translates time in microseconds into machine time units. + * @param time: Microseconds to be converted in MTU + * @return Machine time value + */ uint64_t HAL_MRSUBG_TIMER_UsToMachinetime(uint64_t time); /** - * @brief Translates time machine time in microseconds. - * @param time: Machine time to be converted in microseconds - * @return Time value in microseconds - */ + * @brief Translates time machine time in microseconds. + * @param time: Machine time to be converted in microseconds + * @return Time value in microseconds + */ uint64_t HAL_MRSUBG_TIMER_MachinetimeToUs(uint64_t time); /** - * @brief This function returns the current reference time expressed in system time units. - * The returned value can be used as absolute time parameter where needed in the other - * HAL_MRSUBG_TIMER* APIs - * @return absolute current time expressed in system time units. - */ + * @brief This function returns the current reference time expressed in system time units. + * The returned value can be used as absolute time parameter where needed in the other + * HAL_MRSUBG_TIMER* APIs + * @return absolute current time expressed in system time units. + */ uint64_t HAL_MRSUBG_TIMER_GetCurrentSysTime(void); /** @@ -193,47 +199,47 @@ uint64_t HAL_MRSUBG_TIMER_GetCurrentSysTime(void); */ /** - * @brief Starts a one-shot virtual timer for the given relative timeout value expressed in us - * @param timerHandle: The virtual timer - * @param usRelTimeout: The relative time, from current time, expressed in us - * @retval 0 if the timerHandle is valid. - * @retval 1 if the timerHandle is not valid. It is already started. - */ -uint32_t HAL_MRSUBG_TIMER_StartVirtualTimer(VTIMER_HandleType *timerHandle, uint64_t usRelTimeout); + * @brief Starts a one-shot virtual timer for the given relative timeout value expressed in us + * @param timerHandle: The virtual timer + * @param usRelTimeout: The relative time, from current time, expressed in us + * @retval 0 if the timerHandle is valid. + * @retval 1 if the timerHandle is not valid. It is already started. + */ +uint32_t HAL_MRSUBG_TIMER_StartVirtualTimer(VTIMER_HandleType_t *timerHandle, uint64_t usRelTimeout); /** - * @brief Starts a one-shot virtual timer for the given relative timeout value expressed in ms - * @param timerHandle: The virtual timer - * @param msRelTimeout: The relative time, from current time, expressed in ms - * @retval 0 if the timerHandle is valid. - * @retval 1 if the timerHandle is not valid. It is already started. - */ -uint32_t HAL_MRSUBG_TIMER_StartVirtualTimerMs(VTIMER_HandleType *timerHandle, uint32_t msRelTimeout); + * @brief Starts a one-shot virtual timer for the given relative timeout value expressed in ms + * @param timerHandle: The virtual timer + * @param msRelTimeout: The relative time, from current time, expressed in ms + * @retval 0 if the timerHandle is valid. + * @retval 1 if the timerHandle is not valid. It is already started. + */ +uint32_t HAL_MRSUBG_TIMER_StartVirtualTimerMs(VTIMER_HandleType_t *timerHandle, uint32_t msRelTimeout); /** - * @brief Stops the one-shot virtual timer specified if found - * @param timerHandle: The virtual timer - * @retval None - */ -void HAL_MRSUBG_TIMER_StopVirtualTimer(VTIMER_HandleType *timerHandle); + * @brief Stops the one-shot virtual timer specified if found + * @param timerHandle: The virtual timer + * @retval None + */ +void HAL_MRSUBG_TIMER_StopVirtualTimer(VTIMER_HandleType_t *timerHandle); /** - * @brief Returns the absolute expiry time of a running virtual timer expressed in internal system time units. - * @param timerHandle: The virtual timer - * @retval sysTime: Absolute time expressed in internal system time units. - */ -uint64_t HAL_MRSUBG_TIMER_ExpiryTime(VTIMER_HandleType *timerHandle); + * @brief Returns the absolute expiry time of a running virtual timer expressed in internal system time units. + * @param timerHandle: The virtual timer + * @retval sysTime: Absolute time expressed in internal system time units. + */ +uint64_t HAL_MRSUBG_TIMER_ExpiryTime(VTIMER_HandleType_t *timerHandle); /** - * @brief Virtual timer Timeout Callback. It signals that a host timeout occurred. - * @retval None - */ + * @brief Virtual timer Timeout Callback. It signals that a host timeout occurred. + * @retval None + */ void HAL_MRSUBG_TIMER_TimeoutCallback(void); /** - * @brief Returns the number of timers in the queue. - * @return number of timers in the queue. -*/ + * @brief Returns the number of timers in the queue. + * @return number of timers in the queue. + */ uint32_t HAL_MRSUBG_TIMER_GetPendingTimers(void); void HAL_MRSUBG_TIMER_MspInit(void); diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_pwr.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_pwr.h index a7806d47a3..d0500cb2fe 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_pwr.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_pwr.h @@ -66,15 +66,37 @@ typedef struct } PWR_DEEPSTOPTypeDef; +/** + * @brief PWR ULTRA DEEPSTOP configuration structure definition + * @note This mode is available only for STM32WL3RX device. + * @note The wake up source can be occurred by the following + pins: PB0, PA0, PA7, PA8, PA9, and PA11. + + */ +typedef struct +{ + uint8_t BORStatus; /*!< Specifies the BOR status ENABLE or DISABLE */ + uint8_t WakeUpPinStatus; /*!< Specifies if the wake up source + is ENABLE or DISABLE*/ + uint8_t WakeUpPol; /*!< Specifies the wake up source polarity */ + +} PWR_ULTRA_DEEPSTOPTypeDef; + /** * @brief PWR SHUTDOWN configuration structure definition + * @note For STM32WL3RX device: the wake up source can be occurred + by the following pins: PB0, PA0, PA7, PA8, PA9, and PA11. + * @note For STM32WL3XX device: the wake up source can be occurred + by PB0 pin. + */ typedef struct { uint8_t BORStatus; /*!< Specifies the BOR status ENABLE or DISABLE */ - uint8_t WakeUpPinStatus; /*!< Specifies if the PB0 wake up source + uint8_t WakeUpPinStatus; /*!< Specifies if the wake up source is ENABLE or DISABLE*/ uint8_t WakeUpPol; /*!< Specifies the wake up source polarity */ + } PWR_SHUTDOWNTypeDef; /** @@ -85,7 +107,10 @@ typedef enum POWER_SAVE_LEVEL_DISABLED = 0, POWER_SAVE_LEVEL_SLEEP = 1, POWER_SAVE_LEVEL_DEEPSTOP_TIMER = 2, - POWER_SAVE_LEVEL_DEEPSTOP_NOTIMER = 3 + POWER_SAVE_LEVEL_DEEPSTOP_NOTIMER = 3, +#if defined(STM32WL3RX) + POWER_SAVE_LEVEL_ULTRADEEPSTOP = 4, +#endif } PowerSaveLevels; /** @@ -248,8 +273,9 @@ typedef enum /** @defgroup PWR_LOW_PWR_MODE Low Power mode selection * @{ */ -#define PWR_MODE_DEEPSTOP (0x000000000U) -#define PWR_MODE_SHUTDOWN (PWR_CR1_LPMS) +#define PWR_MODE_DEEPSTOP (0x000000000U) +#define PWR_MODE_ULTRA_DEEPSTOP (PWR_CR1_LPMS) +#define PWR_MODE_SHUTDOWN (PWR_CR1_LPMS) /** * @} */ @@ -376,104 +402,203 @@ typedef enum * the device entered a DEEPSTOP mode. * @retval The state of __FLAG__ (TRUE or FALSE). */ +#if defined(STM32WL3XX) #define __HAL_PWR_GET_FLAG(__FLAG__)( \ ((__FLAG__) == PWR_FLAG_LPUART) ? (READ_BIT(PWR->IWUF, PWR_IWUF_IWUF0) == \ - PWR_IWUF_IWUF0) : \ + PWR_IWUF_IWUF0) : \ ((__FLAG__) == PWR_FLAG_RTC) ? (READ_BIT(PWR->IWUF, PWR_IWUF_IWUF1) == \ - PWR_IWUF_IWUF1) : \ + PWR_IWUF_IWUF1) : \ ((__FLAG__) == PWR_FLAG_LCD) ? (READ_BIT(PWR->IWUF, PWR_IWUF_IWUF2) == \ - PWR_IWUF_IWUF2) : \ + PWR_IWUF_IWUF2) : \ ((__FLAG__) == PWR_FLAG_COMP) ? (READ_BIT(PWR->IWUF, PWR_IWUF_IWUF3) == \ - PWR_IWUF_IWUF3) : \ + PWR_IWUF_IWUF3) : \ ((__FLAG__) == PWR_FLAG_LCSC) ? (READ_BIT(PWR->IWUF, PWR_IWUF_IWUF4) == \ - PWR_IWUF_IWUF4) : \ + PWR_IWUF_IWUF4) : \ ((__FLAG__) == PWR_FLAG_MRSUBG) ? (READ_BIT(PWR->IWUF, PWR_IWUF_WMRSUBGF) == \ - PWR_IWUF_WMRSUBGF) : \ + PWR_IWUF_WMRSUBGF) : \ ((__FLAG__) == PWR_FLAG_MRSUBGHCPU) ? (READ_BIT(PWR->IWUF, PWR_IWUF_WMRSUBGHCPUF) == \ - PWR_IWUF_WMRSUBGHCPUF) : \ + PWR_IWUF_WMRSUBGHCPUF) : \ ((__FLAG__) == PWR_FLAG_LPAWUR) ? (READ_BIT(PWR->IWUF, PWR_IWUF_WLPAWURF) == \ - PWR_IWUF_WLPAWURF) : \ + PWR_IWUF_WLPAWURF) : \ ((__FLAG__) == PWR_FLAG_SMPSBYPR) ? (READ_BIT(PWR->SR2, PWR_SR2_SMPSBYPR) == \ - PWR_SR2_SMPSBYPR) : \ + PWR_SR2_SMPSBYPR) : \ ((__FLAG__) == PWR_FLAG_SMPSENR) ? (READ_BIT(PWR->SR2, PWR_SR2_SMPSENR) == \ - PWR_SR2_SMPSENR) : \ + PWR_SR2_SMPSENR) : \ ((__FLAG__) == PWR_FLAG_SMPSRDY) ? (READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) == \ - PWR_SR2_SMPSRDY) : \ + PWR_SR2_SMPSRDY) : \ ((__FLAG__) == PWR_FLAG_REGLPS) ? (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == \ - PWR_SR2_REGLPS) : \ + PWR_SR2_REGLPS) : \ ((__FLAG__) == PWR_FLAG_REGMS) ? (READ_BIT(PWR->SR2, PWR_SR2_REGMS) == \ - PWR_SR2_REGMS) : \ + PWR_SR2_REGMS) : \ ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == \ - PWR_SR2_PVDO) : \ + PWR_SR2_PVDO) : \ ((__FLAG__) == PWR_FLAG_WUFA0) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF0) == \ - PWR_WUFA_WUF0) : \ + PWR_WUFA_WUF0) : \ ((__FLAG__) == PWR_FLAG_WUFA1) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF1) == \ - PWR_WUFA_WUF1) : \ + PWR_WUFA_WUF1) : \ ((__FLAG__) == PWR_FLAG_WUFA2) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF2) == \ - PWR_WUFA_WUF2) : \ + PWR_WUFA_WUF2) : \ ((__FLAG__) == PWR_FLAG_WUFA3) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF3) == \ - PWR_WUFA_WUF3) : \ + PWR_WUFA_WUF3) : \ ((__FLAG__) == PWR_FLAG_WUFA4) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF4) == \ - PWR_WUFA_WUF4) : \ + PWR_WUFA_WUF4) : \ ((__FLAG__) == PWR_FLAG_WUFA5) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF5) == \ - PWR_WUFA_WUF5) : \ + PWR_WUFA_WUF5) : \ ((__FLAG__) == PWR_FLAG_WUFA6) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF6) == \ - PWR_WUFA_WUF6) : \ + PWR_WUFA_WUF6) : \ ((__FLAG__) == PWR_FLAG_WUFA7) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF7) == \ - PWR_WUFA_WUF7) : \ + PWR_WUFA_WUF7) : \ ((__FLAG__) == PWR_FLAG_WUFA8) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF8) == \ - PWR_WUFA_WUF8) : \ + PWR_WUFA_WUF8) : \ ((__FLAG__) == PWR_FLAG_WUFA9) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF9) == \ - PWR_WUFA_WUF9) : \ + PWR_WUFA_WUF9) : \ ((__FLAG__) == PWR_FLAG_WUFA10) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF10) == \ - PWR_WUFA_WUF10) : \ + PWR_WUFA_WUF10) : \ ((__FLAG__) == PWR_FLAG_WUFA11) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF11) == \ - PWR_WUFA_WUF11) : \ + PWR_WUFA_WUF11) : \ ((__FLAG__) == PWR_FLAG_WUFA12) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF12) == \ - PWR_WUFA_WUF12) : \ + PWR_WUFA_WUF12) : \ ((__FLAG__) == PWR_FLAG_WUFA13) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF13) == \ - PWR_WUFA_WUF13) : \ + PWR_WUFA_WUF13) : \ ((__FLAG__) == PWR_FLAG_WUFA14) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF14) == \ - PWR_WUFA_WUF14) : \ + PWR_WUFA_WUF14) : \ ((__FLAG__) == PWR_FLAG_WUFA15) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF15) == \ - PWR_WUFA_WUF15) : \ + PWR_WUFA_WUF15) : \ ((__FLAG__) == PWR_FLAG_WUFB0) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF0) == \ - PWR_WUFB_WUF0) : \ + PWR_WUFB_WUF0) : \ ((__FLAG__) == PWR_FLAG_WUFB1) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF1) == \ - PWR_WUFB_WUF1) : \ + PWR_WUFB_WUF1) : \ ((__FLAG__) == PWR_FLAG_WUFB2) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF2) == \ - PWR_WUFB_WUF2) : \ + PWR_WUFB_WUF2) : \ ((__FLAG__) == PWR_FLAG_WUFB3) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF3) == \ - PWR_WUFB_WUF3) : \ + PWR_WUFB_WUF3) : \ ((__FLAG__) == PWR_FLAG_WUFB4) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF4) == \ - PWR_WUFB_WUF4) : \ + PWR_WUFB_WUF4) : \ ((__FLAG__) == PWR_FLAG_WUFB5) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF5) == \ - PWR_WUFB_WUF5) : \ + PWR_WUFB_WUF5) : \ ((__FLAG__) == PWR_FLAG_WUFB6) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF6) == \ - PWR_WUFB_WUF6) : \ + PWR_WUFB_WUF6) : \ ((__FLAG__) == PWR_FLAG_WUFB7) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF7) == \ - PWR_WUFB_WUF7) : \ + PWR_WUFB_WUF7) : \ ((__FLAG__) == PWR_FLAG_WUFB8) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF8) == \ - PWR_WUFB_WUF8) : \ + PWR_WUFB_WUF8) : \ ((__FLAG__) == PWR_FLAG_WUFB9) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF9) == \ - PWR_WUFB_WUF9) : \ + PWR_WUFB_WUF9) : \ ((__FLAG__) == PWR_FLAG_WUFB10) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF10) == \ - PWR_WUFB_WUF10) : \ + PWR_WUFB_WUF10) : \ ((__FLAG__) == PWR_FLAG_WUFB11) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF11) == \ - PWR_WUFB_WUF11) : \ + PWR_WUFB_WUF11) : \ ((__FLAG__) == PWR_FLAG_WUFB12) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF12) == \ - PWR_WUFB_WUF12) : \ + PWR_WUFB_WUF12) : \ ((__FLAG__) == PWR_FLAG_WUFB13) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF13) == \ - PWR_WUFB_WUF13) : \ + PWR_WUFB_WUF13) : \ ((__FLAG__) == PWR_FLAG_WUFB14) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF14) == \ - PWR_WUFB_WUF14) : \ + PWR_WUFB_WUF14) : \ ((__FLAG__) == PWR_FLAG_WUFB15) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF15) == \ - PWR_WUFB_WUF15) : \ + PWR_WUFB_WUF15) : \ ((__FLAG__) == PWR_FLAG_WUF) ? (READ_BIT(PWR->SDWN_WUF, PWR_SDWN_WUF_WUF) == \ - PWR_SDWN_WUF_WUF) : \ + PWR_SDWN_WUF_WUF) : \ ((__FLAG__) == PWR_FLAG_DEEPSTOPF) ? (READ_BIT(PWR->EXTSRR, PWR_EXTSRR_DEEPSTOPF) == \ - PWR_EXTSRR_DEEPSTOPF) : \ + PWR_EXTSRR_DEEPSTOPF) : \ (READ_BIT(PWR->EXTSRR, PWR_EXTSRR_RFPHASEF) == PWR_EXTSRR_RFPHASEF)) +#else +#define __HAL_PWR_GET_FLAG(__FLAG__)( \ + ((__FLAG__) == PWR_FLAG_LPUART) ? (READ_BIT(PWR->IWUF, PWR_IWUF_IWUF0) == \ + PWR_IWUF_IWUF0) : \ + ((__FLAG__) == PWR_FLAG_RTC) ? (READ_BIT(PWR->IWUF, PWR_IWUF_IWUF1) == \ + PWR_IWUF_IWUF1) : \ + ((__FLAG__) == PWR_FLAG_LCD) ? (READ_BIT(PWR->IWUF, PWR_IWUF_IWUF2) == \ + PWR_IWUF_IWUF2) : \ + ((__FLAG__) == PWR_FLAG_COMP) ? (READ_BIT(PWR->IWUF, PWR_IWUF_IWUF3) == \ + PWR_IWUF_IWUF3) : \ + ((__FLAG__) == PWR_FLAG_LCSC) ? (READ_BIT(PWR->IWUF, PWR_IWUF_IWUF4) == \ + PWR_IWUF_IWUF4) : \ + ((__FLAG__) == PWR_FLAG_MRSUBG) ? (READ_BIT(PWR->IWUF, PWR_IWUF_WMRSUBGF) == \ + PWR_IWUF_WMRSUBGF) : \ + ((__FLAG__) == PWR_FLAG_MRSUBGHCPU) ? (READ_BIT(PWR->IWUF, PWR_IWUF_WMRSUBGHCPUF) == \ + PWR_IWUF_WMRSUBGHCPUF) : \ + ((__FLAG__) == PWR_FLAG_SMPSBYPR) ? (READ_BIT(PWR->SR2, PWR_SR2_SMPSBYPR) == \ + PWR_SR2_SMPSBYPR) : \ + ((__FLAG__) == PWR_FLAG_SMPSENR) ? (READ_BIT(PWR->SR2, PWR_SR2_SMPSENR) == \ + PWR_SR2_SMPSENR) : \ + ((__FLAG__) == PWR_FLAG_SMPSRDY) ? (READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) == \ + PWR_SR2_SMPSRDY) : \ + ((__FLAG__) == PWR_FLAG_REGLPS) ? (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == \ + PWR_SR2_REGLPS) : \ + ((__FLAG__) == PWR_FLAG_REGMS) ? (READ_BIT(PWR->SR2, PWR_SR2_REGMS) == \ + PWR_SR2_REGMS) : \ + ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == \ + PWR_SR2_PVDO) : \ + ((__FLAG__) == PWR_FLAG_WUFA0) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF0) == \ + PWR_WUFA_WUF0) : \ + ((__FLAG__) == PWR_FLAG_WUFA1) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF1) == \ + PWR_WUFA_WUF1) : \ + ((__FLAG__) == PWR_FLAG_WUFA2) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF2) == \ + PWR_WUFA_WUF2) : \ + ((__FLAG__) == PWR_FLAG_WUFA3) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF3) == \ + PWR_WUFA_WUF3) : \ + ((__FLAG__) == PWR_FLAG_WUFA4) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF4) == \ + PWR_WUFA_WUF4) : \ + ((__FLAG__) == PWR_FLAG_WUFA5) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF5) == \ + PWR_WUFA_WUF5) : \ + ((__FLAG__) == PWR_FLAG_WUFA6) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF6) == \ + PWR_WUFA_WUF6) : \ + ((__FLAG__) == PWR_FLAG_WUFA7) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF7) == \ + PWR_WUFA_WUF7) : \ + ((__FLAG__) == PWR_FLAG_WUFA8) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF8) == \ + PWR_WUFA_WUF8) : \ + ((__FLAG__) == PWR_FLAG_WUFA9) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF9) == \ + PWR_WUFA_WUF9) : \ + ((__FLAG__) == PWR_FLAG_WUFA10) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF10) == \ + PWR_WUFA_WUF10) : \ + ((__FLAG__) == PWR_FLAG_WUFA11) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF11) == \ + PWR_WUFA_WUF11) : \ + ((__FLAG__) == PWR_FLAG_WUFA12) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF12) == \ + PWR_WUFA_WUF12) : \ + ((__FLAG__) == PWR_FLAG_WUFA13) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF13) == \ + PWR_WUFA_WUF13) : \ + ((__FLAG__) == PWR_FLAG_WUFA14) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF14) == \ + PWR_WUFA_WUF14) : \ + ((__FLAG__) == PWR_FLAG_WUFA15) ? (READ_BIT(PWR->WUFA, PWR_WUFA_WUF15) == \ + PWR_WUFA_WUF15) : \ + ((__FLAG__) == PWR_FLAG_WUFB0) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF0) == \ + PWR_WUFB_WUF0) : \ + ((__FLAG__) == PWR_FLAG_WUFB1) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF1) == \ + PWR_WUFB_WUF1) : \ + ((__FLAG__) == PWR_FLAG_WUFB2) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF2) == \ + PWR_WUFB_WUF2) : \ + ((__FLAG__) == PWR_FLAG_WUFB3) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF3) == \ + PWR_WUFB_WUF3) : \ + ((__FLAG__) == PWR_FLAG_WUFB4) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF4) == \ + PWR_WUFB_WUF4) : \ + ((__FLAG__) == PWR_FLAG_WUFB5) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF5) == \ + PWR_WUFB_WUF5) : \ + ((__FLAG__) == PWR_FLAG_WUFB6) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF6) == \ + PWR_WUFB_WUF6) : \ + ((__FLAG__) == PWR_FLAG_WUFB7) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF7) == \ + PWR_WUFB_WUF7) : \ + ((__FLAG__) == PWR_FLAG_WUFB8) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF8) == \ + PWR_WUFB_WUF8) : \ + ((__FLAG__) == PWR_FLAG_WUFB9) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF9) == \ + PWR_WUFB_WUF9) : \ + ((__FLAG__) == PWR_FLAG_WUFB10) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF10) == \ + PWR_WUFB_WUF10) : \ + ((__FLAG__) == PWR_FLAG_WUFB11) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF11) == \ + PWR_WUFB_WUF11) : \ + ((__FLAG__) == PWR_FLAG_WUFB12) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF12) == \ + PWR_WUFB_WUF12) : \ + ((__FLAG__) == PWR_FLAG_WUFB13) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF13) == \ + PWR_WUFB_WUF13) : \ + ((__FLAG__) == PWR_FLAG_WUFB14) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF14) == \ + PWR_WUFB_WUF14) : \ + ((__FLAG__) == PWR_FLAG_WUFB15) ? (READ_BIT(PWR->WUFB, PWR_WUFB_WUF15) == \ + PWR_WUFB_WUF15) : \ + ((__FLAG__) == PWR_FLAG_WUF) ? (READ_BIT(PWR->SDWN_WUF, PWR_SDWN_WUF_WUF) == \ + PWR_SDWN_WUF_WUF) : \ + ((__FLAG__) == PWR_FLAG_DEEPSTOPF) ? (READ_BIT(PWR->EXTSRR, PWR_EXTSRR_DEEPSTOPF) == \ + PWR_EXTSRR_DEEPSTOPF) : \ + (READ_BIT(PWR->EXTSRR, PWR_EXTSRR_RFPHASEF) == PWR_EXTSRR_RFPHASEF)) +#endif /* STM32WL3XX*/ /** @brief Clear PWR flags. * @param __FLAG__ : Specifies the flag to clear. @@ -567,6 +692,7 @@ typedef enum * Indicates that the device entered a DEEPSTOP mode. * @retval None. */ +#if defined(STM32WL3XX) #define __HAL_PWR_CLEAR_FLAG(__FLAG__)( \ ((__FLAG__) == PWR_FLAG_LPUART) ? (SET_BIT(PWR->IWUF, PWR_IWUF_IWUF0)) : \ ((__FLAG__) == PWR_FLAG_RTC) ? (SET_BIT(PWR->IWUF, PWR_IWUF_IWUF1)) : \ @@ -611,6 +737,51 @@ typedef enum ((__FLAG__) == PWR_FLAG_WUF) ? (CLEAR_BIT(PWR->SDWN_WUF, PWR_SDWN_WUF_WUF)) : \ ((__FLAG__) == PWR_FLAG_DEEPSTOPF) ? (SET_BIT(PWR->EXTSRR, PWR_EXTSRR_DEEPSTOPF)) : \ (SET_BIT(PWR->EXTSRR, PWR_EXTSRR_RFPHASEF))) +#else +#define __HAL_PWR_CLEAR_FLAG(__FLAG__)( \ + ((__FLAG__) == PWR_FLAG_LPUART) ? (SET_BIT(PWR->IWUF, PWR_IWUF_IWUF0)) : \ + ((__FLAG__) == PWR_FLAG_RTC) ? (SET_BIT(PWR->IWUF, PWR_IWUF_IWUF1)) : \ + ((__FLAG__) == PWR_FLAG_LCD) ? (SET_BIT(PWR->IWUF, PWR_IWUF_IWUF2)) : \ + ((__FLAG__) == PWR_FLAG_COMP) ? (SET_BIT(PWR->IWUF, PWR_IWUF_IWUF3)) : \ + ((__FLAG__) == PWR_FLAG_LCSC) ? (SET_BIT(PWR->IWUF, PWR_IWUF_IWUF4)) : \ + ((__FLAG__) == PWR_FLAG_MRSUBG) ? (SET_BIT(PWR->IWUF, PWR_IWUF_WMRSUBGF)) : \ + ((__FLAG__) == PWR_FLAG_MRSUBGHCPU) ? (SET_BIT(PWR->IWUF, PWR_IWUF_WMRSUBGHCPUF)) : \ + ((__FLAG__) == PWR_FLAG_WUFA0) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF0)) : \ + ((__FLAG__) == PWR_FLAG_WUFA1) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF1)) : \ + ((__FLAG__) == PWR_FLAG_WUFA2) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF2)) : \ + ((__FLAG__) == PWR_FLAG_WUFA3) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF3)) : \ + ((__FLAG__) == PWR_FLAG_WUFA4) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF4)) : \ + ((__FLAG__) == PWR_FLAG_WUFA5) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF5)) : \ + ((__FLAG__) == PWR_FLAG_WUFA6) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF6)) : \ + ((__FLAG__) == PWR_FLAG_WUFA7) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF7)) : \ + ((__FLAG__) == PWR_FLAG_WUFA8) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF8)) : \ + ((__FLAG__) == PWR_FLAG_WUFA9) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF9)) : \ + ((__FLAG__) == PWR_FLAG_WUFA10) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF10)) : \ + ((__FLAG__) == PWR_FLAG_WUFA11) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF11)) : \ + ((__FLAG__) == PWR_FLAG_WUFA12) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF12)) : \ + ((__FLAG__) == PWR_FLAG_WUFA13) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF13)) : \ + ((__FLAG__) == PWR_FLAG_WUFA14) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF14)) : \ + ((__FLAG__) == PWR_FLAG_WUFA15) ? (SET_BIT(PWR->WUFA, PWR_WUFA_WUF15)) : \ + ((__FLAG__) == PWR_FLAG_WUFB0) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF0)) : \ + ((__FLAG__) == PWR_FLAG_WUFB1) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF1)) : \ + ((__FLAG__) == PWR_FLAG_WUFB2) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF2)) : \ + ((__FLAG__) == PWR_FLAG_WUFB3) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF3)) : \ + ((__FLAG__) == PWR_FLAG_WUFB4) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF4)) : \ + ((__FLAG__) == PWR_FLAG_WUFB5) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF5)) : \ + ((__FLAG__) == PWR_FLAG_WUFB6) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF6)) : \ + ((__FLAG__) == PWR_FLAG_WUFB7) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF7)) : \ + ((__FLAG__) == PWR_FLAG_WUFB8) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF8)) : \ + ((__FLAG__) == PWR_FLAG_WUFB9) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF9)) : \ + ((__FLAG__) == PWR_FLAG_WUFB10) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF10)) : \ + ((__FLAG__) == PWR_FLAG_WUFB11) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF11)) : \ + ((__FLAG__) == PWR_FLAG_WUFB12) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF12)) : \ + ((__FLAG__) == PWR_FLAG_WUFB13) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF13)) : \ + ((__FLAG__) == PWR_FLAG_WUFB14) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF14)) : \ + ((__FLAG__) == PWR_FLAG_WUFB15) ? (SET_BIT(PWR->WUFB, PWR_WUFB_WUF15)) : \ + ((__FLAG__) == PWR_FLAG_WUF) ? (CLEAR_BIT(PWR->SDWN_WUF, PWR_SDWN_WUF_WUF)) : \ + ((__FLAG__) == PWR_FLAG_DEEPSTOPF) ? (SET_BIT(PWR->EXTSRR, PWR_EXTSRR_DEEPSTOPF)) : \ + (SET_BIT(PWR->EXTSRR, PWR_EXTSRR_RFPHASEF))) +#endif /* STM32WL3XX*/ /** * @brief Enable the PVD Line. @@ -639,17 +810,43 @@ typedef enum #define __HAL_PWR_PVD_CLEAR_FLAG() WRITE_REG(SYSCFG->PWRC_ISCR, SYSCFG_PWRC_ISCR_PVD_ISC) /** - * @brief Check if the wake up from SHUTWDOWN happens from PB0 or not. + * @brief Check if the wake up from SHUTWDOWN happens or not. * @retval None + * @note For STM32WL3RX device the wakeup from shutdown mode happens + from the following pins: PB0, PA0, PA7, PA8, PA9, and PA11. + * @note For STM32WL3XX device The wakeup from shutdown mode happens + from PB0 pin. */ #define __HAL_PWR_IO_WAKEUP_SHUTDOWN_GET_FLAG() LL_PWR_IsIOWakeupSDN() /** - * @brief Check if the wake up from SHUTWDOWN happens from PB0 or not. + * @brief Check if the wake up from SHUTWDOWN happens or not. * @retval None + * @note For STM32WL3RX device the wakeup from shutdown mode happens + from the following pins: PB0, PA0, PA7, PA8, PA9, and PA11. + * @note For STM32WL3XX device The wakeup from shutdown mode happens + from PB0 pin. */ #define __HAL_PWR_CLEAR_IO_WAKEUP_SHUTDOWN_FLAG() LL_PWR_ClearIOWakeupFlagSDN() +/** + * @brief Check if the wake up from ULTRA_DEEPSTOP happens or not. + * @retval None + @note The ULTRA_DEEPSTOP mode is available only for STM32WL3RX device. + * @note The wakeup from ultra-deepstop mode happens from the following + pins: PB0, PA0, PA7, PA8, PA9, and PA11. + */ +#define __HAL_PWR_IO_WAKEUP_ULTRA_DEEPSTOP_GET_FLAG() LL_PWR_IsIOWakeupSDN() + +/** + * @brief Check if the wake up from ULTRA_DEEPSTOP happens or not. + * @retval None + @note The ULTRA_DEEPSTOP mode is available only for STM32WL3RX device. + * @note The wakeup from ultra-deepstop mode happens from the following + pins: PB0, PA0, PA7, PA8, PA9, and PA11. + */ +#define __HAL_PWR_CLEAR_IO_WAKEUP_ULTRA_DEEPSTOP_FLAG() LL_PWR_ClearIOWakeupFlagSDN() + /** * @} */ @@ -669,6 +866,7 @@ typedef enum #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL)||\ ((MODE) == PWR_PVD_MODE_IT)) +#if defined(STM32WL3XX) #define IS_PWR_WAKEUP_SOURCE(PIN) (((PIN) == PWR_WAKEUP_ALL) ||\ ((PIN) == PWR_WAKEUP_PIN0 ) ||\ ((PIN) == PWR_WAKEUP_PIN1 ) ||\ @@ -694,6 +892,29 @@ typedef enum ((PIN) == PWR_WAKEUP_LCD) ||\ ((PIN) == PWR_WAKEUP_RTC) ||\ ((PIN) == PWR_WAKEUP_LPUART)) +#else +#define IS_PWR_WAKEUP_SOURCE(PIN) (((PIN) == PWR_WAKEUP_ALL) ||\ + ((PIN) == PWR_WAKEUP_PIN0 ) ||\ + ((PIN) == PWR_WAKEUP_PIN1 ) ||\ + ((PIN) == PWR_WAKEUP_PIN2 ) ||\ + ((PIN) == PWR_WAKEUP_PIN3 ) ||\ + ((PIN) == PWR_WAKEUP_PIN4 ) ||\ + ((PIN) == PWR_WAKEUP_PIN5 ) ||\ + ((PIN) == PWR_WAKEUP_PIN6 ) ||\ + ((PIN) == PWR_WAKEUP_PIN7 ) ||\ + ((PIN) == PWR_WAKEUP_PIN8 ) ||\ + ((PIN) == PWR_WAKEUP_PIN9 ) ||\ + ((PIN) == PWR_WAKEUP_PIN10) ||\ + ((PIN) == PWR_WAKEUP_PIN11) ||\ + ((PIN) == PWR_WAKEUP_PIN12) ||\ + ((PIN) == PWR_WAKEUP_PIN13) ||\ + ((PIN) == PWR_WAKEUP_PIN14) ||\ + ((PIN) == PWR_WAKEUP_PIN15) ||\ + ((PIN) == PWR_WAKEUP_SUBG) ||\ + ((PIN) == PWR_WAKEUP_SUBGHOST) ||\ + ((PIN) == PWR_WAKEUP_RTC) ||\ + ((PIN) == PWR_WAKEUP_LPUART)) +#endif /* (STM32WL3XX) */ #define IS_PWR_WAKEUP_POLARITY(POL) (((POL) == PWR_WUP_RISIEDG) ||\ ((POL) == PWR_WUP_FALLEDG)) @@ -724,8 +945,10 @@ uint32_t HAL_PWR_GetClearWakeupSource(uint32_t WakeUpPort); /* Low power modes configuration functions ************************************/ HAL_StatusTypeDef HAL_PWR_ConfigDEEPSTOP(PWR_DEEPSTOPTypeDef *sConfigDEEPSTOP); HAL_StatusTypeDef HAL_PWR_ConfigSHUTDOWN(PWR_SHUTDOWNTypeDef *sConfigSHUTDOWN); +HAL_StatusTypeDef HAL_PWR_ConfigUltraDeepStop(PWR_ULTRA_DEEPSTOPTypeDef *sConfigUltraDeepStop); void HAL_PWR_EnterSLEEPMode(void); void HAL_PWR_EnterDEEPSTOPMode(void); +void HAL_PWR_EnterUltraDeepStopMode(void); /* Sleep on exit and sev on pending configuration functions *******************/ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_rcc.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_rcc.h index 9410382dc5..b23af27557 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_rcc.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_rcc.h @@ -844,9 +844,13 @@ typedef struct * @brief Force or release APB1 peripheral reset. * @{ */ +#if defined(STM32WL3XX) #define __HAL_RCC_APB1_FORCE_RESET() LL_APB1_GRP1_ForceReset( RCC_APB1ENR_ADCDIGEN|\ RCC_APB1ENR_LPUARTEN|RCC_APB1ENR_USARTEN|RCC_APB1ENR_SPI1EN|RCC_APB1ENR_SPI3EN|RCC_APB1ENR_I2C1EN|RCC_APB1ENR_I2C2EN) - +#else +#define __HAL_RCC_APB1_FORCE_RESET() LL_APB1_GRP1_ForceReset( RCC_APB1ENR_ADCDIGEN|\ + RCC_APB1ENR_LPUARTEN|RCC_APB1ENR_USARTEN|RCC_APB1ENR_SPI3EN|RCC_APB1ENR_I2C1EN) +#endif /* (STM32WL3XX) */ #if defined(SPI1) #define __HAL_RCC_SPI1_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI1) #endif @@ -861,9 +865,13 @@ typedef struct #define __HAL_RCC_I2C2_FORCE_RESET() LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2) #endif - +#if defined(STM32WL3XX) #define __HAL_RCC_APB1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(RCC_APB1ENR_ADCDIGEN|\ RCC_APB1ENR_LPUARTEN|RCC_APB1ENR_USARTEN|RCC_APB1ENR_SPI1EN|RCC_APB1ENR_SPI3EN|RCC_APB1ENR_I2C1EN|RCC_APB1ENR_I2C2EN) +#else +#define __HAL_RCC_APB1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(RCC_APB1ENR_ADCDIGEN|\ + RCC_APB1ENR_LPUARTEN|RCC_APB1ENR_USARTEN|RCC_APB1ENR_SPI3EN|RCC_APB1ENR_I2C1EN) +#endif /* (STM32WL3XX) */ #if defined(SPI1) #define __HAL_RCC_SPI1_RELEASE_RESET() LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI1) @@ -891,14 +899,18 @@ typedef struct #define __HAL_RCC_APB2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL) #if defined(MR_SUBG_RADIO) #define __HAL_RCC_MRSUBG_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_MRSUBG) +#endif /* MR_SUBG_RADIO*/ +#if defined(LPAWUR) #define __HAL_RCC_LPAWUR_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_LPAWUR) -#endif +#endif /* LPAWUR */ #define __HAL_RCC_APB2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL) #if defined(MR_SUBG_RADIO) #define __HAL_RCC_MRSUBG_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_MRSUBG) +#endif /* MR_SUBG_RADIO*/ +#if defined(LPAWUR) #define __HAL_RCC_LPAWUR_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_LPAWUR) -#endif +#endif /* LPAWUR */ /** * @} */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_smbus_ex.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_smbus_ex.h index 2e459cf710..0adb1f2fd6 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_smbus_ex.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_hal_smbus_ex.h @@ -110,16 +110,20 @@ void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); /** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros * @{ */ -#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA0)) == SMBUS_FASTMODEPLUS_PA0) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA1)) == SMBUS_FASTMODEPLUS_PA1) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA1)) == SMBUS_FASTMODEPLUS_PB10) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA1)) == SMBUS_FASTMODEPLUS_PB11) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA1)) == SMBUS_FASTMODEPLUS_PA6) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA1)) == SMBUS_FASTMODEPLUS_PA7) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA1)) == SMBUS_FASTMODEPLUS_PA13) || \ - (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA1)) == SMBUS_FASTMODEPLUS_PA14)) +#if defined(I2C1) || defined(I2C2) +#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ( \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA0)) == SMBUS_FASTMODEPLUS_PA0) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA1)) == SMBUS_FASTMODEPLUS_PA1) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB10)) == SMBUS_FASTMODEPLUS_PB10) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB11)) == SMBUS_FASTMODEPLUS_PB11) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA6)) == SMBUS_FASTMODEPLUS_PA6) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA7)) == SMBUS_FASTMODEPLUS_PA7) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA13)) == SMBUS_FASTMODEPLUS_PA13) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA14)) == SMBUS_FASTMODEPLUS_PA14)) +#endif /* I2C1 || I2C2 */ + /** * @} */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_adc.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_adc.h index cc90541103..cdbd2aef76 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_adc.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_adc.h @@ -339,8 +339,14 @@ typedef struct * @{ */ -#define LL_ADC_SAMPLING_AT_START (0x00000000UL) /*!< Sampling only at conversion start */ -#define LL_ADC_SAMPLING_AT_END (ADC_CONF_ADC_CONT_1V2) /*!< Sampling starts at the end of conversion (default)*/ +#define LL_ADC_SAMPLING_AT_START (0x00000000UL) /*!< Sampling phase starts only at conversion start and + sampling time is 125ns regardless of the sampling + period (default). */ +#define LL_ADC_SAMPLING_AT_END (ADC_CONF_ADC_CONT_1V2) /*!< Sampling phase starts after end of + conversion, and stops upon trigger event (Also known + as Bulb sampling mode). + Sampling time is a function of the sampling period + (Sample rate). */ /** * @} @@ -829,12 +835,23 @@ typedef struct * @retval Temperature (unit: degree Celsius) * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value) */ -#define __LL_ADC_CALC_TEMPERATURE(__TEMPSENSOR_ADC_DATA__,\ - __ADC_WIDTH__) \ -(((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),(__ADC_WIDTH__), LL_ADC_DS_DATA_WIDTH_12_BIT) \ - - (int32_t)*TEMPSENSOR_C30_ADDR + (int32_t)*TEMPSENSOR_TCK_ADDR) \ - / (10UL)) \ -) +#define __LL_ADC_CALC_TEMPERATURE(__TEMPSENSOR_ADC_DATA__, __ADC_WIDTH__) \ + ( ((__ADC_WIDTH__) == LL_ADC_DS_DATA_WIDTH_12_BIT) ? \ + (((__TEMPSENSOR_ADC_DATA__) - (int32_t)*TEMPSENSOR_C30_ADDR + (int32_t)*TEMPSENSOR_TCK_ADDR) / (10L)) \ + : \ + (__LL_ADC_CONVERT_DATA_RESOLUTION( \ + ((int32_t) __LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_WIDTH__), \ + LL_ADC_DS_DATA_WIDTH_16_BIT) \ + - (int32_t) __LL_ADC_CONVERT_DATA_RESOLUTION(((int32_t)*TEMPSENSOR_C30_ADDR), \ + (LL_ADC_DS_DATA_WIDTH_12_BIT), \ + LL_ADC_DS_DATA_WIDTH_16_BIT) \ + + (int32_t) __LL_ADC_CONVERT_DATA_RESOLUTION(((int32_t)*TEMPSENSOR_TCK_ADDR), \ + (LL_ADC_DS_DATA_WIDTH_12_BIT), \ + LL_ADC_DS_DATA_WIDTH_16_BIT)), \ + LL_ADC_DS_DATA_WIDTH_16_BIT, \ + LL_ADC_DS_DATA_WIDTH_12_BIT) / 10L) \ + ) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -2863,7 +2880,7 @@ __STATIC_INLINE int8_t LL_ADC_GET_CALIB_OFFSET_FOR_VINMX_3V6(void) { int8_t calibration_offset = ((*(uint32_t *)ADC_CALIB_ADDRESS_VINMX_3V6) >> 12UL); - return - (int8_t)calibration_offset; + return (int8_t)calibration_offset; } /** @@ -2888,7 +2905,7 @@ __STATIC_INLINE int8_t LL_ADC_GET_CALIB_OFFSET_FOR_VINMX_2V4(void) { int8_t calibration_offset = ((*(uint32_t *)ADC_CALIB_ADDRESS_VINMX_2V4) >> 12UL); - return - (int8_t)calibration_offset; + return (int8_t)calibration_offset; } @@ -2914,7 +2931,7 @@ __STATIC_INLINE int8_t LL_ADC_GET_CALIB_OFFSET_FOR_VINMX_1V2(void) { int8_t calibration_offset = ((*(uint32_t *)ADC_CALIB_ADDRESS_VINMX_1V2) >> 12UL); - return - (int8_t)calibration_offset; + return (int8_t)calibration_offset; } diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_bus.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_bus.h index da0299dfdf..9da374883a 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_bus.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_bus.h @@ -93,11 +93,20 @@ extern "C" { /** @defgroup BUS_LL_APB0_GRP1_PERIPH APB0 PERIPH * @{ */ +#if defined(STM32WL3XX) #define LL_APB0_GRP1_PERIPH_ALL (RCC_APB0ENR_TIM2EN|\ RCC_APB0ENR_TIM16EN|\ RCC_APB0ENR_SYSCFGEN|\ RCC_APB0ENR_LCDEN|\ RCC_APB0ENR_COMPEN|RCC_APB0ENR_DACEN|RCC_APB0ENR_RTCEN|RCC_APB0ENR_LCSCEN|RCC_APB0ENR_WDGEN|RCC_APB0ENR_DBGMCUEN) +#else +#define LL_APB0_GRP1_PERIPH_ALL (RCC_APB0ENR_TIM2EN|\ + RCC_APB0ENR_TIM16EN|\ + RCC_APB0ENR_SYSCFGEN|\ + RCC_APB0ENR_RTCEN|RCC_APB0ENR_WDGEN|RCC_APB0ENR_DBGMCUEN) +#endif /* (STM32WL3XX) */ + + #if defined(TIM1) #define LL_APB0_GRP1_PERIPH_TIM1 RCC_APB0ENR_TIM1EN #endif @@ -136,9 +145,15 @@ extern "C" { /** @defgroup BUS_LL_APB1_GRP1_PERIPH APB1 PERIPH * @{ */ +#if defined(STM32WL3XX) #define LL_APB1_GRP1_PERIPH_ALL (RCC_APB1ENR_SPI1EN|\ RCC_APB1ENR_ADCDIGEN|\ RCC_APB1ENR_ADCANAEN|RCC_APB1ENR_LPUARTEN|RCC_APB1ENR_USARTEN|RCC_APB1ENR_SPI3EN|RCC_APB1ENR_I2C1EN|RCC_APB1ENR_I2C2EN) +#else +#define LL_APB1_GRP1_PERIPH_ALL (RCC_APB1ENR_ADCDIGEN|\ + RCC_APB1ENR_ADCANAEN|RCC_APB1ENR_LPUARTEN|RCC_APB1ENR_USARTEN|RCC_APB1ENR_SPI3EN|RCC_APB1ENR_I2C1EN) +#endif /* (STM32WL3XX) */ + #if defined(SPI1) #define LL_APB1_GRP1_PERIPH_SPI1 RCC_APB1ENR_SPI1EN #endif @@ -158,10 +173,13 @@ extern "C" { /** @defgroup BUS_LL_APB2_GRP1_PERIPH APB2 PERIPH * @{ */ -#if defined(MR_SUBG_RADIO) +#if defined(MR_SUBG_RADIO) && defined(LPAWUR) #define LL_APB2_GRP1_PERIPH_ALL (RCC_APB2ENR_MRSUBGEN|RCC_APB2ENR_LPAWUREN) #define LL_APB2_GRP1_PERIPH_MRSUBG RCC_APB2ENR_MRSUBGEN #define LL_APB2_GRP1_PERIPH_LPAWUR RCC_APB2ENR_LPAWUREN +#else +#define LL_APB2_GRP1_PERIPH_ALL RCC_APB2ENR_MRSUBGEN +#define LL_APB2_GRP1_PERIPH_MRSUBG RCC_APB2ENR_MRSUBGEN #endif /** * @} diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h index e49d7c53f5..b94790b322 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h @@ -433,7 +433,6 @@ typedef struct */ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -454,7 +453,6 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -475,7 +473,6 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); } @@ -512,7 +509,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); @@ -540,7 +536,6 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); } @@ -566,7 +561,6 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM)); } @@ -593,7 +587,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC, Mode); } @@ -617,7 +610,6 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC)); } @@ -642,7 +634,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC, PeriphOrM2MSrcIncMode); } @@ -666,7 +657,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC)); } @@ -691,7 +681,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC, MemoryOrM2MDstIncMode); } @@ -715,7 +704,6 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC)); } @@ -741,7 +729,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize); } @@ -766,7 +753,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE)); } @@ -792,7 +778,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE, MemoryOrM2MDstDataSize); } @@ -817,7 +802,6 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE)); } @@ -844,7 +828,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL, Priority); } @@ -870,7 +853,6 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL)); } @@ -895,7 +877,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT, NbData); } @@ -919,7 +900,6 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT)); } @@ -951,7 +931,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { - (void)DMAx; /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { @@ -986,7 +965,6 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -1010,7 +988,6 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress); } @@ -1032,7 +1009,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1054,7 +1030,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1078,7 +1053,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress); } @@ -1102,7 +1076,6 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { - (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -1124,7 +1097,6 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1146,7 +1118,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1169,7 +1140,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { - (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request); } @@ -1191,7 +1161,6 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID)); } @@ -1211,7 +1180,6 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); } @@ -1223,7 +1191,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); } @@ -1235,7 +1202,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); } @@ -1247,7 +1213,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); } @@ -1259,7 +1224,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); } @@ -1271,7 +1235,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); } @@ -1283,7 +1246,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); } @@ -1295,7 +1257,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL); } @@ -1307,7 +1268,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); } @@ -1319,7 +1279,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); } @@ -1331,7 +1290,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); } @@ -1343,7 +1301,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); } @@ -1355,7 +1312,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); } @@ -1367,7 +1323,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); } @@ -1379,7 +1334,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); } @@ -1391,7 +1345,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL); } @@ -1403,7 +1356,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); } @@ -1415,7 +1367,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); } @@ -1427,7 +1378,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); } @@ -1439,7 +1389,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); } @@ -1451,7 +1400,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); } @@ -1463,7 +1411,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); } @@ -1475,7 +1422,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); } @@ -1487,7 +1433,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL); } @@ -1499,7 +1444,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); } @@ -1511,7 +1455,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); } @@ -1523,7 +1466,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); } @@ -1535,7 +1477,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); } @@ -1547,7 +1488,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); } @@ -1559,7 +1499,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); } @@ -1571,7 +1510,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); } @@ -1583,7 +1521,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) { - (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL); } @@ -1595,7 +1532,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); } @@ -1607,7 +1543,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); } @@ -1619,7 +1554,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); } @@ -1631,7 +1565,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); } @@ -1643,7 +1576,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); } @@ -1655,7 +1587,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); } @@ -1667,7 +1598,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); } @@ -1679,7 +1609,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8); } @@ -1691,7 +1620,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); } @@ -1703,7 +1631,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); } @@ -1715,7 +1642,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); } @@ -1727,7 +1653,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); } @@ -1739,7 +1664,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); } @@ -1751,7 +1675,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); } @@ -1763,7 +1686,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); } @@ -1775,7 +1697,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8); } @@ -1787,7 +1708,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); } @@ -1799,7 +1719,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); } @@ -1811,7 +1730,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); } @@ -1823,7 +1741,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); } @@ -1835,7 +1752,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); } @@ -1847,7 +1763,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); } @@ -1859,7 +1774,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); } @@ -1871,7 +1785,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8); } @@ -1883,7 +1796,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); } @@ -1895,7 +1807,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); } @@ -1907,7 +1818,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); } @@ -1919,7 +1829,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); } @@ -1931,7 +1840,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); } @@ -1943,7 +1851,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); } @@ -1955,7 +1862,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); } @@ -1967,7 +1873,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) { - (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8); } @@ -1995,7 +1900,6 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -2016,7 +1920,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -2037,7 +1940,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -2058,7 +1960,6 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -2079,7 +1980,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -2100,7 +2000,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -2121,7 +2020,6 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); } @@ -2143,7 +2041,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); } @@ -2165,7 +2062,6 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { - (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dmamux.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dmamux.h index 36c24a1281..805caaaf2e 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dmamux.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dmamux.h @@ -102,7 +102,12 @@ extern "C" { #define LL_DMAMUX_REQ_DAC 0x0000001AU /*!< DMAMUX DAC request */ #endif +#if defined(STM32WL3X) #define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_DAC +#else +#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_TIM16_TRG +#endif /* (STM32WL3X) */ + /** * @} */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_lcsc.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_lcsc.h index 5ea914684b..cf941d39fb 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_lcsc.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_lcsc.h @@ -203,7 +203,8 @@ __STATIC_INLINE uint32_t LL_LCSC_GetDampingThreshold_LCAB(LCSC_TypeDef *LCSCx) * @brief Set the duration of TrecoveryVCM (in number of slow clock cycles) * between the enable of the VCMBUFF and the establishment of the Voltage to the value VDD33/2. * @note This time is to be considered between each sequence of LC measurement, called TSCAN in the registers. - * (sequence of LC measurement = LCA, LCB and sometimes LCT). TREC_VCM must not be set to values lower of 0x02 + * (sequence of LC measurement = LCA, LCB and sometimes LCT). + * TREC_VCM must not be set to values lower of 0x02. * @rmtoll CR1 TREC_VCM LL_LCSC_Set_VCMBuff_RecoveryTime * @param LCSCx LCSC Instance * @param value parameter must be a number between 0 and 511 (form 0x0 to 0x1ff) @@ -330,6 +331,29 @@ __STATIC_INLINE uint32_t LL_LCSC_GetLowPulseWidth_LCAB(LCSC_TypeDef *LCSCx) return (uint32_t)(READ_BIT(LCSCx->PULSE_CR, LCSC_PULSE_CR_LCAB_PULSE_WIDTH) >> LCSC_PULSE_CR_LCAB_PULSE_WIDTH_Pos); } +/** + * @brief Set the Pulse trimming for generated pulse. + * @rmtoll PULSE_CR PULSETRIM LL_LCSC_SetLowPulseTrimming + * @param LCSCx LCSC Instance + * @param value parameter must be a number between 0 and 15 (form 0x0 to 0xf) + * @retval None + */ +__STATIC_INLINE void LL_LCSC_SetLowPulseTrimming(LCSC_TypeDef *LCSCx, uint32_t value) +{ + MODIFY_REG(LCSCx->PULSE_CR, LCSC_PULSE_CR_PULSETRIM, value << LCSC_PULSE_CR_PULSETRIM_Pos); +} + +/** + * @brief Get the Pulse trimming for generated pulse. + * @rmtoll PULSE_CR PULSETRIM LL_LCSC_GetLowPulseTrimming + * @param LCSCx LCSC Instance + * @retval the low pulse width trimming value + */ +__STATIC_INLINE uint32_t LL_LCSC_GetLowPulseTrimming(LCSC_TypeDef *LCSCx) +{ + return (uint32_t)(READ_BIT(LCSCx->PULSE_CR, LCSC_PULSE_CR_PULSETRIM) >> LCSC_PULSE_CR_PULSETRIM_Pos); +} + /** * @brief Set the Pulse width programming for generated pulse. * @rmtoll PULSE_CR LCT_PULSE_WIDTH LL_LCSC_SetLowPulseWidth_LCT @@ -592,35 +616,35 @@ __STATIC_INLINE uint32_t LL_LCSC_GetAntiClockWiseTarget(LCSC_TypeDef *LCSCx) /** * @brief Get the LCA Comparator last damping count - * @rmtoll COMP_CTN CMP_LCA_CNT LL_LCSC_GetComparatorLastDampingCount_LCA + * @rmtoll COMP_CNT CMP_LCA_CNT LL_LCSC_GetComparatorLastDampingCount_LCA * @param LCSCx LCSC Instance * @retval the LCA Comparator last damping count */ __STATIC_INLINE uint32_t LL_LCSC_GetComparatorLastDampingCount_LCA(LCSC_TypeDef *LCSCx) { - return (uint32_t)(READ_BIT(LCSCx->COMP_CTN, LCSC_COMP_CTN_CMP_LCA_CNT) >> LCSC_COMP_CTN_CMP_LCA_CNT_Pos); + return (uint32_t)(READ_BIT(LCSCx->COMP_CNT, LCSC_COMP_CNT_CMP_LCA_CNT) >> LCSC_COMP_CNT_CMP_LCA_CNT_Pos); } /** * @brief Get the LCB Comparator last damping count - * @rmtoll COMP_CTN CMP_LCB_CNT LL_LCSC_GetComparatorLastDampingCount_LCB + * @rmtoll COMP_CNT CMP_LCB_CNT LL_LCSC_GetComparatorLastDampingCount_LCB * @param LCSCx LCSC Instance * @retval the LCB Comparator last damping count */ __STATIC_INLINE uint32_t LL_LCSC_GetComparatorLastDampingCount_LCB(LCSC_TypeDef *LCSCx) { - return (uint32_t)(READ_BIT(LCSCx->COMP_CTN, LCSC_COMP_CTN_CMP_LCB_CNT) >> LCSC_COMP_CTN_CMP_LCB_CNT_Pos); + return (uint32_t)(READ_BIT(LCSCx->COMP_CNT, LCSC_COMP_CNT_CMP_LCB_CNT) >> LCSC_COMP_CNT_CMP_LCB_CNT_Pos); } /** * @brief Get the LCT Comparator last damping count - * @rmtoll COMP_CTN CMP_LCT_CNT LL_LCSC_GetComparatorLastDampingCount_LCT + * @rmtoll COMP_CNT CMP_LCT_CNT LL_LCSC_GetComparatorLastDampingCount_LCT * @param LCSCx LCSC Instance * @retval the LCT Comparator last damping count */ __STATIC_INLINE uint32_t LL_LCSC_GetComparatorLastDampingCount_LCT(LCSC_TypeDef *LCSCx) { - return (uint32_t)(READ_BIT(LCSCx->COMP_CTN, LCSC_COMP_CTN_CMP_LCT_CNT) >> LCSC_COMP_CTN_CMP_LCT_CNT_Pos); + return (uint32_t)(READ_BIT(LCSCx->COMP_CNT, LCSC_COMP_CNT_CMP_LCT_CNT) >> LCSC_COMP_CNT_CMP_LCT_CNT_Pos); } /** @@ -668,10 +692,10 @@ __STATIC_INLINE uint32_t LL_LCSC_GetLastDirection(LCSC_TypeDef *LCSCx) } /** - * @brief Get the Minimum of CMP_LCA_CNT, CMP_LCB_CNT reached during the measurement + * @brief Get the Minimum of CMP_LCAB_CNT reached during the measurement * @rmtoll STAT MIN_LCAB_CNT LL_LCSC_GetMin_Counter * @param LCSCx LCSC Instance - * @retval the Minimum of CMP_LCA_CNT + * @retval the Minimum of CMP_LCAB_CNT */ __STATIC_INLINE uint32_t LL_LCSC_GetMin_Counter(LCSC_TypeDef *LCSCx) { @@ -679,10 +703,10 @@ __STATIC_INLINE uint32_t LL_LCSC_GetMin_Counter(LCSC_TypeDef *LCSCx) } /** - * @brief Get the Maximum of CMP_LCA_CNT, CMP_LCB_CNT reached during the measurement + * @brief Get the Maximum of CMP_LCAB_CNT reached during the measurement * @rmtoll STAT MAX_LCAB_CNT LL_LCSC_GetMax_Counter * @param LCSCx LCSC Instance - * @retval the Maximum of CMP_LCA_CNT + * @retval the Maximum of CMP_LCAB_CNT */ __STATIC_INLINE uint32_t LL_LCSC_GetMax_Counter(LCSC_TypeDef *LCSCx) { @@ -690,7 +714,7 @@ __STATIC_INLINE uint32_t LL_LCSC_GetMax_Counter(LCSC_TypeDef *LCSCx) } /** - * @brief Set the Minimum bound of CMP_LCA_COUNT, CMP_LCB_COUNT used when monitoring the MIN_LCAB_CNT + * @brief Set the Minimum bound of CMP_LCAB_COUNT used when monitoring the MIN_LCAB_CNT * @rmtoll STAT MIN_LCAB_CNT_BOUND LL_LCSC_SetMin_CounterOutOfBound * @param LCSCx LCSC Instance * @param value parameter must be a number between 0 and 255 (form 0x0 to 0xff) @@ -702,10 +726,10 @@ __STATIC_INLINE void LL_LCSC_SetMin_CounterOutOfBound(LCSC_TypeDef *LCSCx, uint3 } /** - * @brief Get the Minimum bound of CMP_LCA_COUNT, CMP_LCB_COUNT used when monitoring the MIN_LCAB_CNT + * @brief Get the Minimum bound of CMP_LCAB_COUNT used when monitoring the MIN_LCAB_CNT * @rmtoll STAT MIN_LCAB_CNT_BOUND LL_LCSC_GetMin_CounterOutOfBound * @param LCSCx LCSC Instance - * @retval the Minimum bound of CMP_LCA_COUNT + * @retval the Minimum bound of CMP_LCAB_COUNT */ __STATIC_INLINE uint32_t LL_LCSC_GetMin_CounterOutOfBound(LCSC_TypeDef *LCSCx) { @@ -713,7 +737,7 @@ __STATIC_INLINE uint32_t LL_LCSC_GetMin_CounterOutOfBound(LCSC_TypeDef *LCSCx) } /** - * @brief Set the Maximum bound of CMP_LCA_COUNT, CMP_LCB_COUNT used when monitoring the MAX_LCAB_CNT + * @brief Set the Maximum bound of CMP_LCAB_COUNT used when monitoring the MAX_LCAB_CNT * @rmtoll STAT MAX_LCAB_CNT_BOUND LL_LCSC_SetMax_CounterOutOfBound * @param LCSCx LCSC Instance * @param value parameter must be a number between 0 and 255 (form 0x0 to 0xff) @@ -725,51 +749,16 @@ __STATIC_INLINE void LL_LCSC_SetMax_CounterOutOfBound(LCSC_TypeDef *LCSCx, uint3 } /** - * @brief Get the Maximum bound of CMP_LCA_COUNT, CMP_LCB_COUNT used when monitoring the MAX_LCAB_CNT + * @brief Get the Maximum bound of CMP_LCAB_COUNT used when monitoring the MAX_LCAB_CNT * @rmtoll STAT MAX_LCAB_CNT_BOUND LL_LCSC_GetMax_CounterOutOfBound * @param LCSCx LCSC Instance - * @retval the Maximum bound of CMP_LCA_COUNT + * @retval the Maximum bound of CMP_LCAB_COUNT */ __STATIC_INLINE uint32_t LL_LCSC_GetMax_CounterOutOfBound(LCSC_TypeDef *LCSCx) { return (uint32_t)(READ_BIT(LCSCx->STAT, LCSC_STAT_MAX_LCAB_CNT_BOUND) >> LCSC_STAT_MAX_LCAB_CNT_BOUND_Pos); } -/** - * @brief Get the Revision of the RFIP - * @note to be used for metal fixes - * @rmtoll VER REV LL_LCSC_GetRevision - * @param LCSCx LCSC Instance - * @retval the Revision of the RFIP - */ -__STATIC_INLINE uint32_t LL_LCSC_GetRevision(LCSC_TypeDef *LCSCx) -{ - return (uint32_t)(READ_BIT(LCSCx->VER, LCSC_VER_REV) >> LCSC_VER_REV_Pos); -} - -/** - * @brief Get the Version of the RFIP - * @note to be used for cut upgrades - * @rmtoll VER VER LL_LCSC_GetVersion - * @param LCSCx LCSC Instance - * @retval the Version of the RFIP - */ -__STATIC_INLINE uint32_t LL_LCSC_GetVersion(LCSC_TypeDef *LCSCx) -{ - return (uint32_t)(READ_BIT(LCSCx->VER, LCSC_VER_VER) >> LCSC_VER_VER_Pos); -} - -/** - * @brief Get the Used for major upgrades - * @rmtoll VER PROD LL_LCSC_GetProduct - * @param LCSCx LCSC Instance - * @retval the Used for major upgrades - */ -__STATIC_INLINE uint32_t LL_LCSC_GetProduct(LCSC_TypeDef *LCSCx) -{ - return (uint32_t)(READ_BIT(LCSCx->VER, LCSC_VER_PROD) >> LCSC_VER_PROD_Pos); -} - /** * @brief Indicate if CLKWISE_F is enabled. Clock Wise Flag * @note 0: counter CLKWISE has not reached CLKWISE_THRES @@ -791,7 +780,7 @@ __STATIC_INLINE uint32_t LL_LCSC_IsActiveFlag_CLKWISE(LCSC_TypeDef *LCSCx) */ __STATIC_INLINE void LL_LCSC_ClearFlag_CLKWISE(LCSC_TypeDef *LCSCx) { - SET_BIT(LCSCx->ISR, LCSC_ISR_CLKWISE_F); + WRITE_REG(LCSCx->ISR, LCSC_ISR_CLKWISE_F); } /** @@ -815,7 +804,7 @@ __STATIC_INLINE uint32_t LL_LCSC_IsActiveFlag_ACLKWISE(LCSC_TypeDef *LCSCx) */ __STATIC_INLINE void LL_LCSC_ClearFlag_ACLKWISE(LCSC_TypeDef *LCSCx) { - SET_BIT(LCSCx->ISR, LCSC_ISR_ACLKWISE_F); + WRITE_REG(LCSCx->ISR, LCSC_ISR_ACLKWISE_F); } /** @@ -839,7 +828,7 @@ __STATIC_INLINE uint32_t LL_LCSC_IsActiveFlag_TAMP(LCSC_TypeDef *LCSCx) */ __STATIC_INLINE void LL_LCSC_ClearFlag_TAMP(LCSC_TypeDef *LCSCx) { - SET_BIT(LCSCx->ISR, LCSC_ISR_TAMP_F); + WRITE_REG(LCSCx->ISR, LCSC_ISR_TAMP_F); } /** @@ -863,7 +852,7 @@ __STATIC_INLINE uint32_t LL_LCSC_IsActiveFlag_CNT_OFB(LCSC_TypeDef *LCSCx) */ __STATIC_INLINE void LL_LCSC_ClearFlag_CNT_OFB(LCSC_TypeDef *LCSCx) { - SET_BIT(LCSCx->ISR, LCSC_ISR_CNT_OFB_F); + WRITE_REG(LCSCx->ISR, LCSC_ISR_CNT_OFB_F); } diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_lpawur.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_lpawur.h index b8ee49e08a..1a5156b0e1 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_lpawur.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_lpawur.h @@ -32,6 +32,7 @@ extern "C" { /** @addtogroup STM32WL3x_LL_Driver * @{ */ +#if defined (LPAWUR) /** @addtogroup LPAWUR * @{ @@ -747,8 +748,10 @@ __STATIC_INLINE AgcMode LL_LPAWUR_GetAgcMode(void) * @} */ +#endif /* LPAWUR */ + #ifdef __cplusplus } #endif -#endif /*STM32WL3x_LL_LPAWUR_H */ +#endif /*STM32WL3x_LL_LPAWUR_H */ \ No newline at end of file diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_mrsubg.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_mrsubg.h index 4a0974ff0e..87bced5968 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_mrsubg.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_mrsubg.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2024-2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -16,7 +16,7 @@ ****************************************************************************** */ - /* Define to prevent recursive inclusion -------------------------------------*/ +/* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32WL3x_LL_MRSUBG_H #define STM32WL3x_LL_MRSUBG_H @@ -39,30 +39,48 @@ extern "C" { /** @defgroup MRSUBG_LL_Private_Constants MRSUBG Private Constants * @{ */ + +/* Legacy aliases */ #if defined(IS_169MHZ) - /* WL33xA */ - #define HIGH_BAND_FACTOR 8 /*!< Band select factor for high band. Factor B in the equation of the user manual */ - #define LOW_BAND_FACTOR 20 /*!< Band select factor for middle band. Factor B in the equation of the user manual */ - - #define LOW_BAND_LOWER_LIMIT 159200000 /*!< Lower limit of the low band */ - #define LOW_BAND_UPPER_LIMIT 185600000 /*!< Upper limit of the low band */ - #define HIGH_BAND_LOWER_LIMIT 398000000 /*!< Lower limit of the high band */ - #define HIGH_BAND_UPPER_LIMIT 464000000 /*!< Upper limit of the high band */ +#define STM32WL33XA +#endif /* IS_169MHZ */ + +#if defined(STM32WL33XA) +/* WL33xA */ +#define LOW_BAND_FACTOR 20 /*!< Band select factor for middle band. Factor B in the equation of the user manual */ +#define HIGH_BAND_FACTOR 8 /*!< Band select factor for high band. Factor B in the equation of the user manual */ + +#define LOW_BAND_LOWER_LIMIT 159200000 /*!< Lower limit of the low band */ +#define LOW_BAND_UPPER_LIMIT 185600000 /*!< Upper limit of the low band */ +#define HIGH_BAND_LOWER_LIMIT 398000000 /*!< Lower limit of the high band */ +#define HIGH_BAND_UPPER_LIMIT 464000000 /*!< Upper limit of the high band */ #else - /* WL33x */ - #define HIGH_BAND_FACTOR 4 /*!< Band select factor for high band. Factor B in the equation of the user manual */ - #define LOW_BAND_FACTOR 8 /*!< Band select factor for middle band. Factor B in the equation of the user manual */ - -#define LOW_BAND_LOWER_LIMIT 413000000 /*!< Lower limit of the low band */ -#define LOW_BAND_UPPER_LIMIT 479000000 /*!< Upper limit of the low band */ -#define HIGH_BAND_LOWER_LIMIT 826000000 /*!< Lower limit of the high band */ -#define HIGH_BAND_UPPER_LIMIT 958000000 /*!< Upper limit of the high band */ -#endif +#if defined(STM32WL3RX) +/* WL3x including WL3Rx at 315 MHz */ +#define LOW_LOW_BAND_FACTOR 12 /*!< Band select factor for middle band. Factor B in the equation of the user manual */ +#endif /* STM32WL3RX */ + +#define LOW_BAND_FACTOR 8 /*!< Band select factor for middle band. Factor B in the equation of the user manual */ +#define HIGH_BAND_FACTOR 4 /*!< Band select factor for high band. Factor B in the equation of the user manual */ + +#if defined(STM32WL3RX) +#define LOW_LOW_BAND_LOWER_LIMIT 275500000 /*!< Lower limit of the low low band */ +#define LOW_LOW_BAND_UPPER_LIMIT 318500000 /*!< Upper limit of the low low band */ +#endif /* STM32WL3RX */ + +#define LOW_BAND_LOWER_LIMIT 413000000 /*!< Lower limit of the low band */ +#define LOW_BAND_UPPER_LIMIT 479000000 /*!< Upper limit of the low band */ +#define HIGH_BAND_LOWER_LIMIT 826000000 /*!< Lower limit of the high band */ +#define HIGH_BAND_UPPER_LIMIT 958000000 /*!< Upper limit of the high band */ +#endif /* STM32WL33XA */ -#define MINIMUM_DATARATE 100 /*!< Minimum datarate supported by STM32WL3 100 bps */ -#define MAXIMUM_DATARATE 300000 /*!< Maximum datarate supported by STM32WL3 300 ksps (600 kbps) */ +#define MINIMUM_DATARATE 100 /*!< Minimum datarate supported by STM32WL3x 100 bps */ +#define MAXIMUM_DATARATE 300000 /*!< Maximum datarate supported by STM32WL3x 300 ksps (600 kbps) */ + +/* If we use SEQ_F as the only flag bit to match on, \ +then a match can never occur because SEQ_F is only set when the sequencer terminates. */ +#define SEQ_MASK_NEVER_MATCH MR_SUBG_GLOB_STATUS_RFSEQ_IRQ_STATUS_SEQ_F -#define SEQ_MASK_NEVER_MATCH MR_SUBG_GLOB_STATUS_RFSEQ_IRQ_STATUS_SEQ_F /* If we use SEQ_F as the only flag bit to match on, then a match can never occur because SEQ_F is only set when the sequencer terminates. */ #define SEQ_MASK_ALWAYS_MATCH 0x00000000 /* The Sequencer automatically matches a null mask */ /** @@ -70,11 +88,11 @@ extern "C" { */ /** @defgroup MRSUBG_LL_Exported_Macros MRSUBG Exported Macros -* @{ + * @{ */ -#define IS_PREAMBLE_LEN(VAL) (VAL<=2046) -#define IS_POSTAMBLE_LEN(VAL) (VAL<=126) +#define IS_PREAMBLE_LEN(VAL) (VAL<=2046) +#define IS_POSTAMBLE_LEN(VAL) (VAL<=126) #define IS_SYNC_LEN(VAL) (VAL<=32) #define IS_FRAME_LEN(VAL) (VAL>=2) && (VAL<=2047) #define IS_PREAMBLE_15_4G_LEN(VAL) (((VAL)>=4) && ((VAL)<=64)) @@ -82,19 +100,19 @@ extern "C" { #define IS_MODULATION_15_4G(MOD) (((MOD) == MOD_2FSK) || ((MOD) == MOD_4FSK)) #define IS_FCS_TYPE(TYPE) (((TYPE) == FCS_16BIT) || \ - ((TYPE) == FCS_32BIT)) + ((TYPE) == FCS_32BIT)) #define IS_FEC_TYPE(TYPE) (((TYPE) == FEC_15_4_G_NONE) || \ - ((TYPE) == FEC_15_4_G_NRNSC) || \ - ((TYPE) == FEC_15_4_G_RSC) || \ - ((TYPE) == FEC_15_4_G_RSC_Interleaving)) + ((TYPE) == FEC_15_4_G_NRNSC) || \ + ((TYPE) == FEC_15_4_G_RSC) || \ + ((TYPE) == FEC_15_4_G_RSC_Interleaving)) #define IS_WMBUS_SUBMODE(MODE) (((MODE) == WMBUS_SUBMODE_S1_S2_LONG_HEADER) || \ - ((MODE) == WMBUS_SUBMODE_NOT_CONFIGURED) || \ - ((MODE) == WMBUS_SUBMODE_S1_M_S2_T2_OTHER_TO_METER) || \ - ((MODE) == WMBUS_SUBMODE_T1_T2_METER_TO_OTHER) || \ - ((MODE) == WMBUS_SUBMODE_R2_SHORT_HEADER)) + ((MODE) == WMBUS_SUBMODE_NOT_CONFIGURED) || \ + ((MODE) == WMBUS_SUBMODE_S1_M_S2_T2_OTHER_TO_METER) || \ + ((MODE) == WMBUS_SUBMODE_T1_T2_METER_TO_OTHER) || \ + ((MODE) == WMBUS_SUBMODE_R2_SHORT_HEADER)) /** @brief Macro that checks if SELECTION is a MRSubG_WhiteningBeforeFECType */ #define IS_WHITEFEC_SELECTION(SELECTION) (((SELECTION) == FEC_THEN_WHITENING) || ((SELECTION) == WHITENING_THEN_FEC)) @@ -110,41 +128,76 @@ extern "C" { * @{ */ /** -* @brief STM32WL3 MRSUBG PA modes -*/ -typedef enum{ + * @brief STM32WL3x MRSUBG PA modes + */ +typedef enum +{ PA_LEGACY = 0x00, /* legacy mode */ PA_FIR = 0x01, /* FIR active (to be used in ASK/OOK modulation only) */ PA_DIRECT = 0x02 /* Direct mode */ } MRSubG_PAMode; /** -* @brief STM32WL3 PA drive modes -*/ -typedef enum{ + * @brief STM32WL3x PA drive modes + */ +typedef enum +{ PA_DRV_TX = 0x01, /* up to 10dBm */ PA_DRV_TX_HP = 0x02, /* up to 14dBm */ PA_DRV_TX_TX_HP = 0x03 /* up to 20dBm */ } MRSubG_PA_DRVMode; /** - * @brief STM32WL3 Commands codes enumeration + * @enum SQI_Threshold + * @brief Defines the SQI threshold for SYNC word detection tolerance. + * + * This enum represents the allowed number of bit errors tolerated when detecting + * the SYNC word in the SQI (SYNC Quality Indicator) threshold for SYNC word detection tolerance. The value corresponds + * to the maximum number of bit mismatches accepted between the detected SYNC word + * and the expected SYNC word. + * + * The SQI_THR field occupies bits 18:16 in the relevant control register. + * + * Values: + * - SQI_THR_PERFECT_MATCH (0): No bit errors allowed; exact match required. + * - SQI_THR_1_BIT_ERROR (1): Up to 1 bit error tolerated. + * - ... + * - SQI_THR_7_BIT_ERROR (7): Up to 7 bit errors tolerated. + */ +typedef enum +{ + SQI_THR_PERFECT_MATCH = 0, /* 0 bit error accepted */ + SQI_THR_1_BIT_ERROR = 1, /* 1 bit error accepted */ + SQI_THR_2_BIT_ERROR = 2, /* 2 bits error accepted */ + SQI_THR_3_BIT_ERROR = 3, /* 3 bits error accepted */ + SQI_THR_4_BIT_ERROR = 4, /* 4 bits error accepted */ + SQI_THR_5_BIT_ERROR = 5, /* 5 bits error accepted */ + SQI_THR_6_BIT_ERROR = 6, /* 6 bits error accepted */ + SQI_THR_7_BIT_ERROR = 7 /* 7 bits error accepted */ +} SQI_Threshold; + +/** + * @brief STM32WL3x Commands codes enumeration */ typedef enum { - CMD_NOP = ((uint8_t)(0x00)), /* No action. This 'no' command can be requested at any time, whatever the on-going command or in IDLE */ - CMD_TX = ((uint8_t)(0x01)), /* Start a TX sequence */ - CMD_RX = ((uint8_t)(0x02)), /* Start a RX sequence */ - CMD_LOCKRX = ((uint8_t)(0x03)), /* Start a RF sequence up to PLL locked based on RX frequency */ - CMD_LOCKTX = ((uint8_t)(0x04)), /* Start a RF sequence up to PLL locked based on TX frequency */ - CMD_SABORT = ((uint8_t)(0x05)), /* Stop any on-going RX/TX/LOCKRX/LOCKTX command */ - CMD_CALIB_SAFEASK = ((uint8_t)(0x0A)), /* Launch a PA Safe-ASK calibration to get the max safe PA code to be used */ - CMD_RELOAD_RX_TIMER = ((uint8_t)(0x06)), /* Reload with a new timeout and new stop conditions and restart the RX Timer */ - CMD_CALIB_AGC = ((uint8_t)(0x0B)) /* Start needed HW features to run an AGC_ATTEN trim sequence at SW level */ + CMD_NOP = ((uint8_t)(0x00)), /* No action. This 'no' command can be requested at any time, \ + whatever the on-going command or in IDLE */ + CMD_TX = ((uint8_t)(0x01)), /* Start a TX sequence */ + CMD_RX = ((uint8_t)(0x02)), /* Start a RX sequence */ + CMD_LOCKRX = ((uint8_t)(0x03)), /* Start a RF sequence up to PLL locked based on RX frequency */ + CMD_LOCKTX = ((uint8_t)(0x04)), /* Start a RF sequence up to PLL locked based on TX frequency */ + CMD_SABORT = ((uint8_t)(0x05)), /* Stop any on-going RX/TX/LOCKRX/LOCKTX command */ + CMD_CALIB_SAFEASK = ((uint8_t)(0x0A)), /* Launch a PA Safe-ASK calibration to get the max safe \ + PA code to be used */ + CMD_RELOAD_RX_TIMER = ((uint8_t)(0x06)), /* Reload with a new timeout and \ + new stop conditions and restart the RX Timer */ + CMD_CALIB_AGC = ((uint8_t)(0x0B)) /* Start needed HW features to run an AGC_ATTEN trim \ + sequence at SW level */ } MRSubGCmd; /** - * @brief STM32WL3 MRSUBG FSM state enumaration + * @brief STM32WL3x MRSUBG FSM state enumaration */ typedef enum { @@ -170,53 +223,66 @@ typedef enum } MRSubGFSMState; /** -* @brief BT Values for GFSK -*/ -typedef enum { + * @brief BT Values for GFSK + */ +typedef enum +{ BT_1 = 0, BT_05 = 1 } MRSubG_BTSelect; /** - * @brief STM32WL3 Transmission modes - */ -typedef enum { + * @brief STM32WL3x Transmission modes + */ +typedef enum +{ ISI_EQ_DISABLED = 0x00, ISI_EQ_SP = 0x01, ISI_EQ_DP = 0x02 } MRSubG_ISIEQMode; /** - * @brief STM32WL3 Transmission modes - */ -typedef enum{ - TX_NORMAL = 0x00, /* Only payload is provided through RAM buffers Rest of the frame built from configuration registers (PREAMBLE, SYNC, CRC...). */ - TX_DIRECT_BUFFERS = 0x01, /* Full bit stream (including PREAMBLE, SYNC, CRC...) to be provided through RAM buffers. */ - TX_DIRECT_GPIO = 0x02, /* Full bit stream (including PREAMBLE, SYNC, CRC...) to be provided serially through the TX DATA GPIO. */ + * @brief STM32WL3x Transmission modes + */ +typedef enum +{ + TX_NORMAL = 0x00, /* Only payload is provided through RAM buffers Rest of the frame built from \ + configuration registers (PREAMBLE, SYNC, CRC...). */ + TX_DIRECT_BUFFERS = 0x01, /* Full bit stream (including PREAMBLE, SYNC, CRC...) to be \ + provided through RAM buffers. */ + TX_DIRECT_GPIO = 0x02, /* Full bit stream (including PREAMBLE, SYNC, CRC...) to be \ + provided serially through the TX DATA GPIO. */ TX_PN = 0x03 /* Internal PN generator send a polynomial bit stream on the antenna. */ } MRSubGTXMode; /** - * @brief STM32WL3 Reception modes - */ -typedef enum{ - RX_NORMAL = 0x00, /* Only payload is stored into the RAM buffers. CRC and packet length are readable in dedicated status registers */ + * @brief STM32WL3x Reception modes + */ +typedef enum +{ + RX_NORMAL = 0x00, /* Only payload is stored into the RAM buffers. \ + CRC and packet length are readable in dedicated status registers */ RX_DIRECT_BUFFERS = 0x01, /* Full bit stream is stored into the RAM buffers. */ RX_DIRECT_GPIO = 0x02, /* Full bit stream is provided serially through the RX DATA GPIO */ - RX_IQ_SAMPLING = 0x03, /* Raw I/Q sampling taken at the output of the Channel filter inside the demodulator are stored in RAM. */ - RX_FREQDETEC_SAMPLING = 0x04, /* Raw data taken at the output of the frequency detector inside the demodulator (detection of the instantaneous frequency changes) are stored in RAM. */ - RX_SOFTBIT_SAMPLING = 0x05 /* Raw data taken at the output of the post-filter inside the demodulator (soft bits before the 0/1 detection) are stored in RAM. */ + RX_IQ_SAMPLING = 0x03, /* Raw I/Q sampling taken at the output of the Channel filter \ + inside the demodulator are stored in RAM. */ + RX_FREQDETEC_SAMPLING = 0x04, /* Raw data taken at the output of the frequency detector inside the \ + demodulator (detection of the instantaneous frequency changes) are stored in RAM. */ + RX_SOFTBIT_SAMPLING = 0x05 /* Raw data taken at the output of the post-filter inside the \ + demodulator (soft bits before the 0/1 detection) are stored in RAM. */ } MRSubGRXMode; /** - * @brief STM32WL3 preamble pattern enumeration + * @brief STM32WL3x preamble pattern enumeration */ typedef enum { PRE_SEQ_0101 = 0x00, /* Suitable for 2-(G)FSK and ASK/OOK */ PRE_SEQ_1010 = 0x01, /* Suitable for 2-(G)FSK and ASK/OOK */ - PRE_SEQ_0011 = 0x02, /* Suitable for 2-(G)FSK and ASK/OOK (not recommended - not the most convenient for the receiver) */ - PRE_SEQ_1100 = 0x03, /* Suitable for 2-(G)FSK and ASK/OOK (not recommended - not the most convenient for the receiver) */ + PRE_SEQ_0011 = 0x02, /* Suitable for 2-(G)FSK and ASK/OOK \ + (not recommended - not the most convenient for the receiver) */ + PRE_SEQ_1100 = 0x03, /* Suitable for 2-(G)FSK and ASK/OOK \ + (not recommended - not the most convenient for the receiver) */ PRE_SEQ_0111 = 0x00, /* Suitable for 4-(G)FSK */ PRE_SEQ_0010 = 0x01, /* Suitable for 4-(G)FSK */ PRE_SEQ_1101 = 0x02, /* Suitable for 4-(G)FSK */ @@ -224,7 +290,7 @@ typedef enum } MRSubG_PreambleSeq; /** - * @brief STM32WL3 preamble pattern enumeration + * @brief STM32WL3x preamble pattern enumeration */ typedef enum { @@ -234,19 +300,19 @@ typedef enum } MRSubG_PostambleSeq; /** -* @brief STM32WL3 packet coding options -*/ + * @brief STM32WL3x packet coding options + */ typedef enum { - CODING_NONE = 0x00, /* None */ - CODING_FEC = 0x01, /* FEC in TX / Viterbi in RX */ - CODING_3o6 = 0x02, /* 3of6 coding */ - CODING_MANCHESTER = 0x03 /* Manchester coding */ + CODING_NONE = 0x00, /* None */ + CODING_FEC = 0x01, /* FEC in TX / Viterbi in RX */ + CODING_3o6 = 0x02, /* 3of6 coding */ + CODING_MANCHESTER = 0x03 /* Manchester coding */ } MRSubG_PcktCoding; /** -* @brief Whitening before FEC feature -*/ + * @brief Whitening before FEC feature + */ typedef enum { FEC_THEN_WHITENING = 0, @@ -254,10 +320,10 @@ typedef enum } MRSubG_WhiteningBeforeFECType; /** - * @brief Manchester encoding polarity. - * 0: "0" is encoded with "01" and "1" is encoded with "10" - * 1: "0" is encoded with "10" and "1" is encoded with "01" - */ + * @brief Manchester encoding polarity. + * 0: "0" is encoded with "01" and "1" is encoded with "10" + * 1: "0" is encoded with "10" and "1" is encoded with "01" + */ typedef enum { MANCHESTER_TYPE0 = 0, @@ -265,53 +331,56 @@ typedef enum } MRSubG_ManchesterPolarity; /** - * @brief CRC length in bytes enumeration. - */ -typedef enum { + * @brief CRC length in bytes enumeration. + */ +typedef enum +{ PKT_NO_CRC = 0x00, /*!< No CRC */ PKT_CRC_MODE_8BITS = 0x01, /*!< CRC length 8 bits - poly: 0x07 */ PKT_CRC_MODE_16BITS_1 = 0x02, /*!< CRC length 16 bits - poly: 0x8005 */ PKT_CRC_MODE_16BITS_2 = 0x03, /*!< CRC length 16 bits - poly: 0x1021 */ - FCS_16BIT = 0x03, /*!< CRC length 16 bits - poly: 0x1021 */ + FCS_16BIT = 0x03, /*!< CRC length 16 bits - poly: 0x1021 */ PKT_CRC_MODE_24BITS = 0x04, /*!< CRC length 24 bits - poly: 0x864CFB */ PKT_CRC_MODE_32BITS = 0x05, /*!< CRC length 32 bits - poly: 0x04C11DB7 */ - FCS_32BIT = 0x05, /*!< CRC length 32 bits - poly: 0x04C11DB7 */ + FCS_32BIT = 0x05, /*!< CRC length 32 bits - poly: 0x04C11DB7 */ } MRSubG_PcktCrcMode; /** - * @brief Fixed or Variable length mode. - * 0: FIXED length mode (no LENGTH field added in the frame in TX and no decode in RX) - * 1: VARIABLE length mode (LENGTH field put in the frame in TX and decoded in RX) - */ + * @brief Fixed or Variable length mode. + * 0: FIXED length mode (no LENGTH field added in the frame in TX and no decode in RX) + * 1: VARIABLE length mode (LENGTH field put in the frame in TX and decoded in RX) + */ typedef enum { - FIXED = 0, - VARIABLE = !FIXED + FIXED = 0, + VARIABLE = !FIXED } MRSubG_LengthMode; /** - * @brief 1 or 2 bytes length width. - * 0: LENGTH bit field is defined on 1 byte - * 1: LENGTH bit field is defined on 2 bytes - */ + * @brief 1 or 2 bytes length width. + * 0: LENGTH bit field is defined on 1 byte + * 1: LENGTH bit field is defined on 2 bytes + */ typedef enum { - BYTE_LEN_1 = 0, - BYTES_LEN_2 = 1 + BYTE_LEN_1 = 0, + BYTES_LEN_2 = 1 } MRSubG_LenWidthhMode; /** -* @brief STM32WL3 Frequency Band IDs -*/ -typedef enum{ + * @brief STM32WL3x Frequency Band IDs + */ +typedef enum +{ FQCY_STANDARD = 0x00, /* Standard band */ FQCY_169MHZ = 0x03 /* 169 MHz band */ } MRSubG_Frequency_ID; /** - * @brief Sequencer flag bits - */ -typedef enum { + * @brief Sequencer flag bits + */ +typedef enum +{ /* Indicating if the low power mode was allowed during the wait interval since last SeqAction execution */ SEQ_FLAG_SLEEPENABLE = 0x01, @@ -323,42 +392,48 @@ typedef enum { } MRSubG_Sequencer_Flags; -typedef struct MRSubG_Sequencer_ActionConfiguration MRSubG_Sequencer_ActionConfiguration; +typedef struct MRSubG_Sequencer_ActionConfiguration_t MRSubG_Sequencer_ActionConfiguration_t; /** - * @brief Sequencer ActionConfiguration RAM table structure - */ -struct MRSubG_Sequencer_ActionConfiguration { + * @brief Sequencer ActionConfiguration RAM table structure + */ +struct MRSubG_Sequencer_ActionConfiguration_t +{ /* * NextAction1 */ /** Pointer to NextAction1, executed upon NextAction1Mask match. */ - MRSubG_Sequencer_ActionConfiguration* NextAction1Ptr; + MRSubG_Sequencer_ActionConfiguration_t *NextAction1Ptr; /** Time to wait before NextAction1 execution, in interpolated absolute time units. */ uint32_t NextAction1Interval; - /** Bitmask for NextAction1 - if SubGHz status register against matches against this mask, NextAction1 is performed next. */ + /** Bitmask for NextAction1 - if SubGHz status register against matches against this mask, \ + * NextAction1 is performed next. */ uint32_t NextAction1Mask; - /** Configuration flags (ForceClearEvents, ForceReload and SleepEn) for sequencer hardware, set if NextAction1 is performed next. */ + /** Configuration flags (ForceClearEvents, ForceReload and SleepEn) for sequencer hardware, \ + * set if NextAction1 is performed next. */ uint32_t NextAction1Ctrl; /* NextAction2 */ /** Pointer to NextAction2, executed upon NextAction1Mask match. */ - MRSubG_Sequencer_ActionConfiguration* NextAction2Ptr; + MRSubG_Sequencer_ActionConfiguration_t *NextAction2Ptr; /** Time to wait before NextAction2 execution, in interpolated absolute time units. */ uint32_t NextAction2Interval; - /** Bitmask for NextAction2 - if SubGHz status register against matches against this mask, NextAction2 is performed next. */ + /** Bitmask for NextAction2 - if SubGHz status register against matches against this mask, \ + * NextAction2 is performed next. */ uint32_t NextAction2Mask; - /** Configuration flags (ForceClearEvents, ForceReload and SleepEn) for sequencer hardware, set if NextAction2 is performed next. */ + /** Configuration flags (ForceClearEvents, ForceReload and SleepEn) for sequencer hardware, \ + * set if NextAction2 is performed next. */ uint32_t NextAction2Ctrl; - /** Time to wait for either NextAction1Mask or NextAction2Mask match before aborting, in interpolated absolute time units. - * Set to 0 for no timeout. */ + /** Time to wait for either NextAction1Mask or NextAction2Mask match before aborting, \ + * in interpolated absolute time units. + * Set to 0 for no timeout. */ uint32_t ActionTimeout; /** Dynamic Register Configuration, applied for the current action. */ @@ -366,18 +441,19 @@ struct MRSubG_Sequencer_ActionConfiguration { }; /** - * @brief Sequencer GlobalConfiguration RAM table structure - */ -typedef struct { + * @brief Sequencer GlobalConfiguration RAM table structure + */ +typedef struct +{ /** Pointer to first ActionConfiguration */ - volatile MRSubG_Sequencer_ActionConfiguration* ActionConfigPtr; + volatile MRSubG_Sequencer_ActionConfiguration_t *ActionConfigPtr; /** Configuration flags (ForceClearEvents, ForceReload and SleepEn) for sequencer hardware. */ volatile uint32_t Flags; /** SubGHz static configuration registers. */ MR_SUBG_GLOB_STATIC_TypeDef StaticConfigReg; -} MRSubG_Sequencer_GlobalConfiguration; +} MRSubG_Sequencer_GlobalConfiguration_t; /** * @} @@ -389,687 +465,854 @@ typedef struct { */ /** -* @brief Set the PA Mode. -* @param paMode the PA Mode. -* @retval None. -*/ -__STATIC_INLINE void LL_MRSubG_SetPAMode(MRSubG_PAMode paMode){ + * @brief Set the PA Mode. + * @param paMode the PA Mode. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetPAMode(MRSubG_PAMode paMode) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PA_CONFIG, MR_SUBG_GLOB_STATIC_PA_CONFIG_PA_MODE, paMode); } /** -* @brief Set the PA Drive Mode. -* @param paDrvMode the PA Drive Mode. -* @retval None. -*/ -__STATIC_INLINE void LL_MRSubG_SetPADriveMode(MRSubG_PA_DRVMode paDrvMode){ + * @brief Get the PA Mode. + * @retval The PA Mode. + */ +__STATIC_INLINE MRSubG_PAMode LL_MRSubG_GetPAMode(void) +{ + return (MRSubG_PAMode)READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PA_CONFIG, MR_SUBG_GLOB_STATIC_PA_CONFIG_PA_MODE); +} + +/** + * @brief Set the PA Drive Mode. + * @param paDrvMode the PA Drive Mode. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetPADriveMode(MRSubG_PA_DRVMode paDrvMode) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PA_CONFIG, MR_SUBG_GLOB_STATIC_PA_CONFIG_PA_DRV_MODE, paDrvMode); } /** -* @brief Get the PA Drive Mode. -* @retval The PA Drive Mode. -*/ -__STATIC_INLINE MRSubG_PA_DRVMode LL_MRSubG_GetPADriveMode(void){ + * @brief Get the PA Drive Mode. + * @retval The PA Drive Mode. + */ +__STATIC_INLINE MRSubG_PA_DRVMode LL_MRSubG_GetPADriveMode(void) +{ return (MRSubG_PA_DRVMode) READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PA_CONFIG, MR_SUBG_GLOB_STATIC_PA_CONFIG_PA_DRV_MODE); } /** -* @brief Force the SYNC word to be formatted as 2-(G)FSK bit mapping instead of 4-(G)FSK. -* @param forceSync DISABLE: the SYNC word is treated in 4-(G)FSK mapping as the rest of the frame. -* ENABLE: the SYNC word of the frame is mapped as follows -* '1' is mapped to +Fdev; '0' is mapped to -Fdev for constellation mapping = 0 and 1 -* '1' is mapped to -Fdev; '0' is mapped to +Fdev for constellation mapping = 2 and 3 -* @retval None. -*/ -__STATIC_INLINE void LL_MRSubG_Force2FSKSync(FunctionalState forceSync){ - if(forceSync == ENABLE) + * @brief Force the SYNC word to be formatted as 2-(G)FSK bit mapping instead of 4-(G)FSK. + * @param forceSync DISABLE: the SYNC word is treated in 4-(G)FSK mapping as the rest of the frame. + * ENABLE: the SYNC word of the frame is mapped as follows + * '1' is mapped to +Fdev; '0' is mapped to -Fdev for constellation mapping = 0 and 1 + * '1' is mapped to -Fdev; '0' is mapped to +Fdev for constellation mapping = 2 and 3 + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_Force2FSKSync(FunctionalState forceSync) +{ + if (forceSync == ENABLE) + { SET_BIT(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_FORCE_2FSK_SYNC_MODE); + } else CLEAR_BIT(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_FORCE_2FSK_SYNC_MODE); } /** - * @brief Set the CONST_MAP configuration for - * 2-(G)FSK or 4-(G)FSK - * @param nConMap the configuration. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetConstellationMapping(uint8_t nConMap){ + * @brief Set the CONST_MAP configuration for + * 2-(G)FSK or 4-(G)FSK + * @param nConMap the configuration. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetConstellationMapping(uint8_t nConMap) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_CONST_MAP, nConMap); } /** - * @brief Invert bit to symbol mapping for 4(G)FSK - * @param xNewState new state for FOUR_FSK_SYM_SWAP bit - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SwapSymbolMapping(FunctionalState xNewState){ - if(xNewState == ENABLE) + * @brief Invert bit to symbol mapping for 4(G)FSK + * @param xNewState new state for FOUR_FSK_SYM_SWAP bit + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SwapSymbolMapping(FunctionalState xNewState) +{ + if (xNewState == ENABLE) + { SET_BIT(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_FOUR_FSK_SYM_SWAP); + } else CLEAR_BIT(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_FOUR_FSK_SYM_SWAP); } /** - * @brief Select BT value for GFSK - * @param bSel BT value - * This value is type of @ref MRSubG_BTSelect. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetBTSel(MRSubG_BTSelect bSel){ - if(bSel == BT_05) + * @brief Select BT value for GFSK + * @param bSel BT value + * This value is type of @ref MRSubG_BTSelect. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetBTSel(MRSubG_BTSelect bSel) +{ + if (bSel == BT_05) + { SET_BIT(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_BT_SEL); + } else CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_BT_SEL); } /** - * @brief Select BT value for GFSK - * @param xNewState BT value - * This value is type of @ref MRSubG_BTSelect. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetFrequencyInterpolator(FunctionalState xNewState){ - if(xNewState == ENABLE) + * @brief Select BT value for GFSK + * @param xNewState BT value + * This value is type of @ref MRSubG_BTSelect. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetFrequencyInterpolator(FunctionalState xNewState) +{ + if (xNewState == ENABLE) + { SET_BIT(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_MOD_INTERP_EN); + } else CLEAR_BIT(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_MOD_INTERP_EN); } /** - * @brief Set the ISI cancellation equalizer - * @param isiEq the Equalizer value - * This value is type of @ref MRSubG_ISIEQMode. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetISIEqualizer(MRSubG_ISIEQMode isiEq){ + * @brief Set the ISI cancellation equalizer + * @param isiEq the Equalizer value + * This value is type of @ref MRSubG_ISIEQMode. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetISIEqualizer(MRSubG_ISIEQMode isiEq) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_AS_EQU_CTRL, isiEq); } /** - * @brief Send a specific command to the STM32WL3. - * @param xCommandCode code of the command to send. + * @brief Send a specific command to the STM32WL3x. + * @param xCommandCode code of the command to send. This parameter can be any value of @ref MRSubGCmd. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_StrobeCommand(MRSubGCmd xCommandCode) { + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_StrobeCommand(MRSubGCmd xCommandCode) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->COMMAND, MR_SUBG_GLOB_DYNAMIC_COMMAND_COMMAND_ID, xCommandCode); } /** - * @brief Set the TX_MODE field of the PCKT_CTRL register. - * @param txMode The TX Mode. - * This parameter can be any value of @ref MRSubGTXMode. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetTXMode(MRSubGTXMode txMode){ + * @brief Set the TX_MODE field of the PCKT_CTRL register. + * @param txMode The TX Mode. + * This parameter can be any value of @ref MRSubGTXMode. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetTXMode(MRSubGTXMode txMode) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_TX_MODE, txMode); } /** - * @brief Sets the RX_MODE field of PCKT_CTRL register. - * @param rxMode the rx mode. - * This parameter can be any value of @ref MRSubGRXMode. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetRXMode(MRSubGRXMode rxMode){ + * @brief Sets the RX_MODE field of PCKT_CTRL register. + * @param rxMode the rx mode. + * This parameter can be any value of @ref MRSubGRXMode. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetRXMode(MRSubGRXMode rxMode) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_RX_MODE, rxMode); } /** -* @brief Sets the channel number. -* @param cChannel the channel number. -* @retval None. -*/ -__STATIC_INLINE void LL_MRSubG_SetChannel(uint8_t cChannel){ + * @brief Sets the channel number. + * @param cChannel the channel number. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetChannel(uint8_t cChannel) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->ADDITIONAL_CTRL, MR_SUBG_GLOB_DYNAMIC_ADDITIONAL_CTRL_CH_NUM, cChannel); } /** -* @brief Returns the actual channel number. -* @retval uint8_t Actual channel number. -*/ -__STATIC_INLINE uint8_t LL_MRSubG_GetChannel(void){ + * @brief Returns the actual channel number. + * @retval uint8_t Actual channel number. + */ +__STATIC_INLINE uint8_t LL_MRSubG_GetChannel(void) +{ return READ_REG(MR_SUBG_GLOB_DYNAMIC->ADDITIONAL_CTRL) & MR_SUBG_GLOB_DYNAMIC_ADDITIONAL_CTRL_CH_NUM; } /** -* @brief Set the channel spacing factor in channel space register. -* The channel spacing is From ~732 Hz to ~187 kHz in 732 Hz steps -* @param lChannelSpace the channel spacing expressed in Hz. -* @retval None. -*/ -__STATIC_INLINE void LL_MRSubG_SetChannelSpace(uint8_t lChannelSpace){ - MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->ADDITIONAL_CTRL, MR_SUBG_GLOB_DYNAMIC_ADDITIONAL_CTRL_CH_SPACING, lChannelSpace); + * @brief Set the channel spacing factor in channel space register. + * The channel spacing is From ~732 Hz to ~187 kHz in 732 Hz steps + * @param lChannelSpace the channel spacing expressed in Hz. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetChannelSpace(uint8_t lChannelSpace) +{ + MODIFY_REG_FIELD( + MR_SUBG_GLOB_DYNAMIC->ADDITIONAL_CTRL, + MR_SUBG_GLOB_DYNAMIC_ADDITIONAL_CTRL_CH_SPACING, + lChannelSpace + ); } /** -* @brief Return the channel space register. -* @retval uint8_t Channel spacing. -*/ -__STATIC_INLINE uint8_t LL_MRSubG_GetChannelSpace(void){ - return READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->ADDITIONAL_CTRL, MR_SUBG_GLOB_DYNAMIC_ADDITIONAL_CTRL_CH_SPACING); + * @brief Return the channel space register. + * @retval uint8_t Channel spacing. + */ +__STATIC_INLINE uint8_t LL_MRSubG_GetChannelSpace(void) +{ + return READ_REG_FIELD( + MR_SUBG_GLOB_DYNAMIC->ADDITIONAL_CTRL, + MR_SUBG_GLOB_DYNAMIC_ADDITIONAL_CTRL_CH_SPACING + ); } /** -* @brief Set the PA_DEGEN_ON bit. This will Enable/Disable a degeneration mode, which introduces a pre-distortion to linearize the power control curve. -* @param xNewState enable (ENABLE) to enable or disable (DISABLE) the degeneration. -* @retval None. -*/ -__STATIC_INLINE void LL_MRSubG_SetPADegen(FunctionalState xNewState) { - if(xNewState == ENABLE) { + * @brief Set the PA_DEGEN_ON bit. This will Enable/Disable a degeneration mode, \ + * which introduces a pre-distortion to linearize the power control curve. + * @param xNewState enable (ENABLE) to enable or disable (DISABLE) the degeneration. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetPADegen(FunctionalState xNewState) +{ + if (xNewState == ENABLE) + { SET_BIT(MR_SUBG_RADIO->PA_REG, MR_SUBG_RADIO_PA_REG_PA_DEGEN_ON); - } else { + } + else + { CLEAR_BIT(MR_SUBG_RADIO->PA_REG, MR_SUBG_RADIO_PA_REG_PA_DEGEN_ON); } } /** -* @brief Returns the actual PA_LEVEL_MAX_INDEX. -* @retval uint8_t Actual PA_LEVEL_MAX_INDEX. This parameter will be in the range [0:7]. -*/ -__STATIC_INLINE uint8_t LL_MRSubG_GetPALevelMaxIndex(void){ + * @brief Returns the actual PA_LEVEL_MAX_INDEX. + * @retval uint8_t Actual PA_LEVEL_MAX_INDEX. This parameter will be in the range [0:7]. + */ +__STATIC_INLINE uint8_t LL_MRSubG_GetPALevelMaxIndex(void) +{ return READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PA_CONFIG, MR_SUBG_GLOB_STATIC_PA_CONFIG_PA_LEVEL_MAX_INDEX); } /** -* @brief Sets a specific PA_LEVEL_MAX_INDEX. -* @param cIndex PA_LEVEL_MAX_INDEX to set. -* @retval None -*/ -__STATIC_INLINE void LL_MRSubG_SetPALevelMaxIndex(uint8_t cIndex){ + * @brief Sets a specific PA_LEVEL_MAX_INDEX. + * @param cIndex PA_LEVEL_MAX_INDEX to set. + * @retval None + */ +__STATIC_INLINE void LL_MRSubG_SetPALevelMaxIndex(uint8_t cIndex) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PA_CONFIG, MR_SUBG_GLOB_STATIC_PA_CONFIG_PA_LEVEL_MAX_INDEX, cIndex); } /** - * @brief Set the Almost Empty threshold for the Databuffer. When the number of elements in Databuffer reaches this value an interrupt can can be generated. - * @param cThrTx: almost empty threshold. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetAlmostEmptyThresholdTx(uint16_t cThrTx){ + * @brief Set the Almost Empty threshold for the Databuffer. \ + * When the number of elements in Databuffer reaches this value an interrupt can can be generated. + * @param cThrTx: almost empty threshold. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetAlmostEmptyThresholdTx(uint16_t cThrTx) +{ /* Writes the Almost Empty threshold for Tx in the corresponding register */ - MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->DATABUFFER_THR, MR_SUBG_GLOB_DYNAMIC_DATABUFFER_THR_TX_ALMOST_EMPTY_THR, cThrTx); + MODIFY_REG_FIELD( + MR_SUBG_GLOB_DYNAMIC->DATABUFFER_THR, + MR_SUBG_GLOB_DYNAMIC_DATABUFFER_THR_TX_ALMOST_EMPTY_THR, + cThrTx + ); } /** - * @brief Set the almost full threshold for the Databuffer. When the number of elements in Databuffer reaches this value an interrupt can be generated. - * @param cThrRx almost full threshold. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetAlmostFullThresholdRx(uint16_t cThrRx){ + * @brief Set the almost full threshold for the Databuffer. \ + * When the number of elements in Databuffer reaches this value an interrupt can be generated. + * @param cThrRx almost full threshold. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetAlmostFullThresholdRx(uint16_t cThrRx) +{ /* Writes the Almost Full threshold for Tx in the corresponding register */ - MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->DATABUFFER_THR, MR_SUBG_GLOB_DYNAMIC_DATABUFFER_THR_RX_ALMOST_FULL_THR, cThrRx); + MODIFY_REG_FIELD( + MR_SUBG_GLOB_DYNAMIC->DATABUFFER_THR, + MR_SUBG_GLOB_DYNAMIC_DATABUFFER_THR_RX_ALMOST_FULL_THR, + cThrRx + ); } /** - * @brief Return the RADIO FSM State. - * @retval Value of RADIO_FSM_STATE register - */ -__STATIC_INLINE MRSubGFSMState LL_MRSubG_GetRadioFSMState(void){ - return (MRSubGFSMState)(READ_REG_FIELD(MR_SUBG_GLOB_STATUS->RADIO_FSM_INFO, MR_SUBG_GLOB_STATUS_RADIO_FSM_INFO_RADIO_FSM_STATE)); + * @brief Return the RADIO FSM State. + * @retval Value of RADIO_FSM_STATE register + */ +__STATIC_INLINE MRSubGFSMState LL_MRSubG_GetRadioFSMState(void) +{ + return (MRSubGFSMState)(READ_REG_FIELD(MR_SUBG_GLOB_STATUS->RADIO_FSM_INFO, + MR_SUBG_GLOB_STATUS_RADIO_FSM_INFO_RADIO_FSM_STATE)); } /** - * @brief Set the PREAMBLE field Length. - * @param cPreambleLength length of PREAMBLE field in pairs of bits (0 to 2046 bits). - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetPreambleLength(uint16_t cPreambleLength){ + * @brief Set the PREAMBLE field Length. + * @param cPreambleLength length of PREAMBLE field in pairs of bits (0 to 2046 bits). + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetPreambleLength(uint16_t cPreambleLength) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_PREAMBLE_LENGTH, cPreambleLength); } /** - * @brief Return the PREAMBLE field Length. - * @retval uint16_t Preamble field length in in pairs of bits (0 to 2046 bits). - */ -__STATIC_INLINE uint16_t LL_MRSubG_GetPreambleLength(void){ + * @brief Return the PREAMBLE field Length. + * @retval uint16_t Preamble field length in in pairs of bits (0 to 2046 bits). + */ +__STATIC_INLINE uint16_t LL_MRSubG_GetPreambleLength(void) +{ return READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_PREAMBLE_LENGTH); } /** - * @brief Set the PREAMBLE pattern to be applied. - * @param cPreambleSeq the pattern to apply - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetPreambleSeq(MRSubG_PreambleSeq cPreambleSeq){ - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_PREAMBLE_SEQ, (uint8_t)cPreambleSeq); + * @brief Set the PREAMBLE pattern to be applied. + * @param cPreambleSeq the pattern to apply + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetPreambleSeq(MRSubG_PreambleSeq cPreambleSeq) +{ + MODIFY_REG_FIELD( + MR_SUBG_GLOB_STATIC->PCKT_CONFIG, + MR_SUBG_GLOB_STATIC_PCKT_CONFIG_PREAMBLE_SEQ, + (uint8_t)cPreambleSeq + ); } /** - * @brief Return the PREAMBLE pattern. - * @retval MRSubG_PreambleSeq Preamble pattern - */ -__STATIC_INLINE MRSubG_PreambleSeq LL_MRSubG_GetPreambleSeq(void){ - return (MRSubG_PreambleSeq)(READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_PREAMBLE_SEQ)); + * @brief Return the PREAMBLE pattern. + * @retval MRSubG_PreambleSeq Preamble pattern + */ +__STATIC_INLINE MRSubG_PreambleSeq LL_MRSubG_GetPreambleSeq(void) +{ + return (MRSubG_PreambleSeq)(READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, + MR_SUBG_GLOB_STATIC_PCKT_CONFIG_PREAMBLE_SEQ)); } /** - * @brief Set the POSTAMBLE field Length. - * @param cPostambleLength length of POSTAMBLE field in pairs of bits (0 to 126 bits). - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetPostambleLength(uint16_t cPostambleLength){ - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_POSTAMBLE_LENGTH, cPostambleLength); + * @brief Set the POSTAMBLE field Length. + * @param cPostambleLength length of POSTAMBLE field in pairs of bits (0 to 126 bits). + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetPostambleLength(uint16_t cPostambleLength) +{ + MODIFY_REG_FIELD( + MR_SUBG_GLOB_STATIC->PCKT_CONFIG, + MR_SUBG_GLOB_STATIC_PCKT_CONFIG_POSTAMBLE_LENGTH, + cPostambleLength + ); } /** - * @brief Return the POSTAMBLE field Length. - * @retval uint16_t Postamble field length in in pairs of bits (0 to 126 bits). - */ -__STATIC_INLINE uint16_t LL_MRSubG_GetPostambleLength(void){ + * @brief Return the POSTAMBLE field Length. + * @retval uint16_t Postamble field length in in pairs of bits (0 to 126 bits). + */ +__STATIC_INLINE uint16_t LL_MRSubG_GetPostambleLength(void) +{ return READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_POSTAMBLE_LENGTH); } /** - * @brief Set the POSTAMBLE pattern to be applied. - * @param cPostambleSeq the pattern to apply - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetPostamblSeq(MRSubG_PostambleSeq cPostambleSeq){ - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_POSTAMBLE_SEQ, (uint8_t)cPostambleSeq); + * @brief Set the POSTAMBLE pattern to be applied. + * @param cPostambleSeq the pattern to apply + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetPostamblSeq(MRSubG_PostambleSeq cPostambleSeq) +{ + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_POSTAMBLE_SEQ, + (uint8_t)cPostambleSeq); } /** - * @brief Return the POSTAMBLE pattern. - * @retval MRSubG_PostambleSeq Postamble pattern - */ -__STATIC_INLINE MRSubG_PostambleSeq LL_MRSubG_GetPostambleSeq(void){ - return (MRSubG_PostambleSeq)(READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_POSTAMBLE_SEQ)); + * @brief Return the POSTAMBLE pattern. + * @retval MRSubG_PostambleSeq Postamble pattern + */ +__STATIC_INLINE MRSubG_PostambleSeq LL_MRSubG_GetPostambleSeq(void) +{ + return (MRSubG_PostambleSeq)(READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, + MR_SUBG_GLOB_STATIC_PCKT_CONFIG_POSTAMBLE_SEQ)); } /** - * @brief Set the SYNC_PRESENT bit. - * @param cSyncPresent the enable/disable value for the bit - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetSyncPresent(FunctionalState cSyncPresent){ + * @brief Set the SYNC_PRESENT bit. + * @param cSyncPresent the enable/disable value for the bit + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetSyncPresent(FunctionalState cSyncPresent) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_SYNC_PRESENT, cSyncPresent); } /** - * @brief Get the SYNC_PRESENT bit. - * @retval The enable/disable value for the bit. - */ -__STATIC_INLINE FunctionalState LL_MRSubG_GetSyncPresent(void){ - return (FunctionalState)(READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_SYNC_PRESENT)); + * @brief Get the SYNC_PRESENT bit. + * @retval The enable/disable value for the bit. + */ +__STATIC_INLINE FunctionalState LL_MRSubG_GetSyncPresent(void) +{ + return (FunctionalState)(READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, + MR_SUBG_GLOB_STATIC_PCKT_CONFIG_SYNC_PRESENT)); } /** - * @brief Set the SECONDARY_SYNC_SEL bit. - In TX mode: this bit selects which synchro word is sent on the frame between SYNC and SEC_SYNC - In RX mode: it enables the detection of SEC_SYNC in parallel of SYNC word. - * @param cSecondarySync the enable/disable value for the bit - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetSecondarySync(FunctionalState cSecondarySync){ - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_SECONDARY_SYNC_SEL, cSecondarySync); + * @brief Set the SECONDARY_SYNC_SEL bit. + In TX mode: this bit selects which synchro word is sent on the frame between SYNC and SEC_SYNC + In RX mode: it enables the detection of SEC_SYNC in parallel of SYNC word. + * @param cSecondarySync the enable/disable value for the bit + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetSecondarySync(FunctionalState cSecondarySync) +{ + MODIFY_REG_FIELD( + MR_SUBG_GLOB_STATIC->PCKT_CONFIG, + MR_SUBG_GLOB_STATIC_PCKT_CONFIG_SECONDARY_SYNC_SEL, + cSecondarySync + ); } /** - * @brief Get the SECONDARY_SYNC_SEL bit. - * @retval The enable/disable value for the bit. - */ -__STATIC_INLINE FunctionalState LL_MRSubG_GetSecondarySync(void){ - return (FunctionalState)(READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_SECONDARY_SYNC_SEL)); + * @brief Get the SECONDARY_SYNC_SEL bit. + * @retval The enable/disable value for the bit. + */ +__STATIC_INLINE FunctionalState LL_MRSubG_GetSecondarySync(void) +{ + return (FunctionalState)(READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, + MR_SUBG_GLOB_STATIC_PCKT_CONFIG_SECONDARY_SYNC_SEL)); } /** - * @brief Set the SYNC field Length. - * @param cSyncLength length of SYNC field in bits. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetSyncLength(uint8_t cSyncLength){ + * @brief Set the SYNC field Length. + * @param cSyncLength length of SYNC field in bits. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetSyncLength(uint8_t cSyncLength) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_SYNC_LEN, cSyncLength); } /** - * @brief Return the SYNC field Length. - * @retval uint8_t Sync field length in bits. - */ -__STATIC_INLINE uint8_t LL_MRSubG_GetSyncLength(void){ + * @brief Return the SYNC field Length. + * @retval uint8_t Sync field length in bits. + */ +__STATIC_INLINE uint8_t LL_MRSubG_GetSyncLength(void) +{ return READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_SYNC_LEN); } /** -* @brief Set the SYNC word. -* @param lSyncWord SYNC word given as a 32 bits aligned word. -* @retval None. -*/ -__STATIC_INLINE void LL_MRSubG_SetSyncWord(uint32_t lSyncWord){ + * @brief Set the SYNC word. + * @param lSyncWord SYNC word given as a 32 bits aligned word. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetSyncWord(uint32_t lSyncWord) +{ WRITE_REG(MR_SUBG_GLOB_STATIC->SYNC, lSyncWord); } /** -* @brief Get the SYNC word. -* @retval The Sync word. -*/ -__STATIC_INLINE uint32_t LL_MRSubG_GetSyncWord(void){ - return READ_REG(MR_SUBG_GLOB_STATIC->SYNC); + * @brief Get the SYNC word. + * @retval The Sync word. + */ +__STATIC_INLINE uint32_t LL_MRSubG_GetSyncWord(void) +{ + return READ_REG(MR_SUBG_GLOB_STATIC->SYNC); } /** -* @brief Set the SEC_SYNC word. -* @param lSecSyncWord SEC_SYNC word given as a 32 bits aligned word. -* @retval None. -*/ -__STATIC_INLINE void LL_MRSubG_SetSecondarySyncWord(uint32_t lSecSyncWord){ + * @brief Set the SEC_SYNC word. + * @param lSecSyncWord SEC_SYNC word given as a 32 bits aligned word. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetSecondarySyncWord(uint32_t lSecSyncWord) +{ WRITE_REG(MR_SUBG_GLOB_STATIC->SEC_SYNC, lSecSyncWord); } /** -* @brief Get the SEC_SYNC word. -* @retval The Secondary Sync word. -*/ -__STATIC_INLINE uint32_t LL_MRSubG_GetSecondarySyncWord(void){ - return READ_REG(MR_SUBG_GLOB_STATIC->SEC_SYNC); + * @brief Get the SEC_SYNC word. + * @retval The Secondary Sync word. + */ +__STATIC_INLINE uint32_t LL_MRSubG_GetSecondarySyncWord(void) +{ + return READ_REG(MR_SUBG_GLOB_STATIC->SEC_SYNC); } /** - * @brief Enable or Disable WHITENING for STM32WL3 packets. - * @param xNewState new state for WHITENING mode. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_PacketHandlerWhitening(FunctionalState xNewState){ - if(xNewState == ENABLE) + * @brief Enable or Disable WHITENING for STM32WL3x packets. + * @param xNewState new state for WHITENING mode. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_PacketHandlerWhitening(FunctionalState xNewState) +{ + if (xNewState == ENABLE) + { SET_BIT(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_WHIT_EN); + } else CLEAR_BIT(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_WHIT_EN); } /** - * @brief Enable or Disable BYTE_SWAP for STM32WL3 packets. - * @param xNewState new state for BYTE_SWAP mode. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_PacketHandlerByteSwap(FunctionalState xNewState){ - if(xNewState == ENABLE) + * @brief Enable or Disable BYTE_SWAP for STM32WL3x packets. + * @param xNewState new state for BYTE_SWAP mode. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_PacketHandlerByteSwap(FunctionalState xNewState) +{ + if (xNewState == ENABLE) + { SET_BIT(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_BYTE_SWAP); + } else CLEAR_BIT(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_BYTE_SWAP); } /** - * @brief Set the Fec and Whitening order - * @param xWhitFecOrder new Whitening/FEC order. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_PacketHandlerWhiteningFecOrder(MRSubG_WhiteningBeforeFECType xWhitFecOrder){ - if(xWhitFecOrder == WHITENING_THEN_FEC) + * @brief Set the Fec and Whitening order + * @param xWhitFecOrder new Whitening/FEC order. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_PacketHandlerWhiteningFecOrder(MRSubG_WhiteningBeforeFECType xWhitFecOrder) +{ + if (xWhitFecOrder == WHITENING_THEN_FEC) + { SET_BIT(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_WHIT_BF_FEC); + } else CLEAR_BIT(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_WHIT_BF_FEC); } /** - * @brief Set the Whitening initialization value - * @param whit_init Whitening initialization value. - * In 802.15.4 standard, this initialization seed must be programmed to 0x1FF. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_PacketHandlerSetWhiteningInit(uint16_t whit_init){ + * @brief Set the Whitening initialization value + * @param whit_init Whitening initialization value. + * In 802.15.4 standard, this initialization seed must be programmed to 0x1FF. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_PacketHandlerSetWhiteningInit(uint16_t whit_init) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_WHIT_INIT, whit_init); } /** -* @brief Set the type of coding and decoding for the packets. -* @param cCoding coding/decoding selection. -* @retval None. -*/ -__STATIC_INLINE void LL_MRSubG_PacketHandlerCoding(MRSubG_PcktCoding cCoding){ + * @brief Set the type of coding and decoding for the packets. + * @param cCoding coding/decoding selection. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_PacketHandlerCoding(MRSubG_PcktCoding cCoding) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_CODING_SEL, cCoding); } /** -* @brief Set the Manchester type for the packets. -* @param manType the Manchester encoding polarity. -* 0: '0' is encoded with '01' and '1' is encoded with '10' -* 1: '0' is encoded with '10' and '1' is encoded with '01' -* @retval None. -*/ -__STATIC_INLINE void LL_MRSubG_PacketHandlerManchesterType(MRSubG_ManchesterPolarity manType){ + * @brief Set the Manchester type for the packets. + * @param manType the Manchester encoding polarity. + * 0: '0' is encoded with '01' and '1' is encoded with '10' + * 1: '0' is encoded with '10' and '1' is encoded with '01' + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_PacketHandlerManchesterType(MRSubG_ManchesterPolarity manType) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_MANCHESTER_TYPE, manType); } /** -* @brief Set the CRC mode. -* @param xPktCrcMode This parameter can be one among the @ref MRSubG_PcktCrcMode . -* @retval None. -*/ -__STATIC_INLINE void LL_MRSubG_PacketHandlerSetCrcMode(MRSubG_PcktCrcMode xPktCrcMode){ + * @brief Set the CRC mode. + * @param xPktCrcMode This parameter can be one among the @ref MRSubG_PcktCrcMode . + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_PacketHandlerSetCrcMode(MRSubG_PcktCrcMode xPktCrcMode) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_CRC_MODE, xPktCrcMode); } /** -* @brief Get the CRC mode. -* @retval MRSubG_PcktCrcMode CRC mode in the @ref MRSubG_PcktCrcMode enum. -*/ -__STATIC_INLINE MRSubG_PcktCrcMode LL_MRSubG_PacketHandlerGetCrcMode(void){ + * @brief Get the CRC mode. + * @retval MRSubG_PcktCrcMode CRC mode in the @ref MRSubG_PcktCrcMode enum. + */ +__STATIC_INLINE MRSubG_PcktCrcMode LL_MRSubG_PacketHandlerGetCrcMode(void) +{ return (MRSubG_PcktCrcMode)(READ_REG(MR_SUBG_GLOB_STATIC->PCKT_CONFIG) & MR_SUBG_GLOB_STATIC_PCKT_CONFIG_CRC_MODE); } /** - * @brief Set the PCKTLEN field of the PCKTLEN_CONFIG register. - * @param nPacketLen payload length in bytes. - * @retval None. - */ -__STATIC_INLINE void LL_MRSUBG_SetPacketLength(uint16_t nPacketLen){ + * @brief Set the PCKTLEN field of the PCKTLEN_CONFIG register. + * @param nPacketLen payload length in bytes. + * @retval None. + */ +__STATIC_INLINE void LL_MRSUBG_SetPacketLength(uint16_t nPacketLen) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->PCKTLEN_CONFIG, MR_SUBG_GLOB_DYNAMIC_PCKTLEN_CONFIG_PCKTLEN, nPacketLen); } /** - * @brief Get the PCKTLEN field of the PCKTLEN_CONFIG register. - * @retval Payload length in bytes. - */ -__STATIC_INLINE uint16_t LL_MRSUBG_GetPacketLength(void){ + * @brief Get the PCKTLEN field of the PCKTLEN_CONFIG register. + * @retval Payload length in bytes. + */ +__STATIC_INLINE uint16_t LL_MRSUBG_GetPacketLength(void) +{ return READ_REG(MR_SUBG_GLOB_DYNAMIC->PCKTLEN_CONFIG) & MR_SUBG_GLOB_DYNAMIC_PCKTLEN_CONFIG_PCKTLEN; } /** - * @brief Set the FIX_VAR_LEN field of the PCKT_CONFI register. - * @param lenType length mode. - * 0: FIXED length mode (no LENGTH field added in the frame in TX and no decode in RX) - * 1: VARIABLE length mode (LENGTH field put in the frame in TX and decoded in RX) - * @retval None. - */ -__STATIC_INLINE void LL_MRSUBG_SetFixedVariableLength(MRSubG_LengthMode lenType){ + * @brief Set the FIX_VAR_LEN field of the PCKT_CONFI register. + * @param lenType length mode. + * 0: FIXED length mode (no LENGTH field added in the frame in TX and no decode in RX) + * 1: VARIABLE length mode (LENGTH field put in the frame in TX and decoded in RX) + * @retval None. + */ +__STATIC_INLINE void LL_MRSUBG_SetFixedVariableLength(MRSubG_LengthMode lenType) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_FIX_VAR_LEN, lenType); } /** - * @brief Get the FIX_VAR_LEN field of the PCKT_CONFI register. - * @retval The Fixed/Variable length mode. - */ -__STATIC_INLINE MRSubG_LengthMode LL_MRSUBG_GetFixedVariableLength(void){ - return (MRSubG_LengthMode)(READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_FIX_VAR_LEN)); + * @brief Get the FIX_VAR_LEN field of the PCKT_CONFI register. + * @retval The Fixed/Variable length mode. + */ +__STATIC_INLINE MRSubG_LengthMode LL_MRSUBG_GetFixedVariableLength(void) +{ + return (MRSubG_LengthMode)(READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, + MR_SUBG_GLOB_STATIC_PCKT_CONFIG_FIX_VAR_LEN)); } /** - * @brief Return the payload length for the Basic packet format. - * @retval Payload length in bytes. - */ -__STATIC_INLINE uint16_t LL_MRSubG_PktBasicGetPayloadLength(void){ - return READ_REG(MR_SUBG_GLOB_STATIC->DATABUFFER_SIZE) & MR_SUBG_GLOB_STATIC_DATABUFFER_SIZE_DATABUFFER_SIZE; + * @brief Return the payload length for the Basic packet format. + * @retval Payload length in bytes. + */ +__STATIC_INLINE uint16_t LL_MRSubG_PktBasicGetPayloadLength(void) +{ + return READ_REG(MR_SUBG_GLOB_STATIC->DATABUFFER_SIZE) & MR_SUBG_GLOB_STATIC_DATABUFFER_SIZE_DATABUFFER_SIZE; } /** - * @brief Indicates if the LENGTH field is defined on 1 byte or 2 bytes. - * @param lenWidth the length field to set. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetLenWidth(MRSubG_LenWidthhMode lenWidth){ + * @brief Indicates if the LENGTH field is defined on 1 byte or 2 bytes. + * @param lenWidth the length field to set. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetLenWidth(MRSubG_LenWidthhMode lenWidth) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_LEN_WIDTH, lenWidth); } /** - * @brief Return the LENGTH field, defined on 1 byte or 2 bytes. - * @retval The LENGTH field. - */ -__STATIC_INLINE MRSubG_LenWidthhMode LL_MRSubG_GetLenWidth(void){ - return (MRSubG_LenWidthhMode)(READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_LEN_WIDTH)); + * @brief Return the LENGTH field, defined on 1 byte or 2 bytes. + * @retval The LENGTH field. + */ +__STATIC_INLINE MRSubG_LenWidthhMode LL_MRSubG_GetLenWidth(void) +{ + return (MRSubG_LenWidthhMode)(READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, + MR_SUBG_GLOB_STATIC_PCKT_CONFIG_LEN_WIDTH)); } /** - * @brief Enable or Disable RX_TIMER_RX_CS_TIMEOUT flag. - * @param xNewState new state for RX_TIMER_RX_CS_TIMEOUT flag. - * This parameter can be ENABLE or DISABLE. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetRxCsTimeout(FunctionalState xNewState){ - if(xNewState == ENABLE) + * @brief Enable or Disable RX_TIMER_RX_CS_TIMEOUT flag. + * @param xNewState new state for RX_TIMER_RX_CS_TIMEOUT flag. + * This parameter can be ENABLE or DISABLE. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetRxCsTimeout(FunctionalState xNewState) +{ + if (xNewState == ENABLE) + { SET_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_CS_TIMEOUT_MASK); + } else CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_CS_TIMEOUT_MASK); } /** - * @brief Enable or Disable RX_TIMER_RX_PQI_TIMEOUT flag. - * @param xNewState new state for RX_TIMER_RX_PQI_TIMEOUT flag. - * This parameter can be ENABLE or DISABLE. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetRxPqiTimeout(FunctionalState xNewState){ - if(xNewState == ENABLE) + * @brief Enable or Disable RX_TIMER_RX_PQI_TIMEOUT flag. + * @param xNewState new state for RX_TIMER_RX_PQI_TIMEOUT flag. + * This parameter can be ENABLE or DISABLE. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetRxPqiTimeout(FunctionalState xNewState) +{ + if (xNewState == ENABLE) + { SET_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_PQI_TIMEOUT_MASK); + } else CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_PQI_TIMEOUT_MASK); } /** - * @brief Enable or Disable RX_TIMER_RX_SQI_TIMEOUT flag. - * @param xNewState new state for RX_TIMER_RX_SQI_TIMEOUT flag. - * This parameter can be ENABLE or DISABLE. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetRxSqiTimeout(FunctionalState xNewState){ - if(xNewState == ENABLE) + * @brief Enable or Disable RX_TIMER_RX_SQI_TIMEOUT flag. + * @param xNewState new state for RX_TIMER_RX_SQI_TIMEOUT flag. + * This parameter can be ENABLE or DISABLE. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetRxSqiTimeout(FunctionalState xNewState) +{ + if (xNewState == ENABLE) + { SET_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_SQI_TIMEOUT_MASK); + } else CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_SQI_TIMEOUT_MASK); } /** - * @brief Set or Reset RX_TIMER_RX_OR_nAND_SELECT. - * @param xNewState new state for RX_TIMER_RX_OR_nAND_SELECT bit. - * This parameter can be SET or RESET. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_SetRxOrnAndSelect(FlagStatus xNewState){ - if(xNewState == SET) + * @brief Set or Reset RX_TIMER_RX_OR_nAND_SELECT. + * @param xNewState new state for RX_TIMER_RX_OR_nAND_SELECT bit. + * This parameter can be SET or RESET. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_SetRxOrnAndSelect(FlagStatus xNewState) +{ + if (xNewState == SET) + { SET_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_nAND_SELECT); + } else CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->RX_TIMER, MR_SUBG_GLOB_DYNAMIC_RX_TIMER_RX_OR_nAND_SELECT); } /** - * @brief Enable or Disable FAST_CS_TERM. - * @param xNewState new state for FAST_CS_TERM_EN. - * This parameter can be S_ENABLE or S_DISABLE. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_FastCsTermEn(FunctionalState xNewState){ - if(xNewState == ENABLE) + * @brief Enable or Disable FAST_CS_TERM. + * @param xNewState new state for FAST_CS_TERM_EN. + * This parameter can be S_ENABLE or S_DISABLE. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_FastCsTermEn(FunctionalState xNewState) +{ + if (xNewState == ENABLE) + { SET_BIT(MR_SUBG_GLOB_DYNAMIC->FAST_RX_TIMER, MR_SUBG_GLOB_DYNAMIC_FAST_RX_TIMER_FAST_CS_TERM_EN); + } else CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->FAST_RX_TIMER, MR_SUBG_GLOB_DYNAMIC_FAST_RX_TIMER_FAST_CS_TERM_EN); } /** - * @brief Set or Reset VCO_CALIB_REQ. - * @param xNewState new state for VCO_CALIB_REQ bit. - * This parameter can be SET or RESET. - * @retval None. - */ -__STATIC_INLINE void LL_MRSubG_VCOCalibReq(FlagStatus xNewState){ - if(xNewState == SET) + * @brief Set or Reset VCO_CALIB_REQ. + * @param xNewState new state for VCO_CALIB_REQ bit. + * This parameter can be SET or RESET. + * @retval None. + */ +__STATIC_INLINE void LL_MRSubG_VCOCalibReq(FlagStatus xNewState) +{ + if (xNewState == SET) + { SET_BIT(MR_SUBG_GLOB_DYNAMIC->VCO_CAL_CONFIG, MR_SUBG_GLOB_DYNAMIC_VCO_CAL_CONFIG_VCO_CALIB_REQ); + } else CLEAR_BIT(MR_SUBG_GLOB_DYNAMIC->VCO_CAL_CONFIG, MR_SUBG_GLOB_DYNAMIC_VCO_CAL_CONFIG_VCO_CALIB_REQ); } /** - * @brief Return the CHFLT_E field. - * @retval The CHFLT_E field. - */ -__STATIC_INLINE uint8_t LL_MRSubG_GetChFlt_E(void){ + * @brief Return the CHFLT_E field. + * @retval The CHFLT_E field. + */ +__STATIC_INLINE uint8_t LL_MRSubG_GetChFlt_E(void) +{ return READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD1_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD1_CONFIG_CHFLT_E); } /** - * @brief Return the RSSI_LEVEL_ON_SYNC register. - * @retval The RSSI Level On Sync value. - */ -__STATIC_INLINE uint16_t LL_MRSubG_GetRssiLevelOnSync(void){ + * @brief Return the RSSI_LEVEL_ON_SYNC register. + * @retval The RSSI Level On Sync value. + */ +__STATIC_INLINE uint16_t LL_MRSubG_GetRssiLevelOnSync(void) +{ return READ_REG(MR_SUBG_GLOB_STATUS->RX_INDICATOR) & MR_SUBG_GLOB_STATUS_RX_INDICATOR_RSSI_LEVEL_ON_SYNC; } /** - * @brief Set the MRSUBG RSSI_FLT register. - * @retval The value to store for the register. - */ -__STATIC_INLINE void LL_MRSubG_SetRSSIFilter(uint32_t rssiFilter){ + * @brief Set the MRSUBG RSSI_FLT register. + * @retval The value to store for the register. + */ +__STATIC_INLINE void LL_MRSubG_SetRSSIFilter(uint32_t rssiFilter) +{ WRITE_REG(MR_SUBG_RADIO->RSSI_FLT, rssiFilter); } /** - * @brief Set the RSSI threshold register. - * @retval The value to store for the signal detect threshold. - */ -__STATIC_INLINE void LL_MRSubG_SetRssiThresholdRegister(uint16_t rssiValReg){ + * @brief Set the RSSI threshold register. + * @retval The value to store for the signal detect threshold. + */ +__STATIC_INLINE void LL_MRSubG_SetRssiThresholdRegister(uint16_t rssiValReg) +{ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_RSSI_THR, rssiValReg); } /** - * @brief Set the MRSUBG Clock Recovery 0 register. - * @retval The value to store for the register. - */ -__STATIC_INLINE void LL_MRSubG_SetClkRecCtrl0(uint32_t clkRec){ + * @brief Set the MRSUBG Clock Recovery 0 register. + * @retval The value to store for the register. + */ +__STATIC_INLINE void LL_MRSubG_SetClkRecCtrl0(uint32_t clkRec) +{ WRITE_REG(MR_SUBG_RADIO->CLKREC_CTRL0, clkRec); } /** - * @brief Set the MRSUBG Clock Recovery 1 register. - * @retval The value to store for the register. - */ -__STATIC_INLINE void LL_MRSubG_SetClkRecCtrl1(uint32_t clkRec){ + * @brief Set the MRSUBG Clock Recovery 1 register. + * @retval The value to store for the register. + */ +__STATIC_INLINE void LL_MRSubG_SetClkRecCtrl1(uint32_t clkRec) +{ WRITE_REG(MR_SUBG_RADIO->CLKREC_CTRL1, clkRec); } /** - * @brief Set the MRSUBG AFC0 register. - * @retval The value to store for the AFC0_CONFIG register. - */ -__STATIC_INLINE void LL_MRSubG_SetAFC0(uint32_t afcCfg){ + * @brief Set the MRSUBG AFC0 register. + * @retval The value to store for the AFC0_CONFIG register. + */ +__STATIC_INLINE void LL_MRSubG_SetAFC0(uint32_t afcCfg) +{ WRITE_REG(MR_SUBG_RADIO->AFC0_CONFIG, afcCfg); } /** - * @brief Set the MRSUBG AFC1 register. - * @retval The value to store for the AFC1_CONFIG register. - */ -__STATIC_INLINE void LL_MRSubG_SetAFC1(uint32_t afcCfg){ + * @brief Set the MRSUBG AFC1 register. + * @retval The value to store for the AFC1_CONFIG register. + */ +__STATIC_INLINE void LL_MRSubG_SetAFC1(uint32_t afcCfg) +{ WRITE_REG(MR_SUBG_RADIO->AFC1_CONFIG, afcCfg); } /** - * @brief Set the MRSUBG AFC2 register. - * @retval The value to store for the AFC2_CONFIG register. - */ -__STATIC_INLINE void LL_MRSubG_SetAFC2(uint32_t afcCfg){ + * @brief Set the MRSUBG AFC2 register. + * @retval The value to store for the AFC2_CONFIG register. + */ +__STATIC_INLINE void LL_MRSubG_SetAFC2(uint32_t afcCfg) +{ WRITE_REG(MR_SUBG_RADIO->AFC2_CONFIG, afcCfg); } /** - * @brief Set the MRSUBG AFC3 register. - * @retval The value to store for the AFC3_CONFIG register. - */ -__STATIC_INLINE void LL_MRSubG_SetAFC3(uint32_t afcCfg){ + * @brief Set the MRSUBG AFC3 register. + * @retval The value to store for the AFC3_CONFIG register. + */ +__STATIC_INLINE void LL_MRSubG_SetAFC3(uint32_t afcCfg) +{ WRITE_REG(MR_SUBG_RADIO->AFC3_CONFIG, afcCfg); } +/** + * @brief Low Level function to set the SQI threshold field in AS_QI_CTRL register. + * @param thr Threshold value of type @ref SQI_Threshold. + * @retval None + */ +__STATIC_INLINE void LL_MRSubG_SetSQIThreshold(SQI_Threshold thr) +{ + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_SQI_THR, thr); +} + +/** + * @brief Low Level function to get the SQI threshold field from AS_QI_CTRL register. + * @retval Threshold value of type @ref SQI_Threshold. + */ +__STATIC_INLINE SQI_Threshold LL_MRSubG_GetSQIThreshold(void) +{ + uint8_t thr = READ_REG_FIELD(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_SQI_THR); + return (SQI_Threshold)thr; +} + /** @verbatim ============================================================================== @@ -1077,7 +1320,7 @@ __STATIC_INLINE void LL_MRSubG_SetAFC3(uint32_t afcCfg){ ============================================================================== [..] The LL_SEQUENCER driver contains a set of APIs that can be used to configure - the STM32WL3 MRSubG sequencer hardware. + the STM32WL3x MRSubG sequencer hardware. Typically it is used as follows: *** Step 1: Set up ActionConfiguration tables *** @@ -1086,15 +1329,15 @@ __STATIC_INLINE void LL_MRSubG_SetAFC3(uint32_t afcCfg){ In this step, configuration RAM tables are created for all actions in the flow graph. - (+) Allocate a MRSubG_Sequencer_ActionConfiguration struct for each action - that is part of your flow graph. The sequencer hardware accesses this - struct in RAM as the ActionConfiguration RAM table. + (+) Allocate a MRSubG_Sequencer_ActionConfiguration_t struct for each action + that is part of your flow graph. The sequencer hardware accesses this struct in RAM as + the ActionConfiguration RAM table. It must persist in RAM while the Action is being executed. Make sure that the RAM table is word-aligned. (+) For each ActionConfiguration item: - (++) Set up the dynamic registers (MR_SUBG_GLOB_DYNAMIC) of the STM32WL3 + (++) Set up the dynamic registers (MR_SUBG_GLOB_DYNAMIC) of the STM32WL3x as desired upon execution of the action. This can be performed using the standard MRSubG_* and packet APIs. Do not issue any command in the meantime (i.e., keep COMMAND_ID in @@ -1103,7 +1346,7 @@ __STATIC_INLINE void LL_MRSubG_SetAFC3(uint32_t afcCfg){ table using MRSubG_Sequencer_ApplyDynamicConfig and configure which command is issued when the action gets executed. (++) Change the appropriate values in the - MRSubG_Sequencer_ActionConfiguration struct to configure under + MRSubG_Sequencer_ActionConfiguration_t struct to configure under which conditions either NextAction1 or NextAction2 are executed, to provide a pointer to ActionConfiguration RAM tables for both actions and to configure inter-action intervals. @@ -1120,14 +1363,14 @@ __STATIC_INLINE void LL_MRSubG_SetAFC3(uint32_t afcCfg){ sequencer properties and the contents of the static configuration registers is created. - (+) Allocate a MRSubG_Sequencer_GlobalConfiguration struct. + (+) Allocate a MRSubG_Sequencer_GlobalConfiguration_t struct. The sequencer hardware accesses this struct in RAM as the GlobalConfiguration RAM table. The sequencer hardware will update properties of this RAM table during operation. (+) Modify the GlobalConfiguration struct: - (++) Set up the static registers (MR_SUBG_GLOB_STATIC) of the STM32WL3 + (++) Set up the static registers (MR_SUBG_GLOB_STATIC) of the STM32WL3x as desired upon execution of the action. This can be performed using the standard MRSubG_* and packet APIs. (++) Copy all static register values to the GlobalConfiguration RAM @@ -1152,15 +1395,16 @@ __STATIC_INLINE void LL_MRSubG_SetAFC3(uint32_t afcCfg){ the GlobalConfiguration struct. (++) Re-trigger the sequencer using MRSubG_Sequencer_Trigger. @endverbatim -**/ + **/ /* - * @brief Set global configuration table for sequencer hardware. - * @param Pointer to the global configuration table struct. - * @retval None - */ -__STATIC_INLINE void LL_MRSubG_Sequencer_SetGlobalConfiguration(MRSubG_Sequencer_GlobalConfiguration *cfg){ - /* GLOBALTABLE_PTR is relative to device SRAM base address */ + * @brief Set global configuration table for sequencer hardware. + * @param Pointer to the global configuration table struct. + * @retval None + */ +__STATIC_INLINE void LL_MRSubG_Sequencer_SetGlobalConfiguration(MRSubG_Sequencer_GlobalConfiguration_t *cfg) +{ + /* GLOBALTABLE_PTR is relative to device SRAM_BASE base address */ MR_SUBG_GLOB_RETAINED->SEQ_GLOBALTABLE_PTR = ((uint32_t)cfg) - SRAM_BASE; } @@ -1168,7 +1412,8 @@ __STATIC_INLINE void LL_MRSubG_Sequencer_SetGlobalConfiguration(MRSubG_Sequencer * @brief Determine whether sequencer hardware is currently active. * @retval 1 in case sequencer is active, otherwise 0 */ -__STATIC_INLINE uint8_t LL_MRSubG_Sequencer_IsActive(void){ +__STATIC_INLINE uint8_t LL_MRSubG_Sequencer_IsActive(void) +{ return (MR_SUBG_GLOB_MISC->SEQUENCER_CTRL & MR_SUBG_GLOB_MISC_SEQUENCER_CTRL_DISABLE_SEQ) ? 0 : 1; } @@ -1176,7 +1421,8 @@ __STATIC_INLINE uint8_t LL_MRSubG_Sequencer_IsActive(void){ * @brief Trigger sequencer, i.e., launch sequence of actions. * @retval None */ -__STATIC_INLINE void LL_MRSubG_Sequencer_Trigger(void){ +__STATIC_INLINE void LL_MRSubG_Sequencer_Trigger(void) +{ MR_SUBG_GLOB_MISC->SEQUENCER_CTRL &= ~MR_SUBG_GLOB_MISC_SEQUENCER_CTRL_DISABLE_SEQ; MR_SUBG_GLOB_MISC->SEQUENCER_CTRL |= MR_SUBG_GLOB_MISC_SEQUENCER_CTRL_GEN_SEQ_TRIGGER; } @@ -1185,8 +1431,11 @@ __STATIC_INLINE void LL_MRSubG_Sequencer_Trigger(void){ * @brief Disable sequencer hardware. * @retval None */ -__STATIC_INLINE void LL_MRSubG_Sequencer_Disable(void){ - MR_SUBG_GLOB_MISC->SEQUENCER_CTRL |= MR_SUBG_GLOB_MISC_SEQUENCER_CTRL_DISABLE_SEQ | MR_SUBG_GLOB_MISC_SEQUENCER_CTRL_GEN_SEQ_TRIGGER; +__STATIC_INLINE void LL_MRSubG_Sequencer_Disable(void) +{ + MR_SUBG_GLOB_MISC->SEQUENCER_CTRL |= + MR_SUBG_GLOB_MISC_SEQUENCER_CTRL_DISABLE_SEQ | + MR_SUBG_GLOB_MISC_SEQUENCER_CTRL_GEN_SEQ_TRIGGER; } /** diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_mrsubg_timer.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_mrsubg_timer.h index 29348f52d2..678e25cd17 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_mrsubg_timer.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_mrsubg_timer.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2024-2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -80,7 +80,8 @@ __STATIC_INLINE void LL_MRSUBG_TIMER_DisableCPUWakeupTimer(MR_SUBG_GLOB_RETAINED */ __STATIC_INLINE uint32_t LL_MRSUBG_TIMER_IsEnabledCPUWakeupTimer(MR_SUBG_GLOB_RETAINED_TypeDef *GLOB_RETAINEDx) { - return ((READ_BIT(GLOB_RETAINEDx->WAKEUP_CTRL, MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_CPU_WAKEUP_EN) == (MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_CPU_WAKEUP_EN)) ? 1UL : 0UL); + return ((READ_BIT(GLOB_RETAINEDx->WAKEUP_CTRL, MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_CPU_WAKEUP_EN) \ + == (MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_CPU_WAKEUP_EN)) ? 1UL : 0UL); } /** @@ -91,7 +92,8 @@ __STATIC_INLINE uint32_t LL_MRSUBG_TIMER_IsEnabledCPUWakeupTimer(MR_SUBG_GLOB_RE */ __STATIC_INLINE uint32_t LL_MRSUBG_TIMER_IsEnabledRFIPWakeupTimer(MR_SUBG_GLOB_RETAINED_TypeDef *GLOB_RETAINEDx) { - return ((READ_BIT(GLOB_RETAINEDx->WAKEUP_CTRL, MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_RFIP_WAKEUP_EN) == (MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_RFIP_WAKEUP_EN)) ? 1UL : 0UL); + return ((READ_BIT(GLOB_RETAINEDx->WAKEUP_CTRL, MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_RFIP_WAKEUP_EN) \ + == (MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_RFIP_WAKEUP_EN)) ? 1UL : 0UL); } /** @@ -102,7 +104,7 @@ __STATIC_INLINE uint32_t LL_MRSUBG_TIMER_IsEnabledRFIPWakeupTimer(MR_SUBG_GLOB_R */ __STATIC_INLINE void LL_MRSUBG_TIMER_SetWakeupOffset(MR_SUBG_GLOB_RETAINED_TypeDef *GLOB_RETAINEDx, uint8_t Time) { - MODIFY_REG_FIELD(GLOB_RETAINEDx->WAKEUP_CTRL, MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_SOC_WAKEUP_OFFSET, (Time&0xFF)); + MODIFY_REG_FIELD(GLOB_RETAINEDx->WAKEUP_CTRL, MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_SOC_WAKEUP_OFFSET, (Time & 0xFF)); } /** @@ -112,7 +114,7 @@ __STATIC_INLINE void LL_MRSUBG_TIMER_SetWakeupOffset(MR_SUBG_GLOB_RETAINED_TypeD */ __STATIC_INLINE uint32_t LL_MRSUBG_TIMER_GetWakeupOffset(MR_SUBG_GLOB_RETAINED_TypeDef *GLOB_RETAINEDx) { - return (uint32_t)(READ_REG(GLOB_RETAINEDx->WAKEUP_CTRL)&0xFF); + return (uint32_t)(READ_REG(GLOB_RETAINEDx->WAKEUP_CTRL) & 0xFF); } /** @@ -182,9 +184,10 @@ __STATIC_INLINE void LL_MRSUBG_TIMER_ClearFlag_RFIPWakeup(MR_SUBG_GLOB_MISC_Type * @param GLOB_MISCx Global Misc instance * @retval State of bit (1 or 0). */ - __STATIC_INLINE uint32_t LL_MRSUBG_TIMER_IsActiveFlag_RFIPWakeup(MR_SUBG_GLOB_MISC_TypeDef *GLOB_MISCx) +__STATIC_INLINE uint32_t LL_MRSUBG_TIMER_IsActiveFlag_RFIPWakeup(MR_SUBG_GLOB_MISC_TypeDef *GLOB_MISCx) { - return ((READ_BIT(GLOB_MISCx->WAKEUP_IRQ_STATUS, MR_SUBG_GLOB_MISC_WAKEUP_IRQ_STATUS_RFIP_WAKEUP_F) == (MR_SUBG_GLOB_MISC_WAKEUP_IRQ_STATUS_RFIP_WAKEUP_F)) ? 1UL : 0UL); + return ((READ_BIT(GLOB_MISCx->WAKEUP_IRQ_STATUS, MR_SUBG_GLOB_MISC_WAKEUP_IRQ_STATUS_RFIP_WAKEUP_F) == \ + (MR_SUBG_GLOB_MISC_WAKEUP_IRQ_STATUS_RFIP_WAKEUP_F)) ? 1UL : 0UL); } /** @@ -204,9 +207,10 @@ __STATIC_INLINE void LL_MRSUBG_TIMER_ClearFlag_CPUWakeup(MR_SUBG_GLOB_MISC_TypeD * @param GLOB_MISCx Global Misc instance * @retval State of bit (1 or 0). */ - __STATIC_INLINE uint32_t LL_MRSUBG_TIMER_IsActiveFlag_CPUWakeup(MR_SUBG_GLOB_MISC_TypeDef *GLOB_MISCx) +__STATIC_INLINE uint32_t LL_MRSUBG_TIMER_IsActiveFlag_CPUWakeup(MR_SUBG_GLOB_MISC_TypeDef *GLOB_MISCx) { - return ((READ_BIT(GLOB_MISCx->WAKEUP_IRQ_STATUS, MR_SUBG_GLOB_MISC_WAKEUP_IRQ_STATUS_CPU_WAKEUP_F) == (MR_SUBG_GLOB_MISC_WAKEUP_IRQ_STATUS_CPU_WAKEUP_F)) ? 1UL : 0UL); + return ((READ_BIT(GLOB_MISCx->WAKEUP_IRQ_STATUS, MR_SUBG_GLOB_MISC_WAKEUP_IRQ_STATUS_CPU_WAKEUP_F) == \ + (MR_SUBG_GLOB_MISC_WAKEUP_IRQ_STATUS_CPU_WAKEUP_F)) ? 1UL : 0UL); } /** diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_pwr.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_pwr.h index 431df5052c..31fbb4b0c5 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_pwr.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_pwr.h @@ -54,6 +54,7 @@ extern "C" { */ #define LL_PWR_MODE_DEEPSTOP (0x000000000U) /*!< Low Power Mode Selection DEEPSTOP mode */ #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS) /*!< Low Power Mode Selection SHUTDOWN mode */ +#define LL_PWR_MODE_ULTRA_DEEPSTOP (PWR_CR1_LPMS) /*!< Low Power Mode Selection SHUTDOWN mode */ /** * @} */ @@ -480,7 +481,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBORinSDN(void) #if defined(PWR_SDWN_WUEN_WUEN) /** - * @brief Shutdown I/O Wakeup enable. + * @brief Shutdown/Ultra_deepstop I/O Wakeup enable. * @rmtoll SDWN_WUEN WUEN LL_PWR_EnableIOWakeupSDN * @retval None */ @@ -490,7 +491,7 @@ __STATIC_INLINE void LL_PWR_EnableIOWakeupSDN(void) } /** - * @brief Shutdown I/O Wakeup disable. + * @brief Shutdown/Ultra_deepstop I/O Wakeup disable. * @rmtoll SDWN_WUEN WUEN LL_PWR_DisableIOWakeupSDN * @retval None */ @@ -500,7 +501,7 @@ __STATIC_INLINE void LL_PWR_DisableIOWakeupSDN(void) } /** - * @brief Checks if Shutdown I/O Wakeup is enabled or disabled. + * @brief Checks if Shutdown/Ultra_deepstop I/O Wakeup is enabled or disabled. * @rmtoll SDWN_WUEN WUEN LL_PWR_IsEnabledIOWakeupSDN * @retval State of bit (1 or 0). */ @@ -510,13 +511,13 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledIOWakeupSDN(void) } /** - * @brief Shutdown I/O Wakeup Polarity configuration. + * @brief Shutdown/Ultra_deepstop I/O Wakeup Polarity configuration. * @rmtoll SDWN_WUPOL WUPOL LL_PWR_IOWakeupPolaritySDN * @param pol IO wakeup polarity. This parameter can be one of the following values: * @arg @ref LL_PWR_WUP_RISIEDG * @arg @ref LL_PWR_WUP_FALLEDG * @retval None - * @note The wakeup from shutdown can happen on pulse or level detection + * @note The wakeup from shutdown or ultra_deepstop can happen on pulse or level detection */ __STATIC_INLINE void LL_PWR_IOWakeupPolaritySDN(uint8_t pol) { @@ -524,9 +525,14 @@ __STATIC_INLINE void LL_PWR_IOWakeupPolaritySDN(uint8_t pol) } /** - * @brief Checks if Shutdown I/O Wakeup from PB0 pin occurred. + * @brief Checks if Shutdown/Ultra_deepstop I/O Wakeup occurred. * @rmtoll SDWN_WUF WUF LL_PWR_IsIOWakeupSDN - * @retval State of bit (1 or 0). + * @retval State of bit (1 or 0) + * @note For STM32WL3RX device the I/O wakeup from shutdown and ultra-deepstop modes can be occurred + by the following pins: PB0, PA0, PA7, PA8, PA9, and PA11. + * @note For STM32WL3XX device The I/O wakeup from shutdown mode can be occurred + by PB0 pin. + */ __STATIC_INLINE uint32_t LL_PWR_IsIOWakeupSDN(void) { @@ -534,9 +540,13 @@ __STATIC_INLINE uint32_t LL_PWR_IsIOWakeupSDN(void) } /** - * @brief Clear I/O Wakeup from PB0 pin occurred flag + * @brief Clear I/O Wakeup occurred flag * @rmtoll SDWN_WUF WUF LL_PWR_ClearIOWakeupFlagSDN * @retval None + * @note For STM32WL3RX device the I/O wakeup from shutdown and ultra-deepstop modes can be occurred + by the following pins: PB0, PA0, PA7, PA8, PA9, and PA11 + * @note For STM32WL3XX device The I/O wakeup from shutdown mode can be occurred + by PB0 pin */ __STATIC_INLINE void LL_PWR_ClearIOWakeupFlagSDN(void) { @@ -550,6 +560,7 @@ __STATIC_INLINE void LL_PWR_ClearIOWakeupFlagSDN(void) * @param LowPowerMode Low Power Mode Selection. This parameter can be one of the following values: * @arg @ref LL_PWR_MODE_DEEPSTOP * @arg @ref LL_PWR_MODE_SHUTDOWN + * @arg @ref LL_PWR_MODE_ULTRA_DEEPSTOP * @retval None */ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) @@ -563,6 +574,7 @@ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_MODE_DEEPSTOP * @arg @ref LL_PWR_MODE_SHUTDOWN + * @arg @ref LL_PWR_MODE_ULTRA_DEEPSTOP */ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) @@ -1214,6 +1226,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MRSUBGHCPU(void) return ((READ_BIT(PWR->IWUF, PWR_IWUF_WMRSUBGHCPUF) == (PWR_IWUF_WMRSUBGHCPUF)) ? 1UL : 0UL); } +#if defined(LPAWUR) /** * @brief Get LPAWUR Flag * @rmtoll IWUF WLPAWURF LL_PWR_IsActiveFlag_LPAWUR @@ -1223,6 +1236,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_LPAWUR(void) { return ((READ_BIT(PWR->IWUF, PWR_IWUF_WLPAWURF) == (PWR_IWUF_WLPAWURF)) ? 1UL : 0UL); } +#endif /* LPAWUR */ /** * @brief Get IO BOOT value. @@ -1305,6 +1319,38 @@ __STATIC_INLINE uint32_t LL_PWR_IsSMPSinPRECHARGEMode(void) return ((READ_BIT(PWR->SR2, PWR_SR2_SMPSBYPR) == (PWR_SR2_SMPSBYPR)) ? 1UL : 0UL); } +#if defined (STM32WL3RX) +/** + * @brief Enable ULTRA_DEEPSTOP bit + * @rmtoll PDCRA UDP LL_PWR_EnableUDP + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUDP(void) +{ + SET_BIT(PWR->PDCRA, PWR_PDCRA_UDP); +} + +/** + * @brief Disable ULTRA_DEEPSTOP bit + * @rmtoll PDCRA UDP LL_PWR_DisableUDP + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUDP(void) +{ + CLEAR_BIT(PWR->PDCRA, PWR_PDCRA_UDP); +} + +/** + * @brief Check if ULTRA_DEEPSTOP bit is enabled + * @rmtoll PDCRA UDP LL_PWR_IsEnabledUDP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUDP(void) +{ + return ((READ_BIT(PWR->PDCRA, PWR_PDCRA_UDP) == (PWR_PDCRA_UDP)) ? 1UL : 0UL); +} +#endif /* STM32WL3RX */ + /** * @brief Set SMPS Mode. * @rmtoll CR5 PWR_CR5_NOSMPS LL_PWR_SetSMPSMode @@ -2856,6 +2902,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_MRSUBGHCPU(void) WRITE_REG(PWR->IWUF, PWR_IWUF_WMRSUBGHCPUF); } +#if defined (LPAWUR) /** * @brief Clear LPAWUR wakeup flag * @rmtoll IWUF WLPAWURF LL_PWR_ClearFlag_LPAWUR @@ -2866,6 +2913,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_LPAWUR(void) WRITE_REG(PWR->IWUF, PWR_IWUF_WLPAWURF); } +#endif /* LPAWUR */ /** * @} */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_spi.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_spi.h index 21e47e0b0a..2941394eea 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_spi.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_spi.h @@ -1404,6 +1404,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); * @} */ +#if defined(SPI_I2S_SUPPORT) /** @defgroup I2S_LL I2S * @{ */ @@ -2267,6 +2268,7 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, /** * @} */ +#endif /* SPI_I2S_SUPPORT */ #endif /* defined (SPI1) || defined (SPI3) */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_utils.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_utils.h index ce4653e142..2c11674656 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_utils.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_utils.h @@ -277,10 +277,10 @@ void LL_mDelay(uint32_t Delay); void LL_SetSystemCoreClock(uint32_t HCLKFrequency); uint32_t LL_GetSystemCoreClock(void); -#if defined(STM32WL3XX) +#if defined(STM32WL3XX) || defined(STM32WL3RX) void LL_SetXTALFreq(uint32_t freq); uint32_t LL_GetXTALFreq(void); -#endif /* STM32WL3XX */ +#endif /* STM32WL3XX || (STM32WL3RX) */ /** * @} diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WL3x_HAL_Driver/Release_Notes.html index 28e1769699..ed3799a6d3 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WL3x_HAL_Driver/Release_Notes.html @@ -40,19 +40,107 @@

Purpose

Update History

- +

Main Changes

-

Release of HAL and LL drivers for STM32WL3x devices

+
    +
  • HAL and LL drivers updates to support STM32WL3Rx product line.
    • +
  • Corrections/enhancements to the following HAL drivers: ADC, MRSUBG, RCC, MRSUBG Timer, GPIO, UART, USART, LCSC, PWR.
    • +

Contents

HAL Drivers updates

    +
  • HAL ADC driver +
      +
    • Improving accuracy of calibration value for VINM input (changing sign of the applied value)
      • +
    • Fix rmtoll doxygen comment in LL_ADC_GetCalibPointOffset()
      • +
    • Optimize precision of temperature sensor data conversion
      • +
    • +
  • HAL RCC driver +
      +
    • Add LL RCC APIs to manage RTC clock: LL_RCC_EnableRTC(), LL_RCC_DisableRTC() and LL_RCC_IsEnabledRTC()
      • +
    • +
  • HAL MRSUBG driver +
      +
    • Turned IS_169MHZ define into STM32WL33XA.
      • +
    • Added get and set API for SQI Threshold: +
      __HAL_MRSUBG_SET_SQI_THRESHOLD(__THRVAL__)
      +
      • +
      __HAL_MRSUBG_GET_SQI_THRESHOLD()
      + +
    • Fixed HAL_MRSubG_GetPALeveldBm() when PA is set in LEGACY o FIR mode
      • +
    • Added LL_MRSubG_GetPAMode() to retrieve the current PA mode
      • +
    • Fixed build errors when assertions are enabled.
      • +
    • +
  • HAL MRSUBG_TIMER driver +
      +
    • Enhanced power-saving state mechanism
      • +
    • +
  • HAL GPIO driver +
      +
    • Added else clause to disable pull-up/down resistors when GPIO mode is analog
      • +
    • +
  • HAL PWR driver +
      +
    • Added support to STM32WL3Rx ultra deepstop low power mode.
      • +
    • +
  • HAL LPUART driver +
      +
    • Solve Coverity out-of-bound memory access warning in use of LPUART_PRESCALER_TAB array
      • +
    • +
  • LL ADC driver +
      +
    • Fix assert_param define
      • +
    • +
  • LL LCSC driver +
      +
    • Fixed incorrect clearing of LCSC interrupt flags in LL driver
      • +
    • +
  • LL USART driver +
      +
    • Solve Coverity out-of-bound memory access warning in use of USART_PRESCALER_TAB array
      • +
    • +
+

BSP updates

+

Supported Devices and boards

+
    +
  • NUCLEO-WL33CC1 board
    • +
  • NUCLEO-WL33CC2 board
    • +
  • NUCLEO-WL3RKB1 board
    • +
  • NUCLEO-WL3RKB2 board
    • +
+

Backward compatibility

+
    +
  • Not applicable
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Dependencies

+
    +
  • None
    • +
+

Notes

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+

Release of HAL and LL drivers for STM32WL3x devices

+

Contents

+

HAL Drivers updates

+
  • HAL MRSUBG driver
    • Fixed wrong length of SYNC word in wM-Bus packet initialization function.
    • Fixed HAL_MRSubG_Sequencer_Microseconds return value.
      • -
    • Moved HAL_MRSUBG_TIMER_CPU_WKUP IRQ Handler from MRSUBG to MRSUBG TIMER.
      • -
    • Updated names of IRQ handlers.
      • +
    • HAL_MRSUBG_TIMER_CPU_WKUP IRQ Handler moved from MRSUBG to MRSUBG TIMER.
      • +
    • Updated names for IRQ handlers.
  • HAL LPAWUR driver
      @@ -60,34 +148,43 @@

      HAL Drivers updates

  • HAL RCC driver
      +
    • Add LL RCC APIs to manage RTC clock: LL_RCC_EnableRTC(), LL_RCC_DisableRTC() and LL_RCC_IsEnabledRTC().
    • Added support for RCC_LPUART1_CLKSOURCE_16M with a frequency of 16,000,000.

LL Drivers updates

    -
  • LL RCC driver +
  • LL ADC driver
      -
    • Added LL RCC APIs to manage RTC clock: LL_RCC_EnableRTC(), LL_RCC_DisableRTC() and LL_RCC_IsEnabledRTC().
      • +
    • Fix rmtoll doxygen comment in LL_ADC_GetCalibPointOffset()
      • +
    • +
  • LL USART driver +
      +
    • Solve Coverity out-of-bound memory access warning in use of USART_PRESCALER_TAB array.
      • +
    • +
  • LL LPUART driver +
      +
    • Solve Coverity out-of-bound memory access warning in use of LPUART_PRESCALER_TAB array.
-

Supported Devices and boards

+

Supported Devices and boards

  • NUCLEO-WL33CC1 board
  • NUCLEO-WL33CC2 board
-

Backward compatibility

+

Backward compatibility

  • Not applicable
-

Known Limitations

+

Known Limitations

  • None
-

Dependencies

+

Dependencies

  • None
-

Notes

+

Notes

  • None
@@ -96,7 +193,7 @@

Notes

-

Main Changes

+

Main Changes

Release of HAL and LL drivers for STM32WL3x devices

Improved MRSUBG LL and HAL drivers with new APIs and macros:
    @@ -152,7 +249,7 @@

    Release of

Check the code documentation for further details.

-

Contents

+

Contents

  • Release of HAL/LL drivers
      @@ -160,24 +257,24 @@

      Contents

    • LL: COMP, CRC, DMA, GPIO, I2C, LCSC, LPUART, LPAWUR, MRSUBG, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS

-

Supported Devices and boards

+

Supported Devices and boards

  • NUCLEO-WL33CC1 board
  • NUCLEO-WL33CC2 board
-

Backward compatibility

+

Backward compatibility

  • Not applicable
-

Known Limitations

+

Known Limitations

  • None
-

Dependencies

+

Dependencies

  • None
-

Notes

+

Notes

  • None
@@ -186,9 +283,9 @@

Notes

-

Main Changes

+

Main Changes

First Official Release of HAL and LL drivers for STM32WL33 devices

-

Contents

+

Contents

  • First Official Release of HAL/LL drivers
      @@ -196,23 +293,23 @@

      Contents

    • LL: COMP, CRC, DMA, GPIO, I2C, LCSC, LPUART, LPAWUR, MRSUBG, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS

-

Supported Devices and boards

+

Supported Devices and boards

  • NUCLEO-WL33CC board
-

Backward compatibility

+

Backward compatibility

  • Not applicable
-

Known Limitations

+

Known Limitations

  • None
-

Dependencies

+

Dependencies

  • None
-

Notes

+

Notes

  • None
diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c index d1b9f3dd01..9cd95caf30 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c @@ -107,7 +107,7 @@ static void FLASH_Program_OTPWord(uint32_t Address, uint32_t Data); */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t index; /* Check the parameters */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_gpio.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_gpio.c index be1f56f211..494d58a355 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_gpio.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_gpio.c @@ -212,6 +212,12 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((GPIO_Init->Pull) << (position * 2U)); GPIOx->PUPDR = temp; } + else + { + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + GPIOx->PUPDR = temp; + } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_i2s.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_i2s.c index 01e5a44134..6c66a13071 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_i2s.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_i2s.c @@ -185,6 +185,7 @@ #ifdef HAL_I2S_MODULE_ENABLED +#if defined(SPI_I2S_SUPPORT) /** @addtogroup STM32WL3x_HAL_Driver * @{ */ @@ -1847,5 +1848,6 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, /** * @} */ +#endif /* SPI_I2S_SUPPORT */ #endif /* HAL_I2S_MODULE_ENABLED */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_lpawur.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_lpawur.c index 1090fe2ed2..f6b2694c95 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_lpawur.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_lpawur.c @@ -23,7 +23,7 @@ /** @addtogroup STM32WL3x_HAL_Driver * @{ */ - +#if defined (LPAWUR) /** @addtogroup LPAWUR * @{ */ @@ -350,7 +350,7 @@ void HAL_LPAWUR_IRQHandler(void) /** * @} */ - +#endif /* LPAWUR */ /** * @} */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg.c index fb61750b7f..256ce45b53 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2024-2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -47,29 +47,36 @@ #define S_ABS(a) ((a)>0?(a):-(a)) +#if defined(STM32WL3RX) +#define IS_FREQUENCY_BAND_LOW_LOW(FREQUENCY) ((FREQUENCY) >= LOW_LOW_BAND_LOWER_LIMIT && \ + (FREQUENCY) <= LOW_LOW_BAND_UPPER_LIMIT) +#define IS_FREQUENCY_BAND(FREQUENCY) (IS_FREQUENCY_BAND_HIGH(FREQUENCY) || \ + IS_FREQUENCY_BAND_LOW(FREQUENCY) || \ + IS_FREQUENCY_BAND_LOW_LOW(FREQUENCY)) +#else #define IS_FREQUENCY_BAND(FREQUENCY) (IS_FREQUENCY_BAND_HIGH(FREQUENCY) || \ IS_FREQUENCY_BAND_LOW(FREQUENCY)) +#endif /* STM32WL3RX */ #define IS_FREQUENCY_BAND_HIGH(FREQUENCY) ((FREQUENCY)>=HIGH_BAND_LOWER_LIMIT && \ (FREQUENCY)<=HIGH_BAND_UPPER_LIMIT) - - #define IS_FREQUENCY_BAND_LOW(FREQUENCY) ((FREQUENCY)>=LOW_BAND_LOWER_LIMIT && \ - (FREQUENCY)<=LOW_BAND_UPPER_LIMIT) + (FREQUENCY)<=LOW_BAND_UPPER_LIMIT) #define IS_MODULATION(MOD) (((MOD) == MOD_2FSK) || \ - ((MOD) == MOD_4FSK) || \ - ((MOD) == MOD_2GFSK05) || \ - ((MOD) == MOD_2GFSK1) || \ - ((MOD) == MOD_4GFSK05) || \ - ((MOD) == MOD_4GFSK1) || \ - ((MOD) == MOD_ASK) || \ - ((MOD) == MOD_OOK) || \ - ((MOD) == MOD_POLAR) || \ - ((MOD) == MOD_CW) ) + ((MOD) == MOD_4FSK) || \ + ((MOD) == MOD_2GFSK05) || \ + ((MOD) == MOD_2GFSK1) || \ + ((MOD) == MOD_4GFSK05) || \ + ((MOD) == MOD_4GFSK1) || \ + ((MOD) == MOD_ASK) || \ + ((MOD) == MOD_OOK) || \ + ((MOD) == MOD_POLAR) || \ + ((MOD) == MOD_CW) ) #define IS_DATARATE(DATARATE) (DATARATE>=MINIMUM_DATARATE && DATARATE<=((uint64_t)MAXIMUM_DATARATE)) +#define IS_PAMODEDBM(PAMODE) ((PAMODE == PA_LEGACY) || (PAMODE == PA_FIR)) /** * @} */ @@ -78,26 +85,28 @@ * @{ */ -static const uint32_t s_Channel_Filter_Bandwidth[99]= +static const uint32_t s_Channel_Filter_Bandwidth[99] = { - 1600000,1510000,1422000,1332000,1244000,1154000,1066000, \ - 976000,888000,800000,755000,711000,666000,622000,577000, \ - 533000,488000,444000,400000,377000,355000,333000,311000, \ - 288000,266000,244000,222000,200000,188000,178000,166000, \ - 155000,144000,133000,122000,111000,100000,94400,88900,83300, \ - 77800,72200,66700,61100,55600,50000,47200,44400,41600,38900, \ - 36100,33300,30500,27800,25000,23600,22200,20800,19400,18100, \ - 16600,15300,13900,12500,11800,11100,10400,9700,9000,8300,7600, \ - 6900,6125,5910,5550,5200,4870,4500,4100,3800,3500,3125,2940, \ - 2780,2600,2400,2200,2100,1900,1700 + 1600000, 1510000, 1422000, 1332000, 1244000, 1154000, 1066000, \ + 976000, 888000, 800000, 755000, 711000, 666000, 622000, 577000, \ + 533000, 488000, 444000, 400000, 377000, 355000, 333000, 311000, \ + 288000, 266000, 244000, 222000, 200000, 188000, 178000, 166000, \ + 155000, 144000, 133000, 122000, 111000, 100000, 94400, 88900, 83300, \ + 77800, 72200, 66700, 61100, 55600, 50000, 47200, 44400, 41600, 38900, \ + 36100, 33300, 30500, 27800, 25000, 23600, 22200, 20800, 19400, 18100, \ + 16600, 15300, 13900, 12500, 11800, 11100, 10400, 9700, 9000, 8300, 7600, \ + 6900, 6125, 5910, 5550, 5200, 4870, 4500, 4100, 3800, 3500, 3125, 2940, \ + 2780, 2600, 2400, 2200, 2100, 1900, 1700 }; -const uint32_t SFD_2FSK[] = { +const uint32_t SFD_2FSK[] = +{ 0x904E0000, /* "1001000001001110" */ 0x6F4E0000 /* "0110111101001110" */ }; -const uint32_t SFD_4FSK[] = { +const uint32_t SFD_4FSK[] = +{ 0xD75575FD, /* "11010111010101010111010111111101" */ 0x7DFF75FD /* "01111101111111110111010111111101" */ }; @@ -113,199 +122,235 @@ static WMbusSubmode s_cWMbusSubmode = WMBUS_SUBMODE_NOT_CONFIGURED; */ static uint32_t MRSubG_ComputeDatarate(uint16_t cM, uint8_t cE); -static void MRSubG_SearchDatarateME(uint32_t lDatarate, uint16_t* pcM, uint8_t* pcE); -static void MRSubG_SearchFreqDevME(uint32_t lFDev, uint8_t* pcM, uint8_t* pcE, uint8_t bs); +static void MRSubG_SearchDatarateME(uint32_t lDatarate, uint16_t *pcM, uint8_t *pcE); +static void MRSubG_SearchFreqDevME(uint32_t lFDev, uint8_t *pcM, uint8_t *pcE, uint8_t bs); static uint32_t MRSubG_ComputeFreqDeviation(uint8_t cM, uint8_t cE, uint8_t bs); -static void MRSubG_SearchChannelBwME(uint32_t lBandwidth, uint8_t* pcM, uint8_t* pcE); -static void MRSubG_ComputeSynthWord(uint32_t frequency, uint8_t* synth_int, uint32_t* synth_frac, uint8_t* band); +static void MRSubG_SearchChannelBwME(uint32_t lBandwidth, uint8_t *pcM, uint8_t *pcE); +static void MRSubG_ComputeSynthWord(uint32_t frequency, uint8_t *synth_int, uint32_t *synth_frac, uint8_t *band); static int32_t MRSubG_ConvertRssiToDbm(uint16_t rssi_level_from_register); static uint8_t MRSubG_GetAllowedMaxOutputPower(MRSubG_PA_DRVMode paMode); static void MRSUBG_EvaluateDSSS(MRSubGModSelect xModulation, uint8_t dsssExponent); /** -* @brief Computes the synth word from a given frequency. -* @param frequency Target frequency value expressed in Hz. -* @param synth_int pointer to the int part of the synth word -* @param synth_frac pointer to the fract part of the synth word -* @param band pointer to the high/low band selector -* @retval None. -*/ -static void MRSubG_ComputeSynthWord(uint32_t frequency, uint8_t* synth_int, uint32_t* synth_frac, uint8_t* band) + * @brief Computes the synth word from a given frequency. + * @param frequency Target frequency value expressed in Hz. + * @param synth_int pointer to the int part of the synth word + * @param synth_frac pointer to the fract part of the synth word + * @param band pointer to the high/low band selector + * @retval None. + */ +static void MRSubG_ComputeSynthWord(uint32_t frequency, uint8_t *synth_int, uint32_t *synth_frac, uint8_t *band) { - if(IS_FREQUENCY_BAND_HIGH(frequency)) { + if (IS_FREQUENCY_BAND_HIGH(frequency)) + { *band = HIGH_BAND_FACTOR; } - else { +#if defined(STM32WL3RX) + else if (IS_FREQUENCY_BAND_LOW_LOW(frequency)) + { + *band = LOW_LOW_BAND_FACTOR; + } +#endif /* STM32WL3RX */ + else + { *band = LOW_BAND_FACTOR; } - *synth_int = (uint32_t)(*band * frequency/LL_GetXTALFreq()); + *synth_int = (uint32_t)(*band * frequency / LL_GetXTALFreq()); - *synth_frac = (uint32_t)(((*band * (uint64_t)frequency * (1<<20))/LL_GetXTALFreq()) - (*synth_int * (1<<20))); + *synth_frac = (uint32_t)(((*band * (uint64_t)frequency * (1 << 20)) / LL_GetXTALFreq()) - (*synth_int * (1 << 20))); } /** -* @brief Evaluate the data rate. -* @param cM the mantissa value. -* @param cE the exponent value. -* @retval The datarate. -*/ + * @brief Evaluate the data rate. + * @param cM the mantissa value. + * @param cE the exponent value. + * @retval The datarate. + */ static uint32_t MRSubG_ComputeDatarate(uint16_t cM, uint8_t cE) { - uint32_t f_sys=LL_GetXTALFreq()/3; /* 16 MHz nominal */ + uint32_t f_sys = LL_GetXTALFreq() / 3; /* 16 MHz nominal */ uint64_t dr; - if(cE==0){ - dr = ((uint64_t)f_sys*cM); - return (uint32_t)(dr>>32); + if (cE == 0) + { + dr = ((uint64_t)f_sys * cM); + return (uint32_t)(dr >> 32); } - else if(cE==15){ - return ((uint64_t)f_sys*(8*cM)); + else if (cE == 15) + { + return ((uint64_t)f_sys * (8 * cM)); } - else{ - dr = ((uint64_t)f_sys)*((uint64_t)cM+65536); - return (uint32_t)(dr>>(33-cE)); + else + { + dr = ((uint64_t)f_sys) * ((uint64_t)cM + 65536); + return (uint32_t)(dr >> (33 - cE)); } } -/** -* @brief Returns the mantissa and exponent, whose value used in the datarate formula -* will give the datarate value closer to the given datarate. -* @param lDatarate datarate expressed in sps. -* @param pcM pointer to the returned mantissa value. -* @param pcE pointer to the returned exponent value. -* @retval None. -*/ -static void MRSubG_SearchDatarateME(uint32_t lDatarate, uint16_t* pcM, uint8_t* pcE) +static void MRSubG_SearchDatarateME(uint32_t lDatarate, uint16_t *pcM, uint8_t *pcE) { - uint32_t lDatarateTmp, f_sys=LL_GetXTALFreq()/3; + uint32_t lDatarateTmp; + uint32_t f_sys = LL_GetXTALFreq() / 3; uint8_t uDrE; - uint64_t tgt1,tgt2,tgt; + uint64_t tgt1; + uint64_t tgt2; + uint64_t tgt; /* Search the exponent value */ - for(uDrE = 0; uDrE<16; uDrE++) { + for (uDrE = 0; uDrE < 16; uDrE++) + { lDatarateTmp = MRSubG_ComputeDatarate(0xFFFF, uDrE); - if(lDatarate<=lDatarateTmp) + if (lDatarate <= lDatarateTmp) + { break; + } } (*pcE) = (uint8_t)uDrE; - if(uDrE==0) { - tgt=((uint64_t)lDatarate)<<32; - (*pcM) = (uint16_t)(tgt/f_sys); - tgt1=(uint64_t)f_sys*(*pcM); - tgt2=(uint64_t)f_sys*((*pcM)+1); + if (uDrE == 0) + { + tgt = ((uint64_t)lDatarate) << 32; + (*pcM) = (uint16_t)(tgt / f_sys); + tgt1 = (uint64_t)f_sys * (*pcM); + tgt2 = (uint64_t)f_sys * ((*pcM) + 1); } - else { - tgt=((uint64_t)lDatarate)<<(33-uDrE); - (*pcM) = (uint16_t)((tgt/f_sys)-65536); - tgt1=(uint64_t)f_sys*((*pcM)+65536); - tgt2=(uint64_t)f_sys*((*pcM)+1+65536); + else + { + tgt = ((uint64_t)lDatarate) << (33 - uDrE); + (*pcM) = (uint16_t)((tgt / f_sys) - 65536); + tgt1 = (uint64_t)f_sys * ((*pcM) + 65536); + tgt2 = (uint64_t)f_sys * ((*pcM) + 1 + 65536); } - (*pcM)=((tgt2-tgt)<(tgt-tgt1))?((*pcM)+1):(*pcM); + (*pcM) = ((tgt2 - tgt) < (tgt - tgt1)) ? ((*pcM) + 1) : (*pcM); } /** -* @brief Returns the mantissa and exponent, whose value used in the Frequency Deviation formula -* will give the value closer to the given one. -* @param cM the mantissa value. -* @param cE the exponent value. -* @param bs the band value. -* @retval The frequency deviation. -*/ -static uint32_t MRSubG_ComputeFreqDeviation(uint8_t cM, uint8_t cE, uint8_t bs){ + * @brief Returns the mantissa and exponent, whose value used in the Frequency Deviation formula + * will give the value closer to the given one. + * @param cM the mantissa value. + * @param cE the exponent value. + * @param bs the band value. + * @retval The frequency deviation. + */ +static uint32_t MRSubG_ComputeFreqDeviation(uint8_t cM, uint8_t cE, uint8_t bs) +{ uint32_t f_xo = LL_GetXTALFreq(); - if(cE==0) { - return (uint32_t)((uint64_t)f_xo*(cM*bs/8)/(bs*(1<<19))); + if (cE == 0) + { + return (uint32_t)((uint64_t)f_xo * (cM * bs / 8) / (bs * (1 << 19))); } - return (uint32_t)((uint64_t)f_xo*((256+cM)*(1<<(cE-1))*bs/8)/(bs*(1<<19)));; + return (uint32_t)((uint64_t)f_xo * ((256 + cM) * (1 << (cE - 1)) * bs / 8) / (bs * (1 << 19)));; } /** -* @brief Returns the mantissa and exponent, whose value used in the Frequency Deviation formula -* will give the value closer to the given one. -* @param lFDev frequency deviation expressed in Hz. -* @param pcM pointer to the returned mantissa value. -* @param pcE pointer to the returned exponent value. -* @param bs the high/low band selector -* @retval None. -*/ -static void MRSubG_SearchFreqDevME(uint32_t lFDev, uint8_t* pcM, uint8_t* pcE, uint8_t bs){ + * @brief Returns the mantissa and exponent, whose value used in the Frequency Deviation formula + * will give the value closer to the given one. + * @param lFDev frequency deviation expressed in Hz. + * @param pcM pointer to the returned mantissa value. + * @param pcE pointer to the returned exponent value. + * @param bs the high/low band selector + * @retval None. + */ +static void MRSubG_SearchFreqDevME(uint32_t lFDev, uint8_t *pcM, uint8_t *pcE, uint8_t bs) +{ uint8_t uFDevE; uint32_t lFDevTmp; - uint64_t tgt1,tgt2,tgt; + uint64_t tgt1; + uint64_t tgt2; + uint64_t tgt; /* Search the exponent of the frequency deviation value */ - for(uFDevE = 0; uFDevE != 12; uFDevE++) { + for (uFDevE = 0; uFDevE != 12; uFDevE++) + { lFDevTmp = MRSubG_ComputeFreqDeviation(255, uFDevE, bs); - if(lFDev=0) && ((i_tmp+j-1)<=98)) { - chfltCalculation[j] = (int32_t)lBandwidth - (int32_t)(((uint64_t)s_Channel_Filter_Bandwidth[i_tmp+j-1]*f_dig)/16000000); + for (j = 0; j < 3; j++) + { + if (((i_tmp + j - 1) >= 0) && ((i_tmp + j - 1) <= 98)) + { + chfltCalculation[j] = (int32_t)lBandwidth - + (int32_t)(((uint64_t)s_Channel_Filter_Bandwidth[i_tmp + j - 1] * f_dig) / 16000000); } - else { + else + { chfltCalculation[j] = 0x7FFFFFFF; } } - uint32_t chfltDelta = 0xFFFFFFFF; - for(uint8_t j=0;j<3;j++) { - if(S_ABS(chfltCalculation[j]) 3) { - dsss_acq_thr = dsss_sf/2; + if (dsssExponent > 3) + { + dsss_acq_thr = dsss_sf / 2; } MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->DSSS_CTRL, MR_SUBG_GLOB_STATIC_DSSS_CTRL_DSSS_EN, dsss_en); @@ -369,18 +420,17 @@ static void MRSUBG_EvaluateDSSS(MRSubGModSelect xModulation, uint8_t dsssExponen * @} */ - /** @defgroup MRSUBG_Exported_Functions MRSUBG Exported Functions * @{ */ /** -* @brief Get the IP version of the MRSubG. -* @retval IP version. -*/ -SMRSubGVersion HAL_MRSubGGetVersion(void) + * @brief Get the IP version of the MRSubG. + * @retval IP version. + */ +SMRSubGVersion_t HAL_MRSubGGetVersion(void) { - SMRSubGVersion MRSubGVersion; + SMRSubGVersion_t MRSubGVersion; MRSubGVersion.product = READ_REG_FIELD(MR_SUBG_GLOB_MISC->RFIP_VERSION, MR_SUBG_GLOB_MISC_RFIP_VERSION_PRODUCT); MRSubGVersion.version = READ_REG_FIELD(MR_SUBG_GLOB_MISC->RFIP_VERSION, MR_SUBG_GLOB_MISC_RFIP_VERSION_VERSION); @@ -388,15 +438,15 @@ SMRSubGVersion HAL_MRSubGGetVersion(void) return MRSubGVersion; } - /** -* @brief Initializes the MR_SUBG radio interface according to the specified -* parameters in the pxSRadioInitStruct. -* @param pxSRadioInitStruct pointer to a SMRSubGConfig structure that -* contains the configuration information for the MR_SUBG radio part of STM32WL3. -* @retval Error code: 0=no error, 1=error during calibration of VCO. -*/ -uint8_t HAL_MRSubG_Init(SMRSubGConfig* pxSRadioInitStruct){ + * @brief Initializes the MR_SUBG radio interface according to the specified + * parameters in the pxSRadioInitStruct. + * @param pxSRadioInitStruct pointer to a SMRSubGConfig_t structure that + * contains the configuration information for the MR_SUBG radio part of STM32WL3x. + * @retval Error code: 0=no error, 1=error during calibration of VCO. + */ +uint8_t HAL_MRSubG_Init(SMRSubGConfig_t *pxSRadioInitStruct) +{ assert_param(IS_FREQUENCY_BAND(pxSRadioInitStruct->lFrequencyBase)); assert_param(IS_MODULATION(pxSRadioInitStruct->xModulationSelect)); @@ -446,11 +496,12 @@ uint8_t HAL_MRSubG_Init(SMRSubGConfig* pxSRadioInitStruct){ } /** - * @brief Get the main radio info for the current configuration. - * @param pxSRadioInitStruct pointer to a structure of the type of @ref SMRSubGConfig - * @retval None. - */ -void HAL_MRSubG_GetInfo(SMRSubGConfig* pxSRadioInitStruct){ + * @brief Get the main radio info for the current configuration. + * @param pxSRadioInitStruct pointer to a structure of the type of @ref SMRSubGConfig_t + * @retval None. + */ +void HAL_MRSubG_GetInfo(SMRSubGConfig_t *pxSRadioInitStruct) +{ pxSRadioInitStruct->lFrequencyBase = HAL_MRSubG_GetFrequencyBase(); pxSRadioInitStruct->xModulationSelect = HAL_MRSubG_GetModulation(); pxSRadioInitStruct->lDatarate = HAL_MRSubG_GetDatarate(); @@ -461,11 +512,12 @@ void HAL_MRSubG_GetInfo(SMRSubGConfig* pxSRadioInitStruct){ } /** -* @brief Set the Synth word and the Band Select register according to desired base carrier frequency. -* @param lFBase the base carrier frequency expressed in Hz as unsigned word. -* @retval None. -*/ -void HAL_MRSubG_SetFrequencyBase(uint32_t lFBase){ + * @brief Set the Synth word and the Band Select register according to desired base carrier frequency. + * @param lFBase the base carrier frequency expressed in Hz as unsigned word. + * @retval None. + */ +void HAL_MRSubG_SetFrequencyBase(uint32_t lFBase) +{ uint8_t band; uint8_t synth_int; uint32_t synth_frac; @@ -479,42 +531,66 @@ void HAL_MRSubG_SetFrequencyBase(uint32_t lFBase){ MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_SYNTH_FRAC, synth_frac); MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->ADDITIONAL_CTRL, MR_SUBG_GLOB_DYNAMIC_ADDITIONAL_CTRL_CH_NUM, 0x00); -#if defined(IS_169MHZ) - b_factor = (20-band)/12; +#if defined(STM32WL33XA) + b_factor = (20 - band) / 12; +#elif defined(STM32WL3RX) + if (band == 12) + { + SET_BIT(MR_SUBG_RADIO->RFANA_PLL_IN, MR_SUBG_RADIO_RFANA_PLL_IN_DIV12_SEL); + b_factor = 1; + } + else + { + b_factor = (band / 4) - 1; + } #else - b_factor = (band/4)-1; -#endif + b_factor = (band / 4) - 1; +#endif /* STM32WL3RX */ MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS, b_factor); } /** -* @brief Return the base carrier frequency. -* @retval uint32_t Base carrier frequency expressed in Hz as unsigned word. -*/ + * @brief Return the base carrier frequency. + * @retval uint32_t Base carrier frequency expressed in Hz as unsigned word. + */ uint32_t HAL_MRSubG_GetFrequencyBase(void) { -#if defined(IS_169MHZ) - uint8_t bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS)); - bs = bs?8:20; +#if defined(STM32WL33XA) + uint8_t bs = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS); + bs = bs ? 8 : 20; #else - uint8_t bs = ((READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS)+1)*4); -#endif - uint8_t synth_int = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_SYNTH_INT); + uint8_t bs; +#if defined(STM32WL3RX) + if (READ_BIT(MR_SUBG_RADIO->RFANA_PLL_IN, MR_SUBG_RADIO_RFANA_PLL_IN_DIV12_SEL)) + { + bs = 12; + } + else + { + bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; + } +#else + bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; +#endif /* STM32WL3RX */ +#endif /* STM32WL33XA */ + + uint8_t synth_int = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_SYNTH_INT); uint32_t synth_frac = READ_REG(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ) & MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_SYNTH_FRAC; uint32_t fbase; - fbase = LL_GetXTALFreq()*((uint64_t)(synth_int*(1<<20) + synth_frac))/(bs*(1<<20)); + fbase = LL_GetXTALFreq() * ((uint64_t)(synth_int * (1 << 20) + synth_frac)) / (bs * (1 << 20)); return fbase; } /** -* @brief Set the datarate. -* @param lDatarate datarate expressed in sps. -* @retval None. -*/ -void HAL_MRSubG_SetDatarate(uint32_t lDatarate){ + * @brief Set the datarate. + * @param lDatarate datarate expressed in sps. + * @retval None. + */ +void HAL_MRSubG_SetDatarate(uint32_t lDatarate) +{ uint8_t dr_e; uint16_t dr_m; @@ -528,43 +604,62 @@ void HAL_MRSubG_SetDatarate(uint32_t lDatarate){ } /** -* @brief Return the datarate. -* @retval uint32_t Datarate expressed in sps. -*/ + * @brief Return the datarate. + * @retval uint32_t Datarate expressed in sps. + */ uint32_t HAL_MRSubG_GetDatarate(void) { - uint32_t dr, datarateM, datarateE; + uint32_t dr; + uint32_t datarateM; + uint32_t datarateE; uint32_t f_sys; datarateM = READ_REG(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG) & MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_DATARATE_M; datarateE = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_DATARATE_E); - f_sys = (uint32_t)(LL_GetXTALFreq()/3); + f_sys = (uint32_t)(LL_GetXTALFreq() / 3); if (datarateE == 0) - dr = f_sys*datarateM/(uint64_t)1<<32; + { + dr = f_sys * (datarateM / ((uint64_t)1 << 32)); + } else if (datarateE == 15) /* Jitter free mode */ - dr = f_sys/(8*datarateM); + { + dr = f_sys / (8 * datarateM); + } else - dr = f_sys*((uint64_t)(1<<16) + datarateM)*(1<SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS)); - bs = bs?8:20; +#if defined(STM32WL33XA) + bs = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS); + bs = bs ? 8 : 20; +#else +#if defined(STM32WL3RX) + if (READ_BIT(MR_SUBG_RADIO->RFANA_PLL_IN, MR_SUBG_RADIO_RFANA_PLL_IN_DIV12_SEL)) /* Checking if 315MHz band */ + { + bs = 12; + } + else + { + bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; + } #else - uint8_t bs = ((READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS)+1)*4); -#endif + bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; +#endif /* STM32WL3RX */ +#endif /* STM32WL33XA */ /* Calculates the frequency deviation mantissa and exponent */ MRSubG_SearchFreqDevME(lFDev, &uFDevM, &uFDevE, bs); @@ -574,9 +669,9 @@ void HAL_MRSubG_SetFrequencyDev(uint32_t lFDev){ } /** -* @brief Return the frequency deviation. -* @retval uint32_t Frequency deviation value expressed in Hz. -*/ + * @brief Return the frequency deviation. + * @retval uint32_t Frequency deviation value expressed in Hz. + */ uint32_t HAL_MRSubG_GetFrequencyDev(void) { uint8_t fdev_m; @@ -584,41 +679,53 @@ uint32_t HAL_MRSubG_GetFrequencyDev(void) uint32_t f_dev; uint16_t factor1; uint32_t factor2; + uint8_t bs; -#if defined(IS_169MHZ) - uint8_t bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS)); - bs = bs?8:20; +#if defined(STM32WL33XA) + bs = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS); + bs = bs ? 8 : 20; #else - uint8_t bs = ((READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS)+1)*4); -#endif +#if defined(STM32WL3RX) + if (READ_BIT(MR_SUBG_RADIO->RFANA_PLL_IN, MR_SUBG_RADIO_RFANA_PLL_IN_DIV12_SEL)) /* Checking if 315MHz band */ + { + bs = 12; + } + else + { + bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; + } +#else + bs = (READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->SYNTH_FREQ, MR_SUBG_GLOB_DYNAMIC_SYNTH_FREQ_BS) + 1) * 4; +#endif /* STM32WL3RX */ +#endif /* STM32WL33XA */ fdev_m = READ_REG(MR_SUBG_GLOB_DYNAMIC->MOD1_CONFIG) & MR_SUBG_GLOB_DYNAMIC_MOD1_CONFIG_FDEV_M; fdev_e = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD1_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD1_CONFIG_FDEV_E); - factor1 = fdev_e==0 ? 0 : 256; - factor2 = fdev_e==0 ? 0 : (fdev_e-1); + factor1 = fdev_e == 0 ? 0 : 256; + factor2 = fdev_e == 0 ? 0 : (fdev_e - 1); - f_dev = (LL_GetXTALFreq()*(uint64_t)((factor1+fdev_m)*(1<<(factor2))*bs/8)/(bs*(1<<19))); + f_dev = (LL_GetXTALFreq() * (uint64_t)((factor1 + fdev_m) * (1 << (factor2)) * bs / 8) / (bs * (1 << 19))); return f_dev; } /** -* @brief Set the channel filter bandwidth. -* @param lBandwidth channel filter bandwidth expressed in Hz. -* The API will search the most closer value according to a fixed table of channel -* bandwidth values (@ref s_Channel_Filter_Bandwidth). -* To verify the settled channel bandwidth it is possible to use the HAL_MRSubG_GetChannelBW API. -* @retval None. -*/ + * @brief Set the channel filter bandwidth. + * @param lBandwidth channel filter bandwidth expressed in Hz. + * The API will search the most closer value according to a fixed table of channel + * bandwidth values (@ref s_Channel_Filter_Bandwidth). + * To verify the settled channel bandwidth it is possible to use the HAL_MRSubG_GetChannelBW API. + * @retval None. + */ void HAL_MRSubG_SetChannelBW(uint32_t lBandwidth) { uint8_t uBwM = 0; uint8_t uBwE = 0; uint32_t f_if = 0; uint32_t if_offset = 0; - uint32_t chf_threshold = 400000; - uint32_t f_dig=LL_GetXTALFreq()/3; + uint32_t chf_threshold = CHANNEL_FILTER_THRESHOLD; + uint32_t f_dig = LL_GetXTALFreq() / 3; /* Calculates the channel bandwidth mantissa and exponent */ MRSubG_SearchChannelBwME(lBandwidth, &uBwM, &uBwE); @@ -626,100 +733,121 @@ void HAL_MRSubG_SetChannelBW(uint32_t lBandwidth) MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD1_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD1_CONFIG_CHFLT_M, uBwM); MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD1_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD1_CONFIG_CHFLT_E, uBwE); - /* Set IF to 600 kHz, if channel filter requested is greater then CHF threshold */ - if (lBandwidth > chf_threshold){ + /* Set IF to 600 kHz, if channel filter requested is greater than CHF threshold */ + if (lBandwidth > chf_threshold) + { SET_BIT(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_MODE); /* Define f_if */ - f_if = 600; + f_if = IF_FREQ_HIGH; } - else{ + else + { /* Set antialiasing filter to 684kHz */ CLEAR_BIT(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_MODE); /* Define f_if */ - f_if = 300; + f_if = IF_FREQ_LOW; } - if_offset = (((f_if*100)*65536)/f_dig)*10; + if_offset = (((f_if * 100) * 65536) / f_dig) * 10; /* Set IF */ -#if defined(IS_169MHZ) +#if defined(STM32WL33XA) /* WL33xA */ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_ANA, 0); +#elif defined(STM32WL3RX) + /* Checking if 315MHz band */ + if (READ_BIT(MR_SUBG_RADIO->RFANA_PLL_IN, MR_SUBG_RADIO_RFANA_PLL_IN_DIV12_SEL)) + { + uint32_t if_offset_ana = if_offset * 3 / 2; + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_ANA, if_offset_ana); + } + else + { + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_ANA, if_offset); + } #else - /* WL33x */ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_ANA, if_offset); -#endif +#endif /*STM32WL3RX*/ MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->IF_CTRL, MR_SUBG_GLOB_STATIC_IF_CTRL_IF_OFFSET_DIG, if_offset); } /** -* @brief Return the channel filter bandwidth. -* @retval uint32_t Channel filter bandwidth expressed in Hz. -*/ + * @brief Return the channel filter bandwidth. + * @retval uint32_t Channel filter bandwidth expressed in Hz. + */ uint32_t HAL_MRSubG_GetChannelBW(void) { - uint8_t cm, ce; + uint8_t cm; + uint8_t ce; + uint8_t index; + uint32_t fclk; + uint32_t correction_factor; - uint32_t fclk = (LL_GetXTALFreq()/3); - uint32_t correction_factor = fclk/16000000; + fclk = LL_GetXTALFreq() / 3; + correction_factor = fclk / 16000000; cm = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD1_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD1_CONFIG_CHFLT_M); ce = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD1_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD1_CONFIG_CHFLT_E); - uint8_t index = ce*9 + cm; - return correction_factor*s_Channel_Filter_Bandwidth[index]; + index = ce * 9 + cm; + + return correction_factor * s_Channel_Filter_Bandwidth[index]; } /** -* @brief Set the modulation type. -* @param xModulation modulation to set. -* This parameter shall be of type @ref MRSubGModSelect. -* @param dsssExponent the DSSS spreading exponent. 0 means DSSS disabled. -* @retval None. -*/ -void HAL_MRSubG_SetModulation(MRSubGModSelect xModulation, uint8_t dsssExponent){ + * @brief Set the modulation type. + * @param xModulation modulation to set. + * This parameter shall be of type @ref MRSubGModSelect. + * @param dsssExponent the DSSS spreading exponent. 0 means DSSS disabled. + * @retval None. + */ +void HAL_MRSubG_SetModulation(MRSubGModSelect xModulation, uint8_t dsssExponent) +{ assert_param(IS_MODULATION(xModulation)); /* Internal equalizer */ - switch(xModulation){ - case MOD_2GFSK05: - case MOD_4GFSK05: - case MOD_2GFSK1: - case MOD_4GFSK1: - /*In case of gaussian filter, in order to reduce intersymbol interference (ISI), - * we have to set the internal equalizer to 2 symbols */ - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_AS_EQU_CTRL, 0x02); - break; - default: - /* For non gaussian modulation set internal equalizer to 0 symbols */ - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_AS_EQU_CTRL, 0x00); + switch (xModulation) + { + case MOD_2GFSK05: + case MOD_4GFSK05: + case MOD_2GFSK1: + case MOD_4GFSK1: + /*In case of gaussian filter, in order to reduce intersymbol interference (ISI), + * we have to set the internal equalizer to 2 symbols */ + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_AS_EQU_CTRL, 0x02); + break; + default: + /* For non gaussian modulation set internal equalizer to 0 symbols */ + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->AS_QI_CTRL, MR_SUBG_GLOB_STATIC_AS_QI_CTRL_AS_EQU_CTRL, 0x00); } /* Post filter */ - switch(xModulation){ - case MOD_4GFSK05: - case MOD_4GFSK1: - case MOD_4FSK: - /*In case of 4 level FSK modulation, in order to reduce intersymbol interference (ISI), - * we have to set the post filter len equal to 8 (register value 0). */ - MODIFY_REG_FIELD(MR_SUBG_RADIO->CLKREC_CTRL0, MR_SUBG_RADIO_CLKREC_CTRL0_PSTFLT_LEN, 0x00); - break; - default: - MODIFY_REG_FIELD(MR_SUBG_RADIO->CLKREC_CTRL0, MR_SUBG_RADIO_CLKREC_CTRL0_PSTFLT_LEN, 0x01); + switch (xModulation) + { + case MOD_4GFSK05: + case MOD_4GFSK1: + case MOD_4FSK: + /*In case of 4 level FSK modulation, in order to reduce intersymbol interference (ISI), + * we have to set the post filter len equal to 8 (register value 0). */ + MODIFY_REG_FIELD(MR_SUBG_RADIO->CLKREC_CTRL0, MR_SUBG_RADIO_CLKREC_CTRL0_PSTFLT_LEN, 0x00); + break; + default: + MODIFY_REG_FIELD(MR_SUBG_RADIO->CLKREC_CTRL0, MR_SUBG_RADIO_CLKREC_CTRL0_PSTFLT_LEN, 0x01); } /* Modulation */ - switch(xModulation){ - case MOD_2GFSK05: - case MOD_4GFSK05: - MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_BT_SEL, 1); - xModulation &= 0x0F; - break; - default: - MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_BT_SEL, 0); + switch (xModulation) + { + case MOD_2GFSK05: + case MOD_4GFSK05: + MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_BT_SEL, 1); + xModulation &= 0x0F; + break; + default: + MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_BT_SEL, 0); } /* Evaluate DSSS settings */ @@ -729,29 +857,36 @@ void HAL_MRSubG_SetModulation(MRSubGModSelect xModulation, uint8_t dsssExponent) } /** -* @brief Return the modulation type used. -* @retval MRSubGModSelect Settled modulation type. -*/ + * @brief Return the modulation type used. + * @retval MRSubGModSelect Settled modulation type. + */ MRSubGModSelect HAL_MRSubG_GetModulation(void) { MRSubGModSelect retMod; - retMod = (MRSubGModSelect)(READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_MOD_TYPE)); + uint8_t bt; - if(retMod == MOD_2GFSK1 || retMod == MOD_4GFSK1) + retMod = (MRSubGModSelect)( + READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG, + MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_MOD_TYPE)); + + if (retMod == MOD_2GFSK1 || retMod == MOD_4GFSK1) { /* Check the BT_SEL bit to evaluate if xGFSK1 or 05 */ - uint8_t bt = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_BT_SEL); + bt = READ_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->MOD0_CONFIG, MR_SUBG_GLOB_DYNAMIC_MOD0_CONFIG_BT_SEL); - if (bt) { retMod |= 0x10; } + if (bt) + { + retMod |= 0x10; + } } return retMod; } /** - * @brief Return RSSI value in dBm from content of RSSI_LEVEL_ON_SYNC field. - * @retval int32_t RSSI value. - */ + * @brief Return RSSI value in dBm from content of RSSI_LEVEL_ON_SYNC field. + * @retval int32_t RSSI value. + */ int32_t HAL_MRSubG_GetRssidBm(void) { uint16_t rssiReg = LL_MRSubG_GetRssiLevelOnSync(); @@ -759,33 +894,35 @@ int32_t HAL_MRSubG_GetRssidBm(void) } /** - * @brief Set the value for RSSI threshold according to the following formula: - * RSSIdBm = (rssi_level_xx/2)-(96+GAIN_RX_CHAIN) - See equation 7 in UM_MR_SubG_IP - * @param rssiTh The desired RSSI threshold in dBm. - * @retval None. - */ -void HAL_MRSubG_SetRSSIThreshold(int16_t rssiTh){ - uint16_t rssiValReg = 2*(rssiTh+(96+GAIN_RX_CHAIN)); + * @brief Set the value for RSSI threshold according to the following formula: + * RSSIdBm = (rssi_level_xx/2)-(96+GAIN_RX_CHAIN) - See equation 7 in UM_MR_SubG_IP + * @param rssiTh The desired RSSI threshold in dBm. + * @retval None. + */ +void HAL_MRSubG_SetRSSIThreshold(int16_t rssiTh) +{ + uint16_t rssiValReg = 2 * (rssiTh + (96 + GAIN_RX_CHAIN)); LL_MRSubG_SetRssiThresholdRegister(rssiValReg); } /** - * @brief Get the value for RSSI threshold in dBm - * @retval int32_t the RSSI Threshold in dBm. - */ -int32_t HAL_MRSubG_GetRSSIThreshold(void){ + * @brief Get the value for RSSI threshold in dBm + * @retval int32_t the RSSI Threshold in dBm. + */ +int32_t HAL_MRSubG_GetRSSIThreshold(void) +{ /* Return RSSI Threshold */ uint16_t rssiReg = READ_REG(MR_SUBG_GLOB_STATIC->AS_QI_CTRL) & MR_SUBG_GLOB_STATIC_AS_QI_CTRL_RSSI_THR; return MRSubG_ConvertRssiToDbm(rssiReg); } /** -* @brief Sets a specific PA_LEVEL register, with a value given in dBm. -* @param cIndex PA_LEVEL to set. This parameter shall be in the range [0:7]. -* @param lPowerdBm PA value to write expressed in dBm. -* @param drvMode PA drive modes. -* @retval None. -*/ + * @brief Sets a specific PA_LEVEL register, with a value given in dBm. + * @param cIndex PA_LEVEL to set. This parameter shall be in the range [0:7]. + * @param lPowerdBm PA value to write expressed in dBm. + * @param drvMode PA drive modes. + * @retval None. + */ void HAL_MRSubG_SetPALeveldBm(uint8_t cIndex, int8_t lPowerdBm, MRSubG_PA_DRVMode drvMode) { int32_t pa03 = 0; @@ -801,23 +938,28 @@ void HAL_MRSubG_SetPALeveldBm(uint8_t cIndex, int8_t lPowerdBm, MRSubG_PA_DRVMod maxAllowedValue = MRSubG_GetAllowedMaxOutputPower(drvMode); - if(lPowerdBm > maxAllowedValue){ - lPowerdBm = 0x51; + if (lPowerdBm > maxAllowedValue) + { + lPowerdBm = MAX_DBM; LL_MRSubG_SetPADegen(ENABLE); } - else{ + else + { int8_t tmpPow; - tmpPow = MAX_DBM-((maxAllowedValue-lPowerdBm)*2); + tmpPow = MAX_DBM - ((maxAllowedValue - lPowerdBm) * 2); - lPowerdBm = tmpPow>0?tmpPow:0; + lPowerdBm = tmpPow > 0 ? tmpPow : 0; } - for (int i=cIndex; i>=0; i--){ - if(i<4) - pa03 |= (int32_t)(lPowerdBm)<<(i*8); + for (int16_t i = cIndex; i >= 0; i--) + { + if (i < 4) + { + pa03 |= (int32_t)(lPowerdBm) << (i * 8); + } else - pa07 |= (int32_t)(lPowerdBm)<<((i%4)*8); - + pa07 |= (int32_t)lPowerdBm + << ((i % 4) * 8); lPowerdBm = (lPowerdBm - 10) > 0 ? lPowerdBm - 10 : 0; } @@ -826,36 +968,71 @@ void HAL_MRSubG_SetPALeveldBm(uint8_t cIndex, int8_t lPowerdBm, MRSubG_PA_DRVMod } /** -* @brief Returns a value in dBm. -* @retval int32_t Settled power level expressed in dBm. -*/ + * @brief Returns the current output power level of the Power Amplifier (PA). + * + * This function reads the power level from the hardware register and returns: + * - The value expressed in dBm only if the PA mode is set to LEGACY or FIR mode. + * + * @note The conversion to dBm is performed exclusively when the PA mode is LEGACY or FIR. + * + * @retval int8_t + * - Output power level expressed in dBm + */ int8_t HAL_MRSubG_GetPALeveldBm(void) { - int32_t retDbm; - - /* Get the max PA Index */ uint8_t maxIdx = LL_MRSubG_GetPALevelMaxIndex(); + uint32_t regValue; + uint8_t paLevel; + MRSubG_PAMode paMode; + uint8_t maxAllowedValue; + int16_t paOutputDbm; + + paMode = LL_MRSubG_GetPAMode(); + assert_param(IS_PAMODEDBM(paMode)); - if(maxIdx < 4){ - retDbm = READ_REG(MR_SUBG_GLOB_STATIC->PA_LEVEL_3_0) & MR_SUBG_GLOB_STATIC_PA_LEVEL_3_0_PA_LEVEL0; - return retDbm << maxIdx * 8; + maxAllowedValue = MRSubG_GetAllowedMaxOutputPower(LL_MRSubG_GetPADriveMode()); + + if (paMode == PA_LEGACY) + { + if (maxIdx < 4) + { + regValue = READ_REG(MR_SUBG_GLOB_STATIC->PA_LEVEL_3_0); + paLevel = (uint8_t)((regValue >> (maxIdx * 8)) & 0xFF); + } + else + { + regValue = READ_REG(MR_SUBG_GLOB_STATIC->PA_LEVEL_7_4); + paLevel = (uint8_t)((regValue >> ((maxIdx % 4) * 8)) & 0XFF); + } } - else { - retDbm = READ_REG(MR_SUBG_GLOB_STATIC->PA_LEVEL_7_4) & MR_SUBG_GLOB_STATIC_PA_LEVEL_7_4_PA_LEVEL4; - return retDbm << (maxIdx%4) * 8; + else + { + paLevel = READ_REG_FIELD(MR_SUBG_GLOB_STATIC->PA_LEVEL_7_4, MR_SUBG_GLOB_STATIC_PA_LEVEL_7_4_PA_LEVEL7); } + paOutputDbm = maxAllowedValue - ((MAX_DBM - paLevel) >> 1); + return (int8_t)paOutputDbm; } /** - * @brief Returns the number of bytes after each TX/RX transaction. - * @retval The number of bytes after each TX/RX transaction. - */ -uint32_t HAL_MRSubG_GetBytesOfTransaction(void){ - uint16_t used = READ_REG_FIELD(MR_SUBG_GLOB_STATUS->DATABUFFER_INFO, MR_SUBG_GLOB_STATUS_DATABUFFER_INFO_NB_DATABUFFER_USED); - uint16_t size = READ_REG(MR_SUBG_GLOB_STATIC->DATABUFFER_SIZE) & MR_SUBG_GLOB_STATIC_DATABUFFER_SIZE_DATABUFFER_SIZE; - uint16_t count = READ_REG_FIELD(MR_SUBG_GLOB_STATUS->DATABUFFER_INFO, MR_SUBG_GLOB_STATUS_DATABUFFER_INFO_CURRENT_DATABUFFER_COUNT); + * @brief Returns the number of bytes after each TX/RX transaction. + * @retval The number of bytes after each TX/RX transaction. + */ +uint32_t HAL_MRSubG_GetBytesOfTransaction(void) +{ + uint16_t used = READ_REG_FIELD( + MR_SUBG_GLOB_STATUS->DATABUFFER_INFO, + MR_SUBG_GLOB_STATUS_DATABUFFER_INFO_NB_DATABUFFER_USED + ); + + uint16_t size = READ_REG(MR_SUBG_GLOB_STATIC->DATABUFFER_SIZE) & + MR_SUBG_GLOB_STATIC_DATABUFFER_SIZE_DATABUFFER_SIZE; - return (used*size)+count; + uint16_t count = READ_REG_FIELD( + MR_SUBG_GLOB_STATUS->DATABUFFER_INFO, + MR_SUBG_GLOB_STATUS_DATABUFFER_INFO_CURRENT_DATABUFFER_COUNT + ); + + return (used * size) + count; } /* @@ -866,10 +1043,18 @@ uint32_t HAL_MRSubG_GetBytesOfTransaction(void){ uint32_t HAL_MRSubG_Sequencer_Microseconds(uint32_t microseconds) { /* Determine true frequency (relative to 16MHz clock) of "interpolated absolute time" value */ - uint16_t slow_clock_freq = 32000; - uint16_t scm_counter_currval = READ_REG_FIELD(MR_SUBG_GLOB_MISC->SCM_COUNTER_VAL, MR_SUBG_GLOB_MISC_SCM_COUNTER_VAL_SCM_COUNTER_CURRVAL); + uint16_t slow_clock_freq = SLOW_CLOCK_FREQ_DEFAULT; + + uint16_t scm_counter_currval = READ_REG_FIELD( + MR_SUBG_GLOB_MISC->SCM_COUNTER_VAL, + MR_SUBG_GLOB_MISC_SCM_COUNTER_VAL_SCM_COUNTER_CURRVAL + ); + if (scm_counter_currval != 0) + { slow_clock_freq = 32ull * 16000000ull / scm_counter_currval; + } + uint64_t interpolated_absolute_time = 16u * slow_clock_freq; return (((uint64_t)microseconds) * interpolated_absolute_time / 1000000ull) + 0x20; @@ -901,13 +1086,15 @@ uint32_t HAL_MRSubG_Sequencer_Seconds(uint32_t seconds) * @param cfg Pointer to global configuration table struct. * @retval SUCCESS if operation was successful, ERROR if RAM table pointer is not word-aligned. */ -ErrorStatus HAL_MRSubG_Sequencer_ApplyStaticConfig(MRSubG_Sequencer_GlobalConfiguration *cfg) +ErrorStatus HAL_MRSubG_Sequencer_ApplyStaticConfig(MRSubG_Sequencer_GlobalConfiguration_t *cfg) { /* Ensure GlobalConfiguration RAM table is word-aligned */ if (((uint32_t)cfg) % 4 != 0) + { return ERROR; + } - memcpy((void*)&cfg->StaticConfigReg, (void*)MR_SUBG_GLOB_STATIC, sizeof(MR_SUBG_GLOB_STATIC_TypeDef)); + memcpy((void *)&cfg->StaticConfigReg, (void *)MR_SUBG_GLOB_STATIC, sizeof(MR_SUBG_GLOB_STATIC_TypeDef)); return SUCCESS; } @@ -920,45 +1107,64 @@ ErrorStatus HAL_MRSubG_Sequencer_ApplyStaticConfig(MRSubG_Sequencer_GlobalConfig * @retval SUCCESS if operation was successful, ERROR if RAM table pointer is not word-aligned * or NextAction1Interval / NextAction2Interval value is invalid. */ -ErrorStatus HAL_MRSubG_Sequencer_ApplyDynamicConfig(MRSubG_Sequencer_ActionConfiguration *cfg, MRSubGCmd cmd) +ErrorStatus HAL_MRSubG_Sequencer_ApplyDynamicConfig(MRSubG_Sequencer_ActionConfiguration_t *cfg, MRSubGCmd cmd) { /* Ensure ActionConfiguration RAM table is word-aligned */ if (((uint32_t)cfg) % 4 != 0) + { return ERROR; + } /* NextAction1Interval and NextAction2Interval must not be smaller than (SOC_WAKEUP_OFFSET + 2) slow clock cycles */ - uint32_t soc_wakeup_offset = READ_REG_FIELD(MR_SUBG_GLOB_RETAINED->WAKEUP_CTRL, MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_SOC_WAKEUP_OFFSET); + uint32_t soc_wakeup_offset = READ_REG_FIELD( + MR_SUBG_GLOB_RETAINED->WAKEUP_CTRL, + MR_SUBG_GLOB_RETAINED_WAKEUP_CTRL_SOC_WAKEUP_OFFSET + ); uint32_t min_next_action_interval = (soc_wakeup_offset + 2) * 16; + if (cfg->NextAction1Interval != 0 && cfg->NextAction1Interval < min_next_action_interval) + { return ERROR; + } - if (cfg->NextAction2Interval != 0 && cfg->NextAction2Interval < min_next_action_interval) + if (cfg->NextAction2Interval != 0 && cfg->NextAction2Interval < min_next_action_interval) + { return ERROR; + } /* Copy current dynamic register configuration to ActionConfiguration block */ - memcpy((void*)&cfg->DynamicConfigReg, (void*)MR_SUBG_GLOB_DYNAMIC, sizeof(MR_SUBG_GLOB_DYNAMIC_TypeDef)); + memcpy( + (void *)&cfg->DynamicConfigReg, + (void *)MR_SUBG_GLOB_DYNAMIC, + sizeof(MR_SUBG_GLOB_DYNAMIC_TypeDef) + ); + MODIFY_REG_FIELD(cfg->DynamicConfigReg.COMMAND, MR_SUBG_GLOB_DYNAMIC_COMMAND_COMMAND_ID, cmd); return SUCCESS; } /** - * @brief Set the payload length for the Basic packet format. - * @param nPayloadLength payload length in bytes. - * @retval None. - */ -void HAL_MRSubG_PktBasicSetPayloadLength(uint16_t nPayloadLength){ - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->DATABUFFER_SIZE, MR_SUBG_GLOB_STATIC_DATABUFFER_SIZE_DATABUFFER_SIZE, nPayloadLength); + * @brief Set the payload length for the Basic packet format. + * @param nPayloadLength payload length in bytes. + * @retval None. + */ +void HAL_MRSubG_PktBasicSetPayloadLength(uint16_t nPayloadLength) +{ + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->DATABUFFER_SIZE, MR_SUBG_GLOB_STATIC_DATABUFFER_SIZE_DATABUFFER_SIZE, + nPayloadLength); LL_MRSUBG_SetPacketLength(nPayloadLength); } /** - * @brief Initialize the STM32WL3 Basic packet according to the specified parameters in the MRSubG_PcktBasicFields struct. - * @param pxPktBasicInit Basic packet init structure. - * This parameter is a pointer to @ref MRSubG_PcktBasicFields. - * @retval None. - */ -void HAL_MRSubG_PacketBasicInit(MRSubG_PcktBasicFields* pxPktBasicInit){ + * @brief Initialize the STM32WL3x Basic packet according to the specified parameters + * in the MRSubG_PcktBasicFields_t struct. + * @param pxPktBasicInit Basic packet init structure. + * This parameter is a pointer to @ref MRSubG_PcktBasicFields_t. + * @retval None. + */ +void HAL_MRSubG_PacketBasicInit(MRSubG_PcktBasicFields_t *pxPktBasicInit) +{ /* Check the parameters */ assert_param(IS_PREAMBLE_LEN(pxPktBasicInit->PreambleLength)); @@ -997,12 +1203,15 @@ void HAL_MRSubG_PacketBasicInit(MRSubG_PcktBasicFields* pxPktBasicInit){ } /** - * @brief Initialize the STM32WL3 WMBUS packet according to the specified parameters in the PktWMbusInit struct. - * @param pxPktWMbusInit pointer to a PktWMbusInit structure that contains the configuration information for the specified S2LP WMBUS PACKET FORMAT. - * This parameter is a pointer to @ref MRSubG_WMBUS_PcktFields. - * @retval None. - */ -void HAL_MRSubG_WMBus_PacketInit(MRSubG_WMBUS_PcktFields* pxPktWMbusInit){ + * @brief Initialize the STM32WL3x WMBUS packet according to the specified parameters + * in the PktWMbusInit struct. + * @param pxPktWMbusInit Pointer to a PktWMbusInit structure that contains the configuration + * information for the specified S2LP WMBUS PACKET FORMAT. + * This parameter is a pointer to @ref MRSubG_WMBUS_PcktFields_t. + * @retval None. + */ +void HAL_MRSubG_WMBus_PacketInit(MRSubG_WMBUS_PcktFields_t *pxPktWMbusInit) +{ /* Check the parameters */ assert_param(IS_WMBUS_SUBMODE(pxPktWMbusInit->xWMbusSubmode)); @@ -1012,7 +1221,8 @@ void HAL_MRSubG_WMBus_PacketInit(MRSubG_WMBUS_PcktFields* pxPktWMbusInit){ s_cWMbusSubmode = pxPktWMbusInit->xWMbusSubmode; - if(s_cWMbusSubmode==WMBUS_SUBMODE_S1_S2_LONG_HEADER) { + if (s_cWMbusSubmode == WMBUS_SUBMODE_S1_S2_LONG_HEADER) + { LL_MRSubG_SetPreambleLength(((uint16_t)pxPktWMbusInit->PreambleLength) + WMBUS_PREAMBLE_LEN_S1S2LONGHEADER); /* Set the SYNC */ @@ -1026,7 +1236,8 @@ void HAL_MRSubG_WMBus_PacketInit(MRSubG_WMBUS_PcktFields* pxPktWMbusInit){ LL_MRSubG_SetPostamblSeq(POST_SEQ_1010); } - else if(s_cWMbusSubmode==WMBUS_SUBMODE_S1_M_S2_T2_OTHER_TO_METER) { + else if (s_cWMbusSubmode == WMBUS_SUBMODE_S1_M_S2_T2_OTHER_TO_METER) + { LL_MRSubG_SetPreambleLength(((uint16_t)pxPktWMbusInit->PreambleLength) + WMBUS_PREAMBLE_LEN_S1MS2T2OTHERTOMETER); /* Set the SYNC */ @@ -1042,7 +1253,8 @@ void HAL_MRSubG_WMBus_PacketInit(MRSubG_WMBUS_PcktFields* pxPktWMbusInit){ LL_MRSubG_SetPostamblSeq(POST_SEQ_1010); } - else if(s_cWMbusSubmode==WMBUS_SUBMODE_T1_T2_METER_TO_OTHER) { + else if (s_cWMbusSubmode == WMBUS_SUBMODE_T1_T2_METER_TO_OTHER) + { LL_MRSubG_SetPreambleLength(((uint16_t)pxPktWMbusInit->PreambleLength) + WMBUS_PREAMBLE_LEN_T1T2METERTOOTHER); /* Set the SYNC */ @@ -1053,7 +1265,8 @@ void HAL_MRSubG_WMBus_PacketInit(MRSubG_WMBUS_PcktFields* pxPktWMbusInit){ /* Set the Coding type */ LL_MRSubG_PacketHandlerCoding(CODING_3o6); } - else if(s_cWMbusSubmode==WMBUS_SUBMODE_R2_SHORT_HEADER) { + else if (s_cWMbusSubmode == WMBUS_SUBMODE_R2_SHORT_HEADER) + { LL_MRSubG_SetPreambleLength(((uint16_t)pxPktWMbusInit->PreambleLength) + WMBUS_PREAMBLE_LEN_R2); /* Set the SYNC */ @@ -1072,14 +1285,16 @@ void HAL_MRSubG_WMBus_PacketInit(MRSubG_WMBUS_PcktFields* pxPktWMbusInit){ } /** - * @brief Initialize the STM32WL3 802.15.4 packet according to the specified parameters in the MRSubG_802_15_4_PcktFields struct. - * @param px802_15_4PktInit 802.15.4 packet init structure. - * This parameter is a pointer to @ref MRSubG_802_15_4_PcktFields. - * @retval 1 in case of errors. - */ -void HAL_MRSubG_802_15_4_PacketInit(MRSubG_802_15_4_PcktFields* px802_15_4PktInit){ + * @brief Initialize the STM32WL3x 802.15.4 packet according to the specified parameters + * in the MRSubG_802_15_4_PcktFields_t struct. + * @param px802_15_4PktInit 802.15.4 packet init structure. + * This parameter is a pointer to @ref MRSubG_802_15_4_PcktFields_t. + * @retval 1 in case of errors. + */ +void HAL_MRSubG_802_15_4_PacketInit(MRSubG_802_15_4_PcktFields_t *px802_15_4PktInit) +{ - uint32_t const*sync_word_ptr; + uint32_t const *sync_word_ptr; uint8_t sync_word_len; uint16_t preamble_len; @@ -1091,11 +1306,14 @@ void HAL_MRSubG_802_15_4_PacketInit(MRSubG_802_15_4_PcktFields* px802_15_4PktIni assert_param(IS_FUNCTIONAL_STATE(px802_15_4PktInit->Whitening)); assert_param(IS_FRAME_LEN(px802_15_4PktInit->FrameLength)); - if (px802_15_4PktInit->Modulation == MOD_2FSK) { + if (px802_15_4PktInit->Modulation == MOD_2FSK) + { sync_word_ptr = SFD_2FSK; sync_word_len = 2; preamble_len = px802_15_4PktInit->PreambleLength * 8; - } else { + } + else + { sync_word_ptr = SFD_4FSK; sync_word_len = 4; preamble_len = px802_15_4PktInit->PreambleLength * 16; @@ -1117,21 +1335,33 @@ void HAL_MRSubG_802_15_4_PacketInit(MRSubG_802_15_4_PcktFields* px802_15_4PktIni MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_SYNC_PRESENT, 1); - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_SYNC_LEN, SYNC_BYTE(sync_word_len)); + MODIFY_REG_FIELD( + MR_SUBG_GLOB_STATIC->PCKT_CONFIG, + MR_SUBG_GLOB_STATIC_PCKT_CONFIG_SYNC_LEN, + SYNC_BYTE(sync_word_len) + ); - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_CRC_MODE, px802_15_4PktInit->FCSType); + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CONFIG, MR_SUBG_GLOB_STATIC_PCKT_CONFIG_CRC_MODE, + px802_15_4PktInit->FCSType); - MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->PCKTLEN_CONFIG, MR_SUBG_GLOB_DYNAMIC_PCKTLEN_CONFIG_PCKTLEN, px802_15_4PktInit->FrameLength); + MODIFY_REG_FIELD(MR_SUBG_GLOB_DYNAMIC->PCKTLEN_CONFIG, MR_SUBG_GLOB_DYNAMIC_PCKTLEN_CONFIG_PCKTLEN, + px802_15_4PktInit->FrameLength); MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_FCS_TYPE_4G, - (px802_15_4PktInit->FCSType == FCS_16BIT) ? 1: 0); + (px802_15_4PktInit->FCSType == FCS_16BIT) ? 1 : 0); - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_FEC_TYPE_4G, (px802_15_4PktInit->FecType > 1 ? 1 : 0)); + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_FEC_TYPE_4G, + (px802_15_4PktInit->FecType > 1 ? 1 : 0)); - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_INT_EN_4G, - ((px802_15_4PktInit->FecType == FEC_15_4_G_NRNSC) || (px802_15_4PktInit->FecType == FEC_15_4_G_RSC_Interleaving)) ); + MODIFY_REG_FIELD( + MR_SUBG_GLOB_STATIC->PCKT_CTRL, + MR_SUBG_GLOB_STATIC_PCKT_CTRL_INT_EN_4G, + ((px802_15_4PktInit->FecType == FEC_15_4_G_NRNSC) || + (px802_15_4PktInit->FecType == FEC_15_4_G_RSC_Interleaving)) + ); - MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_CODING_SEL, (px802_15_4PktInit->FecType > 0)); + MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_CODING_SEL, + (px802_15_4PktInit->FecType > 0)); MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_WHIT_EN, px802_15_4PktInit->Whitening); @@ -1139,7 +1369,7 @@ void HAL_MRSubG_802_15_4_PacketInit(MRSubG_802_15_4_PcktFields* px802_15_4PktIni MODIFY_REG_FIELD(MR_SUBG_GLOB_STATIC->PCKT_CTRL, MR_SUBG_GLOB_STATIC_PCKT_CTRL_BYTE_SWAP, 1); - WRITE_REG(MR_SUBG_GLOB_STATIC->CRC_INIT, ((px802_15_4PktInit->FCSType == FCS_16BIT) ? 0 : 0xFFFFFFFF)); + WRITE_REG(MR_SUBG_GLOB_STATIC->CRC_INIT, ((px802_15_4PktInit->FCSType == FCS_16BIT) ? 0 : 0xFFFFFFFF)); } /** diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg_timer.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg_timer.c index 5b4454165d..a2fecfa846 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg_timer.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_mrsubg_timer.c @@ -1,38 +1,38 @@ /** -****************************************************************************** -* @file stm32wl3x_hal_mrsubg_timer.c -* @author GPM WBL Application Team -* @brief Virtual timer and MRSUBG timer high level APIs -* @details This file implements the software layer that provides the virtualization of the -* resources of a single hardware radio timer in order to allocate many user virtual timers. -* The only constraint to the number of virtual timers is the memory. -* Each instance of a virtual timer is placed in an queue ordered by the expiration time -* and it can be linked to a callback. -* The timer tick is in charge to execute the callback linked to each virtual timer -* and to update the hardware timeout to guarantee the expiration of the next virtual -* timer in the queue. -* A special virtual timer called calibration/anti-wrapping timer is automatically armed -* by the software. This timer can address two tasks: -* - it is in charge to maintain the never wrapping virtual time base. -* - if the slow clock calibration is enabled, it starts the calibration procedure at each -* calibration interval specified during the initialization. -* -* A timer is intended as an event programmed in the future at a certain absolute expiration time -* on a time base. In this implementation the time base grows on 64 bits. Then, it never wraps. -* However, due to hardware timer finite length and in order to maintain the timing coherency, the time base -* must be maintained at least one time before the hardware timer wraps. -* Then even if the slow clock calibration is disabled, the calibration/anti-wrapping timer -* is always active with the only role to maintain the time base and it will expire -* at a rate that depends on the hardware timer capability. -* The time base unit is a STU that is the unit exposed to the user and it is equal to 1 us. -* The calibration/anti-wrapping mechanism is not managed by the user. -* -* This software layer also exposes the possibility to read if a radio timer is programmed. -* + ****************************************************************************** + * @file stm32wl3x_hal_mrsubg_timer.c + * @author GPM WBL Application Team + * @brief Virtual timer and MRSUBG timer high level APIs + * @details This file implements the software layer that provides the virtualization of the + * resources of a single hardware radio timer in order to allocate many user virtual timers. + * The only constraint to the number of virtual timers is the memory. + * Each instance of a virtual timer is placed in an queue ordered by the expiration time + * and it can be linked to a callback. + * The timer tick is in charge to execute the callback linked to each virtual timer + * and to update the hardware timeout to guarantee the expiration of the next virtual + * timer in the queue. + * A special virtual timer called calibration/anti-wrapping timer is automatically armed + * by the software. This timer can address two tasks: + * - it is in charge to maintain the never wrapping virtual time base. + * - if the slow clock calibration is enabled, it starts the calibration procedure at each + * calibration interval specified during the initialization. + * + * A timer is intended as an event programmed in the future at a certain absolute expiration time + * on a time base. In this implementation the time base grows on 64 bits. Then, it never wraps. + * However, due to hardware timer finite length and in order to maintain the timing coherency, the time base + * must be maintained at least one time before the hardware timer wraps. + * Then even if the slow clock calibration is disabled, the calibration/anti-wrapping timer + * is always active with the only role to maintain the time base and it will expire + * at a rate that depends on the hardware timer capability. + * The time base unit is a STU that is the unit exposed to the user and it is equal to 1 us. + * The calibration/anti-wrapping mechanism is not managed by the user. + * + * This software layer also exposes the possibility to read if a radio timer is programmed. + * ****************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2024-2025 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -40,7 +40,7 @@ * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** -*/ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32wl3x_hal.h" @@ -61,29 +61,32 @@ * @{ */ -typedef struct { - VTIMER_HandleType calibrationTimer; - VTIMER_HandleType *rootNode; /*!< First timer of the host timer queue */ +typedef struct +{ + VTIMER_HandleType_t calibrationTimer; + VTIMER_HandleType_t *rootNode; /*!< First timer of the host timer queue */ uint8_t enableTimeBase; /*!< Internal flag. User can ignore it*/ uint8_t expired_count; /*!< Progressive number to indicate expired timers */ uint8_t served_count; /*!< Progressive number to indicate served expired timers */ uint8_t stop_notimer_action; /*!< Flag to indicate DEEPSTOP no timer action */ uint64_t cumulative_time; /** Absolute system time since power up */ uint32_t hs_startup_time; /** HS startup time in us */ - uint32_t last_scm_counter; /** Number of 16Mhz fast clock cycles seen in a 32 slow clock period window read in the last calibration*/ - uint32_t fast_clock_freq; /** The fast clock frequency is XO frequency / 3 so typically 16MHz. But it can also be 15.666MHz with a XO at 47MHz or 16.666MHz with a XO at 50MHz. */ + uint32_t last_scm_counter; /** Number of 16Mhz fast clock cycles seen in a 32 slow clock \ + period window read in the last calibration*/ + uint32_t fast_clock_freq; /** The fast clock frequency is XO frequency / 3 so typically 16MHz. \ + But it can also be 15.666MHz with a XO at 47MHz or 16.666MHz with a XO at 50MHz. */ uint32_t slow_clock_freq; /** Slow clock freq */ uint32_t interpolated_freq; /** Interpolated frequency */ uint32_t last_interpolated_freq; /** Last interpolated frequency */ uint64_t timer_max_value; /** TIMER_MAX_VALUE in System Time Unit (1us) */ uint32_t last_calibration_machine_time; /** Last machine time when calibration was performed */ - uint32_t calibration_machine_interval; /** Calibration Interval MTU */ + uint32_t calibration_machine; /** Calibration Interval MTU */ uint64_t last_system_time; /** Last System Time */ uint64_t last_calibration_time; /** Absolute system time when last calibration was performed */ uint8_t calibration_in_progress; /*!< Flag to indicate that a periodic calibration has been started */ - uint8_t close_expiration; /*!< Flag to indicate that a timer is about to expire */ uint64_t periodicCalibrationInterval; /** Calibration Interval in system time unit (us) */ - uint8_t periodic_calibration; /** Tells whether periodic hardware calibration is needed or not, i.e. LSO speed varies with temperature, etc. */ + uint8_t periodic_calibration; /** Tells whether periodic hardware calibration is needed or not, i.e. \ + LSO speed varies with temperature, etc. */ } MRSUBG_TIMER_ContextTypeDef; /** @@ -107,6 +110,8 @@ typedef struct { #define MAX_SCM_DELAY_COUNT 10 /* ms to wait between SCM reads during transitory phase */ #define SCM_DELAY_MS 5 +/* maximum time required to enter low power mode */ +#define LOW_POWER_ENTRY_MARGIN_US 150 /** * @} @@ -119,8 +124,8 @@ typedef struct { */ #define ATOMIC_SECTION_BEGIN() uint32_t uwPRIMASK_Bit = __get_PRIMASK(); \ - __disable_irq(); \ -/* Must be called in the same scope of ATOMIC_SECTION_BEGIN */ + __disable_irq(); \ + /* Must be called in the same scope of ATOMIC_SECTION_BEGIN */ #define ATOMIC_SECTION_END() __set_PRIMASK(uwPRIMASK_Bit) #define MAX(a,b) ((a) < (b) )? (b) : (a) @@ -129,7 +134,9 @@ typedef struct { #define TIME_DIFF(a, b) (((int32_t)((a - b) << (32-TIMER_BITS))) >> (32-TIMER_BITS)) /* This define assumes that a is always greater than b */ #define TIME_ABSDIFF(a, b) ((a - b) & TIMER_MAX_VALUE) -#define INCREMENT_EXPIRE_COUNT_ISR (MRSUBG_TIMER_Context.expired_count = ((MRSUBG_TIMER_Context.expired_count + 1) == MRSUBG_TIMER_Context.served_count) ? MRSUBG_TIMER_Context.expired_count : (MRSUBG_TIMER_Context.expired_count + 1)) +#define INCREMENT_EXPIRE_COUNT_ISR (MRSUBG_TIMER_Context.expired_count \ + = ((MRSUBG_TIMER_Context.expired_count + 1) == MRSUBG_TIMER_Context.served_count) \ + ? MRSUBG_TIMER_Context.expired_count : (MRSUBG_TIMER_Context.expired_count + 1)) #define INCREMENT_EXPIRE_COUNT ATOMIC_SECTION_BEGIN(); INCREMENT_EXPIRE_COUNT_ISR ; ATOMIC_SECTION_END(); /** @@ -171,19 +178,19 @@ static MRSUBG_TIMER_ContextTypeDef MRSUBG_TIMER_Context; static void _get_calibration_data(void); static void _timer_calibrate(void); static void _updateCalibrationData(void); -static void _calibration_callback (void *handle); +static void _calibration_callback(void *handle); static void _update_xtal_startup_time(void); static void _update_system_time(void); static uint64_t _us_to_machinetime(uint64_t time); static uint64_t _machinetime_to_us(uint64_t time); static uint64_t _get_system_time_and_machine(uint32_t *current_machine_time); -static int32_t _start_timer(VTIMER_HandleType *timerHandle, uint64_t time); -static VTIMER_HandleType *_update_user_timeout(VTIMER_HandleType *rootNode, uint8_t *expired); +static int32_t _start_timer(VTIMER_HandleType_t *timerHandle, uint64_t time); +static VTIMER_HandleType_t *_update_user_timeout(VTIMER_HandleType_t *rootNode, uint8_t *expired); static uint32_t VTIMER_SetWakeupTime(uint64_t delay, BOOL allow_sleep); -static VTIMER_HandleType * _insert_timer_in_queue(VTIMER_HandleType *rootNode, VTIMER_HandleType *handle); +static VTIMER_HandleType_t *_insert_timer_in_queue(VTIMER_HandleType_t *rootNode, VTIMER_HandleType_t *handle); static void _virtualTimeBaseEnable(FunctionalState state); -static VTIMER_HandleType * _remove_timer_in_queue(VTIMER_HandleType *rootNode, VTIMER_HandleType *handle); -static VTIMER_HandleType *_check_callbacks(VTIMER_HandleType *rootNode,VTIMER_HandleType **expiredList); +static VTIMER_HandleType_t *_remove_timer_in_queue(VTIMER_HandleType_t *rootNode, VTIMER_HandleType_t *handle); +static VTIMER_HandleType_t *_check_callbacks(VTIMER_HandleType_t *rootNode, VTIMER_HandleType_t **expiredList); /** * @} @@ -197,25 +204,25 @@ static VTIMER_HandleType *_check_callbacks(VTIMER_HandleType *rootNode,VTIMER_Ha /* ------------------------ RADIO Init APIs ----------------------------------*/ /** - * @brief Initialize the radio timer module. It must be placed in the initialization - * section of the application. - * @param MRSUBG_TIMER_InitStruct Radio Timer Initialization parameters - * @retval None - */ + * @brief Initialize the radio timer module. It must be placed in the initialization + * section of the application. + * @param MRSUBG_TIMER_InitStruct Radio Timer Initialization parameters + * @retval None + */ void HAL_MRSUBG_TIMER_Init(MRSUBG_TIMER_InitTypeDef *MRSUBG_TIMER_InitStruct) { /* Wait to be sure that the Radio Timer is active */ - while(LL_MRSUBG_TIMER_GetAbsoluteTime(MR_SUBG_GLOB_MISC) < 0x10); + while (LL_MRSUBG_TIMER_GetAbsoluteTime(MR_SUBG_GLOB_MISC) < 0x10); /* Interrupt Configuration */ LL_MRSUBG_TIMER_ClearFlag_CPUWakeup(MR_SUBG_GLOB_MISC); HAL_MRSUBG_TIMER_MspInit(); /* HSE XTAL clock frequency */ - MRSUBG_TIMER_Context.fast_clock_freq = MRSUBG_TIMER_InitStruct->HSE_XTAL_freq/3; + MRSUBG_TIMER_Context.fast_clock_freq = MRSUBG_TIMER_InitStruct->HSE_XTAL_freq / 3; /* Calibration Setting */ - MRSUBG_TIMER_Context.periodic_calibration = (MRSUBG_TIMER_InitStruct->periodicCalibrationInterval!=0); + MRSUBG_TIMER_Context.periodic_calibration = (MRSUBG_TIMER_InitStruct->periodicCalibrationInterval != 0); if (MRSUBG_TIMER_Context.periodic_calibration || MRSUBG_TIMER_InitStruct->enableInitialCalibration) { _timer_calibrate(); @@ -226,18 +233,24 @@ void HAL_MRSUBG_TIMER_Init(MRSUBG_TIMER_InitTypeDef *MRSUBG_TIMER_InitStruct) MRSUBG_TIMER_Context.slow_clock_freq = SLOW_CLOCK_WORKING_FREQ; MRSUBG_TIMER_Context.interpolated_freq = 16u * MRSUBG_TIMER_Context.slow_clock_freq; MRSUBG_TIMER_Context.last_interpolated_freq = MRSUBG_TIMER_Context.interpolated_freq; - MRSUBG_TIMER_Context.timer_max_value = (((uint64_t)TIMER_MAX_VALUE*1000000ull)/MRSUBG_TIMER_Context.interpolated_freq); + MRSUBG_TIMER_Context.timer_max_value = ( + ((uint64_t)TIMER_MAX_VALUE * 1000000ull) / + MRSUBG_TIMER_Context.interpolated_freq + ); } if (MRSUBG_TIMER_InitStruct->periodicCalibrationInterval == 0) { - MRSUBG_TIMER_Context.calibration_machine_interval = TIMER_MAX_VALUE - TIMER_WRAPPING_MARGIN; + MRSUBG_TIMER_Context.calibration_machine = TIMER_MAX_VALUE - TIMER_WRAPPING_MARGIN; } else { - MRSUBG_TIMER_Context.calibration_machine_interval = MIN(_us_to_machinetime(MRSUBG_TIMER_InitStruct->periodicCalibrationInterval*1000ull), - (TIMER_MAX_VALUE-TIMER_WRAPPING_MARGIN)); + MRSUBG_TIMER_Context.calibration_machine = MIN(_us_to_machinetime \ + (MRSUBG_TIMER_InitStruct->periodicCalibrationInterval * \ + 1000ull), + (TIMER_MAX_VALUE - TIMER_WRAPPING_MARGIN)); } - MRSUBG_TIMER_Context.periodicCalibrationInterval = _machinetime_to_us(MRSUBG_TIMER_Context.calibration_machine_interval); + MRSUBG_TIMER_Context.periodicCalibrationInterval = _machinetime_to_us(\ + MRSUBG_TIMER_Context.calibration_machine); MRSUBG_TIMER_Context.calibration_in_progress = FALSE; /* XTAL startup time configuration */ @@ -254,21 +267,22 @@ void HAL_MRSUBG_TIMER_Init(MRSUBG_TIMER_InitTypeDef *MRSUBG_TIMER_InitStruct) MRSUBG_TIMER_Context.rootNode = NULL; MRSUBG_TIMER_Context.enableTimeBase = TRUE; MRSUBG_TIMER_Context.stop_notimer_action = FALSE; - MRSUBG_TIMER_Context.expired_count=0; - MRSUBG_TIMER_Context.served_count=0; + MRSUBG_TIMER_Context.expired_count = 0; + MRSUBG_TIMER_Context.served_count = 0; /* Configure the Calibration callback and schedule the next calibration */ MRSUBG_TIMER_Context.calibrationTimer.callback = _calibration_callback; MRSUBG_TIMER_Context.calibrationTimer.userData = NULL; - _start_timer(&MRSUBG_TIMER_Context.calibrationTimer, HAL_MRSUBG_TIMER_GetCurrentSysTime() + MRSUBG_TIMER_Context.periodicCalibrationInterval); + _start_timer(&MRSUBG_TIMER_Context.calibrationTimer, + HAL_MRSUBG_TIMER_GetCurrentSysTime() + MRSUBG_TIMER_Context.periodicCalibrationInterval); } /** - * @brief Timer module state machine. Check and schedule the calibration. - * Check expired timers and execute user callback. - * It must be placed inside the infinite loop. - * @retval None - */ + * @brief Timer module state machine. Check and schedule the calibration. + * Check expired timers and execute user callback. + * It must be placed inside the infinite loop. + * @retval None + */ void HAL_MRSUBG_TIMER_Tick(void) { uint8_t expired = 0; @@ -276,20 +290,22 @@ void HAL_MRSUBG_TIMER_Tick(void) /* Check for expired timers */ while (DIFF8(MRSUBG_TIMER_Context.expired_count, MRSUBG_TIMER_Context.served_count)) { - VTIMER_HandleType *expiredList, *curr; + VTIMER_HandleType_t *expiredList, *curr; uint8_t to_be_served = DIFF8(MRSUBG_TIMER_Context.expired_count, MRSUBG_TIMER_Context.served_count); MRSUBG_TIMER_Context.rootNode = _check_callbacks(MRSUBG_TIMER_Context.rootNode, &expiredList); /* Call all the user callbacks */ - curr=expiredList; + curr = expiredList; while (curr != NULL) { /* Save next pointer, in case callback start the timer again */ - VTIMER_HandleType *next = curr->next; + VTIMER_HandleType_t *next = curr->next; curr->active = FALSE; if (curr->callback) - curr->callback(curr); /* we are sure a callback is set?*/ + { + curr->callback(curr); /* we are sure a callback is set?*/ + } curr = next; } @@ -300,22 +316,13 @@ void HAL_MRSUBG_TIMER_Tick(void) INCREMENT_EXPIRE_COUNT; } - if (expiredList == NULL) - { - /* Set the close_expiration flag to handle an expired timer later, since its not yet percived as expired by software checks */ - MRSUBG_TIMER_Context.close_expiration = 1; - } - else - { - MRSUBG_TIMER_Context.close_expiration = 0; - } MRSUBG_TIMER_Context.served_count += to_be_served; } /* Check for periodic calibration */ if (MRSUBG_TIMER_Context.calibration_in_progress) { - if(LL_MRSUBG_TIMER_GetSCM(MR_SUBG_GLOB_MISC) != 0) + if (LL_MRSUBG_TIMER_GetSCM(MR_SUBG_GLOB_MISC) != 0) { /* Calibration is completed */ MRSUBG_TIMER_Context.calibration_in_progress = FALSE; @@ -323,35 +330,26 @@ void HAL_MRSUBG_TIMER_Tick(void) _updateCalibrationData(); HAL_MRSUBG_TIMER_StopVirtualTimer(&MRSUBG_TIMER_Context.calibrationTimer); /* Schedule next calibration event */ - _start_timer(&MRSUBG_TIMER_Context.calibrationTimer, HAL_MRSUBG_TIMER_GetCurrentSysTime() + MRSUBG_TIMER_Context.periodicCalibrationInterval); - } - } - /* Make sure no expired timer was left unarmed due to time missalignment */ - if (MRSUBG_TIMER_Context.close_expiration) - { - if((MRSUBG_TIMER_Context.calibrationTimer.expiryTime) < HAL_MRSUBG_TIMER_GetCurrentSysTime()) - { - INCREMENT_EXPIRE_COUNT; - } - else if ((MRSUBG_TIMER_Context.rootNode->expiryTime) < HAL_MRSUBG_TIMER_GetCurrentSysTime()) - { - INCREMENT_EXPIRE_COUNT; + _start_timer(&MRSUBG_TIMER_Context.calibrationTimer, + HAL_MRSUBG_TIMER_GetCurrentSysTime() + MRSUBG_TIMER_Context.periodicCalibrationInterval); } } } /** - * @brief Returns the admitted low power mode according to the next timer activity. - * @return Low Power mode - */ + * @brief Returns the admitted low power mode according to the next timer activity. + * @return Low Power mode + */ PowerSaveLevels HAL_MRSUBG_TIMER_PowerSaveLevelCheck(void) { uint32_t nextRadioActivity; uint8_t timerState; + uint64_t current_time; uint32_t hs_startup_machine_time; PowerSaveLevels level; - if (((MRSUBG_TIMER_Context.expired_count == MRSUBG_TIMER_Context.served_count) && !MRSUBG_TIMER_Context.calibration_in_progress) == FALSE) + if (((MRSUBG_TIMER_Context.expired_count == MRSUBG_TIMER_Context.served_count) + && !MRSUBG_TIMER_Context.calibration_in_progress) == FALSE) { return POWER_SAVE_LEVEL_DISABLED; } @@ -364,7 +362,9 @@ PowerSaveLevels HAL_MRSUBG_TIMER_PowerSaveLevelCheck(void) if (timerState == WAKEUP_MRSUBG_TIMER_BUSY) { hs_startup_machine_time = _us_to_machinetime(MRSUBG_TIMER_Context.hs_startup_time); - if(TIME_ABSDIFF(nextRadioActivity, LL_MRSUBG_TIMER_GetAbsoluteTime(MR_SUBG_GLOB_MISC)) < (hs_startup_machine_time+LOW_POWER_THR_MTU)) + if (TIME_ABSDIFF(nextRadioActivity, + LL_MRSUBG_TIMER_GetAbsoluteTime(MR_SUBG_GLOB_MISC)) < \ + (hs_startup_machine_time + LOW_POWER_THR_MTU)) { return POWER_SAVE_LEVEL_SLEEP; } @@ -372,18 +372,36 @@ PowerSaveLevels HAL_MRSUBG_TIMER_PowerSaveLevelCheck(void) level = POWER_SAVE_LEVEL_DEEPSTOP_TIMER; } - if(MRSUBG_TIMER_Context.rootNode != NULL && MRSUBG_TIMER_Context.rootNode->active) + if (MRSUBG_TIMER_Context.rootNode != NULL && MRSUBG_TIMER_Context.rootNode->active) { - /* Disable power save if a timer is about to expire */ - if(((MRSUBG_TIMER_Context.rootNode->expiryTime - HAL_MRSUBG_TIMER_GetCurrentSysTime()) < (LOW_POWER_THR_STU + MRSUBG_TIMER_Context.hs_startup_time)*3)|| (MRSUBG_TIMER_Context.close_expiration !=0)) + current_time = HAL_MRSUBG_TIMER_GetCurrentSysTime(); + /* Timer in the past */ + if (MRSUBG_TIMER_Context.rootNode->expiryTime < current_time) { - MRSUBG_TIMER_Context.close_expiration = 1; + /* Active timer has expired but wasn't handled by it's callback, go handle it */ + INCREMENT_EXPIRE_COUNT; return POWER_SAVE_LEVEL_DISABLED; } + /* Timer in the future */ + else + { + /* Active timer is about to expire: within the necessary time to enter in low power state */ + if (MRSUBG_TIMER_Context.rootNode->expiryTime < (current_time + LOW_POWER_ENTRY_MARGIN_US)) + { + return POWER_SAVE_LEVEL_DISABLED; + } + /* Active timer is about to expire: within the necessary time to wakeup from deepstop */ + else if (MRSUBG_TIMER_Context.rootNode->expiryTime < (current_time + LOW_POWER_THR_STU + + MRSUBG_TIMER_Context.hs_startup_time)) + { + return POWER_SAVE_LEVEL_SLEEP; + } + } - if(level == POWER_SAVE_LEVEL_DEEPSTOP_NOTIMER) + if (level == POWER_SAVE_LEVEL_DEEPSTOP_NOTIMER) { - if((MRSUBG_TIMER_Context.rootNode->next == NULL) && (MRSUBG_TIMER_Context.rootNode == &MRSUBG_TIMER_Context.calibrationTimer)) + if ((MRSUBG_TIMER_Context.rootNode->next == NULL) + && (MRSUBG_TIMER_Context.rootNode == &MRSUBG_TIMER_Context.calibrationTimer)) { MRSUBG_TIMER_Context.stop_notimer_action = TRUE; _virtualTimeBaseEnable(DISABLE); @@ -400,17 +418,17 @@ PowerSaveLevels HAL_MRSUBG_TIMER_PowerSaveLevelCheck(void) /* ---------------------- RADIO Activity APIs --------------------------------*/ /** - * @brief Return the status of the RFIP Wakeup timer and the last value programmed in the register. - * @param time: return the RFIP Wakeup time. - * @retval 0 if no timer has been programmed. - * @retval 1 if RFIP Wakeup Timer has been programmed. - */ + * @brief Return the status of the RFIP Wakeup timer and the last value programmed in the register. + * @param time: return the RFIP Wakeup time. + * @retval 0 if no timer has been programmed. + * @retval 1 if RFIP Wakeup Timer has been programmed. + */ uint8_t HAL_MRSUBG_TIMER_GetRadioTimerValue(uint32_t *time) { uint8_t status = 0; *time = 0; - if(LL_MRSUBG_TIMER_IsEnabledRFIPWakeupTimer(MR_SUBG_GLOB_RETAINED)) + if (LL_MRSUBG_TIMER_IsEnabledRFIPWakeupTimer(MR_SUBG_GLOB_RETAINED)) { *time = LL_MRSUBG_TIMER_GetRFIPWakeupTime(MR_SUBG_GLOB_RETAINED); status = WAKEUP_MRSUBG_TIMER_BUSY; @@ -422,31 +440,31 @@ uint8_t HAL_MRSUBG_TIMER_GetRadioTimerValue(uint32_t *time) /* ----------------------- Radio Timer time unit APIs ------------------------*/ /** - * @brief Translates time in microseconds into machine time units. - * @param time: Microseconds to be converted in MTU - * @return Machine time value - */ + * @brief Translates time in microseconds into machine time units. + * @param time: Microseconds to be converted in MTU + * @return Machine time value + */ uint64_t HAL_MRSUBG_TIMER_UsToMachinetime(uint64_t time) { return _us_to_machinetime(time); } /** - * @brief Translates time machine time in microseconds. - * @param time: Machine time to be converted in microseconds - * @return Time value in microseconds - */ + * @brief Translates time machine time in microseconds. + * @param time: Machine time to be converted in microseconds + * @return Time value in microseconds + */ uint64_t HAL_MRSUBG_TIMER_MachinetimeToUs(uint64_t time) { return _machinetime_to_us(time); } /** - * @brief This function returns the current reference time expressed in system time units (1us). - * The returned value can be used as absolute time parameter where needed in the other - * HAL_MRSUBG_TIMER* APIs - * @return absolute current time expressed in system time units (1 us). - */ + * @brief This function returns the current reference time expressed in system time units (1us). + * The returned value can be used as absolute time parameter where needed in the other + * HAL_MRSUBG_TIMER* APIs + * @return absolute current time expressed in system time units (1 us). + */ uint64_t HAL_MRSUBG_TIMER_GetCurrentSysTime(void) { uint32_t current_machine_time; @@ -456,48 +474,48 @@ uint64_t HAL_MRSUBG_TIMER_GetCurrentSysTime(void) /* -------------------------- Virtual timer APIs ---------------------------- */ /** - * @brief Starts a one-shot virtual timer for the given relative timeout value expressed in us - * @param timerHandle: The virtual timer - * @param usRelTimeout: The relative time, from current time, expressed in us - * @retval 0 if the timerHandle is valid. - * @retval 1 if the timerHandle is not valid. It is already started. - */ -uint32_t HAL_MRSUBG_TIMER_StartVirtualTimer(VTIMER_HandleType *timerHandle, uint64_t usRelTimeout) + * @brief Starts a one-shot virtual timer for the given relative timeout value expressed in us + * @param timerHandle: The virtual timer + * @param usRelTimeout: The relative time, from current time, expressed in us + * @retval 0 if the timerHandle is valid. + * @retval 1 if the timerHandle is not valid. It is already started. + */ +uint32_t HAL_MRSUBG_TIMER_StartVirtualTimer(VTIMER_HandleType_t *timerHandle, uint64_t usRelTimeout) { uint8_t retVal; - retVal = _start_timer(timerHandle, (HAL_MRSUBG_TIMER_GetCurrentSysTime()+usRelTimeout)); + retVal = _start_timer(timerHandle, (HAL_MRSUBG_TIMER_GetCurrentSysTime() + usRelTimeout)); _virtualTimeBaseEnable(ENABLE); return retVal; } /** - * @brief Starts a one-shot virtual timer for the given relative timeout value expressed in ms - * @param timerHandle: The virtual timer - * @param msRelTimeout: The relative time, from current time, expressed in ms - * @retval 0 if the timerHandle is valid. - * @retval 1 if the timerHandle is not valid. It is already started. - */ -uint32_t HAL_MRSUBG_TIMER_StartVirtualTimerMs(VTIMER_HandleType *timerHandle, uint32_t msRelTimeout) -{ - uint64_t time = msRelTimeout*1000; + * @brief Starts a one-shot virtual timer for the given relative timeout value expressed in ms + * @param timerHandle: The virtual timer + * @param msRelTimeout: The relative time, from current time, expressed in ms + * @retval 0 if the timerHandle is valid. + * @retval 1 if the timerHandle is not valid. It is already started. + */ +uint32_t HAL_MRSUBG_TIMER_StartVirtualTimerMs(VTIMER_HandleType_t *timerHandle, uint32_t msRelTimeout) +{ + uint64_t time = msRelTimeout * 1000; uint8_t retVal; - retVal = _start_timer(timerHandle, (HAL_MRSUBG_TIMER_GetCurrentSysTime()+time)); + retVal = _start_timer(timerHandle, (HAL_MRSUBG_TIMER_GetCurrentSysTime() + time)); _virtualTimeBaseEnable(ENABLE); return retVal; } /** - * @brief Stops the one-shot virtual timer specified if found - * @param timerHandle: The virtual timer - * @retval None - */ -void HAL_MRSUBG_TIMER_StopVirtualTimer(VTIMER_HandleType *timerHandle) + * @brief Stops the one-shot virtual timer specified if found + * @param timerHandle: The virtual timer + * @retval None + */ +void HAL_MRSUBG_TIMER_StopVirtualTimer(VTIMER_HandleType_t *timerHandle) { - VTIMER_HandleType *rootNode = _remove_timer_in_queue(MRSUBG_TIMER_Context.rootNode, timerHandle); + VTIMER_HandleType_t *rootNode = _remove_timer_in_queue(MRSUBG_TIMER_Context.rootNode, timerHandle); uint8_t expired = 0; - timerHandle->active=FALSE; + timerHandle->active = FALSE; if (MRSUBG_TIMER_Context.rootNode != rootNode) { MRSUBG_TIMER_Context.rootNode = _update_user_timeout(rootNode, &expired); @@ -509,24 +527,24 @@ void HAL_MRSUBG_TIMER_StopVirtualTimer(VTIMER_HandleType *timerHandle) } else { - MRSUBG_TIMER_Context.rootNode = rootNode; + MRSUBG_TIMER_Context.rootNode = rootNode; } } /** - * @brief Returns the absolute expiry time of a running virtual timer expressed in internal system time units (us). - * @param timerHandle: The virtual timer - * @retval sysTime: Absolute time expressed in internal system time units (us). - */ -uint64_t HAL_MRSUBG_TIMER_ExpiryTime(VTIMER_HandleType *timerHandle) + * @brief Returns the absolute expiry time of a running virtual timer expressed in internal system time units (us). + * @param timerHandle: The virtual timer + * @retval sysTime: Absolute time expressed in internal system time units (us). + */ +uint64_t HAL_MRSUBG_TIMER_ExpiryTime(VTIMER_HandleType_t *timerHandle) { return timerHandle->expiryTime; } /** - * @brief Virtual timer Timeout Callback. It signals that a host timeout occurred. - * @retval None - */ + * @brief Virtual timer Timeout Callback. It signals that a host timeout occurred. + * @retval None + */ void HAL_MRSUBG_TIMER_TimeoutCallback(void) { /* Disable host timer */ @@ -538,12 +556,12 @@ void HAL_MRSUBG_TIMER_TimeoutCallback(void) } /** - * @brief Returns the number of timers in the queue. - * @return number of timers in the queue. - */ + * @brief Returns the number of timers in the queue. + * @return number of timers in the queue. + */ uint32_t HAL_MRSUBG_TIMER_GetPendingTimers(void) { - VTIMER_HandleType *curr = MRSUBG_TIMER_Context.rootNode; + VTIMER_HandleType_t *curr = MRSUBG_TIMER_Context.rootNode; uint32_t counter = 0; while (curr != NULL) { @@ -570,10 +588,12 @@ static void _get_calibration_data(void) scm_counter_currval = LL_MRSUBG_TIMER_GetSCM(MR_SUBG_GLOB_MISC); if ((scm_counter_currval != 0) && (scm_counter_currval != MRSUBG_TIMER_Context.last_scm_counter)) { - MRSUBG_TIMER_Context.slow_clock_freq = ((32ull * (uint64_t)MRSUBG_TIMER_Context.fast_clock_freq * 1000)/scm_counter_currval); + MRSUBG_TIMER_Context.slow_clock_freq = ((32ull * \ + (uint64_t)MRSUBG_TIMER_Context.fast_clock_freq * 1000) / \ + scm_counter_currval); MRSUBG_TIMER_Context.last_scm_counter = scm_counter_currval; last_interpolated_freq = MRSUBG_TIMER_Context.interpolated_freq; - MRSUBG_TIMER_Context.interpolated_freq = (16u * MRSUBG_TIMER_Context.slow_clock_freq)/1000; + MRSUBG_TIMER_Context.interpolated_freq = (16u * MRSUBG_TIMER_Context.slow_clock_freq) / 1000; if (last_interpolated_freq == 0) { MRSUBG_TIMER_Context.last_interpolated_freq = MRSUBG_TIMER_Context.interpolated_freq; @@ -583,7 +603,8 @@ static void _get_calibration_data(void) MRSUBG_TIMER_Context.last_interpolated_freq = last_interpolated_freq; } MRSUBG_TIMER_Context.slow_clock_freq /= 1000; - MRSUBG_TIMER_Context.timer_max_value = (((uint64_t)TIMER_MAX_VALUE*1000000ull)/MRSUBG_TIMER_Context.interpolated_freq); + MRSUBG_TIMER_Context.timer_max_value = (((uint64_t)TIMER_MAX_VALUE * 1000000ull) / \ + MRSUBG_TIMER_Context.interpolated_freq); } } @@ -591,9 +612,11 @@ static void _timer_calibrate(void) { uint8_t scm_transitory = 0; /* wait for SCM to leave reset state value */ - while(LL_MRSUBG_TIMER_GetSCM(MR_SUBG_GLOB_MISC) == 0); + while (LL_MRSUBG_TIMER_GetSCM(MR_SUBG_GLOB_MISC) == 0); /* wait for SCM to reach a stable slow clock value after a transitory startup period */ - while((LL_MRSUBG_TIMER_GetSCM(MR_SUBG_GLOB_MISC) != ((32ull * (uint64_t)MRSUBG_TIMER_Context.fast_clock_freq)/SLOW_CLOCK_WORKING_FREQ)) && (scm_transitory++ < MAX_SCM_DELAY_COUNT)) + while ((LL_MRSUBG_TIMER_GetSCM(MR_SUBG_GLOB_MISC) != ((32ull * (uint64_t)MRSUBG_TIMER_Context.fast_clock_freq) / + SLOW_CLOCK_WORKING_FREQ)) && \ + (scm_transitory++ < MAX_SCM_DELAY_COUNT)) { HAL_Delay(SCM_DELAY_MS); } @@ -604,25 +627,29 @@ static void _update_xtal_startup_time(void) { uint16_t time; - time= ((MRSUBG_TIMER_Context.hs_startup_time*MRSUBG_TIMER_Context.slow_clock_freq)/1000000ull); - if(time >= 255) - time = 255; - if(time < 16) + time = ((MRSUBG_TIMER_Context.hs_startup_time * MRSUBG_TIMER_Context.slow_clock_freq) / 1000000ull); + if (time >= TIME_MAX_VALUE) + { + time = TIME_MAX_VALUE; + } + if (time < 16) + { time = 20; + } LL_MRSUBG_TIMER_SetWakeupOffset(MR_SUBG_GLOB_RETAINED, (uint8_t)time); } static void _updateCalibrationData(void) { - _get_calibration_data(); - _update_xtal_startup_time(); - ATOMIC_SECTION_BEGIN(); - _update_system_time(); - ATOMIC_SECTION_END(); + _get_calibration_data(); + _update_xtal_startup_time(); + ATOMIC_SECTION_BEGIN(); + _update_system_time(); + ATOMIC_SECTION_END(); } -static void _calibration_callback (void *handle) +static void _calibration_callback(void *handle) { MRSUBG_TIMER_Context.calibration_in_progress = TRUE; } @@ -633,25 +660,28 @@ static void _update_system_time(void) uint64_t new_time; current_machine_time = LL_MRSUBG_TIMER_GetAbsoluteTime(MR_SUBG_GLOB_MISC) & TIMER_MAX_VALUE; - new_time = ((uint64_t)TIME_ABSDIFF(current_machine_time, MRSUBG_TIMER_Context.last_calibration_machine_time)*1000000ull)/MRSUBG_TIMER_Context.last_interpolated_freq; + new_time = ((uint64_t)TIME_ABSDIFF(current_machine_time, MRSUBG_TIMER_Context.last_calibration_machine_time) \ + * 1000000ull) / MRSUBG_TIMER_Context.last_interpolated_freq; MRSUBG_TIMER_Context.cumulative_time = MRSUBG_TIMER_Context.last_calibration_time + new_time; - if (TIME_ABSDIFF(current_machine_time, MRSUBG_TIMER_Context.last_calibration_machine_time) < MRSUBG_TIMER_Context.calibration_machine_interval) - { - if (MRSUBG_TIMER_Context.periodic_calibration == 0) - { - /* When accounting for slow clock frequency oscillations over time: - * In wrap around conditions of the HW timer, timer_max_value - * added to the cumulative time needs to be calculated using - * last_interpolated_freq, used until this calibration cycle. - */ - MRSUBG_TIMER_Context.cumulative_time += (((uint64_t)TIMER_MAX_VALUE*1000000ull)/MRSUBG_TIMER_Context.last_interpolated_freq); - } - else - { - /* Account for elapsed time when periodic_calibrations are set & a wraparound of the register occurs */ - MRSUBG_TIMER_Context.cumulative_time += MRSUBG_TIMER_Context.periodicCalibrationInterval; - } + if (TIME_ABSDIFF(current_machine_time, + MRSUBG_TIMER_Context.last_calibration_machine_time) < MRSUBG_TIMER_Context.calibration_machine) + { + if (MRSUBG_TIMER_Context.periodic_calibration == 0) + { + /* When accounting for slow clock frequency oscillations over time: + * In wrap around conditions of the HW timer, timer_max_value + * added to the cumulative time needs to be calculated using + * last_interpolated_freq, used until this calibration cycle. + */ + MRSUBG_TIMER_Context.cumulative_time += (((uint64_t)TIMER_MAX_VALUE * 1000000ull) / + MRSUBG_TIMER_Context.last_interpolated_freq); + } + else + { + /* Account for elapsed time when periodic_calibrations are set & a wraparound of the register occurs */ + MRSUBG_TIMER_Context.cumulative_time += MRSUBG_TIMER_Context.periodicCalibrationInterval; + } } MRSUBG_TIMER_Context.last_calibration_machine_time = current_machine_time; MRSUBG_TIMER_Context.last_calibration_time = MRSUBG_TIMER_Context.cumulative_time; @@ -660,7 +690,7 @@ static void _update_system_time(void) * periodicCalibrationInterval (used as timeout for the next calibration cycle) * has to be calculated dynamically using the current frequency value. */ - MRSUBG_TIMER_Context.periodicCalibrationInterval = _machinetime_to_us(MRSUBG_TIMER_Context.calibration_machine_interval); + MRSUBG_TIMER_Context.periodicCalibrationInterval = _machinetime_to_us(MRSUBG_TIMER_Context.calibration_machine); } static uint64_t _us_to_machinetime(uint64_t time) @@ -670,7 +700,7 @@ static uint64_t _us_to_machinetime(uint64_t time) static uint64_t _machinetime_to_us(uint64_t time) { - return ((time*1000000ull)/MRSUBG_TIMER_Context.interpolated_freq); + return ((time * 1000000ull) / MRSUBG_TIMER_Context.interpolated_freq); } static uint64_t _get_system_time_and_machine(uint32_t *current_machine_time) @@ -679,9 +709,11 @@ static uint64_t _get_system_time_and_machine(uint32_t *current_machine_time) ATOMIC_SECTION_BEGIN(); *current_machine_time = LL_MRSUBG_TIMER_GetAbsoluteTime(MR_SUBG_GLOB_MISC); - new_time = ((uint64_t)TIME_ABSDIFF(*current_machine_time, MRSUBG_TIMER_Context.last_calibration_machine_time)*1000000ull) / MRSUBG_TIMER_Context.interpolated_freq; + new_time = ((uint64_t)TIME_ABSDIFF(*current_machine_time, MRSUBG_TIMER_Context.last_calibration_machine_time) \ + * 1000000ull) / MRSUBG_TIMER_Context.interpolated_freq; new_time += MRSUBG_TIMER_Context.cumulative_time; - if (new_time < MRSUBG_TIMER_Context.last_system_time) { + if (new_time < MRSUBG_TIMER_Context.last_system_time) + { new_time += MRSUBG_TIMER_Context.timer_max_value; } MRSUBG_TIMER_Context.last_system_time = new_time; @@ -691,12 +723,12 @@ static uint64_t _get_system_time_and_machine(uint32_t *current_machine_time) return new_time; } -static int32_t _start_timer(VTIMER_HandleType *timerHandle, uint64_t time) +static int32_t _start_timer(VTIMER_HandleType_t *timerHandle, uint64_t time) { uint8_t expired = 0; /* The timer is already started*/ - if(timerHandle->active) + if (timerHandle->active) { return 1; } @@ -716,17 +748,18 @@ static int32_t _start_timer(VTIMER_HandleType *timerHandle, uint64_t time) } /* Set timeout and skip non active timers */ -static VTIMER_HandleType *_update_user_timeout(VTIMER_HandleType *rootNode, uint8_t *expired) +static VTIMER_HandleType_t *_update_user_timeout(VTIMER_HandleType_t *rootNode, uint8_t *expired) { - VTIMER_HandleType *curr = rootNode; - VTIMER_HandleType *rootOrig = rootNode; + VTIMER_HandleType_t *curr = rootNode; + VTIMER_HandleType_t *rootOrig = rootNode; int64_t delay; *expired = 0; while (curr != NULL) { - if (curr->active) { + if (curr->active) + { ATOMIC_SECTION_BEGIN(); - delay = curr->expiryTime-HAL_MRSUBG_TIMER_GetCurrentSysTime(); + delay = curr->expiryTime - HAL_MRSUBG_TIMER_GetCurrentSysTime(); if (delay > 0) { /* Protection against interrupt must be used to avoid that the called function will be interrupted @@ -741,10 +774,12 @@ static VTIMER_HandleType *_update_user_timeout(VTIMER_HandleType *rootNode, uint ATOMIC_SECTION_END(); break; } - curr=curr->next; + curr = curr->next; } if (*expired) + { return rootOrig; + } return curr; } @@ -756,7 +791,7 @@ static uint32_t VTIMER_SetWakeupTime(uint64_t delay, BOOL allow_sleep) delay_mtu = _us_to_machinetime(delay); /* If the delay is too small round to minimum 2 tick */ - delay_mtu = MAX(32,delay_mtu); + delay_mtu = MAX(32, delay_mtu); current_time = LL_MRSUBG_TIMER_GetAbsoluteTime(MR_SUBG_GLOB_MISC); /* 4 least significant bits are not taken into account. Then let's round the value */ LL_MRSUBG_TIMER_SetCPUWakeupTime(MR_SUBG_GLOB_RETAINED, ((current_time + (delay_mtu + 8)) & TIMER_MAX_VALUE)); @@ -765,16 +800,16 @@ static uint32_t VTIMER_SetWakeupTime(uint64_t delay, BOOL allow_sleep) return current_time; } -static VTIMER_HandleType * _insert_timer_in_queue(VTIMER_HandleType *rootNode, VTIMER_HandleType *handle) +static VTIMER_HandleType_t *_insert_timer_in_queue(VTIMER_HandleType_t *rootNode, VTIMER_HandleType_t *handle) { - VTIMER_HandleType *current = rootNode; - VTIMER_HandleType *prev = NULL; - VTIMER_HandleType *returnValue = rootNode; + VTIMER_HandleType_t *current = rootNode; + VTIMER_HandleType_t *prev = NULL; + VTIMER_HandleType_t *returnValue = rootNode; - while ((current!=NULL) && (current->expiryTime < handle->expiryTime)) + while ((current != NULL) && (current->expiryTime < handle->expiryTime)) { prev = current; - current=current->next; + current = current->next; } handle->next = current; @@ -794,7 +829,7 @@ static VTIMER_HandleType * _insert_timer_in_queue(VTIMER_HandleType *rootNode, V static void _virtualTimeBaseEnable(FunctionalState state) { - if(state != DISABLE) + if (state != DISABLE) { if (MRSUBG_TIMER_Context.enableTimeBase == FALSE) { @@ -809,25 +844,29 @@ static void _virtualTimeBaseEnable(FunctionalState state) } } -static VTIMER_HandleType * _remove_timer_in_queue(VTIMER_HandleType *rootNode, VTIMER_HandleType *handle) +static VTIMER_HandleType_t *_remove_timer_in_queue(VTIMER_HandleType_t *rootNode, VTIMER_HandleType_t *handle) { - VTIMER_HandleType *current = rootNode; - VTIMER_HandleType *prev = NULL; - VTIMER_HandleType *returnValue = rootNode; + VTIMER_HandleType_t *current = rootNode; + VTIMER_HandleType_t *prev = NULL; + VTIMER_HandleType_t *returnValue = rootNode; - while ((current!=NULL) && (current != handle)) { + while ((current != NULL) && (current != handle)) + { prev = current; - current=current->next; + current = current->next; } - if (current == NULL) { + if (current == NULL) + { /* Not found */ } - else if (current == rootNode) { + else if (current == rootNode) + { /* New root node */ returnValue = current->next; } - else { + else + { prev->next = current->next; } @@ -835,39 +874,44 @@ static VTIMER_HandleType * _remove_timer_in_queue(VTIMER_HandleType *rootNode, V } /* Check the number of expired timer from rootNode (ordered list of timers) and return the list of expired timers */ -static VTIMER_HandleType *_check_callbacks(VTIMER_HandleType *rootNode,VTIMER_HandleType **expiredList) +static VTIMER_HandleType_t *_check_callbacks(VTIMER_HandleType_t *rootNode, VTIMER_HandleType_t **expiredList) { - VTIMER_HandleType *curr = rootNode; - VTIMER_HandleType *prev = NULL; - VTIMER_HandleType *returnValue = rootNode; + VTIMER_HandleType_t *curr = rootNode; + VTIMER_HandleType_t *prev = NULL; + VTIMER_HandleType_t *returnValue = rootNode; *expiredList = rootNode; int64_t delay; uint32_t expiredCount = 0; - while (curr != NULL) { + while (curr != NULL) + { - if (curr->active) { + if (curr->active) + { delay = curr->expiryTime - HAL_MRSUBG_TIMER_GetCurrentSysTime(); - if (delay > 5) { + if (delay > 5) + { /* End of expired timers list */ break; } } prev = curr; - curr=curr->next; + curr = curr->next; expiredCount++; } - if (expiredCount) { + if (expiredCount) + { /* Some timers expired */ - prev->next=NULL; + prev->next = NULL; returnValue = curr; } - else { + else + { /* No timer expired */ *expiredList = NULL; } diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_pwr.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_pwr.c index 8d0fd7b3ed..6f9b790e18 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_pwr.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_pwr.c @@ -77,9 +77,10 @@ (#) The Core low power modes are : (+) Run. (+) Sleep. - (+) DEEPSTOP with with retention and low speed clock enabled. - (+) DEEPSTOP with with retention and low speed clock disabled. + (+) DEEPSTOP with retention and low speed clock enabled. + (+) DEEPSTOP with retention and low speed clock disabled. (+) Shutdown. + (+) ULTRA-DEEPSTOP. [..] *** PVD configuration *** @@ -90,7 +91,7 @@ (+) PVDO flag is available to indicate when VDD is lower than the PVD threshold. This event can generate an interrupt if enabled. This is done through __HAL_PVD_ENABLE_IT() macro. - (+) The PVD is stopped in Shutdown mode. + (+) The PVD is stopped in Shutdown and ULTRA-DEEPSTOP modes. *** Wake-up pin configuration *** ================================= @@ -330,7 +331,71 @@ void HAL_PWR_EnterDEEPSTOPMode(void) /* Wait for Interrupt Request to enter in DEEPSTOP */ __WFI(); } +#if defined (STM32WL3RX) +/** + * @brief Configures the system to allow the ULTRA-DEEPSTOP mode. + * @retval None. + * @note This mode is available only for STM32WL3RX device. + */ +HAL_StatusTypeDef HAL_PWR_ConfigUltraDeepStop(PWR_ULTRA_DEEPSTOPTypeDef *sConfigUltraDeepStop) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_POLARITY(sConfigUltraDeepStop->WakeUpPol)); + /* BOR configuration during ULTRA-DEEPSTOP mode */ + if (sConfigUltraDeepStop->BORStatus == ENABLE) + { + LL_PWR_EnableBORinSDN(); + } + else + { + LL_PWR_DisableBORinSDN(); + } + + if (sConfigUltraDeepStop->WakeUpPinStatus == ENABLE) + { + LL_PWR_IOWakeupPolaritySDN(sConfigUltraDeepStop->WakeUpPol); + LL_PWR_EnableIOWakeupSDN(); + } + else + { + LL_PWR_DisableIOWakeupSDN(); + } + + /* Disable DIRECT HSE configuration to allow ULTRA-DEEPSTOP request */ + if (LL_RCC_DIRECT_HSE_IsEnabled()) + { + LL_RCC_DIRECT_HSE_Disable(); + } + + return HAL_OK; +} + +/** + * @brief Enter the whole system in ULTRA-DEEPSTOP mode. + * @retval None. + * @note This mode is available only for STM32WL3RX device. + */ +void HAL_PWR_EnterUltraDeepStopMode(void) +{ + /* Clear all the wake-up pin flags */ + LL_PWR_ClearInternalWakeupSource(LL_PWR_WAKEUP_ALL); + LL_PWR_ClearWakeupSource(PWR_WAKEUP_PORTA, LL_PWR_WAKEUP_ALL); + LL_PWR_ClearWakeupSource(PWR_WAKEUP_PORTB, LL_PWR_WAKEUP_ALL); + + /* Enable the device ULTRA_DEEPSTOP configuration */ + LL_PWR_SetPowerMode(LL_PWR_MODE_ULTRA_DEEPSTOP); + + /* Set Ultra Deepstop bit */ + SET_BIT(PWR->PDCRA, PWR_PDCRA_UDP); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Wait for Interrupt Request to enter in ULTRA-DEEPSTOP */ + __WFI(); +} +#endif /* STM32WL3RX */ /** * @brief Configures the system to allow the SHUTDOWN mode. * @param sConfigSHUTDOWN : Pointer to a @ref PWR_SHUTDOWNTypeDef structure that diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_pwr_ex.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_pwr_ex.c index 1623831c5c..de06e797af 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_pwr_ex.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_pwr_ex.c @@ -124,6 +124,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber * PUy bit of PWR_PUCRx register is cleared unless it is reserved. * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input * parameter at the same time are set. + * @note For the STM32WL3R device, the pull-down configuration is not valid on PA6. * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, PWR_GPIO_B * to select the GPIO peripheral. * @param GPIONumber Specify the I/O pins numbers. @@ -164,6 +165,7 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe * in pull-down state in DeepStop and Shutdown modes. * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input * parameter at the same time are reset. + * @note For the STM32WL3R device, the pull-down configuration is not valid on PA6. * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, PWR_GPIO_B * to select the GPIO peripheral. * @param GPIONumber Specify the I/O pins numbers. @@ -313,6 +315,11 @@ void HAL_PWREx_EnterSHUTDOWNMode(void) LL_PWR_ClearWakeupSource(PWR_WAKEUP_PORTA, LL_PWR_WAKEUP_ALL); LL_PWR_ClearWakeupSource(PWR_WAKEUP_PORTB, LL_PWR_WAKEUP_ALL); +#if defined (STM32WL3RX) + /* clear Ultra Deepstop bit before EnterSHUTDOWNMode */ + CLEAR_BIT(PWR->PDCRA, PWR_PDCRA_UDP); +#endif /* STM32WL3RX */ + /* Enable the device Shutdown configuration */ LL_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN); diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_rcc_ex.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_rcc_ex.c index 11d8dd4c6e..d509d251ec 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_rcc_ex.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_rcc_ex.c @@ -41,12 +41,12 @@ * @{ */ -#if defined(STM32WL3XX) +#if defined(STM32WL3XX) || defined(STM32WL3RX) #define __LSCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define LSCO1_GPIO_PORT GPIOA #define LSCO1_PIN GPIO_PIN_4 #define LSCO1_GPIO_AF GPIO_AF0_LCO -#endif +#endif /* (STM32WL3XX) || (STM32WL3Rx) */ #define __LSCO2_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define LSCO2_GPIO_PORT GPIOA @@ -54,12 +54,12 @@ #define LSCO2_GPIO_AF GPIO_AF0_LCO -#if defined(STM32WL3XX) +#if defined(STM32WL3XX) || defined(STM32WL3RX) #define __LSCO3_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() #define LSCO3_GPIO_PORT GPIOB #define LSCO3_PIN GPIO_PIN_12 #define LSCO3_GPIO_AF GPIO_AF2_LCO -#endif +#endif /* (STM32WL3XX) || (STM32WL3Rx) */ /** * @} @@ -265,8 +265,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) frequency = LSE_VALUE; break; case RCC_LPUART1_CLKSOURCE_16M: - frequency = 16000000U; - break; default: frequency = HSE_VALUE / 2; break; diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_timebase_tim_template.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_timebase_tim_template.c index 8dc8938798..a2a8e3df3b 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_timebase_tim_template.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_timebase_tim_template.c @@ -100,6 +100,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + /* Register callback */ + HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&TimHandle); } diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_uart.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_uart.c index 46124042b5..60a762fa94 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_uart.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_uart.c @@ -1190,7 +1190,15 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); pdata8bits++; } - huart->TxXferCount--; + if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) + { + huart->TxXferCount--; + } + else + { + /* Process was aborted during the transmission */ + return HAL_ERROR; + } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) @@ -1302,7 +1310,15 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); pdata8bits++; } - huart->RxXferCount--; + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + huart->RxXferCount--; + } + else + { + /* Process was aborted during the reception */ + return HAL_ERROR; + } } /* At end of Rx process, restore huart->RxState to Ready */ @@ -1810,10 +1826,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -1882,9 +1894,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -1949,9 +1958,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) } #endif /* HAL_DMA_MODULE_ENABLED */ - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -2079,10 +2085,6 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear ISR function pointers */ huart->RxISR = NULL; huart->TxISR = NULL; @@ -2163,8 +2165,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } else { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2185,9 +2185,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) else #endif /* HAL_DMA_MODULE_ENABLED */ { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2262,9 +2259,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } else { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -2291,9 +2285,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) else #endif /* HAL_DMA_MODULE_ENABLED */ { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -3693,8 +3684,6 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - huart->TxXferCount = 0U; - /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -3745,8 +3734,6 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - huart->RxXferCount = 0U; - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3773,8 +3760,6 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - huart->RxXferCount = 0; - /* Check current nb of data still to be received on DMA side. DMA Normal mode, remaining nb of data will be 0 DMA Circular mode, remaining nb of data is reset to RxXferSize */ @@ -3870,7 +3855,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } @@ -3878,7 +3862,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - huart->RxXferCount = 0U; UART_EndRxTransfer(huart); } @@ -3902,7 +3885,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->RxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -3936,10 +3918,6 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -3991,10 +3969,6 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -4032,8 +4006,6 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -4065,8 +4037,6 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_i2c.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_i2c.c index d3a0ffd236..7a371d242b 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_i2c.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_i2c.c @@ -89,7 +89,7 @@ ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx) /* Check the I2C Instance I2Cx */ assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); - +#if defined(I2C1) if (I2Cx == I2C1) { /* Force reset of I2C clock */ @@ -98,6 +98,8 @@ ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx) /* Release reset of I2C clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); } +#endif /* I2C1*/ +#if defined(I2C2) else if (I2Cx == I2C2) { /* Force reset of I2C clock */ @@ -107,6 +109,7 @@ ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx) LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2); } +#endif /* I2C2*/ else { status = ERROR; diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_pwr.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_pwr.c index f0afd1ab6e..7454497cfb 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_pwr.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_pwr.c @@ -76,6 +76,7 @@ ErrorStatus LL_PWR_DeInit(void) LL_PWR_WriteReg(SDWN_WUPOL, 0); #endif /* PWR_SDWN_WUEN_WUEN */ +#if defined (STM32WL3XX) LL_PWR_WriteReg(IWUF, LL_PWR_WAKEUP_LPAWUR | LL_PWR_WAKEUP_SUBG @@ -86,6 +87,14 @@ ErrorStatus LL_PWR_DeInit(void) | LL_PWR_WAKEUP_RTC | LL_PWR_WAKEUP_LPUART ); +#else + LL_PWR_WriteReg(IWUF, + LL_PWR_WAKEUP_SUBG + | LL_PWR_WAKEUP_SUBGHOST + | LL_PWR_WAKEUP_RTC + | LL_PWR_WAKEUP_LPUART + ); +#endif /* (STM32WL3XX) */ LL_PWR_WriteReg(WUFA, LL_PWR_WAKEUP_ALL); LL_PWR_WriteReg(WUFB, LL_PWR_WAKEUP_ALL); diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_spi.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_spi.c index e1d46c9e69..5c25954c93 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_spi.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_spi.c @@ -238,8 +238,10 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) status = SUCCESS; } +#if defined (SPI_I2S_SUPPORT) /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2S_SUPPORT */ return status; } @@ -276,6 +278,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * @} */ +#if defined(SPI_I2S_SUPPORT) /** @addtogroup I2S_LL * @{ */ @@ -539,6 +542,7 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_ /** * @} */ +#endif /* SPI_I2S_SUPPORT */ #endif /* defined (SPI1) || defined (SPI3) */ diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_utils.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_utils.c index d6fbf7db00..c0a7af3844 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_utils.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_ll_utils.c @@ -160,7 +160,7 @@ uint32_t LL_GetSystemCoreClock(void) } -#if defined(STM32WL3XX) +#if defined(STM32WL3XX) || defined(STM32WL3RX) /** * @brief This function set the HSE XTAL frequency expressed in Hz. * @param freq HSE XTAL frequency expressed in Hz. @@ -209,7 +209,7 @@ uint32_t LL_GetXTALFreq(void) { return HSE_xtalFrequency; } -#endif /* STM32WL3XX */ +#endif /* STM32WL3XX || STM32WL3RX */ /** * @} diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 31e488d1cc..53c59791e4 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -23,7 +23,7 @@ * STM32WB0: 1.4.0 * STM32WBA: 1.8.0 * STM32WL: 1.4.0 - * STM32WL3: 1.2.0 + * STM32WL3: 1.3.0 Release notes of each STM32YYxx HAL Drivers available here: From 28d4302f43d9792a22cd7492284d68bb00c9b4c5 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 27 Nov 2025 16:01:46 +0100 Subject: [PATCH 04/10] system(wl3): update STM32WL3x CMSIS Drivers to v1.3.0 Included in STM32CubeWL3 FW v1.3.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32WL3x/Include/stm32wl3rx.h | 11511 ++++++++++++++ .../Device/ST/STM32WL3x/Include/stm32wl3x.h | 20 +- .../Device/ST/STM32WL3x/Include/stm32wl3xx.h | 7862 +++++----- .../ST/STM32WL3x/Include/stm32wl3xxxx.h | 12957 ++++++++++++++++ .../Device/ST/STM32WL3x/Release_Notes.html | 70 +- .../Templates/gcc/linker/STM32WL3Rx8_flash.ld | 191 + .../Templates/gcc/linker/STM32WL3RxB_flash.ld | 191 + .../Templates/gcc/linker/stm32wl3rxx_flash.ld | 191 + .../Source/Templates/gcc/startup_stm32wl3rx.s | 251 + .../Source/Templates/gcc/startup_stm32wl3xx.s | 6 +- .../Source/Templates/system_stm32wl3x.c | 12 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 12 files changed, 29279 insertions(+), 3985 deletions(-) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3xxxx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3Rx8_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3RxB_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3rxx_flash.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3rx.s diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h new file mode 100644 index 0000000000..1c3d0029d1 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Include/stm32wl3rx.h @@ -0,0 +1,11511 @@ +/** + ****************************************************************************** + * @file stm32wl3rx.h + * @author MCD Application Team + * @brief CMSIS Cortex Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32wl33 devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32WL3RX_H +#define STM32WL3RX_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32WL3RX + * @{ + */ + + + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ======================================== STM32WL3x Specific Interrupt Numbers =========================================== */ + FLASH_IRQn = 0, /*!< 0 NVM interrupt */ + RCC_IRQn = 1, /*!< 1 RCC interrupt */ + PVD_IRQn = 2, /*!< 2 PVD interrupt */ + I2C1_IRQn = 3, /*!< 3 I2C1 interrupt */ + SPI3_IRQn = 7, /*!< 7 SPI3 interrupt */ + USART1_IRQn = 8, /*!< 8 USART interrupt */ + LPUART1_IRQn = 9, /*!< 9 Low Power UART interrupt */ + TIM2_IRQn = 10, /*!< 10 Timer 2 interrupt */ + RTC_IRQn = 11, /*!< 11 RTC interrupt */ + ADC_IRQn = 12, /*!< 12 ADC interrupt */ + AES_IRQn = 13, /*!< 13 AES interrupt */ + GPIOA_IRQn = 15, /*!< 15 GPIOA interrupt */ + GPIOB_IRQn = 16, /*!< 16 GPIOB interrupt */ + DMA_IRQn = 17, /*!< 17 DMA interrupt */ + MRSUBG_BUSY_IRQn = 20, /*!< 20 MR_SUBG Busy interrupt */ + MRSUBG_IRQn = 21, /*!< 21 MR_SUBG interrupt */ + MRSUBG_TX_RX_SEQUENCE_IRQn = 22, /*!< 22 MR_SUBG TX/RX Sequence interrupt */ + MRSUBG_TIMER_CPU_WKUP_IRQn = 23, /*!< 23 CPU Wakeup interrupt */ + MRSUBG_WKUP_IRQn = 24, /*!< 24 SUBG Wakeup interrupt */ + TIM16_IRQn = 26, /*!< 26 TIM16 interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ +/** @addtogroup Configuration_of_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< CM0PLUS Core Revision r0p1 */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Vector Table Offset Register supported */ +#define __MPU_PRESENT 1 /*!< M0+ provides an MPU */ +#define __FPU_PRESENT 0 /*!< FPU not present */ +/** + * @} + */ + + + /*!< Device Electronic Signature */ +#define PACKAGE_BASE ((uint32_t)0x40001014U) /*!< Package size data register base address */ +#define UID64_BASE ((uint32_t)0x10001EF0U) /*!< 64-bit Unique device Identification */ +#define FLASHSIZE_BASE ((uint32_t)0x40001014U) /*!< Flash size data register base address */ +#define RAMSIZE_BASE ((uint32_t)0x40001014U) /*!< RAM size data register base address */ +#define DEV_ID_BASE ((uint32_t)0x40000000U) /*!< Device version and cut version register base address */ + + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ +#include "system_stm32wl3x.h" /*!< system_stm32wl3x macros and typedefs System util */ + + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Direct memory access controller (DMA) + */ + +typedef struct { /*!< DMA Structure */ + __IO uint32_t ISR; /*!< (@ 0x00000000) Interrupt status register */ + __IO uint32_t IFCR; /*!< (@ 0x00000004) Interrupt flag clear register */ +} DMA_TypeDef; + +typedef struct { + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ + __IO uint32_t RESERVED; +} DMA_Channel_TypeDef; + + + + +/* =========================================================================================================================== */ +/* ================ DMAMUX ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Direct memory access Multiplexer (DMAMUX) + */ + +/** + * @brief DMA Multiplexer + */ +typedef struct { /*!< DMAMUX Structure */ + __IO uint32_t CxCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +} DMAMUX_Channel_TypeDef; + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Cyclic redundancy check calculation unit (CRC) + */ + +typedef struct { /*!< CRC Structure */ + __IO uint32_t DR; /*!< (@ 0x00000000) Data register */ + __IO uint32_t IDR; /*!< (@ 0x00000004) Independent data register */ + __IO uint32_t CR; /*!< (@ 0x00000008) Control register */ + __IO uint32_t RESERVED; + __IO uint32_t INIT; /*!< (@ 0x00000010) Initial CRC value */ + __IO uint32_t POL; /*!< (@ 0x00000014) Polynomial */ +} CRC_TypeDef; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ IWDG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Independent watchdog (IWDG) + */ + +typedef struct { /*!< IWDG Structure */ + __IO uint32_t KR; /*!< (@ 0x00000000) Key register */ + __IO uint32_t PR; /*!< (@ 0x00000004) Prescaler register */ + __IO uint32_t RLR; /*!< (@ 0x00000008) Reload register */ + __IO uint32_t SR; /*!< (@ 0x0000000C) Status register */ + __IO uint32_t WINR; /*!< (@ 0x00000010) Window register */ +} IWDG_TypeDef; /*!< Size = 20 (0x14) */ + + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Inter-integrated circuit (I2C) + */ + +typedef struct { /*!< I2C1 Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ + __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ + __IO uint32_t OAR1; /*!< (@ 0x00000008) Own address register 1 */ + __IO uint32_t OAR2; /*!< (@ 0x0000000C) Own address register 2 */ + __IO uint32_t TIMINGR; /*!< (@ 0x00000010) Timing register */ + __IO uint32_t TIMEOUTR; /*!< (@ 0x00000014) Timeout register */ + __IO uint32_t ISR; /*!< (@ 0x00000018) Interrupt and Status register */ + __IO uint32_t ICR; /*!< (@ 0x0000001C) Interrupt clear register */ + __IO uint32_t PECR; /*!< (@ 0x00000020) PEC register */ + __IO uint32_t RXDR; /*!< (@ 0x00000024) Receive data register */ + __IO uint32_t TXDR; /*!< (@ 0x00000028) Transmit data register */ +} I2C_TypeDef; /*!< Size = 44 (0x2C) */ + + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FLASH (FLASH) + */ + +typedef struct { /*!< FLASH Structure */ + __IO uint32_t COMMAND; /*!< (@ 0x00000000) Command register */ + __IO uint32_t CONFIG; /*!< (@ 0x00000004) Configuration register */ + __IO uint32_t IRQSTAT; /*!< (@ 0x00000008) Interrupt status register */ + __IO uint32_t IRQMASK; /*!< (@ 0x0000000C) Interrupt mask register */ + __IO uint32_t IRQRAW; /*!< (@ 0x00000010) Intertupt raw status register */ + __IO uint32_t SIZE; /*!< (@ 0x00000014) SIZE register */ + __IO uint32_t ADDRESS; /*!< (@ 0x00000018) Address register */ + __IO uint32_t RESERVED[2]; + __IO uint32_t LFSRVAL; /*!< (@ 0x00000024) LFSRVAL register */ + __IO uint32_t RESERVED2[3]; + __IO uint32_t PAGEPROT0; /*!< (@ 0x00000034) Main Flash page protection register 0 */ + __IO uint32_t PAGEPROT1; /*!< (@ 0x00000038) Main Flash page protection register 1 */ + __IO uint32_t RESERVED1; + __IO uint32_t DATA0; /*!< (@ 0x00000040) Data register 0 */ + __IO uint32_t DATA1; /*!< (@ 0x00000044) Data register 1 */ + __IO uint32_t DATA2; /*!< (@ 0x00000048) Data register 2 */ + __IO uint32_t DATA3; /*!< (@ 0x0000004C) Data register 3 */ +} FLASH_TypeDef; /*!< Size = 80 (0x50) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial peripheral interface/Inter-IC sound (SPI) + */ + +typedef struct { /*!< SPI Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ + __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ + __IO uint32_t SR; /*!< (@ 0x00000008) Status register */ + __IO uint32_t DR; /*!< (@ 0x0000000C) Data register */ + __IO uint32_t CRCPR; /*!< (@ 0x00000010) CRC polynomial register */ + __IO uint32_t RXCRCR; /*!< (@ 0x00000014) RX CRC register */ + __IO uint32_t TXCRCR; /*!< (@ 0x00000018) TX CRC register */ + __IO uint32_t I2SCFGR; /*!< (@ 0x0000001C) I2S configuration register */ + __IO uint32_t I2SPR; /*!< (@ 0x00000020) I2S prescaler register */ +} SPI_TypeDef; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ RCC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Reset and clock control (RCC) + */ + +typedef struct{ /*!< RCC Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) CR register */ + __IO uint32_t ICSCR; /*!< (@ 0x00000004) ICSCR register */ + __IO uint32_t CFGR; /*!< (@ 0x00000008) CFGR register */ + __IO uint32_t CSSWCR; /*!< (@ 0x0000000C) CSSWCR register */ + __IO uint32_t KRMR; /*!< (@ 0x00000010) KRMR register */ + __IO uint32_t RESERVED; + __IO uint32_t CIER; /*!< (@ 0x00000018) CIER register */ + __IO uint32_t CIFR; /*!< (@ 0x0000001C) CIFR register */ + __IO uint32_t CSCMDR; /*!< (@ 0x00000020) CSCMDR register */ + __IO uint32_t RESERVED1[3]; + __IO uint32_t AHBRSTR; /*!< (@ 0x00000030) AHBRSTR register */ + __IO uint32_t APB0RSTR; /*!< (@ 0x00000034) APB0RSTR register */ + __IO uint32_t APB1RSTR; /*!< (@ 0x00000038) APB1RSTR register */ + __IO uint32_t RESERVED2; + __IO uint32_t APB2RSTR; /*!< (@ 0x00000040) APB2RSTR register */ + __IO uint32_t RESERVED3[3]; + __IO uint32_t AHBENR; /*!< (@ 0x00000050) AHBENR register */ + __IO uint32_t APB0ENR; /*!< (@ 0x00000054) APB0ENR register */ + __IO uint32_t APB1ENR; /*!< (@ 0x00000058) APB1ENR register */ + __IO uint32_t RESERVED4; + __IO uint32_t APB2ENR; /*!< (@ 0x00000060) APB2ENR register */ + __IO uint32_t RESERVED5[12]; + __IO uint32_t CSR; /*!< (@ 0x00000094) CSR register */ + __IO uint32_t RFSWHSECR;/*!< (@ 0x00000098) RFSWHSECR register */ + __IO uint32_t RFHSECR; /*!< (@ 0x0000009C) RFHSECR register */ + __IO uint32_t AHBSMENR; /*!< (@ 0x000000A0) AHBSMENR register */ + __IO uint32_t APB0SMENR;/*!< (@ 0x000000A4) APB0SMENR register */ + __IO uint32_t APB1SMENR;/*!< (@ 0x000000A8) APB1SMENR register */ +} RCC_TypeDef; /*!< Size = 172 (0xAC) */ + + + +/* =========================================================================================================================== */ +/* ================ PWR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (PWR) + */ + +typedef struct{ /*!< PWR Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) CR1 register */ + __IO uint32_t CR2; /*!< (@ 0x00000004) CR2 register */ + __IO uint32_t IEWU; /*!< (@ 0x00000008) IEWU register */ + __IO uint32_t IWUP; /*!< (@ 0x0000000C) IWUP register */ + __IO uint32_t IWUF; /*!< (@ 0x00000010) IWUF register */ + __IO uint32_t SR2; /*!< (@ 0x00000014) SR2 register */ + __IO uint32_t RESERVED; + __IO uint32_t CR5; /*!< (@ 0x0000001C) CR5 register */ + __IO uint32_t PUCRA; /*!< (@ 0x00000020) PUCRA register */ + __IO uint32_t PDCRA; /*!< (@ 0x00000024) PDCRA register */ + __IO uint32_t PUCRB; /*!< (@ 0x00000028) PUCRB register */ + __IO uint32_t PDCRB; /*!< (@ 0x0000002C) PDCRB register */ + __IO uint32_t EWUA; /*!< (@ 0x00000030) EWUA register */ + __IO uint32_t WUPA; /*!< (@ 0x00000034) WUPA register */ + __IO uint32_t WUFA; /*!< (@ 0x00000038) WUFA register */ + __IO uint32_t RESERVED1; + __IO uint32_t EWUB; /*!< (@ 0x00000040) EWUB register */ + __IO uint32_t WUPB; /*!< (@ 0x00000044) WUPB register */ + __IO uint32_t WUFB; /*!< (@ 0x00000048) WUFB register */ + __IO uint32_t SDWN_WUEN; /*!< (@ 0x0000004C) SDWN_WUEN register */ + __IO uint32_t SDWN_WUPOL;/*!< (@ 0x00000050) SDWN_WUPOL register */ + __IO uint32_t SDWN_WUF; /*!< (@ 0x00000054) SDWN_WUF register */ + __IO uint32_t BOF_TUNE; /*!< (@ 0x00000058) BOF_TUNE register */ + __IO uint32_t RESERVED2[10]; + __IO uint32_t DBGR; /*!< (@ 0x00000084) DBGR register */ + __IO uint32_t EXTSRR; /*!< (@ 0x00000088) EXTSRR register */ + __IO uint32_t RESERVED3; + __IO uint32_t TRIMR; /*!< (@ 0x00000090) TRIMR register */ + __IO uint32_t ENGTRIM; /*!< (@ 0x00000094) ENGTRIM register */ + __IO uint32_t RESERVED4[2]; + __IO uint32_t ENGTRIM2; /*!< (@ 0x000000A0) ENGTRIM register */ +} PWR_TypeDef; /*!< Size = 164 (0xA4) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCFG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System configuration controller (SYSCFG) + */ + +typedef struct { /*!< SYSCFG Structure */ + __IO uint32_t DIE_ID; /*!< (@ 0x00000000) Die ID register */ + __IO uint32_t JTAG_ID; /*!< (@ 0x00000004) JTAG ID register */ + __IO uint32_t I2C_FMP_CTRL; /*!< (@ 0x00000008) I2C Fast-Mode Plus pin capability control register */ + __IO uint32_t IO_DTR; /*!< (@ 0x0000000C) I/O Interrupt detection type register */ + __IO uint32_t IO_IBER; /*!< (@ 0x00000010) I/O Interrupt Edge register */ + __IO uint32_t IO_IEVR; /*!< (@ 0x00000014) I/O Interrupt polarity event register */ + __IO uint32_t IO_IER; /*!< (@ 0x00000018) I/O Interrupt Enable register */ + __IO uint32_t IO_ISCR; /*!< (@ 0x0000001C) I/O Interrupt Status and Clear register */ + __IO uint32_t PWRC_IER; /*!< (@ 0x00000020) Power Controller Interrupt Enable register */ + __IO uint32_t PWRC_ISCR; /*!< (@ 0x00000024) Power Controller Interrupt Status and Clear register */ + __IO uint32_t GPIO_SWA_CTRL; /*!< (@ 0x00000028) I/O analog switch control register */ + __IO uint32_t INTAI_DTR; /*!< (@ 0x0000002C) Internal asynchronous interrupt detection type register */ + __IO uint32_t INTAI_IBER; /*!< (@ 0x00000030) Internal asynchronous interrupt edge register */ + __IO uint32_t INTAI_IEVR; /*!< (@ 0x00000034) Internal asynchronous interrupt polarity event register */ + __IO uint32_t INTAI_IER; /*!< (@ 0x00000038) Internal asynchronous interrupt enable register */ + __IO uint32_t INTAI_ISCR; /*!< (@ 0x0000003C) Internal asynchronous interrupt detection status and clear register */ + __IO uint32_t SR1; /*!< (@ 0x00000040) SYSCFG status register 1 */ +} SYSCFG_TypeDef; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random number generator (RNG) + */ + +typedef struct { /*!< RNG Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) Control register */ + __IO uint32_t SR; /*!< (@ 0x00000004) Status register */ + __IO uint32_t VAL; /*!< (@ 0x00000008) Data register */ +} RNG_TypeDef; /*!< Size = 12 (0xC) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General-purpose I/Os (GPIO) + */ + +typedef struct { /*!< GPIO Structure */ + __IO uint32_t MODER; /*!< (@ 0x00000000) GPIO port mode register */ + __IO uint32_t OTYPER; /*!< (@ 0x00000004) GPIO port output type register */ + __IO uint32_t OSPEEDR; /*!< (@ 0x00000008) GPIO port output speed register */ + __IO uint32_t PUPDR; /*!< (@ 0x0000000C) GPIO port pull-up/pull-down register */ + __IO uint32_t IDR; /*!< (@ 0x00000010) GPIO port input data register */ + __IO uint32_t ODR; /*!< (@ 0x00000014) GPIO port output data register */ + __IO uint32_t BSRR; /*!< (@ 0x00000018) GPIO port bit set/reset register */ + __IO uint32_t LCKR; /*!< (@ 0x0000001C) GPIO port configuration lock register */ + __IO uint32_t AFR[2]; /*!< (@ 0x00000020) GPIO alternate function register */ + __IO uint32_t BRR; /*!< (@ 0x00000028) GPIO bit reset register */ +} GPIO_TypeDef; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ TIM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Advanced-timers (TIM) + */ + +typedef struct { /*!< TIMx Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ + __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ + __IO uint32_t SMCR; /*!< (@ 0x00000008) Slave mode control register */ + __IO uint32_t DIER; /*!< (@ 0x0000000C) DMA/Interrupt enable register */ + __IO uint32_t SR; /*!< (@ 0x00000010) Status register */ + __IO uint32_t EGR; /*!< (@ 0x00000014) Event generation register */ + __IO uint32_t CCMR1; /*!< (@ 0x00000018) Input capture and output compare mode register 1 */ + __IO uint32_t CCMR2; /*!< (@ 0x0000001C) Input capture and output compare mode register 2 */ + __IO uint32_t CCER; /*!< (@ 0x00000020) Capture/compare enable register */ + __IO uint32_t CNT; /*!< (@ 0x00000024) Counter */ + __IO uint32_t PSC; /*!< (@ 0x00000028) Prescaler */ + __IO uint32_t ARR; /*!< (@ 0x0000002C) Auto-reload register */ + __IO uint32_t RCR; /*!< (@ 0x00000030) Repetition counter register */ + __IO uint32_t CCR1; /*!< (@ 0x00000034) Capture/compare register 1 */ + __IO uint32_t CCR2; /*!< (@ 0x00000038) Capture/compare register 2 */ + __IO uint32_t CCR3; /*!< (@ 0x0000003C) Capture/compare register 3 */ + __IO uint32_t CCR4; /*!< (@ 0x00000040) Capture/compare register 4 */ + __IO uint32_t BDTR; /*!< (@ 0x00000044) Break and dead-time register */ + __IO uint32_t DCR; /*!< (@ 0x00000048) DMA control register */ + __IO uint32_t DMAR; /*!< (@ 0x0000004C) DMA address for full transfer */ + __IO uint32_t OR; /*!< (@ 0x00000050) Option register 1 */ + __IO uint32_t RESERVED[3]; + __IO uint32_t AF1; /*!< (@ 0x00000060) TIM alternate function option register 1 */ + __IO uint32_t RESERVED1; + __IO uint32_t TISEL; /*!< (@ 0x00000068) Input selection register */ +} TIM_TypeDef; /*!< Size = 108 (0x6C) */ + + + +/* =========================================================================================================================== */ +/* ================ USART ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal synchronous asynchronous receiver transmitter (USART) + */ + +typedef struct { /*!< USART Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ + __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ + __IO uint32_t CR3; /*!< (@ 0x00000008) Control register 3 */ + __IO uint32_t BRR; /*!< (@ 0x0000000C) Baud rate register */ + __IO uint32_t GTPR; /*!< (@ 0x00000010) Guard time and prescaler register */ + __IO uint32_t RTOR; /*!< (@ 0x00000014) Receiver timeout register */ + __IO uint32_t RQR; /*!< (@ 0x00000018) Request register */ + __IO uint32_t ISR; /*!< (@ 0x0000001C) Interrupt & status register */ + __IO uint32_t ICR; /*!< (@ 0x00000020) Interrupt flag clear register */ + __IO uint32_t RDR; /*!< (@ 0x00000024) Receive data register */ + __IO uint32_t TDR; /*!< (@ 0x00000028) Transmit data register */ + __IO uint32_t PRESC; /*!< (@ 0x0000002C) Prescaler register */ +} USART_TypeDef; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real-time clock (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __IO uint32_t TR; /*!< (@ 0x00000000) Time register */ + __IO uint32_t DR; /*!< (@ 0x00000004) Date register */ + __IO uint32_t CR; /*!< (@ 0x00000008) Control register */ + __IO uint32_t ISR; /*!< (@ 0x0000000C) Initialization and status register */ + __IO uint32_t PRER; /*!< (@ 0x00000010) Prescaler register */ + __IO uint32_t WUTR; /*!< (@ 0x00000014) Wakeup timer register */ + __IO uint32_t RESERVED; + __IO uint32_t ALRMAR; /*!< (@ 0x0000001C) Alarm A register */ + __IO uint32_t RESERVED1; + __IO uint32_t WPR; /*!< (@ 0x00000024) Write protection register */ + __IO uint32_t SSR; /*!< (@ 0x00000028) Sub second register */ + __IO uint32_t SHIFTR; /*!< (@ 0x0000002C) Shift control register */ + __IO uint32_t TSTR; /*!< (@ 0x00000030) Timestamp time register */ + __IO uint32_t TSDR; /*!< (@ 0x00000034) Timestamp date register */ + __IO uint32_t TSSSR; /*!< (@ 0x00000038) Timestamp sub second register */ + __IO uint32_t CALR; /*!< (@ 0x0000003C) Calibration register */ + __IO uint32_t TAMPCR; /*!< (@ 0x00000040) Tamper configuration register */ + __IO uint32_t ALRMASSR; /*!< (@ 0x00000044) Alarm A sub second register */ + __IO uint32_t RESERVED2; + __IO uint32_t OR; /*!< (@ 0x0000004C) Option register */ + __IO uint32_t BKP0R; /*!< (@ 0x00000050) Backup register 0 */ + __IO uint32_t BKP1R; /*!< (@ 0x00000054) Backup register 1 */ +} RTC_TypeDef; /*!< Size = 88 (0x58) */ + + + +/* =========================================================================================================================== */ +/* ================ AES ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Advanced encryption standard hardware accelerator (AES) + */ + +typedef struct { /*!< AES Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) Control Register */ + __IO uint32_t SR; /*!< (@ 0x00000004) Status Register */ + __IO uint32_t DINR; /*!< (@ 0x00000008) Data Input register */ + __IO uint32_t DOUTR; /*!< (@ 0x0000000C) Data Output register */ + __IO uint32_t KEYR0; /*!< (@ 0x00000010) Key register 0 */ + __IO uint32_t KEYR1; /*!< (@ 0x00000014) Key register 1 */ + __IO uint32_t KEYR2; /*!< (@ 0x00000018) Key register 2 */ + __IO uint32_t KEYR3; /*!< (@ 0x0000001C) Key register 3 */ + __IO uint32_t IVR0; /*!< (@ 0x00000020) Initialization vector register 0 */ + __IO uint32_t IVR1; /*!< (@ 0x00000024) Initialization vector register 1 */ + __IO uint32_t IVR2; /*!< (@ 0x00000028) Initialization vector register 2 */ + __IO uint32_t IVR3; /*!< (@ 0x0000002C) Initialization vector register 3 */ + __IO uint32_t KEYR4; /*!< (@ 0x00000030) Key register 4 */ + __IO uint32_t KEYR5; /*!< (@ 0x00000034) Key register 5 */ + __IO uint32_t KEYR6; /*!< (@ 0x00000038) Key register 6 */ + __IO uint32_t KEYR7; /*!< (@ 0x0000003C) Key register 7 */ + __IO uint32_t SUSP0; /*!< (@ 0x00000040) Suspend register 0 */ + __IO uint32_t SUSP1; /*!< (@ 0x00000044) Suspend register 1 */ + __IO uint32_t SUSP2; /*!< (@ 0x00000048) Suspend register 2 */ + __IO uint32_t SUSP3; /*!< (@ 0x0000004C) Suspend register 3 */ + __IO uint32_t SUSP4; /*!< (@ 0x00000050) Suspend register 4 */ + __IO uint32_t SUSP5; /*!< (@ 0x00000054) Suspend register 5 */ + __IO uint32_t SUSP6; /*!< (@ 0x00000058) Suspend register 6 */ + __IO uint32_t SUSP7; /*!< (@ 0x0000005C) Suspend register 7 */ +} AES_TypeDef; /*!< Size = 96 (0x60) */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ADC (ADC) + */ + +typedef struct { /*!< ADC Structure */ + __IO uint32_t VERSION_ID; /*!< (@ 0x00000000) VERSION_ID register */ + __IO uint32_t CONF; /*!< (@ 0x00000004) ADC configuration register */ + __IO uint32_t CTRL; /*!< (@ 0x00000008) ADC control register */ + __IO uint32_t RESERVED[2]; + __IO uint32_t SWITCH; /*!< (@ 0x00000014) ADC switch control for Input Selection */ + __IO uint32_t RESERVED1; + __IO uint32_t DS_CONF; /*!< (@ 0x0000001C) Downsampler configuration register */ + __IO uint32_t SEQ_1; /*!< (@ 0x00000020) ADC regular sequence programming register 1 */ + __IO uint32_t SEQ_2; /*!< (@ 0x00000024) ADC regular sequence programming register 2 */ + __IO uint32_t COMP_1; /*!< (@ 0x00000028) ADC Gain & offset correction values register 1 */ + __IO uint32_t COMP_2; /*!< (@ 0x0000002C) ADC Gain & offset correction values register 2 */ + __IO uint32_t COMP_3; /*!< (@ 0x00000030) ADC Gain & offset correction values register 3 */ + __IO uint32_t COMP_4; /*!< (@ 0x00000034) ADC Gain & offset correction values register 4 */ + __IO uint32_t COMP_SEL; /*!< (@ 0x00000038) ADC Gain & Offset selection values register */ + __IO uint32_t WD_TH; /*!< (@ 0x0000003C) ADC watchdog threshold register register */ + __IO uint32_t WD_CONF; /*!< (@ 0x00000040) ADC watchdog configuration register */ + __IO uint32_t DS_DATAOUT; /*!< (@ 0x00000044) Downsampler Data output register */ + __IO uint32_t RESERVED2; + __IO uint32_t IRQ_STATUS; /*!< (@ 0x0000004C) Interrupt Status register */ + __IO uint32_t IRQ_ENABLE; /*!< (@ 0x00000050) Enable/disable Interrupts */ +} ADC_TypeDef; /*!< Size = 84 (0x54) */ + + + + +/* =========================================================================================================================== */ +/* ================ DBGMCU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MCU debug component (DBGMCU) + */ + +typedef struct{ /*!< DBGMCU Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) CR register */ + __IO uint32_t DBG_APB0_FZ; /*!< (@ 0x00000004) DBG_APB0_FZ register */ + __IO uint32_t DBG_APB1_FZ; /*!< (@ 0x00000008) DBG_APB1_FZ register */ +} DBGMCU_TypeDef; /*!< Size = 12 (0x0C) */ + + + + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Radio + */ + +typedef struct{ /*!< MR_SUBG_RADIO Structure */ + __IO uint32_t RF_FSM0_TIMEOUT; /*!< (@ 0x00000000) RF_FSM0_TIMEOUT register */ + __IO uint32_t RF_FSM1_TIMEOUT; /*!< (@ 0x00000004) RF_FSM1_TIMEOUT register */ + __IO uint32_t RF_FSM2_TIMEOUT; /*!< (@ 0x00000008) RF_FSM2_TIMEOUT register */ + __IO uint32_t RF_FSM3_TIMEOUT; /*!< (@ 0x0000000C) RF_FSM3_TIMEOUT register */ + __IO uint32_t RF_FSM4_TIMEOUT; /*!< (@ 0x00000010) RF_FSM4_TIMEOUT register */ + __IO uint32_t RF_FSM5_TIMEOUT; /*!< (@ 0x00000014) RF_FSM5_TIMEOUT register */ + __IO uint32_t RF_FSM6_TIMEOUT; /*!< (@ 0x00000018) RF_FSM6_TIMEOUT register */ + __IO uint32_t RF_FSM7_TIMEOUT; /*!< (@ 0x0000001C) RF_FSM7_TIMEOUT register */ + __IO uint32_t AFC0_CONFIG; /*!< (@ 0x00000020) AFC0_CONFIG register */ + __IO uint32_t AFC1_CONFIG; /*!< (@ 0x00000024) AFC1_CONFIG register */ + __IO uint32_t AFC2_CONFIG; /*!< (@ 0x00000028) AFC2_CONFIG register */ + __IO uint32_t AFC3_CONFIG; /*!< (@ 0x0000002C) AFC3_CONFIG register */ + __IO uint32_t CLKREC_CTRL0; /*!< (@ 0x00000030) CLKREC_CTRL0 register */ + __IO uint32_t CLKREC_CTRL1; /*!< (@ 0x00000034) CLKREC_CTRL1 register */ + __IO uint32_t DCREM_CTRL0; /*!< (@ 0x00000038) DCREM_CTRL0 register */ + __IO uint32_t DCREM_CTRL1; /*!< (@ 0x0000003C) DCREM_CTRL1 register */ + __IO uint32_t IQC_CTRL0; /*!< (@ 0x00000040) IQC_CTRL0 register */ + __IO uint32_t IQC_CTRL1; /*!< (@ 0x00000044) IQC_CTRL1 register */ + __IO uint32_t IQC_CTRL2; /*!< (@ 0x00000048) IQC_CTRL2 register */ + __IO uint32_t IQC_CTRL3; /*!< (@ 0x0000004C) IQC_CTRL3 register */ + __IO uint32_t RESERVED; + __IO uint32_t AGC0_CTRL; /*!< (@ 0x00000054) AGC0_CTRL register */ + __IO uint32_t AGC1_CTRL; /*!< (@ 0x00000058) AGC1_CTRL register */ + __IO uint32_t AGC2_CTRL; /*!< (@ 0x0000005C) AGC2_CTRL register */ + __IO uint32_t AGC3_CTRL; /*!< (@ 0x00000060) AGC3_CTRL register */ + __IO uint32_t AGC4_CTRL; /*!< (@ 0x00000064) AGC4_CTRL register */ + __IO uint32_t AGC_ATTEN0; /*!< (@ 0x00000068) AGC_ATTEN0 register */ + __IO uint32_t AGC_ATTEN1; /*!< (@ 0x0000006C) AGC_ATTEN1 register */ + __IO uint32_t AGC_ATTEN2; /*!< (@ 0x00000070) AGC_ATTEN2 register */ + __IO uint32_t AGC_ATTEN3; /*!< (@ 0x00000074) AGC_ATTEN3 register */ + __IO uint32_t AGC_ATTEN4; /*!< (@ 0x00000078) AGC_ATTEN4 register */ + __IO uint32_t AGC_ATTEN5; /*!< (@ 0x0000007C) AGC_ATTEN5 register */ + __IO uint32_t AGC_ATTEN6; /*!< (@ 0x00000080) AGC_ATTEN6 register */ + __IO uint32_t AGC_ATTEN7; /*!< (@ 0x00000084) AGC_ATTEN7 register */ + __IO uint32_t AGC_ATTEN8; /*!< (@ 0x00000088) AGC_ATTEN8 register */ + __IO uint32_t AGC_ATTEN9; /*!< (@ 0x0000008C) AGC_ATTEN9 register */ + __IO uint32_t AGC1_ATTEN_TRIM; /*!< (@ 0x00000090) AGC1_ATTEN_TRIM register */ + __IO uint32_t AGC2_ATTEN_TRIM; /*!< (@ 0x00000094) AGC2_ATTEN_TRIM register */ + __IO uint32_t AGC3_ATTEN_TRIM; /*!< (@ 0x00000098) AGC3_ATTEN_TRIM register */ + __IO uint32_t AGC4_ATTEN_TRIM; /*!< (@ 0x0000009C) AGC4_ATTEN_TRIM register */ + __IO uint32_t AGC_PGA_HWTRIM_OUT; /*!< (@ 0x000000A0) AGC_PGA_HWTRIM_OUT register */ + __IO uint32_t RESERVED1; + __IO uint32_t PA_REG; /*!< (@ 0x000000A8) PA_REG register */ + __IO uint32_t PA_HWTRIM_OUT; /*!< (@ 0x000000AC) PA_HWTRIM_OUT register */ + __IO uint32_t RESERVED2[3]; + __IO uint32_t RSSI_FLT; /*!< (@ 0x000000BC) RSSI_FLT register */ + __IO uint32_t RESERVED3[2]; + __IO uint32_t SYNTH2_ANA_ENG; /*!< (@ 0x000000C8) SYNTH2_ANA_ENG register */ + __IO uint32_t RESERVED4[7]; + __IO uint32_t RXADC_HWDELAYTRIM_OUT; /*!< (@ 0x000000E8) RXADC_HWDELAYTRIM_OUT register */ + __IO uint32_t RESERVED5[2]; + __IO uint32_t RX_AAF_HWTRIM_OUT; /*!< (@ 0x000000F4) RX_AAF_HWTRIM_OUT register */ + __IO uint32_t RESERVED6[2]; + __IO uint32_t SINGEN_ANA_ENG; /*!< (@ 0x00000100) SINGEN_ANA_ENG register */ + __IO uint32_t RESERVED7; + __IO uint32_t RF_INFO_OUT; /*!< (@ 0x00000108) RF_INFO_OUT register */ + __IO uint32_t RFANA_PLL_IN; /*!< (@ 0x0000010C) RFANA_PLL_IN register */ + __IO uint32_t RESERVED8[5]; + __IO uint32_t RF_FSM8_TIMEOUT; /*!< (@ 0x00000124) RF_FSM8_TIMEOUT register */ + __IO uint32_t RF_FSM9_TIMEOUT; /*!< (@ 0x00000128) RF_FSM9_TIMEOUT register */ + __IO uint32_t RF_FSM10_TIMEOUT; /*!< (@ 0x0000012C) RF_FSM10_TIMEOUT register */ + __IO uint32_t RESERVED9[5]; + __IO uint32_t SUBG_DIG_CTRL0; /*!< (@ 0x00000144) SUBG_DIG_CTRL0 register */ +} MR_SUBG_RADIO_TypeDef; /*!< Size = 328 (0x148) */ + + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_STATIC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Static + */ + +typedef struct{ /*!< MR_SUBG_GLOB_STATIC Structure */ + __IO uint32_t PCKT_CONFIG; /*!< (@ 0x00000000) PCKT_CONFIG register */ + __IO uint32_t SYNC; /*!< (@ 0x00000004) SYNC register */ + __IO uint32_t SEC_SYNC; /*!< (@ 0x00000008) SEC_SYNC register */ + __IO uint32_t CRC_INIT; /*!< (@ 0x0000000C) CRC_INIT register */ + __IO uint32_t PCKT_CTRL; /*!< (@ 0x00000010) PCKT_CTRL register */ + __IO uint32_t DATABUFFER0_PTR; /*!< (@ 0x00000014) DATABUFFER0_PTR register */ + __IO uint32_t DATABUFFER1_PTR; /*!< (@ 0x00000018) DATABUFFER1_PTR register */ + __IO uint32_t DATABUFFER_SIZE; /*!< (@ 0x0000001C) DATABUFFER_SIZE register */ + __IO uint32_t PA_LEVEL_3_0; /*!< (@ 0x00000020) PA_LEVEL_3_0 register */ + __IO uint32_t PA_LEVEL_7_4; /*!< (@ 0x00000024) PA_LEVEL_7_4 register */ + __IO uint32_t PA_CONFIG; /*!< (@ 0x00000028) PA_CONFIG register */ + __IO uint32_t IF_CTRL; /*!< (@ 0x0000002C) IF_CTRL register */ + __IO uint32_t AS_QI_CTRL; /*!< (@ 0x00000030) AS_QI_CTRL register */ + __IO uint32_t IQC_CONFIG; /*!< (@ 0x00000034) IQC_CONFIG register */ + __IO uint32_t DSSS_CTRL; /*!< (@ 0x00000038) DSSS_CTRL register */ +} MR_SUBG_GLOB_STATIC_TypeDef; /*!< Size = 60 (0x3C) */ + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_DYNAMIC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Dynamic + */ + +typedef struct{ /*!< MR_SUBG_GLOB_DYNAMIC Structure */ + __IO uint32_t PCKTLEN_CONFIG; /*!< (@ 0x00000000) PCKTLEN_CONFIG register */ + __IO uint32_t MOD0_CONFIG; /*!< (@ 0x00000004) MOD0_CONFIG register */ + __IO uint32_t MOD1_CONFIG; /*!< (@ 0x00000008) MOD1_CONFIG register */ + __IO uint32_t SYNTH_FREQ; /*!< (@ 0x0000000C) SYNTH_FREQ register */ + __IO uint32_t VCO_CAL_CONFIG; /*!< (@ 0x00000010) VCO_CAL_CONFIG register */ + __IO uint32_t RX_TIMER; /*!< (@ 0x00000014) RX_TIMER register */ + __IO uint32_t DATABUFFER_THR; /*!< (@ 0x00000018) DATABUFFER_THR register */ + __IO uint32_t RFSEQ_IRQ_ENABLE; /*!< (@ 0x0000001C) RFSEQ_IRQ_ENABLE register */ + __IO uint32_t ADDITIONAL_CTRL; /*!< (@ 0x00000020) ADDITIONAL_CTRL register */ + __IO uint32_t FAST_RX_TIMER; /*!< (@ 0x00000024) FAST_RX_TIMER register */ + __IO uint32_t COMMAND; /*!< (@ 0x00000028) COMMAND register */ +} MR_SUBG_GLOB_DYNAMIC_TypeDef; /*!< Size = 44 (0x2C) */ + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_STATUS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Status + */ + +typedef struct{ /*!< MR_SUBG_GLOB_STATUS Structure */ + __IO uint32_t RFSEQ_IRQ_STATUS; /*!< (@ 0x00000000) RFSEQ_IRQ_STATUS register */ + __IO uint32_t RFSEQ_STATUS_DETAIL; /*!< (@ 0x00000004) RFSEQ_STATUS_DETAIL register */ + __IO uint32_t RADIO_FSM_INFO; /*!< (@ 0x00000008) RADIO_FSM_INFO register */ + __IO uint32_t RX_INDICATOR; /*!< (@ 0x0000000C) RX_INDICATOR register */ + __IO uint32_t RX_INFO_REG; /*!< (@ 0x00000010) RX_INFO_REG register */ + __IO uint32_t RX_CRC_REG; /*!< (@ 0x00000014) RX_CRC_REG register */ + __IO uint32_t QI_INFO; /*!< (@ 0x00000018) QI_INFO register */ + __IO uint32_t DATABUFFER_INFO; /*!< (@ 0x0000001C) DATABUFFER_INFO register */ + __IO uint32_t TIME_CAPTURE; /*!< (@ 0x00000020) TIME_CAPTURE register */ + __IO uint32_t IQC_CORRECTION_OUT; /*!< (@ 0x00000024) IQC_CORRECTION_OUT register */ + __IO uint32_t PA_SAFEASK_OUT; /*!< (@ 0x00000028) PA_SAFEASK_OUT register */ + __IO uint32_t VCO_CALIB_OUT; /*!< (@ 0x0000002C) VCO_CALIB_OUT register */ + __IO uint32_t SEQ_INFO; /*!< (@ 0x00000030) SEQ_INFO register */ + __IO uint32_t SEQ_EVENT_STATUS; /*!< (@ 0x00000034) SEQ_EVENT_STATUS register */ +} MR_SUBG_GLOB_STATUS_TypeDef; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_MISC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Misc + */ + +typedef struct{ /*!< MR_SUBG_GLOB_MISC Structure */ + __IO uint32_t RFIP_VERSION; /*!< (@ 0x00000000) RFIP_VERSION register */ + __IO uint32_t RRM_UDRA_CTRL; /*!< (@ 0x00000004) RRM_UDRA_CTRL register */ + __IO uint32_t SEQUENCER_CTRL; /*!< (@ 0x00000008) SEQUENCER_CTRL register */ + __IO uint32_t ABSOLUTE_TIME; /*!< (@ 0x0000000C) ABSOLUTE_TIME register */ + __IO uint32_t SCM_COUNTER_VAL; /*!< (@ 0x00000010) SCM_COUNTER_VAL register */ + __IO uint32_t SCM_MIN_MAX; /*!< (@ 0x00000014) SCM_MIN_MAX register */ + __IO uint32_t WAKEUP_IRQ_STATUS; /*!< (@ 0x00000018) WAKEUP_IRQ_STATUS register */ +} MR_SUBG_GLOB_MISC_TypeDef; /*!< Size = 28 (0x1C) */ + + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_RETAINED ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Retained + */ + +typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */ + __IO uint32_t RFIP_WAKEUPTIME; /*!< (@ 0x00000000) RFIP_WAKEUPTIME register */ + __IO uint32_t CPU_WAKEUPTIME; /*!< (@ 0x00000004) CPU_WAKEUPTIME register */ + __IO uint32_t WAKEUP_CTRL; /*!< (@ 0x00000008) WAKEUP_CTRL register */ + __IO uint32_t RRM_CMDLIST_PTR; /*!< (@ 0x0000000C) RRM_CMDLIST_PTR register */ + __IO uint32_t SEQ_GLOBALTABLE_PTR; /*!< (@ 0x00000010) SEQ_GLOBALTABLE_PTR register */ +} MR_SUBG_GLOB_RETAINED_TypeDef; /*!< Size = 20 (0x14) */ + + + + + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ +#define FLASH_BASE (0x10040000UL) /*!< Main FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + + +/*!< System Memory, OTP bytes */ + +/* Base addresses */ +#define SYSTEM_MEMORY_BASE (0x10000000UL) /*!< System Memory : 6KB (0x10000000 – 0x100017FF) */ +#define OTP_AREA_BASE (0x10001800UL) /*!< OTP area : 1kB (0x10001800 – 0x10001BFF) */ + +#define SRAM0_BASE SRAM_BASE /*!< SRAM0 (16 KB) base address */ +#define SRAM1_BASE (SRAM_BASE + 0x00004000UL) /*!< SRAM1 (16 KB) base address */ + +/* End addresses */ +#define SRAM0_END_ADDR (0x20003FFFUL) /*!< RAM0 : 16KB (0x20000000 – 0x20003FFF) */ +#define SRAM1_END_ADDR (0x20007FFFUL) /*!< RAM1 : 16KB (0x20004000 – 0x20007FFF) */ + +#define SYSTEM_MEMORY_END_ADDR (0x100017FFUL) /*!< System Memory : 6KB (0x10000000 – 0x100017FF) */ +#define OTP_AREA_END_ADDR (0x10001BFFUL) /*!< OTP area : 1KB (0x10001800 – 0x10001BFF) */ + +/*!< Peripheral memory map */ +#define APB0PERIPH_BASE PERIPH_BASE +#define APB1PERIPH_BASE (PERIPH_BASE + 0x01000000LU) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x08000000LU) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x09000000LU) + + +/*!< APB0 peripherals */ +#define SYSCFG_BASE (APB0PERIPH_BASE + 0x0000UL) +#define FLASH_R_BASE (APB0PERIPH_BASE + 0x1000UL) +#define TIM2_BASE (APB0PERIPH_BASE + 0x2000UL) +#define IWDG_BASE (APB0PERIPH_BASE + 0x3000UL) +#define RTC_BASE (APB0PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB0PERIPH_BASE + 0x5000UL) +#define DBGMCU_BASE (APB0PERIPH_BASE + 0x8000UL) + + +/*!< APB1 peripherals */ +#define I2C1_BASE (APB1PERIPH_BASE + 0x0000UL) +#define USART1_BASE (APB1PERIPH_BASE + 0x4000UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x5000UL) +#define ADC1_BASE (APB1PERIPH_BASE + 0x6000UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x7000UL) + +/*!< AHB peripherals */ +#define GPIOA_BASE (AHBPERIPH_BASE + 0x000000UL) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x100000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x200000UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x400000UL) +#define PWR_BASE (AHBPERIPH_BASE + 0x500000UL) +#define RNG_BASE (AHBPERIPH_BASE + 0x600000UL) +#define DMA1_BASE (AHBPERIPH_BASE + 0x700000UL) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x800000UL) +#define AES_BASE (AHBPERIPH_BASE + 0x900000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) + +/*!< APB2 peripherals */ +#define MR_SUBG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define MR_SUBG_RADIO_BASE (MR_SUBG_BASE + 0x0000UL) +#define MR_SUBG_GLOB_STATIC_BASE (MR_SUBG_BASE + 0x0400UL) +#define MR_SUBG_GLOB_DYNAMIC_BASE (MR_SUBG_BASE + 0x0500UL) +#define MR_SUBG_GLOB_STATUS_BASE (MR_SUBG_BASE + 0x0600UL) +#define MR_SUBG_GLOB_MISC_BASE (MR_SUBG_BASE + 0x0700UL) +#define MR_SUBG_GLOB_RETAINED_BASE (MR_SUBG_BASE + 0x0780UL) + + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + +/* Peripherals available on APB0 bus */ +#define SYSCFG ((SYSCFG_TypeDef*) SYSCFG_BASE) +#define FLASH ((FLASH_TypeDef*) FLASH_R_BASE) +#define TIM2 ((TIM_TypeDef*) TIM2_BASE) +#define IWDG ((IWDG_TypeDef*) IWDG_BASE) +#define RTC ((RTC_TypeDef*) RTC_BASE) +#define TIM16 ((TIM_TypeDef*) TIM16_BASE) +#define DBGMCU ((DBGMCU_TypeDef*) DBGMCU_BASE) + +/* Peripherals available on APB1 bus */ +#define I2C1 ((I2C_TypeDef*) I2C1_BASE) +#define USART1 ((USART_TypeDef*) USART1_BASE) +#define LPUART1 ((USART_TypeDef*) LPUART1_BASE) +#define ADC1 ((ADC_TypeDef*) ADC1_BASE) +#define SPI3 ((SPI_TypeDef*) SPI3_BASE) + +/* Peripherals available on AHB bus */ +#define GPIOA ((GPIO_TypeDef*) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef*) GPIOB_BASE) +#define CRC ((CRC_TypeDef*) CRC_BASE) +#define RCC ((RCC_TypeDef*) RCC_BASE) +#define PWR ((PWR_TypeDef*) PWR_BASE) +#define RNG ((RNG_TypeDef*) RNG_BASE) +#define DMA1 ((DMA_TypeDef*) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define AES ((AES_TypeDef*) AES_BASE) + +/* Peripherals available on APB2 bus */ +#define MR_SUBG_RADIO ((MR_SUBG_RADIO_TypeDef*) MR_SUBG_RADIO_BASE) +#define MR_SUBG_GLOB_STATIC ((MR_SUBG_GLOB_STATIC_TypeDef*) MR_SUBG_GLOB_STATIC_BASE) +#define MR_SUBG_GLOB_DYNAMIC ((MR_SUBG_GLOB_DYNAMIC_TypeDef*) MR_SUBG_GLOB_DYNAMIC_BASE) +#define MR_SUBG_GLOB_STATUS ((MR_SUBG_GLOB_STATUS_TypeDef*) MR_SUBG_GLOB_STATUS_BASE) +#define MR_SUBG_GLOB_MISC ((MR_SUBG_GLOB_MISC_TypeDef*) MR_SUBG_GLOB_MISC_BASE) +#define MR_SUBG_GLOB_RETAINED ((MR_SUBG_GLOB_RETAINED_TypeDef*) MR_SUBG_GLOB_RETAINED_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* ============================================================================================================================*/ +/*===================== SYSCFG =====================*/ +/* ============================================================================================================================*/ + +/* ===================================================== DIE_ID =====================================================*/ +#define SYSCFG_DIE_ID_PRODUCT_Pos (8UL) /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Direct memory access controller (DMA) + */ + +typedef struct { /*!< DMA Structure */ + __IO uint32_t ISR; /*!< (@ 0x00000000) Interrupt status register */ + __IO uint32_t IFCR; /*!< (@ 0x00000004) Interrupt flag clear register */ +} DMA_TypeDef; + +typedef struct { + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ + __IO uint32_t RESERVED; +} DMA_Channel_TypeDef; + + + + +/* =========================================================================================================================== */ +/* ================ DMAMUX ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Direct memory access Multiplexer (DMAMUX) + */ + +/** + * @brief DMA Multiplexer + */ +typedef struct { /*!< DMAMUX Structure */ + __IO uint32_t CxCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +} DMAMUX_Channel_TypeDef; + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Cyclic redundancy check calculation unit (CRC) + */ + +typedef struct { /*!< CRC Structure */ + __IO uint32_t DR; /*!< (@ 0x00000000) Data register */ + __IO uint32_t IDR; /*!< (@ 0x00000004) Independent data register */ + __IO uint32_t CR; /*!< (@ 0x00000008) Control register */ + __IO uint32_t RESERVED; + __IO uint32_t INIT; /*!< (@ 0x00000010) Initial CRC value */ + __IO uint32_t POL; /*!< (@ 0x00000014) Polynomial */ +} CRC_TypeDef; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ IWDG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Independent watchdog (IWDG) + */ + +typedef struct { /*!< IWDG Structure */ + __IO uint32_t KR; /*!< (@ 0x00000000) Key register */ + __IO uint32_t PR; /*!< (@ 0x00000004) Prescaler register */ + __IO uint32_t RLR; /*!< (@ 0x00000008) Reload register */ + __IO uint32_t SR; /*!< (@ 0x0000000C) Status register */ + __IO uint32_t WINR; /*!< (@ 0x00000010) Window register */ +} IWDG_TypeDef; /*!< Size = 20 (0x14) */ + + +/* =========================================================================================================================== */ +/* ================ I2C ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Inter-integrated circuit (I2C) + */ + +typedef struct { /*!< I2C1 Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ + __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ + __IO uint32_t OAR1; /*!< (@ 0x00000008) Own address register 1 */ + __IO uint32_t OAR2; /*!< (@ 0x0000000C) Own address register 2 */ + __IO uint32_t TIMINGR; /*!< (@ 0x00000010) Timing register */ + __IO uint32_t TIMEOUTR; /*!< (@ 0x00000014) Timeout register */ + __IO uint32_t ISR; /*!< (@ 0x00000018) Interrupt and Status register */ + __IO uint32_t ICR; /*!< (@ 0x0000001C) Interrupt clear register */ + __IO uint32_t PECR; /*!< (@ 0x00000020) PEC register */ + __IO uint32_t RXDR; /*!< (@ 0x00000024) Receive data register */ + __IO uint32_t TXDR; /*!< (@ 0x00000028) Transmit data register */ +} I2C_TypeDef; /*!< Size = 44 (0x2C) */ + + + +/* =========================================================================================================================== */ +/* ================ FLASH ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FLASH (FLASH) + */ + +typedef struct { /*!< FLASH Structure */ + __IO uint32_t COMMAND; /*!< (@ 0x00000000) Command register */ + __IO uint32_t CONFIG; /*!< (@ 0x00000004) Configuration register */ + __IO uint32_t IRQSTAT; /*!< (@ 0x00000008) Interrupt status register */ + __IO uint32_t IRQMASK; /*!< (@ 0x0000000C) Interrupt mask register */ + __IO uint32_t IRQRAW; /*!< (@ 0x00000010) Intertupt raw status register */ + __IO uint32_t SIZE; /*!< (@ 0x00000014) SIZE register */ + __IO uint32_t ADDRESS; /*!< (@ 0x00000018) Address register */ + __IO uint32_t RESERVED[2]; + __IO uint32_t LFSRVAL; /*!< (@ 0x00000024) LFSRVAL register */ + __IO uint32_t RESERVED2[3]; + __IO uint32_t PAGEPROT0; /*!< (@ 0x00000034) Main Flash page protection register 0 */ + __IO uint32_t PAGEPROT1; /*!< (@ 0x00000038) Main Flash page protection register 1 */ + __IO uint32_t RESERVED1; + __IO uint32_t DATA0; /*!< (@ 0x00000040) Data register 0 */ + __IO uint32_t DATA1; /*!< (@ 0x00000044) Data register 1 */ + __IO uint32_t DATA2; /*!< (@ 0x00000048) Data register 2 */ + __IO uint32_t DATA3; /*!< (@ 0x0000004C) Data register 3 */ +} FLASH_TypeDef; /*!< Size = 80 (0x50) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial peripheral interface/Inter-IC sound (SPI) + */ + +typedef struct { /*!< SPI Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ + __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ + __IO uint32_t SR; /*!< (@ 0x00000008) Status register */ + __IO uint32_t DR; /*!< (@ 0x0000000C) Data register */ + __IO uint32_t CRCPR; /*!< (@ 0x00000010) CRC polynomial register */ + __IO uint32_t RXCRCR; /*!< (@ 0x00000014) RX CRC register */ + __IO uint32_t TXCRCR; /*!< (@ 0x00000018) TX CRC register */ + __IO uint32_t I2SCFGR; /*!< (@ 0x0000001C) I2S configuration register */ + __IO uint32_t I2SPR; /*!< (@ 0x00000020) I2S prescaler register */ +} SPI_TypeDef; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ RCC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Reset and clock control (RCC) + */ + +typedef struct{ /*!< RCC Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) CR register */ + __IO uint32_t ICSCR; /*!< (@ 0x00000004) ICSCR register */ + __IO uint32_t CFGR; /*!< (@ 0x00000008) CFGR register */ + __IO uint32_t CSSWCR; /*!< (@ 0x0000000C) CSSWCR register */ + __IO uint32_t KRMR; /*!< (@ 0x00000010) KRMR register */ + __IO uint32_t RESERVED; + __IO uint32_t CIER; /*!< (@ 0x00000018) CIER register */ + __IO uint32_t CIFR; /*!< (@ 0x0000001C) CIFR register */ + __IO uint32_t CSCMDR; /*!< (@ 0x00000020) CSCMDR register */ + __IO uint32_t RESERVED1[3]; + __IO uint32_t AHBRSTR; /*!< (@ 0x00000030) AHBRSTR register */ + __IO uint32_t APB0RSTR; /*!< (@ 0x00000034) APB0RSTR register */ + __IO uint32_t APB1RSTR; /*!< (@ 0x00000038) APB1RSTR register */ + __IO uint32_t RESERVED2; + __IO uint32_t APB2RSTR; /*!< (@ 0x00000040) APB2RSTR register */ + __IO uint32_t RESERVED3[3]; + __IO uint32_t AHBENR; /*!< (@ 0x00000050) AHBENR register */ + __IO uint32_t APB0ENR; /*!< (@ 0x00000054) APB0ENR register */ + __IO uint32_t APB1ENR; /*!< (@ 0x00000058) APB1ENR register */ + __IO uint32_t RESERVED4; + __IO uint32_t APB2ENR; /*!< (@ 0x00000060) APB2ENR register */ + __IO uint32_t RESERVED5[12]; + __IO uint32_t CSR; /*!< (@ 0x00000094) CSR register */ + __IO uint32_t RFSWHSECR;/*!< (@ 0x00000098) RFSWHSECR register */ + __IO uint32_t RFHSECR; /*!< (@ 0x0000009C) RFHSECR register */ + __IO uint32_t AHBSMENR; /*!< (@ 0x000000A0) AHBSMENR register */ + __IO uint32_t APB0SMENR;/*!< (@ 0x000000A4) APB0SMENR register */ + __IO uint32_t APB1SMENR;/*!< (@ 0x000000A8) APB1SMENR register */ +} RCC_TypeDef; /*!< Size = 172 (0xAC) */ + + + +/* =========================================================================================================================== */ +/* ================ PWR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (PWR) + */ + +typedef struct{ /*!< PWR Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) CR1 register */ + __IO uint32_t CR2; /*!< (@ 0x00000004) CR2 register */ + __IO uint32_t IEWU; /*!< (@ 0x00000008) IEWU register */ + __IO uint32_t IWUP; /*!< (@ 0x0000000C) IWUP register */ + __IO uint32_t IWUF; /*!< (@ 0x00000010) IWUF register */ + __IO uint32_t SR2; /*!< (@ 0x00000014) SR2 register */ + __IO uint32_t RESERVED; + __IO uint32_t CR5; /*!< (@ 0x0000001C) CR5 register */ + __IO uint32_t PUCRA; /*!< (@ 0x00000020) PUCRA register */ + __IO uint32_t PDCRA; /*!< (@ 0x00000024) PDCRA register */ + __IO uint32_t PUCRB; /*!< (@ 0x00000028) PUCRB register */ + __IO uint32_t PDCRB; /*!< (@ 0x0000002C) PDCRB register */ + __IO uint32_t EWUA; /*!< (@ 0x00000030) EWUA register */ + __IO uint32_t WUPA; /*!< (@ 0x00000034) WUPA register */ + __IO uint32_t WUFA; /*!< (@ 0x00000038) WUFA register */ + __IO uint32_t RESERVED1; + __IO uint32_t EWUB; /*!< (@ 0x00000040) EWUB register */ + __IO uint32_t WUPB; /*!< (@ 0x00000044) WUPB register */ + __IO uint32_t WUFB; /*!< (@ 0x00000048) WUFB register */ + __IO uint32_t SDWN_WUEN; /*!< (@ 0x0000004C) SDWN_WUEN register */ + __IO uint32_t SDWN_WUPOL;/*!< (@ 0x00000050) SDWN_WUPOL register */ + __IO uint32_t SDWN_WUF; /*!< (@ 0x00000054) SDWN_WUF register */ + __IO uint32_t BOF_TUNE; /*!< (@ 0x00000058) BOF_TUNE register */ + __IO uint32_t RESERVED2[10]; + __IO uint32_t DBGR; /*!< (@ 0x00000084) DBGR register */ + __IO uint32_t EXTSRR; /*!< (@ 0x00000088) EXTSRR register */ + __IO uint32_t RESERVED3; + __IO uint32_t TRIMR; /*!< (@ 0x00000090) TRIMR register */ + __IO uint32_t ENGTRIM; /*!< (@ 0x00000094) ENGTRIM register */ + __IO uint32_t RESERVED4[2]; + __IO uint32_t ENGTRIM2; /*!< (@ 0x000000A0) ENGTRIM register */ +} PWR_TypeDef; /*!< Size = 164 (0xA4) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCFG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief System configuration controller (SYSCFG) + */ + +typedef struct { /*!< SYSCFG Structure */ + __IO uint32_t DIE_ID; /*!< (@ 0x00000000) Die ID register */ + __IO uint32_t JTAG_ID; /*!< (@ 0x00000004) JTAG ID register */ + __IO uint32_t I2C_FMP_CTRL; /*!< (@ 0x00000008) I2C Fast-Mode Plus pin capability control register */ + __IO uint32_t IO_DTR; /*!< (@ 0x0000000C) I/O Interrupt detection type register */ + __IO uint32_t IO_IBER; /*!< (@ 0x00000010) I/O Interrupt Edge register */ + __IO uint32_t IO_IEVR; /*!< (@ 0x00000014) I/O Interrupt polarity event register */ + __IO uint32_t IO_IER; /*!< (@ 0x00000018) I/O Interrupt Enable register */ + __IO uint32_t IO_ISCR; /*!< (@ 0x0000001C) I/O Interrupt Status and Clear register */ + __IO uint32_t PWRC_IER; /*!< (@ 0x00000020) Power Controller Interrupt Enable register */ + __IO uint32_t PWRC_ISCR; /*!< (@ 0x00000024) Power Controller Interrupt Status and Clear register */ + __IO uint32_t GPIO_SWA_CTRL; /*!< (@ 0x00000028) I/O analog switch control register */ + __IO uint32_t INTAI_DTR; /*!< (@ 0x0000002C) Internal asynchronous interrupt detection type register */ + __IO uint32_t INTAI_IBER; /*!< (@ 0x00000030) Internal asynchronous interrupt edge register */ + __IO uint32_t INTAI_IEVR; /*!< (@ 0x00000034) Internal asynchronous interrupt polarity event register */ + __IO uint32_t INTAI_IER; /*!< (@ 0x00000038) Internal asynchronous interrupt enable register */ + __IO uint32_t INTAI_ISCR; /*!< (@ 0x0000003C) Internal asynchronous interrupt detection status and clear register */ + __IO uint32_t SR1; /*!< (@ 0x00000040) SYSCFG status register 1 */ +} SYSCFG_TypeDef; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random number generator (RNG) + */ + +typedef struct { /*!< RNG Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) Control register */ + __IO uint32_t SR; /*!< (@ 0x00000004) Status register */ + __IO uint32_t VAL; /*!< (@ 0x00000008) Data register */ +} RNG_TypeDef; /*!< Size = 12 (0xC) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General-purpose I/Os (GPIO) + */ + +typedef struct { /*!< GPIO Structure */ + __IO uint32_t MODER; /*!< (@ 0x00000000) GPIO port mode register */ + __IO uint32_t OTYPER; /*!< (@ 0x00000004) GPIO port output type register */ + __IO uint32_t OSPEEDR; /*!< (@ 0x00000008) GPIO port output speed register */ + __IO uint32_t PUPDR; /*!< (@ 0x0000000C) GPIO port pull-up/pull-down register */ + __IO uint32_t IDR; /*!< (@ 0x00000010) GPIO port input data register */ + __IO uint32_t ODR; /*!< (@ 0x00000014) GPIO port output data register */ + __IO uint32_t BSRR; /*!< (@ 0x00000018) GPIO port bit set/reset register */ + __IO uint32_t LCKR; /*!< (@ 0x0000001C) GPIO port configuration lock register */ + __IO uint32_t AFR[2]; /*!< (@ 0x00000020) GPIO alternate function register */ + __IO uint32_t BRR; /*!< (@ 0x00000028) GPIO bit reset register */ +} GPIO_TypeDef; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ TIM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Advanced-timers (TIM) + */ + +typedef struct { /*!< TIMx Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ + __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ + __IO uint32_t SMCR; /*!< (@ 0x00000008) Slave mode control register */ + __IO uint32_t DIER; /*!< (@ 0x0000000C) DMA/Interrupt enable register */ + __IO uint32_t SR; /*!< (@ 0x00000010) Status register */ + __IO uint32_t EGR; /*!< (@ 0x00000014) Event generation register */ + __IO uint32_t CCMR1; /*!< (@ 0x00000018) Input capture and output compare mode register 1 */ + __IO uint32_t CCMR2; /*!< (@ 0x0000001C) Input capture and output compare mode register 2 */ + __IO uint32_t CCER; /*!< (@ 0x00000020) Capture/compare enable register */ + __IO uint32_t CNT; /*!< (@ 0x00000024) Counter */ + __IO uint32_t PSC; /*!< (@ 0x00000028) Prescaler */ + __IO uint32_t ARR; /*!< (@ 0x0000002C) Auto-reload register */ + __IO uint32_t RCR; /*!< (@ 0x00000030) Repetition counter register */ + __IO uint32_t CCR1; /*!< (@ 0x00000034) Capture/compare register 1 */ + __IO uint32_t CCR2; /*!< (@ 0x00000038) Capture/compare register 2 */ + __IO uint32_t CCR3; /*!< (@ 0x0000003C) Capture/compare register 3 */ + __IO uint32_t CCR4; /*!< (@ 0x00000040) Capture/compare register 4 */ + __IO uint32_t BDTR; /*!< (@ 0x00000044) Break and dead-time register */ + __IO uint32_t DCR; /*!< (@ 0x00000048) DMA control register */ + __IO uint32_t DMAR; /*!< (@ 0x0000004C) DMA address for full transfer */ + __IO uint32_t OR; /*!< (@ 0x00000050) Option register 1 */ + __IO uint32_t RESERVED[3]; + __IO uint32_t AF1; /*!< (@ 0x00000060) TIM alternate function option register 1 */ + __IO uint32_t RESERVED1; + __IO uint32_t TISEL; /*!< (@ 0x00000068) Input selection register */ +} TIM_TypeDef; /*!< Size = 108 (0x6C) */ + + + +/* =========================================================================================================================== */ +/* ================ USART ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal synchronous asynchronous receiver transmitter (USART) + */ + +typedef struct { /*!< USART Structure */ + __IO uint32_t CR1; /*!< (@ 0x00000000) Control register 1 */ + __IO uint32_t CR2; /*!< (@ 0x00000004) Control register 2 */ + __IO uint32_t CR3; /*!< (@ 0x00000008) Control register 3 */ + __IO uint32_t BRR; /*!< (@ 0x0000000C) Baud rate register */ + __IO uint32_t GTPR; /*!< (@ 0x00000010) Guard time and prescaler register */ + __IO uint32_t RTOR; /*!< (@ 0x00000014) Receiver timeout register */ + __IO uint32_t RQR; /*!< (@ 0x00000018) Request register */ + __IO uint32_t ISR; /*!< (@ 0x0000001C) Interrupt & status register */ + __IO uint32_t ICR; /*!< (@ 0x00000020) Interrupt flag clear register */ + __IO uint32_t RDR; /*!< (@ 0x00000024) Receive data register */ + __IO uint32_t TDR; /*!< (@ 0x00000028) Transmit data register */ + __IO uint32_t PRESC; /*!< (@ 0x0000002C) Prescaler register */ +} USART_TypeDef; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real-time clock (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __IO uint32_t TR; /*!< (@ 0x00000000) Time register */ + __IO uint32_t DR; /*!< (@ 0x00000004) Date register */ + __IO uint32_t CR; /*!< (@ 0x00000008) Control register */ + __IO uint32_t ISR; /*!< (@ 0x0000000C) Initialization and status register */ + __IO uint32_t PRER; /*!< (@ 0x00000010) Prescaler register */ + __IO uint32_t WUTR; /*!< (@ 0x00000014) Wakeup timer register */ + __IO uint32_t RESERVED; + __IO uint32_t ALRMAR; /*!< (@ 0x0000001C) Alarm A register */ + __IO uint32_t RESERVED1; + __IO uint32_t WPR; /*!< (@ 0x00000024) Write protection register */ + __IO uint32_t SSR; /*!< (@ 0x00000028) Sub second register */ + __IO uint32_t SHIFTR; /*!< (@ 0x0000002C) Shift control register */ + __IO uint32_t TSTR; /*!< (@ 0x00000030) Timestamp time register */ + __IO uint32_t TSDR; /*!< (@ 0x00000034) Timestamp date register */ + __IO uint32_t TSSSR; /*!< (@ 0x00000038) Timestamp sub second register */ + __IO uint32_t CALR; /*!< (@ 0x0000003C) Calibration register */ + __IO uint32_t TAMPCR; /*!< (@ 0x00000040) Tamper configuration register */ + __IO uint32_t ALRMASSR; /*!< (@ 0x00000044) Alarm A sub second register */ + __IO uint32_t RESERVED2; + __IO uint32_t OR; /*!< (@ 0x0000004C) Option register */ + __IO uint32_t BKP0R; /*!< (@ 0x00000050) Backup register 0 */ + __IO uint32_t BKP1R; /*!< (@ 0x00000054) Backup register 1 */ +} RTC_TypeDef; /*!< Size = 88 (0x58) */ + + + +/* =========================================================================================================================== */ +/* ================ AES ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Advanced encryption standard hardware accelerator (AES) + */ + +typedef struct { /*!< AES Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) Control Register */ + __IO uint32_t SR; /*!< (@ 0x00000004) Status Register */ + __IO uint32_t DINR; /*!< (@ 0x00000008) Data Input register */ + __IO uint32_t DOUTR; /*!< (@ 0x0000000C) Data Output register */ + __IO uint32_t KEYR0; /*!< (@ 0x00000010) Key register 0 */ + __IO uint32_t KEYR1; /*!< (@ 0x00000014) Key register 1 */ + __IO uint32_t KEYR2; /*!< (@ 0x00000018) Key register 2 */ + __IO uint32_t KEYR3; /*!< (@ 0x0000001C) Key register 3 */ + __IO uint32_t IVR0; /*!< (@ 0x00000020) Initialization vector register 0 */ + __IO uint32_t IVR1; /*!< (@ 0x00000024) Initialization vector register 1 */ + __IO uint32_t IVR2; /*!< (@ 0x00000028) Initialization vector register 2 */ + __IO uint32_t IVR3; /*!< (@ 0x0000002C) Initialization vector register 3 */ + __IO uint32_t KEYR4; /*!< (@ 0x00000030) Key register 4 */ + __IO uint32_t KEYR5; /*!< (@ 0x00000034) Key register 5 */ + __IO uint32_t KEYR6; /*!< (@ 0x00000038) Key register 6 */ + __IO uint32_t KEYR7; /*!< (@ 0x0000003C) Key register 7 */ + __IO uint32_t SUSP0; /*!< (@ 0x00000040) Suspend register 0 */ + __IO uint32_t SUSP1; /*!< (@ 0x00000044) Suspend register 1 */ + __IO uint32_t SUSP2; /*!< (@ 0x00000048) Suspend register 2 */ + __IO uint32_t SUSP3; /*!< (@ 0x0000004C) Suspend register 3 */ + __IO uint32_t SUSP4; /*!< (@ 0x00000050) Suspend register 4 */ + __IO uint32_t SUSP5; /*!< (@ 0x00000054) Suspend register 5 */ + __IO uint32_t SUSP6; /*!< (@ 0x00000058) Suspend register 6 */ + __IO uint32_t SUSP7; /*!< (@ 0x0000005C) Suspend register 7 */ +} AES_TypeDef; /*!< Size = 96 (0x60) */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ADC (ADC) + */ + +typedef struct { /*!< ADC Structure */ + __IO uint32_t VERSION_ID; /*!< (@ 0x00000000) VERSION_ID register */ + __IO uint32_t CONF; /*!< (@ 0x00000004) ADC configuration register */ + __IO uint32_t CTRL; /*!< (@ 0x00000008) ADC control register */ + __IO uint32_t RESERVED[2]; + __IO uint32_t SWITCH; /*!< (@ 0x00000014) ADC switch control for Input Selection */ + __IO uint32_t RESERVED1; + __IO uint32_t DS_CONF; /*!< (@ 0x0000001C) Downsampler configuration register */ + __IO uint32_t SEQ_1; /*!< (@ 0x00000020) ADC regular sequence programming register 1 */ + __IO uint32_t SEQ_2; /*!< (@ 0x00000024) ADC regular sequence programming register 2 */ + __IO uint32_t COMP_1; /*!< (@ 0x00000028) ADC Gain & offset correction values register 1 */ + __IO uint32_t COMP_2; /*!< (@ 0x0000002C) ADC Gain & offset correction values register 2 */ + __IO uint32_t COMP_3; /*!< (@ 0x00000030) ADC Gain & offset correction values register 3 */ + __IO uint32_t COMP_4; /*!< (@ 0x00000034) ADC Gain & offset correction values register 4 */ + __IO uint32_t COMP_SEL; /*!< (@ 0x00000038) ADC Gain & Offset selection values register */ + __IO uint32_t WD_TH; /*!< (@ 0x0000003C) ADC watchdog threshold register register */ + __IO uint32_t WD_CONF; /*!< (@ 0x00000040) ADC watchdog configuration register */ + __IO uint32_t DS_DATAOUT; /*!< (@ 0x00000044) Downsampler Data output register */ + __IO uint32_t RESERVED2; + __IO uint32_t IRQ_STATUS; /*!< (@ 0x0000004C) Interrupt Status register */ + __IO uint32_t IRQ_ENABLE; /*!< (@ 0x00000050) Enable/disable Interrupts */ +} ADC_TypeDef; /*!< Size = 84 (0x54) */ + + + +#if defined (STM32WL3XX) +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< COMP Structure */ + __IO uint32_t CSR; /*!< (@ 0x00000000) Control and status register */ +} COMP_TypeDef; /*!< Size = 4 (0x04) */ + + + +/* =========================================================================================================================== */ +/* ================ DAC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Digital to Analog Converter (DAC) + */ + +typedef struct { /*!< DAC Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) Control register */ + __IO uint32_t SWTRIGR; /*!< (@ 0x00000004) Software trigger register */ + __IO uint32_t RESERVED[2]; + __IO uint32_t DHR; /*!< (@ 0x00000010) Channel data holding register */ + __IO uint32_t RESERVED1[6]; + __IO uint32_t DOR; /*!< (@ 0x0000002C) Channel data output register */ + __IO uint32_t RESERVED2; + __IO uint32_t SR; /*!< (@ 0x00000034) Status register */ +} DAC_TypeDef; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ LCSC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief LC Sensor Controller (LCSC) + */ + +typedef struct{ /*!< LCSC Structure */ + __IO uint32_t CR0; /*!< (@ 0x00000000) LCSC_CR0 register */ + __IO uint32_t CR1; /*!< (@ 0x00000004) LCSC_CR1 register */ + __IO uint32_t CR2; /*!< (@ 0x00000008) LCSC_CR2 register */ + __IO uint32_t PULSE_CR; /*!< (@ 0x0000000C) LCSC_PULSE_CR register */ + __IO uint32_t ENR; /*!< (@ 0x00000010) LCSC_ENR register */ + __IO uint32_t WHEEL_SR; /*!< (@ 0x00000014) LCSC_WHEEL_SR register */ + __IO uint32_t CONFR; /*!< (@ 0x00000018) LCSC_CONFR register */ + __IO uint32_t COMP_CNT; /*!< (@ 0x0000001C) LCSC_COMP_CNT register */ + __IO uint32_t SR; /*!< (@ 0x00000020) LCSC_SR register */ + __IO uint32_t STAT; /*!< (@ 0x00000024) LCSC_STAT register */ + __IO uint32_t RESERVED[6]; + __IO uint32_t ISR; /*!< (@ 0x00000044) LCSC_ISR register */ +} LCSC_TypeDef; /*!< Size = 72 (0x48) */ + + +#endif /* (STM32WL3XX) */ + +/* =========================================================================================================================== */ +/* ================ DBGMCU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MCU debug component (DBGMCU) + */ + +typedef struct{ /*!< DBGMCU Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) CR register */ + __IO uint32_t DBG_APB0_FZ; /*!< (@ 0x00000004) DBG_APB0_FZ register */ + __IO uint32_t DBG_APB1_FZ; /*!< (@ 0x00000008) DBG_APB1_FZ register */ +} DBGMCU_TypeDef; /*!< Size = 12 (0x0C) */ + + + +#if defined (STM32WL3XX) +/* =========================================================================================================================== */ +/* ================ LCD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Liquid crystal display controller (LCD) + */ + +typedef struct { /*!< LCD Structure */ + __IO uint32_t CR; /*!< (@ 0x00000000) Control register */ + __IO uint32_t FCR; /*!< (@ 0x00000004) Frame control register */ + __IO uint32_t SR; /*!< (@ 0x00000008) Status register */ + __IO uint32_t CLR; /*!< (@ 0x0000000C) Clear register */ + __IO uint32_t RESERVED; + __IO uint32_t RAM_COM0; /*!< (@ 0x00000014) Disaplay Memory COM 0 */ + __IO uint32_t RESERVED1; + __IO uint32_t RAM_COM1; /*!< (@ 0x0000001C) Disaplay Memory COM 1 */ + __IO uint32_t RESERVED2; + __IO uint32_t RAM_COM2; /*!< (@ 0x00000024) Disaplay Memory COM 2 */ + __IO uint32_t RESERVED3; + __IO uint32_t RAM_COM3; /*!< (@ 0x0000002C) Disaplay Memory COM 3 */ + __IO uint32_t RESERVED4; + __IO uint32_t RAM_COM4; /*!< (@ 0x00000034) Disaplay Memory COM 4 */ + __IO uint32_t RESERVED5; + __IO uint32_t RAM_COM5; /*!< (@ 0x0000003C) Disaplay Memory COM 5 */ + __IO uint32_t RESERVED6; + __IO uint32_t RAM_COM6; /*!< (@ 0x00000044) Disaplay Memory COM 6 */ + __IO uint32_t RESERVED7; + __IO uint32_t RAM_COM7; /*!< (@ 0x0000004C) Disaplay Memory COM 7 */ +} LCD_TypeDef; /*!< Size = 80 (0x50) */ + +#endif /* (STM32WL3XX) */ + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Radio + */ + +typedef struct{ /*!< MR_SUBG_RADIO Structure */ + __IO uint32_t RF_FSM0_TIMEOUT; /*!< (@ 0x00000000) RF_FSM0_TIMEOUT register */ + __IO uint32_t RF_FSM1_TIMEOUT; /*!< (@ 0x00000004) RF_FSM1_TIMEOUT register */ + __IO uint32_t RF_FSM2_TIMEOUT; /*!< (@ 0x00000008) RF_FSM2_TIMEOUT register */ + __IO uint32_t RF_FSM3_TIMEOUT; /*!< (@ 0x0000000C) RF_FSM3_TIMEOUT register */ + __IO uint32_t RF_FSM4_TIMEOUT; /*!< (@ 0x00000010) RF_FSM4_TIMEOUT register */ + __IO uint32_t RF_FSM5_TIMEOUT; /*!< (@ 0x00000014) RF_FSM5_TIMEOUT register */ + __IO uint32_t RF_FSM6_TIMEOUT; /*!< (@ 0x00000018) RF_FSM6_TIMEOUT register */ + __IO uint32_t RF_FSM7_TIMEOUT; /*!< (@ 0x0000001C) RF_FSM7_TIMEOUT register */ + __IO uint32_t AFC0_CONFIG; /*!< (@ 0x00000020) AFC0_CONFIG register */ + __IO uint32_t AFC1_CONFIG; /*!< (@ 0x00000024) AFC1_CONFIG register */ + __IO uint32_t AFC2_CONFIG; /*!< (@ 0x00000028) AFC2_CONFIG register */ + __IO uint32_t AFC3_CONFIG; /*!< (@ 0x0000002C) AFC3_CONFIG register */ + __IO uint32_t CLKREC_CTRL0; /*!< (@ 0x00000030) CLKREC_CTRL0 register */ + __IO uint32_t CLKREC_CTRL1; /*!< (@ 0x00000034) CLKREC_CTRL1 register */ + __IO uint32_t DCREM_CTRL0; /*!< (@ 0x00000038) DCREM_CTRL0 register */ + __IO uint32_t DCREM_CTRL1; /*!< (@ 0x0000003C) DCREM_CTRL1 register */ + __IO uint32_t IQC_CTRL0; /*!< (@ 0x00000040) IQC_CTRL0 register */ + __IO uint32_t IQC_CTRL1; /*!< (@ 0x00000044) IQC_CTRL1 register */ + __IO uint32_t IQC_CTRL2; /*!< (@ 0x00000048) IQC_CTRL2 register */ + __IO uint32_t IQC_CTRL3; /*!< (@ 0x0000004C) IQC_CTRL3 register */ + __IO uint32_t RESERVED; + __IO uint32_t AGC0_CTRL; /*!< (@ 0x00000054) AGC0_CTRL register */ + __IO uint32_t AGC1_CTRL; /*!< (@ 0x00000058) AGC1_CTRL register */ + __IO uint32_t AGC2_CTRL; /*!< (@ 0x0000005C) AGC2_CTRL register */ + __IO uint32_t AGC3_CTRL; /*!< (@ 0x00000060) AGC3_CTRL register */ + __IO uint32_t AGC4_CTRL; /*!< (@ 0x00000064) AGC4_CTRL register */ + __IO uint32_t AGC_ATTEN0; /*!< (@ 0x00000068) AGC_ATTEN0 register */ + __IO uint32_t AGC_ATTEN1; /*!< (@ 0x0000006C) AGC_ATTEN1 register */ + __IO uint32_t AGC_ATTEN2; /*!< (@ 0x00000070) AGC_ATTEN2 register */ + __IO uint32_t AGC_ATTEN3; /*!< (@ 0x00000074) AGC_ATTEN3 register */ + __IO uint32_t AGC_ATTEN4; /*!< (@ 0x00000078) AGC_ATTEN4 register */ + __IO uint32_t AGC_ATTEN5; /*!< (@ 0x0000007C) AGC_ATTEN5 register */ + __IO uint32_t AGC_ATTEN6; /*!< (@ 0x00000080) AGC_ATTEN6 register */ + __IO uint32_t AGC_ATTEN7; /*!< (@ 0x00000084) AGC_ATTEN7 register */ + __IO uint32_t AGC_ATTEN8; /*!< (@ 0x00000088) AGC_ATTEN8 register */ + __IO uint32_t AGC_ATTEN9; /*!< (@ 0x0000008C) AGC_ATTEN9 register */ + __IO uint32_t AGC1_ATTEN_TRIM; /*!< (@ 0x00000090) AGC1_ATTEN_TRIM register */ + __IO uint32_t AGC2_ATTEN_TRIM; /*!< (@ 0x00000094) AGC2_ATTEN_TRIM register */ + __IO uint32_t AGC3_ATTEN_TRIM; /*!< (@ 0x00000098) AGC3_ATTEN_TRIM register */ + __IO uint32_t AGC4_ATTEN_TRIM; /*!< (@ 0x0000009C) AGC4_ATTEN_TRIM register */ + __IO uint32_t AGC_PGA_HWTRIM_OUT; /*!< (@ 0x000000A0) AGC_PGA_HWTRIM_OUT register */ + __IO uint32_t RESERVED1; + __IO uint32_t PA_REG; /*!< (@ 0x000000A8) PA_REG register */ + __IO uint32_t PA_HWTRIM_OUT; /*!< (@ 0x000000AC) PA_HWTRIM_OUT register */ + __IO uint32_t RESERVED2[3]; + __IO uint32_t RSSI_FLT; /*!< (@ 0x000000BC) RSSI_FLT register */ + __IO uint32_t RESERVED3[2]; + __IO uint32_t SYNTH2_ANA_ENG; /*!< (@ 0x000000C8) SYNTH2_ANA_ENG register */ + __IO uint32_t RESERVED4[7]; + __IO uint32_t RXADC_HWDELAYTRIM_OUT; /*!< (@ 0x000000E8) RXADC_HWDELAYTRIM_OUT register */ + __IO uint32_t RESERVED5[2]; + __IO uint32_t RX_AAF_HWTRIM_OUT; /*!< (@ 0x000000F4) RX_AAF_HWTRIM_OUT register */ + __IO uint32_t RESERVED6[2]; + __IO uint32_t SINGEN_ANA_ENG; /*!< (@ 0x00000100) SINGEN_ANA_ENG register */ + __IO uint32_t RESERVED7; + __IO uint32_t RF_INFO_OUT; /*!< (@ 0x00000108) RF_INFO_OUT register */ +#if defined (STM32WL3RX) + __IO uint32_t RFANA_PLL_IN; /*!< (@ 0x0000010C) RFANA_PLL_IN register */ + __IO uint32_t RESERVED8[5]; +#else + __IO uint32_t RESERVED8[6]; +#endif /* STM32WL3RX */ + __IO uint32_t RF_FSM8_TIMEOUT; /*!< (@ 0x00000124) RF_FSM8_TIMEOUT register */ + __IO uint32_t RF_FSM9_TIMEOUT; /*!< (@ 0x00000128) RF_FSM9_TIMEOUT register */ + __IO uint32_t RF_FSM10_TIMEOUT; /*!< (@ 0x0000012C) RF_FSM10_TIMEOUT register */ + __IO uint32_t RESERVED9[5]; + __IO uint32_t SUBG_DIG_CTRL0; /*!< (@ 0x00000144) SUBG_DIG_CTRL0 register */ +} MR_SUBG_RADIO_TypeDef; /*!< Size = 328 (0x148) */ + + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_STATIC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Static + */ + +typedef struct{ /*!< MR_SUBG_GLOB_STATIC Structure */ + __IO uint32_t PCKT_CONFIG; /*!< (@ 0x00000000) PCKT_CONFIG register */ + __IO uint32_t SYNC; /*!< (@ 0x00000004) SYNC register */ + __IO uint32_t SEC_SYNC; /*!< (@ 0x00000008) SEC_SYNC register */ + __IO uint32_t CRC_INIT; /*!< (@ 0x0000000C) CRC_INIT register */ + __IO uint32_t PCKT_CTRL; /*!< (@ 0x00000010) PCKT_CTRL register */ + __IO uint32_t DATABUFFER0_PTR; /*!< (@ 0x00000014) DATABUFFER0_PTR register */ + __IO uint32_t DATABUFFER1_PTR; /*!< (@ 0x00000018) DATABUFFER1_PTR register */ + __IO uint32_t DATABUFFER_SIZE; /*!< (@ 0x0000001C) DATABUFFER_SIZE register */ + __IO uint32_t PA_LEVEL_3_0; /*!< (@ 0x00000020) PA_LEVEL_3_0 register */ + __IO uint32_t PA_LEVEL_7_4; /*!< (@ 0x00000024) PA_LEVEL_7_4 register */ + __IO uint32_t PA_CONFIG; /*!< (@ 0x00000028) PA_CONFIG register */ + __IO uint32_t IF_CTRL; /*!< (@ 0x0000002C) IF_CTRL register */ + __IO uint32_t AS_QI_CTRL; /*!< (@ 0x00000030) AS_QI_CTRL register */ + __IO uint32_t IQC_CONFIG; /*!< (@ 0x00000034) IQC_CONFIG register */ + __IO uint32_t DSSS_CTRL; /*!< (@ 0x00000038) DSSS_CTRL register */ +} MR_SUBG_GLOB_STATIC_TypeDef; /*!< Size = 60 (0x3C) */ + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_DYNAMIC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Dynamic + */ + +typedef struct{ /*!< MR_SUBG_GLOB_DYNAMIC Structure */ + __IO uint32_t PCKTLEN_CONFIG; /*!< (@ 0x00000000) PCKTLEN_CONFIG register */ + __IO uint32_t MOD0_CONFIG; /*!< (@ 0x00000004) MOD0_CONFIG register */ + __IO uint32_t MOD1_CONFIG; /*!< (@ 0x00000008) MOD1_CONFIG register */ + __IO uint32_t SYNTH_FREQ; /*!< (@ 0x0000000C) SYNTH_FREQ register */ + __IO uint32_t VCO_CAL_CONFIG; /*!< (@ 0x00000010) VCO_CAL_CONFIG register */ + __IO uint32_t RX_TIMER; /*!< (@ 0x00000014) RX_TIMER register */ + __IO uint32_t DATABUFFER_THR; /*!< (@ 0x00000018) DATABUFFER_THR register */ + __IO uint32_t RFSEQ_IRQ_ENABLE; /*!< (@ 0x0000001C) RFSEQ_IRQ_ENABLE register */ + __IO uint32_t ADDITIONAL_CTRL; /*!< (@ 0x00000020) ADDITIONAL_CTRL register */ + __IO uint32_t FAST_RX_TIMER; /*!< (@ 0x00000024) FAST_RX_TIMER register */ + __IO uint32_t COMMAND; /*!< (@ 0x00000028) COMMAND register */ +} MR_SUBG_GLOB_DYNAMIC_TypeDef; /*!< Size = 44 (0x2C) */ + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_STATUS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Status + */ + +typedef struct{ /*!< MR_SUBG_GLOB_STATUS Structure */ + __IO uint32_t RFSEQ_IRQ_STATUS; /*!< (@ 0x00000000) RFSEQ_IRQ_STATUS register */ + __IO uint32_t RFSEQ_STATUS_DETAIL; /*!< (@ 0x00000004) RFSEQ_STATUS_DETAIL register */ + __IO uint32_t RADIO_FSM_INFO; /*!< (@ 0x00000008) RADIO_FSM_INFO register */ + __IO uint32_t RX_INDICATOR; /*!< (@ 0x0000000C) RX_INDICATOR register */ + __IO uint32_t RX_INFO_REG; /*!< (@ 0x00000010) RX_INFO_REG register */ + __IO uint32_t RX_CRC_REG; /*!< (@ 0x00000014) RX_CRC_REG register */ + __IO uint32_t QI_INFO; /*!< (@ 0x00000018) QI_INFO register */ + __IO uint32_t DATABUFFER_INFO; /*!< (@ 0x0000001C) DATABUFFER_INFO register */ + __IO uint32_t TIME_CAPTURE; /*!< (@ 0x00000020) TIME_CAPTURE register */ + __IO uint32_t IQC_CORRECTION_OUT; /*!< (@ 0x00000024) IQC_CORRECTION_OUT register */ + __IO uint32_t PA_SAFEASK_OUT; /*!< (@ 0x00000028) PA_SAFEASK_OUT register */ + __IO uint32_t VCO_CALIB_OUT; /*!< (@ 0x0000002C) VCO_CALIB_OUT register */ + __IO uint32_t SEQ_INFO; /*!< (@ 0x00000030) SEQ_INFO register */ + __IO uint32_t SEQ_EVENT_STATUS; /*!< (@ 0x00000034) SEQ_EVENT_STATUS register */ +} MR_SUBG_GLOB_STATUS_TypeDef; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_MISC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Misc + */ + +typedef struct{ /*!< MR_SUBG_GLOB_MISC Structure */ + __IO uint32_t RFIP_VERSION; /*!< (@ 0x00000000) RFIP_VERSION register */ + __IO uint32_t RRM_UDRA_CTRL; /*!< (@ 0x00000004) RRM_UDRA_CTRL register */ + __IO uint32_t SEQUENCER_CTRL; /*!< (@ 0x00000008) SEQUENCER_CTRL register */ + __IO uint32_t ABSOLUTE_TIME; /*!< (@ 0x0000000C) ABSOLUTE_TIME register */ + __IO uint32_t SCM_COUNTER_VAL; /*!< (@ 0x00000010) SCM_COUNTER_VAL register */ + __IO uint32_t SCM_MIN_MAX; /*!< (@ 0x00000014) SCM_MIN_MAX register */ + __IO uint32_t WAKEUP_IRQ_STATUS; /*!< (@ 0x00000018) WAKEUP_IRQ_STATUS register */ +} MR_SUBG_GLOB_MISC_TypeDef; /*!< Size = 28 (0x1C) */ + + + +/* =========================================================================================================================== */ +/* ================ MR_SUBG_GLOB_RETAINED ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief MR_SUBG Global Retained + */ + +typedef struct{ /*!< MR_SUBG_GLOB_RETAINED Structure */ + __IO uint32_t RFIP_WAKEUPTIME; /*!< (@ 0x00000000) RFIP_WAKEUPTIME register */ + __IO uint32_t CPU_WAKEUPTIME; /*!< (@ 0x00000004) CPU_WAKEUPTIME register */ + __IO uint32_t WAKEUP_CTRL; /*!< (@ 0x00000008) WAKEUP_CTRL register */ + __IO uint32_t RRM_CMDLIST_PTR; /*!< (@ 0x0000000C) RRM_CMDLIST_PTR register */ + __IO uint32_t SEQ_GLOBALTABLE_PTR; /*!< (@ 0x00000010) SEQ_GLOBALTABLE_PTR register */ +} MR_SUBG_GLOB_RETAINED_TypeDef; /*!< Size = 20 (0x14) */ + + + +#if defined (STM32WL3XX) +/* =========================================================================================================================== */ +/* ================ LPAWUR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low Power Autonomous Wakeup Radio IP + */ + +typedef struct{ /*!< LPAWUR Structure */ + __IO uint32_t FRAME_CONFIG0; /*!< (@ 0x00000000) FRAME_CONFIG0 register */ + __IO uint32_t FRAME_CONFIG1; /*!< (@ 0x00000004) FRAME_CONFIG1 register */ + __IO uint32_t FRAME_SYNC_CONFIG; /*!< (@ 0x00000008) FRAME_SYNC_CONFIG register */ + __IO uint32_t RFIP_CONFIG; /*!< (@ 0x0000000C) RFIP_CONFIG register */ + __IO uint32_t RF_CONFIG; /*!< (@ 0x00000010) RF_CONFIG register */ + __IO uint32_t AGC_CONFIG; /*!< (@ 0x00000014) AGC_CONFIG register */ + __IO uint32_t RESERVED; + __IO uint32_t PAYLOAD_0; /*!< (@ 0x0000001C) PAYLOAD_0 register */ + __IO uint32_t PAYLOAD_1; /*!< (@ 0x00000020) PAYLOAD_1 register */ + __IO uint32_t RESERVED1[7]; + __IO uint32_t RFIP_VERSION; /*!< (@ 0x00000040) RFIP_VERSION register */ + __IO uint32_t IRQ_ENABLE; /*!< (@ 0x00000044) IRQ_ENABLE register */ + __IO uint32_t STATUS; /*!< (@ 0x00000048) STATUS register */ +} LPAWUR_TypeDef; /*!< Size = 76 (0x4C) */ +#endif /* (STM32WL3XX) */ + + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ +#define FLASH_BASE (0x10040000UL) /*!< Main FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ + + +/*!< System Memory, OTP bytes */ + +/* Base addresses */ +#define SYSTEM_MEMORY_BASE (0x10000000UL) /*!< System Memory : 6KB (0x10000000 – 0x100017FF) */ +#define OTP_AREA_BASE (0x10001800UL) /*!< OTP area : 1kB (0x10001800 – 0x10001BFF) */ + +#define SRAM0_BASE SRAM_BASE /*!< SRAM0 (16 KB) base address */ +#define SRAM1_BASE (SRAM_BASE + 0x00004000UL) /*!< SRAM1 (16 KB) base address */ + +/* End addresses */ +#define SRAM0_END_ADDR (0x20003FFFUL) /*!< RAM0 : 16KB (0x20000000 – 0x20003FFF) */ +#define SRAM1_END_ADDR (0x20007FFFUL) /*!< RAM1 : 16KB (0x20004000 – 0x20007FFF) */ + +#define SYSTEM_MEMORY_END_ADDR (0x100017FFUL) /*!< System Memory : 6KB (0x10000000 – 0x100017FF) */ +#define OTP_AREA_END_ADDR (0x10001BFFUL) /*!< OTP area : 1KB (0x10001800 – 0x10001BFF) */ + +/*!< Peripheral memory map */ +#define APB0PERIPH_BASE PERIPH_BASE +#define APB1PERIPH_BASE (PERIPH_BASE + 0x01000000LU) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x08000000LU) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x09000000LU) + + +/*!< APB0 peripherals */ +#define SYSCFG_BASE (APB0PERIPH_BASE + 0x0000UL) +#define FLASH_R_BASE (APB0PERIPH_BASE + 0x1000UL) +#define TIM2_BASE (APB0PERIPH_BASE + 0x2000UL) +#define IWDG_BASE (APB0PERIPH_BASE + 0x3000UL) +#define RTC_BASE (APB0PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB0PERIPH_BASE + 0x5000UL) +#if defined (STM32WL3XX) +#define DAC1_BASE (APB0PERIPH_BASE + 0x6000UL) +#define LCD_BASE (APB0PERIPH_BASE + 0x7000UL) +#endif /* (STM32WL3XX)*/ +#define DBGMCU_BASE (APB0PERIPH_BASE + 0x8000UL) +#if defined (STM32WL3XX) +#define COMP_BASE (APB0PERIPH_BASE + 0x9000UL) +#define LCSC_BASE (APB0PERIPH_BASE + 0xA000UL) +#endif /* (STM32WL3XX)*/ + + +/*!< APB1 peripherals */ +#define I2C1_BASE (APB1PERIPH_BASE + 0x0000UL) +#if defined (STM32WL3XX) +#define I2C2_BASE (APB1PERIPH_BASE + 0x1000UL) +#define SPI1_BASE (APB1PERIPH_BASE + 0x2000UL) +#endif /* (STM32WL3XX)*/ +#define USART1_BASE (APB1PERIPH_BASE + 0x4000UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x5000UL) +#define ADC1_BASE (APB1PERIPH_BASE + 0x6000UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x7000UL) + +/*!< AHB peripherals */ +#define GPIOA_BASE (AHBPERIPH_BASE + 0x000000UL) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x100000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x200000UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x400000UL) +#define PWR_BASE (AHBPERIPH_BASE + 0x500000UL) +#define RNG_BASE (AHBPERIPH_BASE + 0x600000UL) +#define DMA1_BASE (AHBPERIPH_BASE + 0x700000UL) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x800000UL) +#define AES_BASE (AHBPERIPH_BASE + 0x900000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001CUL) + +/*!< APB2 peripherals */ +#define MR_SUBG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define MR_SUBG_RADIO_BASE (MR_SUBG_BASE + 0x0000UL) +#define MR_SUBG_GLOB_STATIC_BASE (MR_SUBG_BASE + 0x0400UL) +#define MR_SUBG_GLOB_DYNAMIC_BASE (MR_SUBG_BASE + 0x0500UL) +#define MR_SUBG_GLOB_STATUS_BASE (MR_SUBG_BASE + 0x0600UL) +#define MR_SUBG_GLOB_MISC_BASE (MR_SUBG_BASE + 0x0700UL) +#define MR_SUBG_GLOB_RETAINED_BASE (MR_SUBG_BASE + 0x0780UL) +#if defined (STM32WL3XX) +#define LPAWUR_BASE (APB2PERIPH_BASE + 0x1000UL) +#endif /* (STM32WL3XX) */ + + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + +/* Peripherals available on APB0 bus */ +#define SYSCFG ((SYSCFG_TypeDef*) SYSCFG_BASE) +#define FLASH ((FLASH_TypeDef*) FLASH_R_BASE) +#define TIM2 ((TIM_TypeDef*) TIM2_BASE) +#define IWDG ((IWDG_TypeDef*) IWDG_BASE) +#define RTC ((RTC_TypeDef*) RTC_BASE) +#define TIM16 ((TIM_TypeDef*) TIM16_BASE) +#if defined (STM32WL3XX) +#define DAC1 ((DAC_TypeDef*) DAC1_BASE) +#define LCD ((LCD_TypeDef*) LCD_BASE) +#endif /* (STM32WL3XX) */ +#define DBGMCU ((DBGMCU_TypeDef*) DBGMCU_BASE) +#if defined (STM32WL3XX) +#define COMP1 ((COMP_TypeDef*) COMP_BASE) +#define LCSC ((LCSC_TypeDef*) LCSC_BASE) +#endif /* (STM32WL3XX) */ + +/* Peripherals available on APB1 bus */ +#define I2C1 ((I2C_TypeDef*) I2C1_BASE) +#if defined (STM32WL3XX) +#define I2C2 ((I2C_TypeDef*) I2C2_BASE) +#define SPI1 ((SPI_TypeDef*) SPI1_BASE) +#endif /* (STM32WL3XX) */ +#define USART1 ((USART_TypeDef*) USART1_BASE) +#define LPUART1 ((USART_TypeDef*) LPUART1_BASE) +#define ADC1 ((ADC_TypeDef*) ADC1_BASE) +#define SPI3 ((SPI_TypeDef*) SPI3_BASE) + +/* Peripherals available on AHB bus */ +#define GPIOA ((GPIO_TypeDef*) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef*) GPIOB_BASE) +#define CRC ((CRC_TypeDef*) CRC_BASE) +#define RCC ((RCC_TypeDef*) RCC_BASE) +#define PWR ((PWR_TypeDef*) PWR_BASE) +#define RNG ((RNG_TypeDef*) RNG_BASE) +#define DMA1 ((DMA_TypeDef*) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define AES ((AES_TypeDef*) AES_BASE) + +/* Peripherals available on APB2 bus */ +#define MR_SUBG_RADIO ((MR_SUBG_RADIO_TypeDef*) MR_SUBG_RADIO_BASE) +#define MR_SUBG_GLOB_STATIC ((MR_SUBG_GLOB_STATIC_TypeDef*) MR_SUBG_GLOB_STATIC_BASE) +#define MR_SUBG_GLOB_DYNAMIC ((MR_SUBG_GLOB_DYNAMIC_TypeDef*) MR_SUBG_GLOB_DYNAMIC_BASE) +#define MR_SUBG_GLOB_STATUS ((MR_SUBG_GLOB_STATUS_TypeDef*) MR_SUBG_GLOB_STATUS_BASE) +#define MR_SUBG_GLOB_MISC ((MR_SUBG_GLOB_MISC_TypeDef*) MR_SUBG_GLOB_MISC_BASE) +#define MR_SUBG_GLOB_RETAINED ((MR_SUBG_GLOB_RETAINED_TypeDef*) MR_SUBG_GLOB_RETAINED_BASE) +#if defined (STM32WL3XX) +#define LPAWUR ((LPAWUR_TypeDef*) LPAWUR_BASE) +#endif /* (STM32WL3XX) */ + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* ============================================================================================================================*/ +/*===================== SYSCFG =====================*/ +/* ============================================================================================================================*/ + +/* ===================================================== DIE_ID =====================================================*/ +#define SYSCFG_DIE_ID_PRODUCT_Pos (8UL) /*! Release Notes for STM32WL33x CMSIS -
@@ -34,16 +34,17 @@

Release Notes for

STM32WL3xx CMSIS

-

Copyright © 2024 STMicroelectronics
+

Copyright © 2024-2025 STMicroelectronics

Purpose

-

This driver provides the CMSIS device for the STM32WL33x products. +

This driver provides the CMSIS device for the STM32WL3xx products. This covers

  • STM32WL33x devices
    • +
  • STM32WL3Rx devices

This driver is composed of the description of the registers under “Include” directory.

@@ -59,11 +60,41 @@

Purpose

Update history

- + + +
+

Main Changes

+
    +
  • Added support to STM32WL3Rx product line.
    • +
  • [LCSC] LCSC_VER register removed from the accessible register list, +as it is Non-User.
    • +
  • [LCSC] Fixed a typo on an LCSC register name (COMP_CTN -> +COMP_CNT)
    • +
  • [MRSUBG] RSSI_FLT bit #3 renamed to +FREEZE_SYNC_ON_SYNC_OOK_PEAK_DECAY
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Development Toolchains and +Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
    • +
+

Supported Devices and boards

+
    +
  • STM32WL3xx devices
    • +
+
+
+
+
-

Main Changes

+

Main Changes

  • Documentation based on jQuery 1.7.1 removed
@@ -73,17 +104,18 @@

Contents

  • Renamed some interrupt to improve clarity and consistency
  • Added FQCY_BAND_ID bits definition for RF_INFO_OUT register
    • -

    Known Limitations

    +

    Known Limitations

    • CMSIS devices files are delivered “as is” and have not been fully validated
    -

    Development Toolchains and -Compilers

    +

    Development Toolchains +and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
    -

    Supported Devices and boards

    +

    Supported Devices and +boards

    • STM32WL3xx devices
    @@ -94,7 +126,7 @@

    Supported Devices and boards

    -

    Main Changes

    +

    Main Changes

    Release

    • Release of CMSIS for STM32WL3xx devices
      • @@ -103,17 +135,17 @@

      Contents

      • CMSIS devices files for STM32WL3xx
      -

      Known Limitations

      +

      Known Limitations

      • CMSIS devices files are delivered “as is” and have not been fully validated
      -

      Development Toolchains +

      Development Toolchains and Compilers

      • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
      -

      Supported Devices and +

      Supported Devices and boards

      • STM32WL3xx devices
        • @@ -125,7 +157,7 @@

        Supported Devices and
        -

        Main Changes

        +

        Main Changes

        First Release

        • First Official Release of CMSIS for STM32WL33x devices
          • @@ -134,17 +166,17 @@

          Contents

          • CMSIS devices files for STM32WL33x
          -

          Known Limitations

          +

          Known Limitations

          • CMSIS devices files are delivered “as is” and have not been fully validated
          -

          Development Toolchains +

          Development Toolchains and Compilers

          • IAR Embedded Workbench for ARM (EWARM) toolchain V9.30.1
          -

          Supported Devices and +

          Supported Devices and boards

          • STM32WL33x devices
            • diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3Rx8_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3Rx8_flash.ld new file mode 100644 index 0000000000..cfa191b9dd --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3Rx8_flash.ld @@ -0,0 +1,191 @@ +/******************************************************************************* +* STM32WL3x generic linker file for GCC +* Main linker variables to control it are: +* +* MEMORY_FLASH_APP_SIZE: define the size of the application in case not all the flash is needed. +* Default value is: 64KB +* +* MEMORY_FLASH_APP_OFFSET: define the offset of the application. +* Default value is: 0 offset +* +* MEMORY_RAM_APP_OFFSET: define the offset in RAM from which variables can be +* allocated. +* +*******************************************************************************/ + +/******************************************************************************* +* Memory Definitions +*******************************************************************************/ +/* +STM32WL3x memory map ++-----------------------+ 0x20001FFF +| RAM (8K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1004FFFF +| | +| FLASH (64K) | ++-----------------------+ 0x10040000 +| | ++-----------------------| 0x100017FF +| ROM (6K) | ++-----------------------+ 0x10000000 +*/ + + +_MEMORY_RAM_BEGIN_ = 0x20000000; +_MEMORY_RAM_SIZE_ = 0x2000; /* 8KB */ +_MEMORY_RAM_END_ = 0x20001FFF; + +_MEMORY_FLASH_BEGIN_ = 0x10040000; +_MEMORY_FLASH_SIZE_ = 0x10000; /* 64KB */ +_MEMORY_FLASH_END_ = 0x1004FFFF; + +_MEMORY_ROM_BEGIN_ = 0x10000000; +_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ +_MEMORY_ROM_END_ = 0x100017FF; + + +MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; +MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); +RESET_MANAGER_SIZE = DEFINED(RESET_MANAGER_SIZE) ? (RESET_MANAGER_SIZE) : (0x800) ; + + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x000; /* required amount of heap */ +_Min_Stack_Size = 0xC00; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ + REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET + REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE + REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ +} + +/* Define output sections */ +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .intvec (ORIGIN(REGION_FLASH)) : + { + . = ALIGN(4); + + KEEP(*(.intvec)) /* Startup code */ + + . = ALIGN(4); + } >REGION_FLASH + + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + + KEEP(*(.cmd_call_table)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(i.*) /* i.* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.constdata) + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; + } >REGION_FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* RAM preamble, uninitialized */ + .ram_preamble 0x20000004 (NOLOAD) : + { + KEEP(*(.ram_vr)) + } >REGION_RAM AT> REGION_FLASH + + /* RAM preamble, unininitialized */ + .ram_preamble_2 0x20000034 (NOLOAD) : + { + KEEP(*(.crash_info_ram_vr)) + } >REGION_RAM + /* Uninitialized data section */ + + .bss DEFINED(MEMORY_RAM_APP_OFFSET) ? (ORIGIN(REGION_RAM) + MEMORY_RAM_APP_OFFSET) : . : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + } >REGION_RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >REGION_RAM AT> REGION_FLASH + + /* Data section that will not be initialized to any value. */ + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + . = ALIGN(4); + } >REGION_RAM + + .heap (NOLOAD): + { + . = ALIGN(4); + _sheap = .; + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = ALIGN(4); + _eheap = .; + } >REGION_RAM + + /* This is to emulate place at end of IAR linker */ + CSTACK (ORIGIN(REGION_RAM) + LENGTH(REGION_RAM) - _Min_Stack_Size) (NOLOAD) : + { + . = ALIGN(4); + . = . + _Min_Stack_Size; + . = ALIGN(4); + _estack = .; /* define a global symbol at stack end */ + . = ALIGN(4); + } > REGION_RAM + + + .rom_info (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.rom_info)) + . = ALIGN(4); + } >REGION_ROM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3RxB_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3RxB_flash.ld new file mode 100644 index 0000000000..98834d5850 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/STM32WL3RxB_flash.ld @@ -0,0 +1,191 @@ +/******************************************************************************* +* STM32WL3x generic linker file for GCC +* Main linker variables to control it are: +* +* MEMORY_FLASH_APP_SIZE: define the size of the application in case not all the flash is needed. +* Default value is: 128KB +* +* MEMORY_FLASH_APP_OFFSET: define the offset of the application. +* Default value is: 0 offset +* +* MEMORY_RAM_APP_OFFSET: define the offset in RAM from which variables can be +* allocated. +* +*******************************************************************************/ + +/******************************************************************************* +* Memory Definitions +*******************************************************************************/ +/* +STM32WL3x memory map ++-----------------------+ 0x20003FFF +| RAM (16K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1005FFFF +| | +| FLASH (128K) | ++-----------------------+ 0x10040000 +| | ++-----------------------| 0x100017FF +| ROM (6K) | ++-----------------------+ 0x10000000 +*/ + + +_MEMORY_RAM_BEGIN_ = 0x20000000; +_MEMORY_RAM_SIZE_ = 0x4000; /* 16KB */ +_MEMORY_RAM_END_ = 0x20003FFF; + +_MEMORY_FLASH_BEGIN_ = 0x10040000; +_MEMORY_FLASH_SIZE_ = 0x20000; /* 128KB */ +_MEMORY_FLASH_END_ = 0x1005FFFF; + +_MEMORY_ROM_BEGIN_ = 0x10000000; +_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ +_MEMORY_ROM_END_ = 0x100017FF; + + +MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; +MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); +RESET_MANAGER_SIZE = DEFINED(RESET_MANAGER_SIZE) ? (RESET_MANAGER_SIZE) : (0x800) ; + + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x000; /* required amount of heap */ +_Min_Stack_Size = 0xC00; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ + REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET + REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE + REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ +} + +/* Define output sections */ +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .intvec (ORIGIN(REGION_FLASH)) : + { + . = ALIGN(4); + + KEEP(*(.intvec)) /* Startup code */ + + . = ALIGN(4); + } >REGION_FLASH + + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + + KEEP(*(.cmd_call_table)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(i.*) /* i.* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.constdata) + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; + } >REGION_FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* RAM preamble, uninitialized */ + .ram_preamble 0x20000004 (NOLOAD) : + { + KEEP(*(.ram_vr)) + } >REGION_RAM AT> REGION_FLASH + + /* RAM preamble, unininitialized */ + .ram_preamble_2 0x20000034 (NOLOAD) : + { + KEEP(*(.crash_info_ram_vr)) + } >REGION_RAM + /* Uninitialized data section */ + + .bss DEFINED(MEMORY_RAM_APP_OFFSET) ? (ORIGIN(REGION_RAM) + MEMORY_RAM_APP_OFFSET) : . : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + } >REGION_RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >REGION_RAM AT> REGION_FLASH + + /* Data section that will not be initialized to any value. */ + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + . = ALIGN(4); + } >REGION_RAM + + .heap (NOLOAD): + { + . = ALIGN(4); + _sheap = .; + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = ALIGN(4); + _eheap = .; + } >REGION_RAM + + /* This is to emulate place at end of IAR linker */ + CSTACK (ORIGIN(REGION_RAM) + LENGTH(REGION_RAM) - _Min_Stack_Size) (NOLOAD) : + { + . = ALIGN(4); + . = . + _Min_Stack_Size; + . = ALIGN(4); + _estack = .; /* define a global symbol at stack end */ + . = ALIGN(4); + } > REGION_RAM + + + .rom_info (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.rom_info)) + . = ALIGN(4); + } >REGION_ROM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3rxx_flash.ld b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3rxx_flash.ld new file mode 100644 index 0000000000..98834d5850 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/linker/stm32wl3rxx_flash.ld @@ -0,0 +1,191 @@ +/******************************************************************************* +* STM32WL3x generic linker file for GCC +* Main linker variables to control it are: +* +* MEMORY_FLASH_APP_SIZE: define the size of the application in case not all the flash is needed. +* Default value is: 128KB +* +* MEMORY_FLASH_APP_OFFSET: define the offset of the application. +* Default value is: 0 offset +* +* MEMORY_RAM_APP_OFFSET: define the offset in RAM from which variables can be +* allocated. +* +*******************************************************************************/ + +/******************************************************************************* +* Memory Definitions +*******************************************************************************/ +/* +STM32WL3x memory map ++-----------------------+ 0x20003FFF +| RAM (16K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1005FFFF +| | +| FLASH (128K) | ++-----------------------+ 0x10040000 +| | ++-----------------------| 0x100017FF +| ROM (6K) | ++-----------------------+ 0x10000000 +*/ + + +_MEMORY_RAM_BEGIN_ = 0x20000000; +_MEMORY_RAM_SIZE_ = 0x4000; /* 16KB */ +_MEMORY_RAM_END_ = 0x20003FFF; + +_MEMORY_FLASH_BEGIN_ = 0x10040000; +_MEMORY_FLASH_SIZE_ = 0x20000; /* 128KB */ +_MEMORY_FLASH_END_ = 0x1005FFFF; + +_MEMORY_ROM_BEGIN_ = 0x10000000; +_MEMORY_ROM_SIZE_ = 0x01800; /* 6KB */ +_MEMORY_ROM_END_ = 0x100017FF; + + +MEMORY_FLASH_APP_OFFSET = DEFINED(MEMORY_FLASH_APP_OFFSET) ? (MEMORY_FLASH_APP_OFFSET) : (0) ; +MEMORY_FLASH_APP_SIZE = DEFINED(MEMORY_FLASH_APP_SIZE) ? (MEMORY_FLASH_APP_SIZE) : (_MEMORY_FLASH_SIZE_ - MEMORY_FLASH_APP_OFFSET); +RESET_MANAGER_SIZE = DEFINED(RESET_MANAGER_SIZE) ? (RESET_MANAGER_SIZE) : (0x800) ; + + +/* Entry Point */ +ENTRY(Reset_Handler) + + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x000; /* required amount of heap */ +_Min_Stack_Size = 0xC00; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + REGION_RAM (xrw) : ORIGIN = _MEMORY_RAM_BEGIN_, LENGTH = _MEMORY_RAM_SIZE_ + REGION_FLASH_BOOTLOADER (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_, LENGTH = MEMORY_FLASH_APP_OFFSET + REGION_FLASH (rx) : ORIGIN = _MEMORY_FLASH_BEGIN_ + MEMORY_FLASH_APP_OFFSET, LENGTH = MEMORY_FLASH_APP_SIZE + REGION_ROM (rx) : ORIGIN = _MEMORY_ROM_BEGIN_, LENGTH = _MEMORY_ROM_SIZE_ +} + +/* Define output sections */ +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .intvec (ORIGIN(REGION_FLASH)) : + { + . = ALIGN(4); + + KEEP(*(.intvec)) /* Startup code */ + + . = ALIGN(4); + } >REGION_FLASH + + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + + KEEP(*(.cmd_call_table)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(i.*) /* i.* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.constdata) + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + . = ALIGN(4); + _etext = .; + } >REGION_FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* RAM preamble, uninitialized */ + .ram_preamble 0x20000004 (NOLOAD) : + { + KEEP(*(.ram_vr)) + } >REGION_RAM AT> REGION_FLASH + + /* RAM preamble, unininitialized */ + .ram_preamble_2 0x20000034 (NOLOAD) : + { + KEEP(*(.crash_info_ram_vr)) + } >REGION_RAM + /* Uninitialized data section */ + + .bss DEFINED(MEMORY_RAM_APP_OFFSET) ? (ORIGIN(REGION_RAM) + MEMORY_RAM_APP_OFFSET) : . : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start */ + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + } >REGION_RAM + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >REGION_RAM AT> REGION_FLASH + + /* Data section that will not be initialized to any value. */ + .noinit (NOLOAD): + { + . = ALIGN(4); + *(.noinit) + . = ALIGN(4); + } >REGION_RAM + + .heap (NOLOAD): + { + . = ALIGN(4); + _sheap = .; + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = ALIGN(4); + _eheap = .; + } >REGION_RAM + + /* This is to emulate place at end of IAR linker */ + CSTACK (ORIGIN(REGION_RAM) + LENGTH(REGION_RAM) - _Min_Stack_Size) (NOLOAD) : + { + . = ALIGN(4); + . = . + _Min_Stack_Size; + . = ALIGN(4); + _estack = .; /* define a global symbol at stack end */ + . = ALIGN(4); + } > REGION_RAM + + + .rom_info (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.rom_info)) + . = ALIGN(4); + } >REGION_ROM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3rx.s b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3rx.s new file mode 100644 index 0000000000..d46dc26e29 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3rx.s @@ -0,0 +1,251 @@ +/** + ****************************************************************************** + * @file : startup_stm32wl3rx.s + * @author : GPM WBL Application Team + * @brief : STM32WL3x Ultra Low Power Devices vector + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global __vector_table +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .intvec,"a",%progbits + .type __vector_table, %object + .size __vector_table, .-__vector_table + + +__vector_table: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word FLASH_IRQHandler /* IRQ0: FLASH Controller interrupt */ + .word RCC_IRQHandler /* IRQ1: RCC interrupt */ + .word PVD_IRQHandler /* IRQ2: PVD interrupt */ + .word I2C1_IRQHandler /* IRQ3: I2C1 interrupt */ + .word 0x00000000 /* IRQ4: Reserved */ + .word 0x00000000 /* IRQ5: Reserved */ + .word 0x00000000 /* IRQ6: Reserved */ + .word SPI3_IRQHandler /* IRQ7: SPI3 interrupt */ + .word USART1_IRQHandler /* IRQ8: USART1 interrupt */ + .word LPUART1_IRQHandler /* IRQ9: LPUART1 interrupt */ + .word TIM2_IRQHandler /* IRQ10: TIM2 interrupt */ + .word RTC_IRQHandler /* IRQ11: RTC interrupt */ + .word ADC_IRQHandler /* IRQ12: ADC interrupt */ + .word AES_IRQHandler /* IRQ13: AES interrupt */ + .word 0x00000000 /* IRQ14: Reserved */ + .word GPIOA_IRQHandler /* IRQ15: GPIOA interrupt */ + .word GPIOB_IRQHandler /* IRQ16: GPIOB interrupt */ + .word DMA_IRQHandler /* IRQ17: DMA interrupt */ + .word 0x00000000 /* IRQ18: Reserved */ + .word 0x00000000 /* IRQ19: Reserved */ + .word MRSUBG_BUSY_IRQHandler /* IRQ20: MR SUBG BUSY interrupt */ + .word MRSUBG_IRQHandler /* IRQ21: MR SUBG interrupt */ + .word MRSUBG_TX_RX_SEQUENCE_IRQHandler /* IRQ22: MR SUBG TX RX Sequence interrupt */ + .word MRSUBG_TIMER_CPU_WKUP_IRQHandler /* IRQ23: MR SUBG TIMER CPU Wakeup interrupt */ + .word MRSUBG_WKUP_IRQHandler /* IRQ24: MR SUBG Wakeup interrupt */ + .word 0x00000000 /* IRQ25: Reserved */ + .word TIM16_IRQHandler /* IRQ26: TIM16 interrupt */ + .word 0x00000000 /* IRQ27: Reserved */ + .word 0x00000000 /* IRQ28: Reserved */ + .word 0x00000000 /* IRQ29: Reserved */ + .word 0x00000000 /* IRQ30: Reserved */ + .word 0x00000000 /* IRQ31: Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak GPIOA_IRQHandler + .thumb_set GPIOA_IRQHandler,Default_Handler + + .weak GPIOB_IRQHandler + .thumb_set GPIOB_IRQHandler,Default_Handler + + .weak DMA_IRQHandler + .thumb_set DMA_IRQHandler,Default_Handler + + .weak MRSUBG_BUSY_IRQHandler + .thumb_set MRSUBG_BUSY_IRQHandler,Default_Handler + + .weak MRSUBG_IRQHandler + .thumb_set MRSUBG_IRQHandler,Default_Handler + + .weak MRSUBG_TX_RX_SEQUENCE_IRQHandler + .thumb_set MRSUBG_TX_RX_SEQUENCE_IRQHandler,Default_Handler + + .weak MRSUBG_TIMER_CPU_WKUP_IRQHandler + .thumb_set MRSUBG_TIMER_CPU_WKUP_IRQHandler,Default_Handler + + .weak MRSUBG_WKUP_IRQHandler + .thumb_set MRSUBG_WKUP_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s index 28bf2e6da6..ed0d82befe 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s @@ -83,8 +83,6 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call static constructors */ - bl __libc_init_array /* Call the application's entry point.*/ bl main @@ -158,8 +156,8 @@ __vector_table: .word COMP1_IRQHandler /* IRQ19: COMP1 interrupt */ .word MRSUBG_BUSY_IRQHandler /* IRQ20: MR SUBG BUSY interrupt */ .word MRSUBG_IRQHandler /* IRQ21: MR SUBG interrupt */ - .word MRSUBG_TX_RX_SEQUENCE_IRQHandler /* IRQ22: MR SUBG TX RX Sequence interrupt */ - .word MRSUBG_TIMER_CPU_WKUP_IRQHandler /* IRQ23: MR SUBG TIMER CPU Wakeup interrupt */ + .word MRSUBG_TX_RX_SEQUENCE_IRQHandler /* IRQ22: MR SUBG TX RX Sequence interrupt */ + .word MRSUBG_TIMER_CPU_WKUP_IRQHandler /* IRQ23: MR SUBG TIMER CPU Wakeup interrupt */ .word MRSUBG_WKUP_IRQHandler /* IRQ24: MR SUBG Wakeup interrupt */ .word DAC_IRQHandler /* IRQ25: DAC interrupt */ .word TIM16_IRQHandler /* IRQ26: TIM16 interrupt */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/system_stm32wl3x.c b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/system_stm32wl3x.c index c572cce21c..3bafa496d2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/system_stm32wl3x.c +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/system_stm32wl3x.c @@ -110,7 +110,7 @@ /*!< HW TRIMMING Defines */ #define VALIDITY_TAG 0xFCBCECCC /*!< TAG to validate the content of the - trimming area content. */ + trimming area content. */ #define VALIDITY_LOCATION 0x10001EF8 /*!< ROM address of the the validity trimming values content. */ /*!< SMPS Configuration Defines */ @@ -157,13 +157,13 @@ /* The RAM_VR variable is a mirroring in RAM of some registers information. It is a sort of virtual register in RAM. */ -#if defined ( __ICCARM__ ) +#if defined(__ICCARM__) #pragma location=".ram_vr" __root __no_init RAM_VR_TypeDef RAM_VR; #else -#if defined ( __ARMCC_VERSION ) +#if defined(__ARMCC_VERSION) __attribute__((section(".bss" ".ram_vr"))) -#elif defined ( __GNUC__ ) +#elif defined(__GNUC__) __attribute__((section(".ram_vr"))) #endif RAM_VR_TypeDef RAM_VR __attribute__((used)); @@ -191,7 +191,6 @@ void CPUcontextRestore(void); * @param None * @retval None */ - void SystemInit(void) { uint32_t mainRegulator, smpsOutVoltage, lsiBw, hsiCalib; @@ -203,7 +202,8 @@ void SystemInit(void) RAM_VR.WakeupFromSleepFlag = 1; /* A wakeup from power save occurred */ CPUcontextRestore(); /* Restore the context */ /* if the context restore worked properly, we should never return here */ - while(1) { + while(1) + { NVIC_SystemReset(); } } diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 81f3a26cb7..451d998d2e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -23,7 +23,7 @@ * STM32WB0: 1.4.0 * STM32WBA: 1.8.0 * STM32WL: 1.3.0 - * STM32WL3: 1.2.0 + * STM32WL3: 1.3.0 Release notes of each STM32YYxx CMSIS available here: From cfbac0311d38ed4d3ae68f629f4fa25f01934e6e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 27 Nov 2025 16:01:47 +0100 Subject: [PATCH 05/10] core(wl3): update wrapped files Signed-off-by: Frederic Pillon --- cores/arduino/stm32/stm32_def_build.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index 84d3554da5..ae3d823f19 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -518,7 +518,9 @@ #define CMSIS_STARTUP_FILE "startup_stm32wb55xx_cm4.s" #elif defined(STM32WB5Mxx) #define CMSIS_STARTUP_FILE "startup_stm32wb5mxx_cm4.s" - #elif defined(STM32WL3xx) + #elif defined(STM32WL3RX) + #define CMSIS_STARTUP_FILE "startup_stm32wl3rx.s" + #elif defined(STM32WL3XX) #define CMSIS_STARTUP_FILE "startup_stm32wl3xx.s" #elif defined(STM32WL54xx) && defined(USE_CM0PLUS_STARTUP_FILE) #define CMSIS_STARTUP_FILE "startup_stm32wl54xx_cm0plus.s" From 73bf3cfd7debbf0da97738044733b94a2b22b349 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 23 Sep 2025 14:48:50 +0200 Subject: [PATCH 06/10] fix(wl3): HAL and LL warnings Signed-off-by: Frederic Pillon --- .../Inc/stm32wl3x_ll_dma.h | 104 ++++++++++++++++++ .../Src/stm32wl3x_hal_flash_ex.c | 2 +- 2 files changed, 105 insertions(+), 1 deletion(-) diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h index b94790b322..e49d7c53f5 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h +++ b/system/Drivers/STM32WL3x_HAL_Driver/Inc/stm32wl3x_ll_dma.h @@ -433,6 +433,7 @@ typedef struct */ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -453,6 +454,7 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN); } @@ -473,6 +475,7 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); } @@ -509,6 +512,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); @@ -536,6 +540,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); } @@ -561,6 +566,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM)); } @@ -587,6 +593,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC, Mode); } @@ -610,6 +617,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC)); } @@ -634,6 +642,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC, PeriphOrM2MSrcIncMode); } @@ -657,6 +666,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC)); } @@ -681,6 +691,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC, MemoryOrM2MDstIncMode); } @@ -704,6 +715,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC)); } @@ -729,6 +741,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize); } @@ -753,6 +766,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE)); } @@ -778,6 +792,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE, MemoryOrM2MDstDataSize); } @@ -802,6 +817,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE)); } @@ -828,6 +844,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe */ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL, Priority); } @@ -853,6 +870,7 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t */ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL)); } @@ -877,6 +895,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT, NbData); } @@ -900,6 +919,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR, DMA_CNDTR_NDT)); } @@ -931,6 +951,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { + (void)DMAx; /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { @@ -965,6 +986,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -988,6 +1010,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress); } @@ -1009,6 +1032,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1030,6 +1054,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1053,6 +1078,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress); } @@ -1076,6 +1102,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { + (void)DMAx; WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress); } @@ -1097,6 +1124,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR)); } @@ -1118,6 +1146,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR)); } @@ -1140,6 +1169,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { + (void)DMAx; MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request); } @@ -1161,6 +1191,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID)); } @@ -1180,6 +1211,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); } @@ -1191,6 +1223,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); } @@ -1202,6 +1235,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); } @@ -1213,6 +1247,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); } @@ -1224,6 +1259,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); } @@ -1235,6 +1271,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); } @@ -1246,6 +1283,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); } @@ -1257,6 +1295,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL); } @@ -1268,6 +1307,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); } @@ -1279,6 +1319,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); } @@ -1290,6 +1331,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); } @@ -1301,6 +1343,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); } @@ -1312,6 +1355,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); } @@ -1323,6 +1367,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); } @@ -1334,6 +1379,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); } @@ -1345,6 +1391,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL); } @@ -1356,6 +1403,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); } @@ -1367,6 +1415,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); } @@ -1378,6 +1427,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); } @@ -1389,6 +1439,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); } @@ -1400,6 +1451,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); } @@ -1411,6 +1463,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); } @@ -1422,6 +1475,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); } @@ -1433,6 +1487,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL); } @@ -1444,6 +1499,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); } @@ -1455,6 +1511,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); } @@ -1466,6 +1523,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); } @@ -1477,6 +1535,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); } @@ -1488,6 +1547,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); } @@ -1499,6 +1559,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); } @@ -1510,6 +1571,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); } @@ -1521,6 +1583,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) { + (void)DMAx; return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL); } @@ -1532,6 +1595,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); } @@ -1543,6 +1607,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); } @@ -1554,6 +1619,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); } @@ -1565,6 +1631,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); } @@ -1576,6 +1643,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); } @@ -1587,6 +1655,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); } @@ -1598,6 +1667,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); } @@ -1609,6 +1679,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8); } @@ -1620,6 +1691,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); } @@ -1631,6 +1703,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); } @@ -1642,6 +1715,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); } @@ -1653,6 +1727,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); } @@ -1664,6 +1739,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); } @@ -1675,6 +1751,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); } @@ -1686,6 +1763,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); } @@ -1697,6 +1775,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8); } @@ -1708,6 +1787,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); } @@ -1719,6 +1799,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); } @@ -1730,6 +1811,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); } @@ -1741,6 +1823,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); } @@ -1752,6 +1835,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); } @@ -1763,6 +1847,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); } @@ -1774,6 +1859,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); } @@ -1785,6 +1871,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8); } @@ -1796,6 +1883,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); } @@ -1807,6 +1895,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); } @@ -1818,6 +1907,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); } @@ -1829,6 +1919,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); } @@ -1840,6 +1931,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); } @@ -1851,6 +1943,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); } @@ -1862,6 +1955,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); } @@ -1873,6 +1967,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) { + (void)DMAx; WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8); } @@ -1900,6 +1995,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx) */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -1920,6 +2016,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -1940,6 +2037,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -1960,6 +2058,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE); } @@ -1980,6 +2079,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE); } @@ -2000,6 +2100,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE); } @@ -2020,6 +2121,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); } @@ -2041,6 +2143,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); } @@ -2062,6 +2165,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { + (void)DMAx; return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c index 9cd95caf30..d1b9f3dd01 100644 --- a/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c +++ b/system/Drivers/STM32WL3x_HAL_Driver/Src/stm32wl3x_hal_flash_ex.c @@ -107,7 +107,7 @@ static void FLASH_Program_OTPWord(uint32_t Address, uint32_t Data); */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_ERROR; uint32_t index; /* Check the parameters */ From 8cc519f4ca1655777ab7a4797213a302ef4acc25 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 23 Sep 2025 09:50:23 +0200 Subject: [PATCH 07/10] feat(wl3): add __libc_init_array call to startup Signed-off-by: Frederic Pillon --- .../ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s | 2 ++ 1 file changed, 2 insertions(+) diff --git a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s index ed0d82befe..b0ce567927 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32WL3x/Source/Templates/gcc/startup_stm32wl3xx.s @@ -83,6 +83,8 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss +/* Call static constructors */ + bl __libc_init_array /* Call the application's entry point.*/ bl main From 648336c911a7fc36ef7295ab1b22cf0d897b40c7 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 27 Nov 2025 16:04:55 +0100 Subject: [PATCH 08/10] ci(variant): update Signed-off-by: Frederic Pillon --- boards.txt | 16 ++++++++-------- variants/STM32WL3x/WL30K(8-B)V/boards_entry.txt | 4 ++-- variants/STM32WL3x/WL31C(8-B)V/boards_entry.txt | 4 ++-- .../boards_entry.txt | 16 ++++++++-------- .../STM32WL3x/WL33C(8-B-C)Vx(X)/boards_entry.txt | 12 ++++++------ .../STM32WL3x/WL3RK(8-B)Vx(X)/boards_entry.txt | 8 ++++---- 6 files changed, 30 insertions(+), 30 deletions(-) diff --git a/boards.txt b/boards.txt index d80f727533..4ced76c2dd 100644 --- a/boards.txt +++ b/boards.txt @@ -1026,7 +1026,7 @@ Nucleo_64.menu.pnum.NUCLEO_WL33CC1.upload.maximum_data_size=32768 Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.mcu=cortex-m0plus Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.board=NUCLEO_WL33CC1 Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.series=STM32WL3x -Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.product_line=STM32WL3xx +Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.product_line=STM32WL3XX Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.variant_h=variant_NUCLEO_WL33CCx.h Nucleo_64.menu.pnum.NUCLEO_WL33CC1.build.st_extra_flags=-D{build.product_line} {build.xSerial} -D__CORTEX_SC=0 @@ -1045,7 +1045,7 @@ Nucleo_64.menu.pnum.NUCLEO_WL33CC2.upload.maximum_data_size=32768 Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.mcu=cortex-m0plus Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.board=NUCLEO_WL33CC2 Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.series=STM32WL3x -Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.product_line=STM32WL3xx +Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.product_line=STM32WL3XX Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.variant_h=variant_NUCLEO_WL33CCx.h Nucleo_64.menu.pnum.NUCLEO_WL33CC2.build.st_extra_flags=-D{build.product_line} {build.xSerial} -D__CORTEX_SC=0 @@ -13647,7 +13647,7 @@ GenWL3.menu.pnum.GENERIC_WL33C8VX=Generic WL33C8Vx GenWL3.menu.pnum.GENERIC_WL33C8VX.upload.maximum_size=65536 GenWL3.menu.pnum.GENERIC_WL33C8VX.upload.maximum_data_size=16384 GenWL3.menu.pnum.GENERIC_WL33C8VX.build.board=GENERIC_WL33C8VX -GenWL3.menu.pnum.GENERIC_WL33C8VX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33C8VX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33C8VX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33C8VX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -13656,7 +13656,7 @@ GenWL3.menu.pnum.GENERIC_WL33C8VXX=Generic WL33C8VxX GenWL3.menu.pnum.GENERIC_WL33C8VXX.upload.maximum_size=65536 GenWL3.menu.pnum.GENERIC_WL33C8VXX.upload.maximum_data_size=16384 GenWL3.menu.pnum.GENERIC_WL33C8VXX.build.board=GENERIC_WL33C8VXX -GenWL3.menu.pnum.GENERIC_WL33C8VXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33C8VXX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33C8VXX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33C8VXX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -13665,7 +13665,7 @@ GenWL3.menu.pnum.GENERIC_WL33CBVX=Generic WL33CBVx GenWL3.menu.pnum.GENERIC_WL33CBVX.upload.maximum_size=131072 GenWL3.menu.pnum.GENERIC_WL33CBVX.upload.maximum_data_size=32768 GenWL3.menu.pnum.GENERIC_WL33CBVX.build.board=GENERIC_WL33CBVX -GenWL3.menu.pnum.GENERIC_WL33CBVX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33CBVX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33CBVX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33CBVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -13674,7 +13674,7 @@ GenWL3.menu.pnum.GENERIC_WL33CBVXX=Generic WL33CBVxX GenWL3.menu.pnum.GENERIC_WL33CBVXX.upload.maximum_size=131072 GenWL3.menu.pnum.GENERIC_WL33CBVXX.upload.maximum_data_size=32768 GenWL3.menu.pnum.GENERIC_WL33CBVXX.build.board=GENERIC_WL33CBVXX -GenWL3.menu.pnum.GENERIC_WL33CBVXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33CBVXX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33CBVXX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33CBVXX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -13683,7 +13683,7 @@ GenWL3.menu.pnum.GENERIC_WL33CCVX=Generic WL33CCVx GenWL3.menu.pnum.GENERIC_WL33CCVX.upload.maximum_size=262144 GenWL3.menu.pnum.GENERIC_WL33CCVX.upload.maximum_data_size=32768 GenWL3.menu.pnum.GENERIC_WL33CCVX.build.board=GENERIC_WL33CCVX -GenWL3.menu.pnum.GENERIC_WL33CCVX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33CCVX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33CCVX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33CCVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -13692,7 +13692,7 @@ GenWL3.menu.pnum.GENERIC_WL33CCVXX=Generic WL33CCVxX GenWL3.menu.pnum.GENERIC_WL33CCVXX.upload.maximum_size=262144 GenWL3.menu.pnum.GENERIC_WL33CCVXX.upload.maximum_data_size=32768 GenWL3.menu.pnum.GENERIC_WL33CCVXX.build.board=GENERIC_WL33CCVXX -GenWL3.menu.pnum.GENERIC_WL33CCVXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33CCVXX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33CCVXX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33CCVXX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd diff --git a/variants/STM32WL3x/WL30K(8-B)V/boards_entry.txt b/variants/STM32WL3x/WL30K(8-B)V/boards_entry.txt index 7797ba7477..ee435bb49f 100644 --- a/variants/STM32WL3x/WL30K(8-B)V/boards_entry.txt +++ b/variants/STM32WL3x/WL30K(8-B)V/boards_entry.txt @@ -8,7 +8,7 @@ GenWL3.menu.pnum.GENERIC_WL30K8VX=Generic WL30K8Vx GenWL3.menu.pnum.GENERIC_WL30K8VX.upload.maximum_size=65536 GenWL3.menu.pnum.GENERIC_WL30K8VX.upload.maximum_data_size=8192 GenWL3.menu.pnum.GENERIC_WL30K8VX.build.board=GENERIC_WL30K8VX -GenWL3.menu.pnum.GENERIC_WL30K8VX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL30K8VX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL30K8VX.build.variant=STM32WL3x/WL30K(8-B)V GenWL3.menu.pnum.GENERIC_WL30K8VX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL30.svd @@ -17,7 +17,7 @@ GenWL3.menu.pnum.GENERIC_WL30KBVX=Generic WL30KBVx GenWL3.menu.pnum.GENERIC_WL30KBVX.upload.maximum_size=131072 GenWL3.menu.pnum.GENERIC_WL30KBVX.upload.maximum_data_size=16384 GenWL3.menu.pnum.GENERIC_WL30KBVX.build.board=GENERIC_WL30KBVX -GenWL3.menu.pnum.GENERIC_WL30KBVX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL30KBVX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL30KBVX.build.variant=STM32WL3x/WL30K(8-B)V GenWL3.menu.pnum.GENERIC_WL30KBVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL30.svd diff --git a/variants/STM32WL3x/WL31C(8-B)V/boards_entry.txt b/variants/STM32WL3x/WL31C(8-B)V/boards_entry.txt index 79e202ec50..1aad4f9603 100644 --- a/variants/STM32WL3x/WL31C(8-B)V/boards_entry.txt +++ b/variants/STM32WL3x/WL31C(8-B)V/boards_entry.txt @@ -8,7 +8,7 @@ GenWL3.menu.pnum.GENERIC_WL31C8VX=Generic WL31C8Vx GenWL3.menu.pnum.GENERIC_WL31C8VX.upload.maximum_size=65536 GenWL3.menu.pnum.GENERIC_WL31C8VX.upload.maximum_data_size=8192 GenWL3.menu.pnum.GENERIC_WL31C8VX.build.board=GENERIC_WL31C8VX -GenWL3.menu.pnum.GENERIC_WL31C8VX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL31C8VX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL31C8VX.build.variant=STM32WL3x/WL31C(8-B)V GenWL3.menu.pnum.GENERIC_WL31C8VX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL31.svd @@ -17,7 +17,7 @@ GenWL3.menu.pnum.GENERIC_WL31CBVX=Generic WL31CBVx GenWL3.menu.pnum.GENERIC_WL31CBVX.upload.maximum_size=131072 GenWL3.menu.pnum.GENERIC_WL31CBVX.upload.maximum_data_size=16384 GenWL3.menu.pnum.GENERIC_WL31CBVX.build.board=GENERIC_WL31CBVX -GenWL3.menu.pnum.GENERIC_WL31CBVX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL31CBVX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL31CBVX.build.variant=STM32WL3x/WL31C(8-B)V GenWL3.menu.pnum.GENERIC_WL31CBVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL31.svd diff --git a/variants/STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X)/boards_entry.txt b/variants/STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X)/boards_entry.txt index 99f9923341..e9cba0f8d8 100644 --- a/variants/STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X)/boards_entry.txt +++ b/variants/STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X)/boards_entry.txt @@ -8,7 +8,7 @@ GenWL3.menu.pnum.GENERIC_WL31K8VX=Generic WL31K8Vx GenWL3.menu.pnum.GENERIC_WL31K8VX.upload.maximum_size=65536 GenWL3.menu.pnum.GENERIC_WL31K8VX.upload.maximum_data_size=8192 GenWL3.menu.pnum.GENERIC_WL31K8VX.build.board=GENERIC_WL31K8VX -GenWL3.menu.pnum.GENERIC_WL31K8VX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL31K8VX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL31K8VX.build.variant=STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL31K8VX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL31.svd @@ -17,7 +17,7 @@ GenWL3.menu.pnum.GENERIC_WL31KBVX=Generic WL31KBVx GenWL3.menu.pnum.GENERIC_WL31KBVX.upload.maximum_size=131072 GenWL3.menu.pnum.GENERIC_WL31KBVX.upload.maximum_data_size=16384 GenWL3.menu.pnum.GENERIC_WL31KBVX.build.board=GENERIC_WL31KBVX -GenWL3.menu.pnum.GENERIC_WL31KBVX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL31KBVX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL31KBVX.build.variant=STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL31KBVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL31.svd @@ -26,7 +26,7 @@ GenWL3.menu.pnum.GENERIC_WL33K8VX=Generic WL33K8Vx GenWL3.menu.pnum.GENERIC_WL33K8VX.upload.maximum_size=65536 GenWL3.menu.pnum.GENERIC_WL33K8VX.upload.maximum_data_size=16384 GenWL3.menu.pnum.GENERIC_WL33K8VX.build.board=GENERIC_WL33K8VX -GenWL3.menu.pnum.GENERIC_WL33K8VX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33K8VX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33K8VX.build.variant=STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33K8VX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -35,7 +35,7 @@ GenWL3.menu.pnum.GENERIC_WL33K8VXX=Generic WL33K8VxX GenWL3.menu.pnum.GENERIC_WL33K8VXX.upload.maximum_size=65536 GenWL3.menu.pnum.GENERIC_WL33K8VXX.upload.maximum_data_size=16384 GenWL3.menu.pnum.GENERIC_WL33K8VXX.build.board=GENERIC_WL33K8VXX -GenWL3.menu.pnum.GENERIC_WL33K8VXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33K8VXX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33K8VXX.build.variant=STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33K8VXX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -44,7 +44,7 @@ GenWL3.menu.pnum.GENERIC_WL33KBVX=Generic WL33KBVx GenWL3.menu.pnum.GENERIC_WL33KBVX.upload.maximum_size=131072 GenWL3.menu.pnum.GENERIC_WL33KBVX.upload.maximum_data_size=32768 GenWL3.menu.pnum.GENERIC_WL33KBVX.build.board=GENERIC_WL33KBVX -GenWL3.menu.pnum.GENERIC_WL33KBVX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33KBVX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33KBVX.build.variant=STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33KBVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -53,7 +53,7 @@ GenWL3.menu.pnum.GENERIC_WL33KBVXX=Generic WL33KBVxX GenWL3.menu.pnum.GENERIC_WL33KBVXX.upload.maximum_size=131072 GenWL3.menu.pnum.GENERIC_WL33KBVXX.upload.maximum_data_size=32768 GenWL3.menu.pnum.GENERIC_WL33KBVXX.build.board=GENERIC_WL33KBVXX -GenWL3.menu.pnum.GENERIC_WL33KBVXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33KBVXX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33KBVXX.build.variant=STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33KBVXX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -62,7 +62,7 @@ GenWL3.menu.pnum.GENERIC_WL33KCVX=Generic WL33KCVx GenWL3.menu.pnum.GENERIC_WL33KCVX.upload.maximum_size=262144 GenWL3.menu.pnum.GENERIC_WL33KCVX.upload.maximum_data_size=32768 GenWL3.menu.pnum.GENERIC_WL33KCVX.build.board=GENERIC_WL33KCVX -GenWL3.menu.pnum.GENERIC_WL33KCVX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33KCVX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33KCVX.build.variant=STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33KCVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -71,7 +71,7 @@ GenWL3.menu.pnum.GENERIC_WL33KCVXX=Generic WL33KCVxX GenWL3.menu.pnum.GENERIC_WL33KCVXX.upload.maximum_size=262144 GenWL3.menu.pnum.GENERIC_WL33KCVXX.upload.maximum_data_size=32768 GenWL3.menu.pnum.GENERIC_WL33KCVXX.build.board=GENERIC_WL33KCVXX -GenWL3.menu.pnum.GENERIC_WL33KCVXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33KCVXX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33KCVXX.build.variant=STM32WL3x/WL31K(8-B)V_WL33K(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33KCVXX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd diff --git a/variants/STM32WL3x/WL33C(8-B-C)Vx(X)/boards_entry.txt b/variants/STM32WL3x/WL33C(8-B-C)Vx(X)/boards_entry.txt index fafd83d986..9f9c7973e6 100644 --- a/variants/STM32WL3x/WL33C(8-B-C)Vx(X)/boards_entry.txt +++ b/variants/STM32WL3x/WL33C(8-B-C)Vx(X)/boards_entry.txt @@ -8,7 +8,7 @@ GenWL3.menu.pnum.GENERIC_WL33C8VX=Generic WL33C8Vx GenWL3.menu.pnum.GENERIC_WL33C8VX.upload.maximum_size=65536 GenWL3.menu.pnum.GENERIC_WL33C8VX.upload.maximum_data_size=16384 GenWL3.menu.pnum.GENERIC_WL33C8VX.build.board=GENERIC_WL33C8VX -GenWL3.menu.pnum.GENERIC_WL33C8VX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33C8VX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33C8VX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33C8VX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -17,7 +17,7 @@ GenWL3.menu.pnum.GENERIC_WL33C8VXX=Generic WL33C8VxX GenWL3.menu.pnum.GENERIC_WL33C8VXX.upload.maximum_size=65536 GenWL3.menu.pnum.GENERIC_WL33C8VXX.upload.maximum_data_size=16384 GenWL3.menu.pnum.GENERIC_WL33C8VXX.build.board=GENERIC_WL33C8VXX -GenWL3.menu.pnum.GENERIC_WL33C8VXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33C8VXX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33C8VXX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33C8VXX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -26,7 +26,7 @@ GenWL3.menu.pnum.GENERIC_WL33CBVX=Generic WL33CBVx GenWL3.menu.pnum.GENERIC_WL33CBVX.upload.maximum_size=131072 GenWL3.menu.pnum.GENERIC_WL33CBVX.upload.maximum_data_size=32768 GenWL3.menu.pnum.GENERIC_WL33CBVX.build.board=GENERIC_WL33CBVX -GenWL3.menu.pnum.GENERIC_WL33CBVX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33CBVX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33CBVX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33CBVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -35,7 +35,7 @@ GenWL3.menu.pnum.GENERIC_WL33CBVXX=Generic WL33CBVxX GenWL3.menu.pnum.GENERIC_WL33CBVXX.upload.maximum_size=131072 GenWL3.menu.pnum.GENERIC_WL33CBVXX.upload.maximum_data_size=32768 GenWL3.menu.pnum.GENERIC_WL33CBVXX.build.board=GENERIC_WL33CBVXX -GenWL3.menu.pnum.GENERIC_WL33CBVXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33CBVXX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33CBVXX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33CBVXX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -44,7 +44,7 @@ GenWL3.menu.pnum.GENERIC_WL33CCVX=Generic WL33CCVx GenWL3.menu.pnum.GENERIC_WL33CCVX.upload.maximum_size=262144 GenWL3.menu.pnum.GENERIC_WL33CCVX.upload.maximum_data_size=32768 GenWL3.menu.pnum.GENERIC_WL33CCVX.build.board=GENERIC_WL33CCVX -GenWL3.menu.pnum.GENERIC_WL33CCVX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33CCVX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33CCVX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33CCVX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd @@ -53,7 +53,7 @@ GenWL3.menu.pnum.GENERIC_WL33CCVXX=Generic WL33CCVxX GenWL3.menu.pnum.GENERIC_WL33CCVXX.upload.maximum_size=262144 GenWL3.menu.pnum.GENERIC_WL33CCVXX.upload.maximum_data_size=32768 GenWL3.menu.pnum.GENERIC_WL33CCVXX.build.board=GENERIC_WL33CCVXX -GenWL3.menu.pnum.GENERIC_WL33CCVXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL33CCVXX.build.product_line=STM32WL3XX GenWL3.menu.pnum.GENERIC_WL33CCVXX.build.variant=STM32WL3x/WL33C(8-B-C)Vx(X) GenWL3.menu.pnum.GENERIC_WL33CCVXX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WL3x/STM32WL33.svd diff --git a/variants/STM32WL3x/WL3RK(8-B)Vx(X)/boards_entry.txt b/variants/STM32WL3x/WL3RK(8-B)Vx(X)/boards_entry.txt index d22daf3c07..fafcbf8632 100644 --- a/variants/STM32WL3x/WL3RK(8-B)Vx(X)/boards_entry.txt +++ b/variants/STM32WL3x/WL3RK(8-B)Vx(X)/boards_entry.txt @@ -8,7 +8,7 @@ GenWL3.menu.pnum.GENERIC_WL3RK8VX=Generic WL3RK8Vx GenWL3.menu.pnum.GENERIC_WL3RK8VX.upload.maximum_size=65536 GenWL3.menu.pnum.GENERIC_WL3RK8VX.upload.maximum_data_size=8192 GenWL3.menu.pnum.GENERIC_WL3RK8VX.build.board=GENERIC_WL3RK8VX -GenWL3.menu.pnum.GENERIC_WL3RK8VX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL3RK8VX.build.product_line=STM32WL3RX GenWL3.menu.pnum.GENERIC_WL3RK8VX.build.variant=STM32WL3x/WL3RK(8-B)Vx(X) # Generic WL3RK8VxX @@ -16,7 +16,7 @@ GenWL3.menu.pnum.GENERIC_WL3RK8VXX=Generic WL3RK8VxX GenWL3.menu.pnum.GENERIC_WL3RK8VXX.upload.maximum_size=65536 GenWL3.menu.pnum.GENERIC_WL3RK8VXX.upload.maximum_data_size=8192 GenWL3.menu.pnum.GENERIC_WL3RK8VXX.build.board=GENERIC_WL3RK8VXX -GenWL3.menu.pnum.GENERIC_WL3RK8VXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL3RK8VXX.build.product_line=STM32WL3RX GenWL3.menu.pnum.GENERIC_WL3RK8VXX.build.variant=STM32WL3x/WL3RK(8-B)Vx(X) # Generic WL3RKBVx @@ -24,7 +24,7 @@ GenWL3.menu.pnum.GENERIC_WL3RKBVX=Generic WL3RKBVx GenWL3.menu.pnum.GENERIC_WL3RKBVX.upload.maximum_size=131072 GenWL3.menu.pnum.GENERIC_WL3RKBVX.upload.maximum_data_size=16384 GenWL3.menu.pnum.GENERIC_WL3RKBVX.build.board=GENERIC_WL3RKBVX -GenWL3.menu.pnum.GENERIC_WL3RKBVX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL3RKBVX.build.product_line=STM32WL3RX GenWL3.menu.pnum.GENERIC_WL3RKBVX.build.variant=STM32WL3x/WL3RK(8-B)Vx(X) # Generic WL3RKBVxX @@ -32,6 +32,6 @@ GenWL3.menu.pnum.GENERIC_WL3RKBVXX=Generic WL3RKBVxX GenWL3.menu.pnum.GENERIC_WL3RKBVXX.upload.maximum_size=131072 GenWL3.menu.pnum.GENERIC_WL3RKBVXX.upload.maximum_data_size=16384 GenWL3.menu.pnum.GENERIC_WL3RKBVXX.build.board=GENERIC_WL3RKBVXX -GenWL3.menu.pnum.GENERIC_WL3RKBVXX.build.product_line=STM32WL3xx +GenWL3.menu.pnum.GENERIC_WL3RKBVXX.build.product_line=STM32WL3RX GenWL3.menu.pnum.GENERIC_WL3RKBVXX.build.variant=STM32WL3x/WL3RK(8-B)Vx(X) From e42ffb469939d37616f579bd63c1142eacf24ffe Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 27 Nov 2025 16:39:54 +0100 Subject: [PATCH 09/10] system(wl3): update STM32WL3x system Signed-off-by: Frederic Pillon --- system/STM32WL3x/system_stm32wl3x.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/system/STM32WL3x/system_stm32wl3x.c b/system/STM32WL3x/system_stm32wl3x.c index 4f48cbf259..3d000f3baa 100644 --- a/system/STM32WL3x/system_stm32wl3x.c +++ b/system/STM32WL3x/system_stm32wl3x.c @@ -101,7 +101,7 @@ /*!< HW TRIMMING Defines */ #define VALIDITY_TAG 0xFCBCECCC /*!< TAG to validate the content of the - trimming area content. */ + trimming area content. */ #define VALIDITY_LOCATION 0x10001EF8 /*!< ROM address of the the validity trimming values content. */ /*!< SMPS Configuration Defines */ @@ -148,13 +148,13 @@ /* The RAM_VR variable is a mirroring in RAM of some registers information. It is a sort of virtual register in RAM. */ -#if defined ( __ICCARM__ ) +#if defined(__ICCARM__) #pragma location=".ram_vr" __root __no_init RAM_VR_TypeDef RAM_VR; #else -#if defined ( __ARMCC_VERSION ) +#if defined(__ARMCC_VERSION) __attribute__((section(".bss" ".ram_vr"))) -#elif defined ( __GNUC__ ) +#elif defined(__GNUC__) __attribute__((section(".ram_vr"))) #endif RAM_VR_TypeDef RAM_VR __attribute__((used)); @@ -182,7 +182,6 @@ void CPUcontextRestore(void); * @param None * @retval None */ - void SystemInit(void) { uint32_t mainRegulator, smpsOutVoltage, lsiBw, hsiCalib; @@ -194,7 +193,8 @@ void SystemInit(void) RAM_VR.WakeupFromSleepFlag = 1; /* A wakeup from power save occurred */ CPUcontextRestore(); /* Restore the context */ /* if the context restore worked properly, we should never return here */ - while(1) { + while(1) + { NVIC_SystemReset(); } } From dd4046d00ff75897a598554fa02829a60cd93b33 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 27 Nov 2025 16:59:27 +0100 Subject: [PATCH 10/10] chore(cmake): update database Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 262 +++++++++++++++++- .../CMakeLists.txt | 31 +++ .../CMakeLists.txt | 1 + .../STM32WL3x/WL3RK(8-B)Vx(X)/CMakeLists.txt | 31 +++ 4 files changed, 317 insertions(+), 8 deletions(-) create mode 100644 variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/CMakeLists.txt create mode 100644 variants/STM32WL3x/WL3RK(8-B)Vx(X)/CMakeLists.txt diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index a5223248c9..36baf1a8c7 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -81104,6 +81104,88 @@ target_compile_options(GENERIC_H745XIHX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H745ZGTX +# ----------------------------------------------------------------------------- + +set(GENERIC_H745ZGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H745Z(G-I)T_H755ZIT") +set(GENERIC_H745ZGTX_MAXSIZE 1048576) +set(GENERIC_H745ZGTX_MAXDATASIZE 884736) +set(GENERIC_H745ZGTX_MCU cortex-m7) +set(GENERIC_H745ZGTX_FPCONF "-") +add_library(GENERIC_H745ZGTX INTERFACE) +target_compile_options(GENERIC_H745ZGTX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H745xG" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H745ZGTX_MCU} +) +target_compile_definitions(GENERIC_H745ZGTX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H745ZGTX" + "BOARD_NAME=\"GENERIC_H745ZGTX\"" + "BOARD_ID=GENERIC_H745ZGTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H745ZGTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H745ZGTX_VARIANT_PATH} +) + +target_link_options(GENERIC_H745ZGTX INTERFACE + "LINKER:--default-script=${GENERIC_H745ZGTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=884736" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H745ZGTX_MCU} +) + +add_library(GENERIC_H745ZGTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H745ZGTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H745ZGTX_serial_generic INTERFACE) +target_compile_options(GENERIC_H745ZGTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H745ZGTX_serial_none INTERFACE) +target_compile_options(GENERIC_H745ZGTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H745ZGTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H745ZGTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H745ZGTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H745ZGTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H745ZGTX_usb_HID INTERFACE) +target_compile_options(GENERIC_H745ZGTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H745ZGTX_usb_none INTERFACE) +target_compile_options(GENERIC_H745ZGTX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H745ZGTX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H745ZGTX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H745ZGTX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H745ZGTX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H745ZGTX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H745ZGTX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H745ZITX # ----------------------------------------------------------------------------- @@ -82662,6 +82744,88 @@ target_compile_options(GENERIC_H755XIHX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H755ZITX +# ----------------------------------------------------------------------------- + +set(GENERIC_H755ZITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H745Z(G-I)T_H755ZIT") +set(GENERIC_H755ZITX_MAXSIZE 2097152) +set(GENERIC_H755ZITX_MAXDATASIZE 884736) +set(GENERIC_H755ZITX_MCU cortex-m7) +set(GENERIC_H755ZITX_FPCONF "-") +add_library(GENERIC_H755ZITX INTERFACE) +target_compile_options(GENERIC_H755ZITX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H755xx" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H755ZITX_MCU} +) +target_compile_definitions(GENERIC_H755ZITX INTERFACE + "STM32H7xx" + "ARDUINO_GENERIC_H755ZITX" + "BOARD_NAME=\"GENERIC_H755ZITX\"" + "BOARD_ID=GENERIC_H755ZITX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H755ZITX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${GENERIC_H755ZITX_VARIANT_PATH} +) + +target_link_options(GENERIC_H755ZITX INTERFACE + "LINKER:--default-script=${GENERIC_H755ZITX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=884736" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H755ZITX_MCU} +) + +add_library(GENERIC_H755ZITX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H755ZITX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H755ZITX_serial_generic INTERFACE) +target_compile_options(GENERIC_H755ZITX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H755ZITX_serial_none INTERFACE) +target_compile_options(GENERIC_H755ZITX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H755ZITX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H755ZITX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H755ZITX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H755ZITX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H755ZITX_usb_HID INTERFACE) +target_compile_options(GENERIC_H755ZITX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H755ZITX_usb_none INTERFACE) +target_compile_options(GENERIC_H755ZITX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H755ZITX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H755ZITX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H755ZITX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H755ZITX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H755ZITX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H755ZITX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H757AIIX # ----------------------------------------------------------------------------- @@ -107712,7 +107876,7 @@ set(GENERIC_WL33C8VX_MCU cortex-m0plus) set(GENERIC_WL33C8VX_FPCONF "-") add_library(GENERIC_WL33C8VX INTERFACE) target_compile_options(GENERIC_WL33C8VX INTERFACE - "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" "SHELL:" "SHELL:" "SHELL: " @@ -107766,7 +107930,7 @@ set(GENERIC_WL33C8VXX_MCU cortex-m0plus) set(GENERIC_WL33C8VXX_FPCONF "-") add_library(GENERIC_WL33C8VXX INTERFACE) target_compile_options(GENERIC_WL33C8VXX INTERFACE - "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" "SHELL:" "SHELL:" "SHELL: " @@ -107820,7 +107984,7 @@ set(GENERIC_WL33CBVX_MCU cortex-m0plus) set(GENERIC_WL33CBVX_FPCONF "-") add_library(GENERIC_WL33CBVX INTERFACE) target_compile_options(GENERIC_WL33CBVX INTERFACE - "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" "SHELL:" "SHELL:" "SHELL: " @@ -107874,7 +108038,7 @@ set(GENERIC_WL33CBVXX_MCU cortex-m0plus) set(GENERIC_WL33CBVXX_FPCONF "-") add_library(GENERIC_WL33CBVXX INTERFACE) target_compile_options(GENERIC_WL33CBVXX INTERFACE - "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" "SHELL:" "SHELL:" "SHELL: " @@ -107928,7 +108092,7 @@ set(GENERIC_WL33CCVX_MCU cortex-m0plus) set(GENERIC_WL33CCVX_FPCONF "-") add_library(GENERIC_WL33CCVX INTERFACE) target_compile_options(GENERIC_WL33CCVX INTERFACE - "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" "SHELL:" "SHELL:" "SHELL: " @@ -107982,7 +108146,7 @@ set(GENERIC_WL33CCVXX_MCU cortex-m0plus) set(GENERIC_WL33CCVXX_FPCONF "-") add_library(GENERIC_WL33CCVXX INTERFACE) target_compile_options(GENERIC_WL33CCVXX INTERFACE - "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" "SHELL:" "SHELL:" "SHELL: " @@ -115344,7 +115508,7 @@ set(NUCLEO_WL33CC1_MCU cortex-m0plus) set(NUCLEO_WL33CC1_FPCONF "-") add_library(NUCLEO_WL33CC1 INTERFACE) target_compile_options(NUCLEO_WL33CC1 INTERFACE - "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" "SHELL:" "SHELL:" "SHELL: " @@ -115426,7 +115590,7 @@ set(NUCLEO_WL33CC2_MCU cortex-m0plus) set(NUCLEO_WL33CC2_FPCONF "-") add_library(NUCLEO_WL33CC2 INTERFACE) target_compile_options(NUCLEO_WL33CC2 INTERFACE - "SHELL:-DSTM32WL3xx -D__CORTEX_SC=0" + "SHELL:-DSTM32WL3XX -D__CORTEX_SC=0" "SHELL:" "SHELL:" "SHELL: " @@ -119212,6 +119376,88 @@ target_compile_options(WEACT_H562RG_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# WeActMiniH723VGTX +# ----------------------------------------------------------------------------- + +set(WeActMiniH723VGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)") +set(WeActMiniH723VGTX_MAXSIZE 1048576) +set(WeActMiniH723VGTX_MAXDATASIZE 327680) +set(WeActMiniH723VGTX_MCU cortex-m7) +set(WeActMiniH723VGTX_FPCONF "-") +add_library(WeActMiniH723VGTX INTERFACE) +target_compile_options(WeActMiniH723VGTX INTERFACE + "SHELL:-DCORE_CM7 -DSTM32H723xx" + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${WeActMiniH723VGTX_MCU} +) +target_compile_definitions(WeActMiniH723VGTX INTERFACE + "STM32H7xx" + "ARDUINO_WeActMiniH723VGTX" + "BOARD_NAME=\"WeActMiniH723VGTX\"" + "BOARD_ID=WeActMiniH723VGTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(WeActMiniH723VGTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H7xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H7xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/ + ${WeActMiniH723VGTX_VARIANT_PATH} +) + +target_link_options(WeActMiniH723VGTX INTERFACE + "LINKER:--default-script=${WeActMiniH723VGTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=327680" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${WeActMiniH723VGTX_MCU} +) + +add_library(WeActMiniH723VGTX_serial_disabled INTERFACE) +target_compile_options(WeActMiniH723VGTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(WeActMiniH723VGTX_serial_generic INTERFACE) +target_compile_options(WeActMiniH723VGTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(WeActMiniH723VGTX_serial_none INTERFACE) +target_compile_options(WeActMiniH723VGTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(WeActMiniH723VGTX_usb_CDC INTERFACE) +target_compile_options(WeActMiniH723VGTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(WeActMiniH723VGTX_usb_CDCgen INTERFACE) +target_compile_options(WeActMiniH723VGTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(WeActMiniH723VGTX_usb_HID INTERFACE) +target_compile_options(WeActMiniH723VGTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(WeActMiniH723VGTX_usb_none INTERFACE) +target_compile_options(WeActMiniH723VGTX_usb_none INTERFACE + "SHELL:" +) +add_library(WeActMiniH723VGTX_xusb_FS INTERFACE) +target_compile_options(WeActMiniH723VGTX_xusb_FS INTERFACE + "SHELL:" +) +add_library(WeActMiniH723VGTX_xusb_HS INTERFACE) +target_compile_options(WeActMiniH723VGTX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(WeActMiniH723VGTX_xusb_HSFS INTERFACE) +target_compile_options(WeActMiniH723VGTX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # WeActMiniH743VITX # ----------------------------------------------------------------------------- diff --git a/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/CMakeLists.txt b/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32H5xx/H563I(G-I)(K-T)_H563LIHxQ_H573II(K-T)_H573LIHxQ/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/CMakeLists.txt b/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/CMakeLists.txt index 2a4d55b6b1..508670a5ed 100644 --- a/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/CMakeLists.txt +++ b/variants/STM32H7xx/H723V(E-G)(H-T)_H730VB(H-T)_H733VG(H-T)/CMakeLists.txt @@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c variant_generic.cpp + variant_WeActMiniH723VGTX.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) diff --git a/variants/STM32WL3x/WL3RK(8-B)Vx(X)/CMakeLists.txt b/variants/STM32WL3x/WL3RK(8-B)Vx(X)/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32WL3x/WL3RK(8-B)Vx(X)/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) +