diff --git a/svd/STM32WL3x/STM32WL30.svd b/svd/STM32WL3x/STM32WL30.svd new file mode 100644 index 0000000..b1d3555 --- /dev/null +++ b/svd/STM32WL3x/STM32WL30.svd @@ -0,0 +1,25841 @@ + + + + STM32WL30 + 0.1 + STM32WL30 + + CM0+ + r0p0 + little + true + false + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + AES + AES + 0x48900000 + + 0x0 + 0x60 + registers + + + AES + AES interrupt + 13 + + + + AES_CR + AES_CR + AES_CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + EN + EN: AES IP enable + + 0 + 1 + read-write + + + DATATYPE + DATATYPE[1:0]: Data type selection + + 1 + 2 + read-write + + + MODE + MODE[1:0]: AES operating mode + + 3 + 2 + read-write + + + CHMOD_1_0 + CHMOD[1:0]: AES Chaining Mode selection + + 5 + 2 + read-write + + + CCFC + CCFC: Computation Complete Flag Clear + + 7 + 1 + read-write + + + ERRC + ERRC: Error clear + + 8 + 1 + read-write + + + CCFIE + CCFIE: CCF Flag Interrupt Enable + + 9 + 1 + read-write + + + ERRIE + ERRIE: Error Interrupt Enable + + 10 + 1 + read-write + + + DMAINEN + DMAINEN: DMA Input Enable + + 11 + 1 + read-write + + + DMAOUTEN + DMAOUTEN: DMA Output Enable + + 12 + 1 + read-write + + + GCMPH + GCMPH[1:0]: GCM or CCM Phase selection + + 13 + 2 + read-write + + + CHMOD_2 + CHMOD[2]: Chaining mode selection, bit [2] + + 16 + 1 + read-write + + + KEYSIZE + KEYSIZE: Key Size selection. + 18 + 1 + read-write + + + NPBLB + NPBLB: Number of Padding Bytes in Last Block of payload. + 20 + 4 + read-write + + + + + AES_SR + AES_SR + AES_SR register + 0x04 + 0x20 + read-only + 0x00000000 + + + CCF + CCF: Computation complete flag + + 0 + 1 + read-only + + + RDERR + RDERR: Read error flag + + 1 + 1 + read-only + + + WRERR + WRERR: Write error flag + + 2 + 1 + read-only + + + BUSY + BUSY: Busy flag + + 3 + 1 + read-only + + + + + AES_DINR + AES_DINR + AES_DINR register + 0x08 + 0x20 + read-write + 0x00000000 + + + DINR + DINR[x+31:x]: One of four 32-bit words of a 128-bit input data block being written into the peripheral + + 0 + 32 + read-write + + + + + AES_DOUTR + AES_DOUTR + AES_DOUTR register + 0x0C + 0x20 + read-only + 0x00000000 + + + DOUTR + DOUTR[x+31:x]: One of four 32-bit words of a 128-bit output data block being read from the + + 0 + 32 + read-only + + + + + AES_KEYR0 + AES_KEYR0 + AES_KEYRx register + 0x10 + 0x20 + read-write + 0x00000000 + + + KEY + KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)] + + 0 + 32 + read-write + + + + + AES_KEYR1 + AES_KEYR1 + AES_KEYRx register + 0x14 + 0x20 + read-write + 0x00000000 + + + KEY + KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)] + + 0 + 32 + read-write + + + + + AES_KEYR2 + AES_KEYR2 + AES_KEYRx register + 0x18 + 0x20 + read-write + 0x00000000 + + + KEY + KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)] + + 0 + 32 + read-write + + + + + AES_KEYR3 + AES_KEYR3 + AES_KEYRx register + 0x1C + 0x20 + read-write + 0x00000000 + + + KEY + KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)] + + 0 + 32 + read-write + + + + + AES_IVR0 + AES_IVR0 + AES_IVRx register + 0x20 + 0x20 + read-write + 0x00000000 + + + IVI + IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]) + + 0 + 32 + read-write + + + + + AES_IVR1 + AES_IVR1 + AES_IVRx register + 0x24 + 0x20 + read-write + 0x00000000 + + + IVI + IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]) + + 0 + 32 + read-write + + + + + AES_IVR2 + AES_IVR2 + AES_IVRx register + 0x28 + 0x20 + read-write + 0x00000000 + + + IVI + IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]) + + 0 + 32 + read-write + + + + + AES_IVR3 + AES_IVR3 + AES_IVRx register + 0x2C + 0x20 + read-write + 0x00000000 + + + IVI + IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]) + + 0 + 32 + read-write + + + + + + + CRC + CRC + 0x48200000 + + 0x0 + 0x18 + registers + + + + CRC_DR + CRC_DR + CRC_DR register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits. +This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. +If the data size is less than 32 bits, the least significant bits are used to write/read the +correct value. + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC_IDR register + 0x04 + 0x20 + read-write + 0x00000000 + + + IDR + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC_CR register + 0x08 + 0x20 + read-write + 0x00000000 + + + RESET + RESET bit +This bit is set by software to reset the CRC calculation unit and set the data register to the value +stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware + 0 + 1 + read-write + + + POLYSIZE + Polynomial size +These bits control the size of the polynomial. +-00: 32 bit polynomial +-01: 16 bit polynomial +-10: 8 bit polynomial +-11: 7 bit polynomial + 3 + 2 + read-write + + + REV_IN + Reverse input data +These bits control the reversal of the bit order of the input data +-00: Bit order not affected +-01: Bit reversal done by byte +-10: Bit reversal done by half-word +-11: Bit reversal done by word + 5 + 2 + read-write + + + REV_OUT + Reverse output data +This bit controls the reversal of the bit order of the output data. +-0: Bit order not affected +-1: Bit-reversed output format + 7 + 1 + read-write + + + + + CRC_INIT + CRC_INIT + CRC_INIT register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + INIT + Programmable initial CRC value +This register is used to write the CRC initial value. + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC_POL register + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + POL + POL[31:0]: Programmable polynomial +This register is used to write the coefficients of the polynomial to be used for CRC calculation. +If the polynomial size is less than 32 bits, the least significant bits have to be used to program the +correct value. + 0 + 32 + read-write + + + + + + + DBGMCU + DBGMCU + 0x40008000 + + 0x0 + 0xC + registers + + + + CR + CR + CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + DBG_SLEEP + Allow debug of the CPU in SLEEP mode +- 0: Normal operation. All clocks will be disabled automatically in SLEEP mode +- 1: Automatic clock stop disabled. All active CPU clocks and oscillators will continue to run during SLEEP mode, allowing full CPU debug capability. On exit from SLEEP mode, the clock settings will be set to the SLEEP mode exit state. + 0 + 1 + read-write + + + DBG_STOP + Allow debug of the CPU in DEEPSTOP mode +- 0: Normal operation. All clocks will be disabled automatically in STOP mode +- 1: Automatic clock stop disabled. All active CPU clocks and oscillators will continue to run during STOP mode, allowing full CPU debug capability. On exit from STOP mode, the clock settings will be set to the STOP mode exit state. + 1 + 1 + read-write + + + + + DBG_APB0_FZ + DBG_APB0_FZ + DBG_APB0_FZ register + 0x04 + 0x20 + read-write + 0x00000000 + + + DBG_TIM2_STOP + TIM2 stop in the CPU debug +- 0: Normal operation. TIM2 continues to operate while the CPU is in debug mode +- 1: Stop in debug. TIM2 is frozen while the CPU is in debug mode. + 0 + 1 + read-write + + + DBG_TIM16_STOP + TIM16 stop in the CPU debug +- 0: Normal operation. TIM16 continues to operate while the CPU is in debug mode +- 1: Stop in debug. TIM16 is frozen while the CPU is in debug mode. + 1 + 1 + read-write + + + DBG_RTC_STOP + RTC stop in CPU debug +- 0: Normal operation. RTC continues to operate while the CPU is in debug mode +- 1: Stop in debug. RTC is frozen while the CPU is in debug mode. + 12 + 1 + read-write + + + DBG_IWDG_STOP + IWDG stop in the CPU debug +- 0: Normal operation. IWDG continues to operate while the CPU is in debug mode +- 1: Stop in debug. IWDG is frozen while the CPU is in debug mode. + 14 + 1 + read-write + + + + + DBG_APB1_FZ + DBG_APB1_FZ + DBG_APB1_FZ register + 0x08 + 0x20 + read-write + 0x00000000 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout stop in CPU debug +- 0: Normal operation. I2C1 SMBUS timeout continues to operate while the CPU is in debug mode +- 1: Stop in debug. I2C1 SMBUS timeou is frozen while the CPU is in debug mode. + 21 + 1 + read-write + + + DBG_I2C2_STOP + I2C2 SMBUS timeout stop in CPU debug +- 0: Normal operation. I2C2 SMBUS timeout continues to operate while the CPU is in debug mode +- 1: Stop in debug. I2C2 SMBUS timeou is frozen while the CPU is in debug mode. + 23 + 1 + read-write + + + + + + + DMAMUX + DMAMUX address block description + DMAMUX + 0x48800000 + + 0x0 + 0x20 + registers + + + + C0CR + C0CR + CxCR register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C1CR + C1CR + CxCR register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C2CR + C2CR + CxCR register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C3CR + C3CR + CxCR register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C4CR + C4CR + CxCR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C5CR + C5CR + CxCR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C6CR + C6CR + CxCR register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C7CR + C7CR + CxCR register + 0x1C + 0x20 + read-write + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + + + DMA + DMA address block description + DMA + 0x48700000 + + 0x0 + 0xA4 + registers + + + DMA + DMA interrupt + 17 + + + + DMA_ISR + DMA_ISR + DMA_ISR register + 0x00 + 0x20 + read-only + 0x0000 + 0xFFFF + + + GIF1 + GIF1: Channel 1 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 1 + +1: A TE, HT or TC event occurred on channel 1 + 0 + 1 + read-only + + + TCIF1 + TCIF1: Channel 1 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 1 + +1: A transfer complete (TC) event occurred on channel 1 + 1 + 1 + read-only + + + HTIF1 + HTIF1: Channel 1 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 1 + +1: A half transfer (HT) event occurred on channel 1 + 2 + 1 + read-only + + + TE1F1 + TEIF1: Channel 1 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 1 + +1: A transfer error (TE) occurred on channel 1 + 3 + 1 + read-only + + + GIF2 + GIF2: Channel 2 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 2 + +1: A TE, HT or TC event occurred on channel 2 + 4 + 1 + read-only + + + TCIF2 + TCIF2: Channel 2 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 2 + +1: A transfer complete (TC) event occurred on channel 2 + 5 + 1 + read-only + + + HTIF2 + HTIF2: Channel 2 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 2 + +1: A half transfer (HT) event occurred on channel 2 + 6 + 1 + read-only + + + TE1F2 + TEIF2: Channel 2 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 2 + +1: A transfer error (TE) occurred on channel 2 + 7 + 1 + read-only + + + GIF3 + GIF3: Channel 3 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 3 + +1: A TE, HT or TC event occurred on channel 3 + 8 + 1 + read-only + + + TCIF3 + TCIF3: Channel 3 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 3 + +1: A transfer complete (TC) event occurred on channel 3 + 9 + 1 + read-only + + + HTIF3 + HTIF3: Channel 3 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 3 + +1: A half transfer (HT) event occurred on channel 3 + 10 + 1 + read-only + + + TE1F3 + TEIF3: Channel 3 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 3 + +1: A transfer error (TE) occurred on channel 3 + 11 + 1 + read-only + + + GIF4 + GIF4: Channel 4 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 4 + +1: A TE, HT or TC event occurred on channel 4 + 12 + 1 + read-only + + + TCIF4 + TCIF4: Channel 4 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 4 + +1: A transfer complete (TC) event occurred on channel 4 + 13 + 1 + read-only + + + HTIF4 + HTIF4: Channel 4 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 4 + +1: A half transfer (HT) event occurred on channel 4 + 14 + 1 + read-only + + + TE1F4 + TEIF4: Channel 4 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 4 + +1: A transfer error (TE) occurred on channel 4 + 15 + 1 + read-only + + + GIF5 + GIF5: Channel 5 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 5 + +1: A TE, HT or TC event occurred on channel 5 + 16 + 1 + read-only + + + TCIF5 + TCIF5: Channel 5 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 5 + +1: A transfer complete (TC) event occurred on channel 5 + 17 + 1 + read-only + + + HTIF5 + HTIF5: Channel 5 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 5 + +1: A half transfer (HT) event occurred on channel 5 + 18 + 1 + read-only + + + TE1F5 + TEIF5: Channel 5 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 5 + +1: A transfer error (TE) occurred on channel 5 + 19 + 1 + read-only + + + GIF6 + GIF6: Channel 6 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 6 + +1: A TE, HT or TC event occurred on channel 6 + 20 + 1 + read-only + + + TCIF6 + TCIF6: Channel 6 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 6 + +1: A transfer complete (TC) event occurred on channel 6 + 21 + 1 + read-only + + + HTIF6 + HTIF6: Channel 6 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 6 + +1: A half transfer (HT) event occurred on channel 6 + 22 + 1 + read-only + + + TE1F6 + TEIF6: Channel 6 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 6 + +1: A transfer error (TE) occurred on channel 6 + 23 + 1 + read-only + + + GIF7 + GIF7: Channel 7 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 7 + +1: A TE, HT or TC event occurred on channel 7 + 24 + 1 + read-only + + + TCIF7 + TCIF7: Channel 7 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 7 + +1: A transfer complete (TC) event occurred on channel 7 + 25 + 1 + read-only + + + HTIF7 + HTIF7: Channel 7 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 7 + +1: A half transfer (HT) event occurred on channel 7 + 26 + 1 + read-only + + + TE1F7 + TEIF7: Channel 7 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 7 + +1: A transfer error (TE) occurred on channel 7 + 27 + 1 + read-only + + + GIF8 + GIF8: Channel 8 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 8 + +1: A TE, HT or TC event occurred on channel 8 + 28 + 1 + read-only + + + TCIF8 + TCIF8: Channel 8 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 8 + +1: A transfer complete (TC) event occurred on channel 8 + 29 + 1 + read-only + + + HTIF8 + HTIF8: Channel 8 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 8 + +1: A half transfer (HT) event occurred on channel 8 + 30 + 1 + read-only + + + TE1F8 + TEIF8: Channel 8 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 8 + +1: A transfer error (TE) occurred on channel 8 + 31 + 1 + read-only + + + + + DMA_IFCR + DMA_IFCR + DMA_IFCR register + 0x04 + 0x20 + write-only + 0x0000 + 0xFFFF + + + CGIF1 + CGIF1: Channel 1 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 0 + 1 + write-only + + + CTCIF1 + CTCIF1: Channel 1 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 1 + 1 + write-only + + + CHTIF1 + CHTIF1: Channel 1 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 2 + 1 + write-only + + + CTEIF1 + CTEIF1: Channel 1 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 3 + 1 + write-only + + + CGIF2 + CGIF2: Channel 2 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 4 + 1 + write-only + + + CTCIF2 + CTCIF2: Channel 2 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 5 + 1 + write-only + + + CHTIF2 + CHTIF2: Channel 2 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 6 + 1 + write-only + + + CTEIF2 + CTEIF2: Channel 2 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 7 + 1 + write-only + + + CGIF3 + CGIF3: Channel 3 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 8 + 1 + write-only + + + CTCIF3 + CTCIF3: Channel 3 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 9 + 1 + write-only + + + CHTIF3 + CHTIF3: Channel 3 half transfer clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 10 + 1 + write-only + + + CTEIF3 + CTEIF3: Channel 3 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 11 + 1 + write-only + + + CGIF4 + CGIF4: Channel 4 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 12 + 1 + write-only + + + CTCIF4 + CTCIF4: Channel 4 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 13 + 1 + write-only + + + CHTIF4 + CHTIF4: Channel 4 half transfer clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 14 + 1 + write-only + + + CTEIF4 + CTEIF4: Channel 4 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 15 + 1 + write-only + + + CGIF5 + CGIF5: Channel 5 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 16 + 1 + write-only + + + CTCIF5 + CTCIF5: Channel 5 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 17 + 1 + write-only + + + CHTIF5 + CHTIF5: Channel 5 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 18 + 1 + write-only + + + CTEIF5 + CTEIF5: Channel 5 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 19 + 1 + write-only + + + CGIF6 + CGIF6: Channel 6 global interrupt clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 20 + 1 + write-only + + + CTCIF6 + CTCIF6: Channel 6 transfer complete clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 21 + 1 + write-only + + + CHTIF6 + CHTIF6: Channel 6 half transfer clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 22 + 1 + write-only + + + CTEIF6 + CTEIF6: Channel 6 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 23 + 1 + write-only + + + CGIF7 + CGIF7: Channel 7 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 24 + 1 + write-only + + + CTCIF7 + CTCIF7: Channel 7 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 25 + 1 + write-only + + + CHTIF7 + CHTIF7: Channel 7 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 26 + 1 + write-only + + + CTEIF7 + CTEIF7: Channel 7 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 27 + 1 + write-only + + + CGIF8 + CGIF8: Channel 8 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 28 + 1 + write-only + + + CTCIF8 + CTCIF8: Channel 8 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 29 + 1 + write-only + + + CHTIF8 + CHTIF8: Channel 8 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 30 + 1 + write-only + + + CTEIF8 + CTEIF8: Channel 8 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 31 + 1 + write-only + + + + + DMA_CCR1 + DMA_CCR1 + DMA_CCRx register + 0x08 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR1 + DMA_CNDTR1 + DMA_CNDTRx register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR1 + DMA_CPAR1 + DMA_CPARx register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR1 + DMA_CMAR1 + DMA_CMARx register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR2 + DMA_CCR2 + DMA_CCRx register + 0x1C + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR2 + DMA_CNDTR2 + DMA_CNDTRx register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR2 + DMA_CPAR2 + DMA_CPARx register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR2 + DMA_CMAR2 + DMA_CMARx register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR3 + DMA_CCR3 + DMA_CCRx register + 0x30 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR3 + DMA_CNDTR3 + DMA_CNDTRx register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR3 + DMA_CPAR3 + DMA_CPARx register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR3 + DMA_CMAR3 + DMA_CMARx register + 0x3C + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR4 + DMA_CCR4 + DMA_CCRx register + 0x44 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR4 + DMA_CNDTR4 + DMA_CNDTRx register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR4 + DMA_CPAR4 + DMA_CPARx register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR4 + DMA_CMAR4 + DMA_CMARx register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR5 + DMA_CCR5 + DMA_CCRx register + 0x58 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR5 + DMA_CNDTR5 + DMA_CNDTRx register + 0x5C + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR5 + DMA_CPAR5 + DMA_CPARx register + 0x60 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR5 + DMA_CMAR5 + DMA_CMARx register + 0x64 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR6 + DMA_CCR6 + DMA_CCRx register + 0x6C + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR6 + DMA_CNDTR6 + DMA_CNDTRx register + 0x70 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR6 + DMA_CPAR6 + DMA_CPARx register + 0x74 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR6 + DMA_CMAR6 + DMA_CMARx register + 0x78 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR7 + DMA_CCR7 + DMA_CCRx register + 0x80 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR7 + DMA_CNDTR7 + DMA_CNDTRx register + 0x84 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR7 + DMA_CPAR7 + DMA_CPARx register + 0x88 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR7 + DMA_CMAR7 + DMA_CMARx register + 0x8C + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR8 + DMA_CCR8 + DMA_CCRx register + 0x94 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR8 + DMA_CNDTR8 + DMA_CNDTRx register + 0x98 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR8 + DMA_CPAR8 + DMA_CPARx register + 0x9C + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR8 + DMA_CMAR8 + DMA_CMARx register + 0xA0 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + + + DYNAMIC_REG + DYNAMIC_REG + 0x49000500 + + 0x0 + 0x40 + registers + + + + PCKTLEN_CONFIG + PCKTLEN_CONFIG + PCKTLEN_CONFIG register + 0x0 + 0x20 + read-write + 0x00000014 + + + PCKTLEN + This bit field has different meanings/usages: + + 0 + 16 + read-write + + + + + MOD0_CONFIG + MOD0_CONFIG + MOD0_CONFIG register + 0x4 + 0x20 + read-write + 0x00083A93 + + + DATARATE_M + The mantissa of the specified data rate (default: 38. + 0 + 16 + read-write + + + DATARATE_E + The exponent of the specified data rate (default: 38. + 16 + 4 + read-write + + + MOD_TYPE + Select the modulation type + + 20 + 3 + read-write + + + CONST_MAP + Also known as FOUR_GFSK_CONST_MAP + + 24 + 2 + read-write + + + BT_SEL + Select BT value for GFSK + + 26 + 1 + read-write + + + PA_CLKON_LOCKONTX + Enable the clock on analog PA in LOCKONTX state + + 31 + 1 + read-write + + + + + MOD1_CONFIG + MOD1_CONFIG + MOD1_CONFIG register + 0x8 + 0x20 + read-write + 0x00400435 + + + FDEV_M + Mantissa of the frequency deviation (default: 28. + 0 + 8 + read-write + + + FDEV_E + Exponent of the frequency deviation (default: 28. + 8 + 4 + read-write + + + CHFLT_M + Mantissa of the channel filter BW (default: 100 kHz) + 16 + 4 + read-write + + + CHFLT_E + Exponent of the channel filter BW (default: 100 kHz) + 20 + 4 + read-write + + + + + SNYTH_FREQ + SNYTH_FREQ + SNYTH_FREQ register + 0xc + 0x20 + read-write + 0x04851615 + + + SYNTH_FRAC + Fractional part of the PLL fractional divide factor (default: 868 MHz, XTAL: 48 MHz) + 0 + 20 + read-write + + + SYNTH_INT + PLL integer divide factor (default: 868 MHz, XTAL: 48 MHz) + 20 + 8 + read-write + + + BS + Synthesizer band selector, i. + 30 + 1 + read-write + + + + + VCO_CAL_CONFIG + VCO_CAL_CONFIG + VCO_CAL_CONFIG register + 0x10 + 0x20 + read-write + 0x00400088 + + + VCO_CALAMP_EXT + VCO magnitude calibration word in thermometric code + + 0 + 14 + read-write + + + VCO_CALAMP_EXT_SEL + Select the mode to provide an external VCO amplitude calibration value through VCO_CALAMP_EXT bit field + + 15 + 1 + read-write + + + VCO_CALFREQ_EXT + VCO Cbank frequency calibration word. + 16 + 7 + read-write + + + VCO_CALFREQ_EXT_SEL + Select the mode to provide an external VCO frequency calibration value through VCO_CALFREQ_EXT bit field + + 23 + 1 + read-write + + + VCO_CALIB_REQ + Define if the Radio FSM must launch a VCO calibration request after VCO start-up + + 31 + 1 + read-write + + + + + RX_TIMER + RX_TIMER + RX_TIMER register + 0x14 + 0x20 + read-write + 0x00000000 + + + RX_TIMEOUT + RX timer timeout (relative duration in interpolated absolute time unit) + 0 + 23 + read-write + + + RX_CS_TIMEOUT_MASK + - 0: CS flag does not contribute to timeout disabling + + 28 + 1 + read-write + + + RX_PQI_TIMEOUT_MASK + - 0: PREAMBLE valid flag does not contribute to timeout disabling + + 29 + 1 + read-write + + + RX_SQI_TIMEOUT_MASK + - 0: SYNC valid flag does not contribute to timeout disabling + + 30 + 1 + read-write + + + RX_OR_nAND_SELECT + Select logical OR or logcial AND to apply on CS/PQI/SQI timeout mask + + 31 + 1 + read-write + + + + + DATABUFFER_THR + DATABUFFER_THR + DATABUFFER_THR register + 0x18 + 0x20 + read-write + 0x00000000 + + + RX_ALMOST_FULL_THR + Almost Full threshold for RX Data Buffers + + 0 + 16 + read-write + + + TX_ALMOST_EMPTY_THR + Almost Empty threshold for TX Data Buffers. + 16 + 16 + read-write + + + + + RFSEQ_IRQ_ENABLE + RFSEQ_IRQ_ENABLE + RFSEQ_IRQ_ENABLE register + 0x1c + 0x20 + read-write + 0x00000000 + + + TX_DONE_E + Enable interrupt on TX_DONE_F flag + 0 + 1 + read-write + + + RX_OK_E + Enable interrupt on RX_OK_F flag + 1 + 1 + read-write + + + RX_TIMEOUT_E + Enable interrupt on RX_TIMEOUT_F flag + 2 + 1 + read-write + + + RX_CRC_ERROR_E + Enable interrupt on RX_CRC_ERROR_F flag + 3 + 1 + read-write + + + FAST_RX_TERM_E + Enable interrupt on FAST_RX_TERM_F flag + 4 + 1 + read-write + + + RXTIMER_STOP_CDT_E + Enable interrupt on RXTIMER_STOP_CDT_F flag + 7 + 1 + read-write + + + SABORT_DONE_E + Enable interrupt on SABORT command treated and done flag + 8 + 1 + read-write + + + COMMAND_REJECTED_E + Enable interrupt on COMMAND_REJECTED flag + 9 + 1 + read-write + + + CS_E + Enable interrupt on CS_F flag + 12 + 1 + read-write + + + PREAMBLE_VALID_E + Enable interrupt on PREAMBLE_VALID_F flag + 13 + 1 + read-write + + + SYNC_VALID_E + Enable interrupt on SYNC_VALID_F flag + 14 + 1 + read-write + + + DATABUFFER0_USED_E + Enable interrupt on DATABUFFER0_USED_F flag + 16 + 1 + read-write + + + DATABUFFER1_USED_E + Enable interrupt on DATABUFFER1_USED_F flag + 17 + 1 + read-write + + + RX_ALMOST_FULL_0_E + Enable interrupt on RX_ALMOST_FULL_0_F flag + 18 + 1 + read-write + + + RX_ALMOST_FULL_1_E + Enable interrupt on RX_ALMOST_FULL_1_F flag + 19 + 1 + read-write + + + TX_ALMOST_EMPTY_0_E + Enable interrupt on TX_ALMOST_EMPTY_0_F flag + 20 + 1 + read-write + + + TX_ALMOST_EMPTY_1_E + Enable interrupt on TX_ALMOST_EMPTY_1_F flag + 21 + 1 + read-write + + + AHB_ACCESS_ERROR_E + Enable interrupt on AHB_ACCESS_ERROR_F flag + 22 + 1 + read-write + + + HW_ANA_FAILURE_E + Enable interrupt on HW_ANA_FAILURE_F flag + 24 + 1 + read-write + + + SEQ_E + Enable interrupt on SEQ_F flag + 26 + 1 + read-write + + + RRM_CMD_START_E + Enable interrupt on RRM_CMD_END_F flag + 27 + 1 + read-write + + + RRM_CMD_END_E + Enable interrupt on RRM_CMD_END_F flag + 28 + 1 + read-write + + + SAFEASK_CALIB_DONE_E + Enable interrupt on SAFEASK_CALIB_DONE_F flag + 30 + 1 + read-write + + + AGC_CALIB_DONE_E + Enable interrupt on AGC_CALIB_DONE_F flag + 31 + 1 + read-write + + + + + ADDITIONAL_CTRL + ADDITIONAL_CTRL + ADDITIONAL_CTRL register + 0x20 + 0x20 + read-write + 0x00038800 + + + CH_NUM + Channel number. + 0 + 8 + read-write + + + CH_SPACING + Channel spacing. + 8 + 8 + read-only + + + PA_FC + Power control bandwidth selection according data rate + + 16 + 2 + read-write + + + TIME_CAPTURESEL + Select the trigger event to capture the interpolated absolute time in the TIME_CAPTURE[31:0] register + + 20 + 3 + read-write + + + AS_ENABLE + Enable the antenna switching feature. + 31 + 1 + read-write + + + + + FAST_RX_TIMER + FAST_RX_TIMER + FAST_RX_TIMER register + 0x24 + 0x20 + read-write + 0x00000000 + + + FAST_RX_TIMEOUT + Fast RX termination timer value (corresponding to the delay to measure the RSSI and to let the HW check CS flag information) + + 0 + 8 + read-write + + + FAST_CS_TERM_EN + Enable the Fast RX Termination feature + + 8 + 1 + read-write + + + + + COMMAND + COMMAND + COMMAND register + 0x28 + 0x20 + read-write + 0x00000000 + + + COMMAND_ID + Opcode coresponding to a command: + + 0 + 4 + read-write + + + BACK2ACTIVE + Select the default/return state for the Radio FSM to be ACTIVE2 + + 25 + 1 + read-write + + + BACK2LOCKON + Request to the Radio FSM to stay in LOCKON state when exiting a RX or a TX + + 26 + 1 + read-write + + + + + + + FLASH_CTRL + 4kb addressable space + FLASH_CTRL + 0x40001000 + + 0x0 + 0x200 + registers + + + Flash + Non-volatile memory (flash) +controller + 0 + + + + COMMAND + COMMAND + COMMAND register + 0x00 + 0x20 + read-write + 0x00000000 + + + COMMAND + Macro commands for flash operations (may require DATA0...DATA3 to be set): +- 0x11 : ERASE +- 0x22 : MASSERASE +- 0x33 : WRITE +- 0x55 : MASSREAD +- 0xAA : SLEEP +- 0xBB : WAKEUP +- 0xCC : BURSTWRITE +- 0xEE : OTPWRITE +- 0xFF : KEYWRITE + 0 + 8 + read-write + + + + + CONFIG + CONFIG + CONFIG register + 0x04 + 0x20 + read-write + 0x00000010 + + + REMAP + CPU access routing (it supersedes PREMAP configuration): +- 0 : FLASH memory addressed +- 1 : SRAM0 memory addressed + 1 + 1 + read-write + + + DIS_GROUP_WRITE + Burst write Control: +- 0 : burst write allowed +- 1 : burst write forbidden + 2 + 1 + read-write + + + WAIT_STATE + Add latency to flash read opeations: +- 00 : no latency +- 01 : 1 clock cycle latency +- 10 : 2 clock cycles latency +- 11 : 3 clock cycles latency + 4 + 2 + read-write + + + SLEEP_SM + Flash memory power-down mode enable in SLEEP mode +This bit allows to have the Flash memory in power-down mode or in idle mode when the +device is in Sleep mode. +- 0: When the device is in Sleep mode, the NVM is in Idle mode. +- 1: When the device is in Sleep mode, the NVM is in power-down mode. + 6 + 1 + read-write + + + + + IRQSTAT + IRQSTAT + IRQSTAT register + 0x08 + 0x20 + read-write + 0x00000000 + + + CMDDONE_MIS + (1: clear, 0: inactive) CMDDONE_MIS flag + 0 + 1 + read-write + + + CMDSTART_MIS + (1: clear, 0: inactive) CMDSTART_MIS flag + 1 + 1 + read-write + + + CMDBUSYERR_MIS + (1: clear, 0: inactive) CMDBUSYERR_MIS flag + 2 + 1 + read-write + + + ILLCMD_MIS + (1: clear, 0: inactive) ILLCMD_MIS flag + 3 + 1 + read-write + + + READOK_MIS + (1: clear, 0: inactive) READOK_MIS flag + 4 + 1 + read-write + + + FNREADY_MIS + (1: clear, 0: inactive) FNREADY_MIS flag + 5 + 1 + read-write + + + + + IRQMASK + IRQMASK + IRQMASK register + 0x0C + 0x20 + read-write + 0x0000003F + + + CMDDONEM + (1: mask, 0: inactive) CMDDONE_MIS mask + 0 + 1 + read-write + + + CMDSTARTM + (1: mask, 0: inactive) CMDSTART_MIS mask + 1 + 1 + read-write + + + CMDBUSYERRM + (1: mask, 0: inactive) CMDBUSYERR_MIS mask + 2 + 1 + read-write + + + ILLCMDM + (1: mask, 0: inactive) ILLCMD_MIS mask + 3 + 1 + read-write + + + READOKM + (1: mask, 0: inactive) READOK_MIS mask + 4 + 1 + read-write + + + FNREADYM + (1: mask, 0: inactive) FNREADY_MIS mask + 5 + 1 + read-write + + + + + IRQRAW + IRQRAW + IRQRAW register + 0x10 + 0x20 + read-write + 0x00000001 + + + CMDDONE_RIS + (1: active, 0: inactive) COMMAND sequence ended + 0 + 1 + read-write + + + CMDSTART_RIS + (1: active, 0: inactive) COMMAND sequence started + 1 + 1 + read-write + + + CMDBUSYERR_RIS + (1: active, 0: inactive) COMMAND issued while flash busy + 2 + 1 + read-write + + + ILLCMD_RIS + (1: active, 0: inactive) Illegal command issued + 3 + 1 + read-write + + + READOK_RIS + (1: active, 0: inactive) READ COMMAND completed successfully + 4 + 1 + read-write + + + CMDSLEEPERR_RIS + (1: active, 0: inactive) COMMAND issued while flash in sleep-mode (SLM=1) + 5 + 1 + read-write + + + + + SIZE + SIZE + SIZE register + 0x14 + 0x20 + read-only + 0x0000FFFF + + + FLASH_SIZE + Maximum valid address for flash memory: +- 00 : 0x03FFF (64kb) +- 01 : 0x07FFF (128kb) +- 10 : 0x0BFFF (192kb) +- 11 : 0x0FFFF (256kb) + 0 + 17 + read-only + + + RAM_SIZE + RAM memory size selection: +- 0 : 16kb +- 1 : 32kb + 17 + 1 + read-only + + + FLASH_SECURE + Flash memory protection (0: no key present, 1: key present) + 19 + 1 + read-only + + + JTAG_DISABLE + Flash+JTAG protection (0: no JTAG protection - see FLASH_SECURE, 1: Flash and JTAG protected) + 20 + 1 + read-only + + + PACKAGE_SIZE + Package selection: +- 0- : CSP +- 10 : 32pins +- 11 : 48pins + 21 + 2 + read-only + + + + + ADDRESS + ADDRESS + ADDRESS register + 0x18 + 0x20 + read-write + 0x00000000 + + + YADDR + Flash column address offset to be used with some COMMAND + 0 + 6 + read-write + + + XADDR + Flash row address offset to be used with some COMMAND + 6 + 10 + read-write + + + + + LFSRVAL + LFSRVAL + LFSRVAL register + 0x24 + 0x20 + read-only + 0xFFFFFFFF + + + LFSRVAL + Flash read data CRC signature + 0 + 32 + read-only + + + + + PAGEPROT0 + PAGEPROT0 + PAGEPROT0 register + 0x34 + 0x20 + read-write + 0x00000000 + + + SEGSIZE0 + First segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 0 + 7 + read-write + + + SEGOFFSET0 + First segment, 7-bit page protection offset (first page number in protected segment) + 8 + 7 + read-write + + + SEGSIZE1 + Second segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 16 + 7 + read-write + + + SEGOFFSET1 + Second segment, 7-bit page protection offset (first page number in protected segment) + 24 + 7 + read-write + + + + + PAGEPROT1 + PAGEPROT1 + PAGEPROT1 register + 0x38 + 0x20 + read-write + 0x00000000 + + + SEGSIZE2 + Third segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 0 + 7 + read-write + + + SEGOFFSET2 + Third segment, 7-bit page protection offset (first page number in protected segment) + 8 + 7 + read-write + + + SEGSIZE3 + Fourth segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 16 + 7 + read-write + + + SEGOFFSET3 + Fourth segment, 7-bit page protection offset (first page number in protected segment) + 24 + 7 + read-write + + + + + DATA0 + DATA0 + DATA0 register + 0x40 + 0x20 + read-write + 0xFFFFFFFF + + + DATA0 + Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD + 0 + 32 + read-write + + + + + DATA1 + DATA1 + DATA1 register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + DATA1 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA2 + DATA2 + DATA2 register + 0x48 + 0x20 + read-write + 0xFFFFFFFF + + + DATA2 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA3 + DATA3 + DATA3 register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + DATA3 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + UNLOCK012 + UNLOCK012 + UNLOCK012 register + 0x50 + 0x20 + read-write + 0xFFFFFFFF + + + UNLOCK012 + (NOT TO BE DOCUMENTED) Remove read-write protection from IFR0, IFR1, IFR2 sectors + 0 + 32 + read-write + + + + + UNLOCK3 + UNLOCK3 + UNLOCK3 register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + UNLOCK3 + (NOT TO BE DOCUMENTED) Remove read-write protection from IFR3 sector + 0 + 32 + read-write + + + + + + + GPIOA + GPIOA + 0x48000000 + + 0x0 + 0x2C + registers + + + GPIOA + GPIOA interrupt + 15 + + + + MODER + MODER + MODER register + 0x00 + 0x20 + read-write + 0x000000A0 + + + MODE0 + MODE0[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 0 + 2 + read-write + + + MODE1 + MODE1[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 2 + 2 + read-write + + + MODE2 + MODE2[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 4 + 2 + read-write + + + MODE3 + MODE3[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 6 + 2 + read-write + + + MODE4 + MODE4[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 8 + 2 + read-write + + + MODE5 + MODE5[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 10 + 2 + read-write + + + MODE6 + MODE6[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 12 + 2 + read-write + + + MODE7 + MODE7[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 14 + 2 + read-write + + + MODE8 + MODE8[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 16 + 2 + read-write + + + MODE9 + MODE9[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 18 + 2 + read-write + + + MODE10 + MODE10[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 20 + 2 + read-write + + + MODE11 + MODE11[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 22 + 2 + read-write + + + MODE12 + MODE12[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 24 + 2 + read-write + + + MODE13 + MODE13[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 26 + 2 + read-write + + + MODE14 + MODE14[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 28 + 2 + read-write + + + MODE15 + MODE15[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 30 + 2 + read-write + + + + + OTYPER + OTYPER + OTYPER register + 0x04 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 0 + 1 + read-write + + + OT1 + OT1: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 1 + 1 + read-write + + + OT2 + OT2: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 2 + 1 + read-write + + + OT3 + OT3: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 3 + 1 + read-write + + + OT4 + OT4: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 4 + 1 + read-write + + + OT5 + OT5: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 5 + 1 + read-write + + + OT6 + OT6: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 6 + 1 + read-write + + + OT7 + OT7: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 7 + 1 + read-write + + + OT8 + OT8: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 8 + 1 + read-write + + + OT9 + OT9: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 9 + 1 + read-write + + + OT10 + OT10: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 10 + 1 + read-write + + + OT11 + OT11: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 11 + 1 + read-write + + + OT12 + OT12: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 12 + 1 + read-write + + + OT13 + OT13: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 13 + 1 + read-write + + + OT14 + OT14: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 14 + 1 + read-write + + + OT15 + OT15: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 15 + 1 + read-write + + + + + OSPEEDR + OSPEEDR + OSPEEDR register + 0x08 + 0x20 + read-write + 0x00000030 + + + OSPEED0 + OSPEED0[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 0 + 2 + read-write + + + OSPEED1 + OSPEED1[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 2 + 2 + read-write + + + OSPEED2 + OSPEED2[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 4 + 2 + read-write + + + OSPEED3 + OSPEED3[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 6 + 2 + read-write + + + OSPEED4 + OSPEED4[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 8 + 2 + read-write + + + OSPEED5 + OSPEED5[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 10 + 2 + read-write + + + OSPEED6 + OSPEED6[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 12 + 2 + read-write + + + OSPEED7 + OSPEED7[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 14 + 2 + read-write + + + OSPEED8 + OSPEED8[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 16 + 2 + read-write + + + OSPEED9 + OSPEED9[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 18 + 2 + read-write + + + OSPEED10 + OSPEED10[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 20 + 2 + read-write + + + OSPEED11 + OSPEED11[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 22 + 2 + read-write + + + OSPEED12 + OSPEED12[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 24 + 2 + read-write + + + OSPEED13 + OSPEED13[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 26 + 2 + read-write + + + OSPEED14 + OSPEED14[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 28 + 2 + read-write + + + OSPEED15 + OSPEED15[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 30 + 2 + read-write + + + + + PUPDR + PUPDR + PUPDR register + 0x0C + 0x20 + read-write + 0x55555595 + + + PUPD0 + PUPD0: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 0 + 2 + read-write + + + PUPD1 + PUPD1: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 2 + 2 + read-write + + + PUPD2 + PUPD2: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 4 + 2 + read-write + + + PUPD3 + PUPD3: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 6 + 2 + read-write + + + PUPD4 + PUPD4: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 8 + 2 + read-write + + + PUPD5 + PUPD5: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 10 + 2 + read-write + + + PUPD6 + PUPD6: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 12 + 2 + read-write + + + PUPD7 + PUPD7: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 14 + 2 + read-write + + + PUPD8 + PUPD8: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 16 + 2 + read-write + + + PUPD9 + PUPD9: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 18 + 2 + read-write + + + PUPD10 + PUPD10: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 20 + 2 + read-write + + + PUPD11 + PUPD11: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 22 + 2 + read-write + + + PUPD12 + PUPD12: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 24 + 2 + read-write + + + PUPD13 + PUPD13: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 26 + 2 + read-write + + + PUPD14 + PUPD14: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 28 + 2 + read-write + + + PUPD15 + PUPD15: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 30 + 2 + read-write + + + + + IDR + IDR + IDR register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + ID0: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 0 + 1 + read-only + + + ID1 + ID1: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 1 + 1 + read-only + + + ID2 + ID2: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 2 + 1 + read-only + + + ID3 + ID3: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 3 + 1 + read-only + + + ID4 + ID4: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 4 + 1 + read-only + + + ID5 + ID5: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 5 + 1 + read-only + + + ID6 + ID6: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 6 + 1 + read-only + + + ID7 + ID7: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 7 + 1 + read-only + + + ID8 + ID8: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 8 + 1 + read-only + + + ID9 + ID9: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 9 + 1 + read-only + + + ID10 + ID10: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 10 + 1 + read-only + + + ID11 + ID11: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 11 + 1 + read-only + + + ID12 + ID12: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 12 + 1 + read-only + + + ID13 + ID13: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 13 + 1 + read-only + + + ID14 + ID14: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 14 + 1 + read-only + + + ID15 + ID15: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 15 + 1 + read-only + + + + + ODR + ODR + ODR register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + OD0: Port A output data bit +These bits can be read and written by software + 0 + 1 + read-write + + + OD1 + OD1: Port A output data bit +These bits can be read and written by software + 1 + 1 + read-write + + + OD2 + OD2: Port A output data bit +These bits can be read and written by software + 2 + 1 + read-write + + + OD3 + OD3: Port A output data bit +These bits can be read and written by software + 3 + 1 + read-write + + + OD4 + OD4: Port A output data bit +These bits can be read and written by software + 4 + 1 + read-write + + + OD5 + OD5: Port A output data bit +These bits can be read and written by software + 5 + 1 + read-write + + + OD6 + OD6: Port A output data bit +These bits can be read and written by software + 6 + 1 + read-write + + + OD7 + OD7: Port A output data bit +These bits can be read and written by software + 7 + 1 + read-write + + + OD8 + OD8: Port A output data bit +These bits can be read and written by software + 8 + 1 + read-write + + + OD9 + OD9: Port A output data bit +These bits can be read and written by software + 9 + 1 + read-write + + + OD10 + OD10: Port A output data bit +These bits can be read and written by software + 10 + 1 + read-write + + + OD11 + OD11: Port A output data bit +These bits can be read and written by software + 11 + 1 + read-write + + + OD12 + OD12: Port A output data bit +These bits can be read and written by software + 12 + 1 + read-write + + + OD13 + OD13: Port A output data bit +These bits can be read and written by software + 13 + 1 + read-write + + + OD14 + OD14: Port A output data bit +These bits can be read and written by software + 14 + 1 + read-write + + + OD15 + OD15: Port A output data bit +These bits can be read and written by software + 15 + 1 + read-write + + + + + BSRR + BSRR + BSRR register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +0: No action on the corresponding ODx bit +1: Sets the corresponding ODx bit + 0 + 1 + write-only + + + BS1 + BS1: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +0: No action on the corresponding ODx bit +1: Sets the corresponding ODx bit + 1 + 1 + write-only + + + BS2 + BS2: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +0: No action on the corresponding ODx bit +1: Sets the corresponding ODx bit + 2 + 1 + write-only + + + BS3 + BS3: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + BS4 + BS4: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + BS5 + BS5: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000 + 5 + 1 + write-only + + + BS6 + BS6: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + BS7 + BS7: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000 + 7 + 1 + write-only + + + BS8 + BS8: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + BS9 + BS9: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + BS10 + BS10: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + BS11 + BS11: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + BS12 + BS12: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + BS13 + BS13: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + BS14 + BS14: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + BS15 + BS15: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + BR0 + BR0: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + BR1 + BR1: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + BR2 + BR2: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + BR3 + BR3: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + BR4 + BR4: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + BR5 + BR5: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + BR6 + BR6: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + BR7 + BR7: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + BR8 + BR8: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + BR9 + BR9: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + BR10 + BR10: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + BR11 + BR11: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + BR12 + BR12: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + BR13 + BR13: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + BR14 + BR14: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + BR15 + BR15: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + + + LCKR + LCKR + LCKR register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0: Port A lock bit 0 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 0 + 1 + read-write + + + LCK1 + LCK1: Port A lock bit 1 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 1 + 1 + read-write + + + LCK2 + LCK2: Port A lock bit 2 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 2 + 1 + read-write + + + LCK3 + LCK3: Port A lock bit 3 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 3 + 1 + read-write + + + LCK4 + LCK4: Port A lock bit 4 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 4 + 1 + read-write + + + LCK5 + LCK5: Port A lock bit 5 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 5 + 1 + read-write + + + LCK6 + LCK6: Port A lock bit 6 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 6 + 1 + read-write + + + LCK7 + LCK7: Port A lock bit 7 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 7 + 1 + read-write + + + LCK8 + LCK8: Port A lock bit 8 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 8 + 1 + read-write + + + LCK9 + LCK9: Port A lock bit 9 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 9 + 1 + read-write + + + LCK10 + LCK10: Port A lock bit 10 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 10 + 1 + read-write + + + LCK11 + LCK11: Port A lock bit 11 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 11 + 1 + read-write + + + LCK12 + LCK12: Port A lock bit 12 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 12 + 1 + read-write + + + LCK13 + LCK13: Port A lock bit 13 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 13 + 1 + read-write + + + LCK14 + LCK14: Port A lock bit 14 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 14 + 1 + read-write + + + LCK15 + LCK15: Port A lock bit 15 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 15 + 1 + read-write + + + LCKK + LCKK: Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +-0: Port configuration lock key not active +-1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU +reset or peripheral reset. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Any error in the lock sequence aborts the lock. +After the first lock sequence on any bit of the port, any read access on the LCKK bit will +return 1 until the next MCU reset or peripheral reset + 16 + 1 + read-write + + + + + AFRL + AFRL + AFRL register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL1 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL2 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL3 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL4 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL5 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL6 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL7 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + AFRH + AFRH + AFRH register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL9 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL10 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL11 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL12 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL13 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL14 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL15 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + BRR + BRR + BRR register + 0x28 + 0x20 + read-write + 0x00000000 + + + BR0 + BR0: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 0 + 1 + write-only + + + BR1 + BR1: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 1 + 1 + write-only + + + BR2 + BR2: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 2 + 1 + write-only + + + BR3 + BR3: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 3 + 1 + write-only + + + BR4 + BR4: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 4 + 1 + write-only + + + BR5 + BR5: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 5 + 1 + write-only + + + BR6 + BR6: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 6 + 1 + write-only + + + BR7 + BR7: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 7 + 1 + write-only + + + BR8 + BR8: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 8 + 1 + write-only + + + BR9 + BR9: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 9 + 1 + write-only + + + BR10 + BR10: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 10 + 1 + write-only + + + BR11 + BR11: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 11 + 1 + write-only + + + BR12 + BR12: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 12 + 1 + write-only + + + BR13 + BR13: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 13 + 1 + write-only + + + BR14 + BR14: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 14 + 1 + write-only + + + BR15 + BR15: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 15 + 1 + write-only + + + + + + + GPIOB + GPIOB + 0x48100000 + + 0x0 + 0x2C + registers + + + GPIOB + GPIOB interrupt + 16 + + + + MODER + MODER + MODER register + 0x00 + 0x20 + read-write + 0x00000000 + + + MODE0 + MODE0[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 0 + 2 + read-write + + + MODE1 + MODE1[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 2 + 2 + read-write + + + MODE2 + MODE2[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 4 + 2 + read-write + + + MODE3 + MODE3[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 6 + 2 + read-write + + + MODE4 + MODE4[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 8 + 2 + read-write + + + MODE5 + MODE5[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 10 + 2 + read-write + + + MODE6 + MODE6[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 12 + 2 + read-write + + + MODE7 + MODE7[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 14 + 2 + read-write + + + MODE8 + MODE8[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 16 + 2 + read-write + + + MODE9 + MODE9[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 18 + 2 + read-write + + + MODE10 + MODE10[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 20 + 2 + read-write + + + MODE11 + MODE11[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 22 + 2 + read-write + + + MODE12 + MODE12[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 24 + 2 + read-write + + + MODE13 + MODE13[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 26 + 2 + read-write + + + MODE14 + MODE14[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 28 + 2 + read-write + + + MODE15 + MODE15[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 30 + 2 + read-write + + + + + OTYPER + OTYPER + OTYPER register + 0x04 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 0 + 1 + read-write + + + OT1 + OT1: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 1 + 1 + read-write + + + OT2 + OT2: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 2 + 1 + read-write + + + OT3 + OT3: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 3 + 1 + read-write + + + OT4 + OT4: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 4 + 1 + read-write + + + OT5 + OT5: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 5 + 1 + read-write + + + OT6 + OT6: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 6 + 1 + read-write + + + OT7 + OT7: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 7 + 1 + read-write + + + OT8 + OT8: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 8 + 1 + read-write + + + OT9 + OT9: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 9 + 1 + read-write + + + OT10 + OT10: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 10 + 1 + read-write + + + OT11 + OT11: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 11 + 1 + read-write + + + OT12 + OT12: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 12 + 1 + read-write + + + OT13 + OT13: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 13 + 1 + read-write + + + OT14 + OT14: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 14 + 1 + read-write + + + OT15 + OT15: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 15 + 1 + read-write + + + + + OSPEEDR + OSPEEDR + OSPEEDR register + 0x08 + 0x20 + read-write + 0x00000000 + + + OSPEED0 + OSPEED0[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 0 + 2 + read-write + + + OSPEED1 + OSPEED1[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 2 + 2 + read-write + + + OSPEED2 + OSPEED2[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 4 + 2 + read-write + + + OSPEED3 + OSPEED3[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 6 + 2 + read-write + + + OSPEED4 + OSPEED4[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 8 + 2 + read-write + + + OSPEED5 + OSPEED5[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 10 + 2 + read-write + + + OSPEED6 + OSPEED6[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 12 + 2 + read-write + + + OSPEED7 + OSPEED7[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 14 + 2 + read-write + + + OSPEED8 + OSPEED8[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 16 + 2 + read-write + + + OSPEED9 + OSPEED9[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 18 + 2 + read-write + + + OSPEED10 + OSPEED10[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 20 + 2 + read-write + + + OSPEED11 + OSPEED11[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 22 + 2 + read-write + + + OSPEED12 + OSPEED12[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 24 + 2 + read-write + + + OSPEED13 + OSPEED13[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 26 + 2 + read-write + + + OSPEED14 + OSPEED14[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 28 + 2 + read-write + + + OSPEED15 + OSPEED15[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 30 + 2 + read-write + + + + + PUPDR + PUPDR + PUPDR register + 0x0C + 0x20 + read-write + 0x55555555 + + + PUPD0 + PUPD0: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 0 + 2 + read-write + + + PUPD1 + PUPD1: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 2 + 2 + read-write + + + PUPD2 + PUPD2: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 4 + 2 + read-write + + + PUPD3 + PUPD3: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 6 + 2 + read-write + + + PUPD4 + PUPD4: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 8 + 2 + read-write + + + PUPD5 + PUPD5: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 10 + 2 + read-write + + + PUPD6 + PUPD6: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 12 + 2 + read-write + + + PUPD7 + PUPD7: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 14 + 2 + read-write + + + PUPD8 + PUPD8: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 16 + 2 + read-write + + + PUPD9 + PUPD9: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 18 + 2 + read-write + + + PUPD10 + PUPD10: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 20 + 2 + read-write + + + PUPD11 + PUPD11: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 22 + 2 + read-write + + + PUPD12 + PUPD12: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 24 + 2 + read-write + + + PUPD13 + PUPD13: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 26 + 2 + read-write + + + PUPD14 + PUPD14: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 28 + 2 + read-write + + + PUPD15 + PUPD15: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 30 + 2 + read-write + + + + + IDR + IDR + IDR register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + ID0: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 0 + 1 + read-only + + + ID1 + ID1: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 1 + 1 + read-only + + + ID2 + ID2: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 2 + 1 + read-only + + + ID3 + ID3: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 3 + 1 + read-only + + + ID4 + ID4: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 4 + 1 + read-only + + + ID5 + ID5: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 5 + 1 + read-only + + + ID6 + ID6: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 6 + 1 + read-only + + + ID7 + ID7: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 7 + 1 + read-only + + + ID8 + ID8: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 8 + 1 + read-only + + + ID9 + ID9: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 9 + 1 + read-only + + + ID10 + ID10: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 10 + 1 + read-only + + + ID11 + ID11: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 11 + 1 + read-only + + + ID12 + ID12: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 12 + 1 + read-only + + + ID13 + ID13: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 13 + 1 + read-only + + + ID14 + ID14: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 14 + 1 + read-only + + + ID15 + ID15: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 15 + 1 + read-only + + + + + ODR + ODR + ODR register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + OD0: Port B output data bit +These bits can be read and written by software + 0 + 1 + read-write + + + OD1 + OD1: Port B output data bit +These bits can be read and written by software + 1 + 1 + read-write + + + OD2 + OD2: Port B output data bit +These bits can be read and written by software + 2 + 1 + read-write + + + OD3 + OD3: Port B output data bit +These bits can be read and written by software + 3 + 1 + read-write + + + OD4 + OD4: Port B output data bit +These bits can be read and written by software + 4 + 1 + read-write + + + OD5 + OD5: Port B output data bit +These bits can be read and written by software + 5 + 1 + read-write + + + OD6 + OD6: Port B output data bit +These bits can be read and written by software + 6 + 1 + read-write + + + OD7 + OD7: Port B output data bit +These bits can be read and written by software + 7 + 1 + read-write + + + OD8 + OD8: Port B output data bit +These bits can be read and written by software + 8 + 1 + read-write + + + OD9 + OD9: Port B output data bit +These bits can be read and written by software + 9 + 1 + read-write + + + OD10 + OD10: Port B output data bit +These bits can be read and written by software + 10 + 1 + read-write + + + OD11 + OD11: Port B output data bit +These bits can be read and written by software + 11 + 1 + read-write + + + OD12 + OD12: Port B output data bit +These bits can be read and written by software + 12 + 1 + read-write + + + OD13 + OD13: Port B output data bit +These bits can be read and written by software + 13 + 1 + read-write + + + OD14 + OD14: Port B output data bit +These bits can be read and written by software + 14 + 1 + read-write + + + OD15 + OD15: Port B output data bit +These bits can be read and written by software + 15 + 1 + read-write + + + + + BSRR + BSRR + BSRR register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + BS1 + BS1: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + BS2 + BS2: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + BS3 + BS3: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + BS4 + BS4: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + BS5 + BS5: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + BS6 + BS6: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + BS7 + BS7: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + BS8 + BS8: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + BS9 + BS9: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + BS10 + BS10: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + BS11 + BS11: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + BS12 + BS12: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + BS13 + BS13: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + BS14 + BS14: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + BS15 + BS15: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + BR0 + BR0: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + BR1 + BR1: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + BR2 + BR2: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + BR3 + BR3: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + BR4 + BR4: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + BR5 + BR5: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + BR6 + BR6: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + BR7 + BR7: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + BR8 + BR8: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + BR9 + BR9: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + BR10 + BR10: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + BR11 + BR11: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + BR12 + BR12: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + BR13 + BR13: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + BR14 + BR14: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + BR15 + BR15: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + + + LCKR + LCKR + LCKR register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0: Port B lock bit 0 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 0 + 1 + read-write + + + LCK1 + LCK1: Port B lock bit 1 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 1 + 1 + read-write + + + LCK2 + LCK2: Port B lock bit 2 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 2 + 1 + read-write + + + LCK3 + LCK3: Port B lock bit 3 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 3 + 1 + read-write + + + LCK4 + LCK4: Port B lock bit 4 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 4 + 1 + read-write + + + LCK5 + LCK5: Port B lock bit 5 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 5 + 1 + read-write + + + LCK6 + LCK6: Port B lock bit 6 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 6 + 1 + read-write + + + LCK7 + LCK7: Port B lock bit 7 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 7 + 1 + read-write + + + LCK8 + LCK8: Port B lock bit 8 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 8 + 1 + read-write + + + LCK9 + LCK9: Port B lock bit 9 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 9 + 1 + read-write + + + LCK10 + LCK10: Port B lock bit 10 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 10 + 1 + read-write + + + LCK11 + LCK11: Port B lock bit 11 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 11 + 1 + read-write + + + LCK12 + LCK12: Port B lock bit 12 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 12 + 1 + read-write + + + LCK13 + LCK13: Port B lock bit 13 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 13 + 1 + read-write + + + LCK14 + LCK14: Port B lock bit 14 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 14 + 1 + read-write + + + LCK15 + LCK15: Port B lock bit 15 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 15 + 1 + read-write + + + LCKK + LCKK: Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +-0: Port configuration lock key not active +-1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU +reset or peripheral reset. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Any error in the lock sequence aborts the lock. +After the first lock sequence on any bit of the port, any read access on the LCKK bit will +return 1 until the next MCU reset or peripheral reset + 16 + 1 + read-write + + + + + AFRL + AFRL + AFRL register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL1 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL2 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL3 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL4 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL5 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL6 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL7 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + AFRH + AFRH + AFRH register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL9 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL10 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL11 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL12 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL13 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL14 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL15 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + BRR + BRR + BRR register + 0x28 + 0x20 + read-write + + + BR0 + BR0: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 0 + 1 + write-only + + + BR1 + BR1: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 1 + 1 + write-only + + + BR2 + BR2: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 2 + 1 + write-only + + + BR3 + BR3: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 3 + 1 + write-only + + + BR4 + BR4: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 4 + 1 + write-only + + + BR5 + BR5: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 5 + 1 + write-only + + + BR6 + BR6: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 6 + 1 + write-only + + + BR7 + BR7: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 7 + 1 + write-only + + + BR8 + BR8: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 8 + 1 + write-only + + + BR9 + BR9: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 9 + 1 + write-only + + + BR10 + BR10: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 10 + 1 + write-only + + + BR11 + BR11: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 11 + 1 + write-only + + + BR12 + BR12: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 12 + 1 + write-only + + + BR13 + BR13: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 13 + 1 + write-only + + + BR14 + BR14: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 14 + 1 + write-only + + + BR15 + BR15: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 15 + 1 + write-only + + + + + + + IWDG + IWDG + 0x40003000 + + 0x0 + 0x14 + registers + + + + IWDG_KR + IWDG_KR + IWDG_KR register + 0x00 + 0x20 + read-write + 0x00000000 + + + KEY + Key value. +Software can only write these bits. Reading returns the reset value. +These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. +Writing the key value 0x5555 to enables access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers. +Writing the key value CCCCh starts the watchdog + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG_PR register + 0x04 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider. +Set and reset by software. +These bits are write access protected. They are written by software to select the prescaler divider feeding the counter clock. +PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. +000: divider/4 +001: divider/8 +010: divider/16 +011: divider/32 +100: divider/64 +101: divider/128 +110: divider/256 +111: divider/256 + 0 + 3 + read-write + + + + + IWDG_RLR + IWDG_RLR + IWDG_RLR register + 0x08 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value. +Set and reset by software. +These bits are write access protected. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. +The timeout period is a function of this value and the clock prescaler. +The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG_SR register + 0x0C + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value update. +Read only bit. +This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is +reset by hardware when the prescaler update operation is completed in the VDD voltage +domain (takes up to 5 RC 40 kHz cycles). +Prescaler value can be updated only when PVU bit is reset + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update. +Read only bit. +This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Reload value can be updated only when RVU bit is reset + 1 + 1 + read-only + + + WVU + Watchdog counter window value update. +Read only bit. +This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Window value can be updated only when WVU bit is reset. +This bit is generated only if generic 'window' = 1 + 2 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG_WINR register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value. +Set and reset by software. +These bits are write access protected. These bits contain the high limit of the window value to be compared to the downcounter. +To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 +The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + + + LPUART + LPUART + 0x41005000 + + 0x0 + 0x30 + registers + + + LPUART + LPUART interrupt + 9 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + UE + UE: USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and +current operations are discarded. The configuration of the USART is kept, but all the status +flags, in the USART_ISR are reset. This bit is set and cleared by software. +-0: USART prescaler and outputs disabled, low power mode +-1: USART enabled + 0 + 1 + read-write + + + UESM + UESM: LPUART enable in Stop mode +When this bit is cleared, the LPUART is not able to wake up the MCU from Stop mode. +When this bit is set, the LPUART is able to wake up the MCU from Stop mode, provided that +the LPUART clock selection is LSE in the RCC. +This bit is set and cleared by software. +-0: LPUART not able to wake up the MCU from Stop mode. +-1: LPUART able to wake up the MCU from Stop mode. When this function is active, the +clock source for the LPUART must be LSE (see RCC chapter) + 1 + 1 + read-write + + + RE + RE: Receiver enable +This bit enables the receiver. It is set and cleared by software. +-0: Receiver is disabled +-1: Receiver is enabled and begins searching for a start bit + 2 + 1 + read-write + + + TE + TE: Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +-0: Transmitter is disabled +-1: Transmitter is enabled + 3 + 1 + read-write + + + IDLEIE + IDLEIE: IDLE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register + 4 + 1 + read-write + + + RXNEIE_RXFNEIE + RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the +USART_ISR register + 5 + 1 + read-write + + + TCIE + TCIE: Transmission complete interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TC=1 in the USART_ISR register + 6 + 1 + read-write + + + TXEIE_TXFNFIE + TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register + 7 + 1 + read-write + + + PEIE + PEIE: PE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever PE=1 in the USART_ISR register + 8 + 1 + read-write + + + PS + PS: Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE +bit set). It is set and cleared by software. The parity will be selected after the current byte. +-0: Even parity +-1: Odd parity +This bit field can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + PCE + PCE: Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity +control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit +if M=0) and parity is checked on the received data. This bit is set and cleared by software. +Once it is set, PCE is active after the current byte (in reception and in transmission). +-0: Parity control disabled +-1: Parity control enabled +This bit field can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + WAKE + WAKE: Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by +software. +-0: Idle line +-1: Address mark +This bit field can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + M_0 + M0: Word length +This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit +-28 (M1)description. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + MME: Mute mode enable +This bit activates the mute mode function of the USART. When set, the USART can switch +between the active and mute modes, as defined by the WAKE bit. It is set and cleared by +software. +-0: Receiver in active mode permanently +-1: Receiver can switch between mute mode and active mode + 13 + 1 + read-write + + + CMIE + CMIE: Character match interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 14 + 1 + read-write + + + DEDT + DEDT[4:0]: Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted +message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample +time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only +when the DEDT and DEAT times have both elapsed. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + DEAT[4:0]: Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and +the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, +depending on the oversampling rate). +This bit field can only be written when the USART is disabled (UE=0). + 21 + 5 + read-write + + + M_1 + Word length +This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0).s + 28 + 1 + read-write + + + FIFOEN + FIFOEN :FIFO mode enable +This bit is set and cleared by software. +-0: FIFO mode is disabled. +-1: FIFO mode is enabled. + 29 + 1 + read-write + + + TXFEIE + TXFEIE :TXFIFO empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFE=1 in the USART_ISR register + 30 + 1 + read-write + + + RXFFIE + RXFFIE :RXFIFO Full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when RXFF=1 in the USART_ISR register + 31 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + ADDM7 + ADDM7:7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +-0: 4-bit address detection +-1: 7-bit address detection (in 8-bit data mode) +This bit can only be written when the USART is disabled (UE=0) + 4 + 1 + read-write + + + STOP + STOP[1:0]: STOP bits +These bits are used for programming the stop bits. +-00: 1 stop bit +-01: 0.5 stop bit. +-10: 2 stop bits +-11: 1.5 stop bits +This bit field can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + SWAP + SWAP: Swap TX/RX pins +This bit is set and cleared by software. +-0: TX/RX pins are used as defined in standard pinout +-1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired +connection to another UART. +This bit field can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + RXINV + RXINV: RX pin active level inversion +This bit is set and cleared by software. +-0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the RX line. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + TXINV + TXINV: TX pin active level inversion +This bit is set and cleared by software. +-0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the TX line. +This bit field can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + DATAINV + DATAINV: Binary data inversion +This bit is set and cleared by software. +-0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) +-1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The +parity bit is also inverted. +This bit field can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + MSBFIRST + MSBFIRST: Most significant bit first +This bit is set and cleared by software. +-0: data is transmitted/received with data bit 0 first, following the start bit. +-1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. +This bit field can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + ADD + ADD[7:0]: Address of the USART node +This bit-field gives the address of the USART node or a character code to be recognized. +This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- +bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. +It may also be used for character detection during normal reception, Mute mode inactive (for +example, end of block detection in ModBus protocol). In this case, the whole received character (8- +bit) is compared to the ADD[7:0] value and CMF flag is set on match. +This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled +(UE=0) + 24 + 8 + read-write + + + + + CR3 + CR3 + CR3 register + 0x08 + 0x20 + read-write + 0x00000000 + + + EIE + EIE: Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing +error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR += 1 in the USART_ISR register). +-0: Interrupt is inhibited +-1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) +in the USART_ISR register. + 0 + 1 + read-write + + + HDSEL + HDSEL: Half-duplex selection +Selection of Single-wire Half-duplex mode +-0: Half duplex mode is not selected +-1: Half duplex mode is selected +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + DMAR + DMAR: DMA enable receiver +This bit is set/reset by software +-1: DMA mode is enabled for reception +-0: DMA mode is disabled for reception + 6 + 1 + read-write + + + DMAT + DMAT: DMA enable transmitter +This bit is set/reset by software +-1: DMA mode is enabled for transmission +-0: DMA mode is disabled for transmission + 7 + 1 + read-write + + + RTSE + RTSE: RTS enable +-0: RTS hardware flow control disabled +-1: RTS output enabled, data is only requested when there is space in the receive buffer. The +transmission of data is expected to cease after the current character has been transmitted. +The nRTS output is asserted (pulled to 0) when data can be received. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CTSE + CTSE: CTS enable +-0: CTS hardware flow control disabled +-1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). +If the nCTS input is deasserted while data is being transmitted, then the transmission is +completed before stopping. If data is written into the data register while nCTS is asserted, +the transmission is postponed until nCTS is asserted. +This bit can only be written when the USART is disabled (UE=0) + 9 + 1 + read-write + + + CTSIE + CTSIE: CTS interrupt enable +-0: Interrupt is inhibited +-1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 10 + 1 + read-write + + + OVRDIS + OVRDIS: Overrun Disable +This bit is used to disable the receive overrun detection. +-0: Overrun Error Flag, ORE, is set when received data is not read before receiving new +data. +-1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set +the ORE flag is not set and the new received data overwrites the previous content of the +USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data +will be written directly in USARTx_RDR register. Even when FIFO management is enabled, +the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + DDRE + DDRE: DMA Disable on Reception Error +-0: DMA is not disabled in case of reception error. The corresponding error flag is set but +RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not +asserted, so the erroneous data is not transferred (no DMA request), but next correct +received data will be transferred. (used for Smartcard mode) +-1: DMA is disabled following a reception error. The corresponding error flag is set, as well +as RXNE. The DMA request is masked until the error flag is cleared. This means that the +software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case +FIFO mode is enabled) before clearing the error flag. +This bit can only be written when the USART is disabled (UE=0). + 13 + 1 + read-write + + + DEM + DEM: Driver enable mode +This bit allows the user to activate the external transceiver control, through the DE signal. +-0: DE function is disabled. +-1: DE function is enabled. The DE signal is output on the RTS pin. +This bit can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + DEP + DEP: Driver enable polarity selection +-0: DE signal is active high. +-1: DE signal is active low. +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + WUS + WUS[1:0]: Wakeup from Stop mode interrupt flag selection +This bit-field specify the event which activates the WUF (Wakeup from Stop mode flag). +-00: WUF active on address match (as defined by ADD[7:0] and ADDM7) +-01:Reserved. +-10: WUF active on Start bit detection +-11: WUF active on RXNE. +This bit field can only be written when the LPUART is disabled (UE=0). + 20 + 2 + read-write + + + WUFIE + WUFIE: Wakeup from Stop mode interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An LPUART interrupt is generated whenever WUF=1 in the LPUART_ISR register + 22 + 1 + read-write + + + TXFTIE + TXFTIE: TXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in +TXFTCFG. + 23 + 1 + read-write + + + RXFTCFG + RXFTCFG: Receive FIFO threshold configuration +-000:Receive FIFO reaches 1/8 of its depth. +-001:Receive FIFO reaches 1/4 of its depth. +-010:Receive FIFO reaches 1/2 of its depth. +-011:Receive FIFO reaches 3/4 of its depth. +-100:Receive FIFO reaches 7/8 of its depth. +-101:Receive FIFO becomes full. +Remaining combinations: Reserved. + 25 + 3 + read-write + + + RXFTIE + RXFTIE: RXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when Receive FIFO reaches the threshold +programmed in RXFTCFG. + 28 + 1 + read-write + + + TXFTCFG + TXFTCFG: TXFIFO threshold configuration +-000:TXFIFO reaches 1/8 of its depth. +-001:TXFIFO reaches 1/4 of its depth. +-010:TXFIFO reaches 1/2 of its depth. +-011:TXFIFO reaches 3/4 of its depth. +-100:TXFIFO reaches 7/8 of its depth. +-101:TXFIFO becomes empty. +Remaining combinations: Reserved. + 29 + 3 + read-write + + + + + BRR + BRR + BRR register + 0x0C + 0x20 + read-write + 0x00000000 + + + BRR + BRR[19:0] + 0 + 20 + read-write + + + + + RQR + RQR + RQR register + 0x18 + 0x20 + read-write + 0x00000000 + + + SBKRQ + SBKRQ: Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as +the transmit machine is available. + 1 + 1 + write-only + + + MMRQ + MMRQ: Mute mode request +Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + RXFRQ: Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This allows to discard the received data without reading them, and avoid an overrun +condition. + 3 + 1 + write-only + + + TXFRQ + TXFRQ: Transmit data flush request +When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. +This allows to discard the transmit data. This bit must be used only in Smartcard mode, +when data has not been sent due to errors (NACK) and the FE flag is active in the +USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved +and forced by hardware to 0 +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE +(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is +supported in both UART and Smartcard modes. + 4 + 1 + write-only + + + + + ISR + ISR + ISR register + 0x1C + 0x20 + read-only + 0x000000C0 + + + PE + PE: Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by +software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +-0: No parity error +-1: Parity error + 0 + 1 + read-only + + + FE + FE: Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character +is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +In Smartcard mode, in transmission, this bit is set when the maximum number of transmit +attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR1 register. +-0: No Framing error is detected +-1: Framing error or break character is detected + 1 + 1 + read-only + + + NF + NF: START bit Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by +software, writing 1 to the NFCF bit in the USART_ICR register. +-0: No noise is detected +-1: Noise is detected + 2 + 1 + read-only + + + ORE + ORE: Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case +FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the +USARTx_ICR register. +An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. +-0: No overrun error +-1: Overrun error is detected + 3 + 1 + read-only + + + IDLE + IDLE: Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if +IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in +the USART_ICR register. +-0: No Idle line is detected +-1: Idle line is detected + 4 + 1 + read-only + + + RXNE_RXFNE + RXNE/RXFNE:Read data register not empty/RXFIFO not empty +RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been +transferred +to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from +the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It +is cleared when the RXFIFO is empty. +The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR +register. +An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. +-0: Data is not received +-1: Received data is ready to be read. + 5 + 1 + read-only + + + TC + TC: Transmission complete +This bit indicates when the last data written in the USART_TDR has been transmitted out of +the shift register. +It is set by hardware if the transmission of a frame containing data is complete and if +TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is +cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the +USART_TDR register. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +-0: Transmission is not complete +-1: Transmission is complete + 6 + 1 + read-only + + + TXE_TXFNF + TXE/TXFNF: Transmit data register empty/TXFIFO not full +When FIFO mode is disabled, TXE is set by hardware when the content of the +USARTx_TDR register has been transferred into the shift register. It is cleared by a write to +the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the +USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of +transmission failure). +When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so +data can be written in the USART_TDR. Every write in the USART_TDR places the data in +the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag +is cleared indicating that data can not be written into the USART_TDR. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After +sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to +writing in TXFIFO. (TXFNF and TXFE will be set at the same time). +An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. +-0: Data register is full/Transmit FIFO is full. +-1: Data register/Transmit FIFO is not full + 7 + 1 + read-only + + + CTSIF + CTSIF: CTS interrupt flag +This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared +by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +-0: No change occurred on the nCTS status line +-1: A change occurred on the nCTS status line + 9 + 1 + read-only + + + CTS + CTS: CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. +-0: nCTS line set +-1: nCTS line reset + 10 + 1 + read-only + + + BUSY + BUSY: Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the +RX line (successful start bit detected). It is reset at the end of the reception (successful or +not). +-0: USART is idle (no reception) +-1: Reception on going + 16 + 1 + read-only + + + CMF + CMF: Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is +cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. +-0: No Character match detected +-1: Character Match detected + 17 + 1 + read-only + + + SBKF + SBKF: Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing +1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during +the stop bit of break transmission. +-0: No break character is transmitted +-1: Break character will be transmitted + 18 + 1 + read-only + + + RWU + RWU: Receiver wakeup from Mute mode +This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a +wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) +is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the +MMRQ bit in the USART_RQR register. +-0: Receiver in active mode +-1: Receiver in mute mode + 19 + 1 + read-only + + + WUF + WUF: Wakeup from Stop mode flag +This bit is set by hardware, when a wakeup event is detected. The event is defined by the +WUS bit field. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. +An interrupt is generated if WUFIE=1 in the LPUART_CR3 register + 20 + 1 + read-only + + + TEACK + TEACK: Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by +the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 +in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + REACK: Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by +the USART. +It can be used to verify that the USART is ready for reception before entering Stop mode. + 22 + 1 + read-only + + + TXFE + TXFE: TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one +data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in +the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. +-0: TXFIFO is not empty. +-1: TXFIFO is empty. + 23 + 1 + read-only + + + RXFF + RXFF: RXFIFO Full +This bit is set by hardware when RXFIFO is Full. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. +-0: RXFIFO is not Full. +-1: RXFIFO is Full. + 24 + 1 + read-only + + + RXFT + RXFT: RXFIFO threshold flag +This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 +register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and +one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in +the USART_CR3 register. +-0: Receive FIFO doesnt reach the programmed threshold. +-1: Receive FIFO reached the programmed threshold + 26 + 1 + read-only + + + TXFT + TXFT: TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG +in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is +generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. +-0: TXFIFO doesnt reach the programmed threshold. +-1: TXFIFO reached the programmed threshold + 27 + 1 + read-only + + + + + ICR + ICR + ICR register + 0x20 + 0x20 + read-write + 0x00000000 + + + PECF + PECF: Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + FECF: Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register + 1 + 1 + write-only + + + NECF + NECF: Noise detected clear flag +Writing 1 to this bit clears the NF flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + ORECF: Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + IDLECF: Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TCCF + TCCF: Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register + 6 + 1 + write-only + + + CTSCF + CTSCF: CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register + 9 + 1 + write-only + + + CMCF + CMCF: Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register + 17 + 1 + write-only + + + WUCF + WUCF: Wakeup from Stop mode clear flag +Writing 1 to this bit clears the WUF flag in the LPUART_ISR register. + 20 + 1 + write-only + + + + + RDR + RDR + RDR register + 0x24 + 0x20 + read-only + 0x0 + + + RDR + RDR[8:0]: Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the +internal bus (see Figure 124). +When receiving with the parity enabled, the value read in the MSB bit is the received parity +bit. + 0 + 9 + read-only + + + + + TDR + TDR + TDR register + 0x28 + 0x20 + read-write + 0x0 + + + TDR + TDR[8:0]: Transmit data value +Contains the data character to be transmitted. +The USARTx_TDR register provides the parallel interface between the internal bus and the +output shift register (see Figure 124). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), +the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect +because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + PRESC + PRESC + PRESC register + 0x2C + 0x20 + read-write + 0x0 + + + PRESCALER + PRESCALER[3:0]: Clock prescaler +The USART input clock can be divided by a prescaler: +-0000: input clock not divided +-0001: input clock divided by 2 +-0010: input clock divided by 4 +-0011: input clock divided by 6 +-0100: input clock divided by 8 +-0101: input clock divided by 10 +-0110: input clock divided by 12 +-0111: input clock divided by 16 +-1000: input clock divided by 32 +-1001: input clock divided by 64 +-1010: input clock divided by 128 +-1011: input clock divided by 256 +Remaing combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, +programmed prescaler value will be '1011' i.e. input clock divided by 256 + 0 + 4 + read-write + + + + + + + MISC + MISC + 0x49000700 + + 0x0 + 0x80 + registers + + + + RFIP_VERSION + RFIP_VERSION + RFIP_VERSION register + 0x0 + 0x20 + read-only + 0x00001200 + + + REVISION + Revision of the MR_SubG (to be used for metal fixes) + 4 + 4 + read-only + + + VERSION + Version of the MR_SubG (to be used for cut upgrades) + 8 + 4 + read-only + + + PRODUCT + Used for major upgrades (new protocols support / new features) + 12 + 4 + read-only + + + + + RRM_UDRA_CTRL + RRM_UDRA_CTRL + RRM_UDRA_CTRL register + 0x4 + 0x20 + write-only + 0x00000000 + + + RRM_CMD_REQ + Action bit: write 1 to request a RRM-UDRA command. + 0 + 1 + write-only + + + + + SEQUENCER_CTRL + SEQUENCER_CTRL + SEQUENCER_CTRL register + 0x8 + 0x20 + read-write + 0x00000000 + + + GEN_SEQ_TRIGGER + Action bit: write 1 to generate a trigger event on Sequencer. + 0 + 1 + write-only + + + DISABLE_SEQ + Enable/disable the Sequencer + + 1 + 1 + read-write + + + + + ABSOLUTE_TIME + ABSOLUTE_TIME + ABSOLUTE_TIME register + 0xc + 0x20 + read-only + 0x00000000 + + + ABSOLUTE_TIME + Indicate the interpolated absolute. + 0 + 32 + read-only + + + + + SCM_COUNTER_VAL + SCM_COUNTER_VAL + SCM_COUNTER_VAL register + 0x10 + 0x20 + read-only + 0x00000000 + + + SCM_COUNTER_CURRVAL + Slow Clock Measurement: number of 16 MHz clock cycles contained in 32 slow clock periods. + 0 + 15 + read-only + + + + + SCM_MIN_MAX + SCM_MIN_MAX + SCM_MIN_MAX register + 0x14 + 0x20 + read-write + 0x00007FFF + + + SCM_COUNTER_MINVAL + Slow Clock Measurement: minimum SCM_COUNTER value seen since the counter is ON and since last clear request. + 0 + 15 + read-only + + + SCM_COUNTER_MAXVAL + Slow Clock Measurement: maximum SCM_COUNTER value seen since the counter is ON and since last clear request. + 16 + 15 + read-only + + + CLEAR_MIN_MAX + Write 1' to clear the SCM_COUNTER_MINVAL and SCM_COUNTER_MAXVAL bit fields. + 31 + 1 + write-only + + + + + WAKEUP_IRQ_STATUS + WAKEUP_IRQ_STATUS + WAKEUP_IRQ_STATUS register + 0x18 + 0x20 + read-write + 0x00000000 + + + CPU_WAKEUP_F + Set when the interpolated absolute time matches the CPU_WAKEUPTIME while WAKEUP_CTRL. + 0 + 1 + + + RFIP_WAKEUP_F + Set when the interpolated absolute time matches the RFIP_WAKEUPTIME while WAKEUP_CTRL. + 1 + 1 + + + + + + + MR_SUBG + MR_SUBG + 0x49000000 + + 0x0 + 0x400 + registers + + + MR_SUBG_BUSY + MR_SUBG Busy interrupt + 20 + + + MR_SUBG + MR_SUBG interrupt + 21 + + + TX_RX_SEQUENCE + MR_SUBG TX/RX Sequence +interrupt + 22 + + + + RF_FSM0_TIMEOUT + RF_FSM0_TIMEOUT + RF_FSM0_TIMEOUT register + 0x00 + 0x20 + read-write + 0x00000000 + + + ENA_RFREG_TIMER + Timeout for the RF regulator startup (duration in ENA_RF_REG state) + + 0 + 8 + read-write + + + + + RF_FSM1_TIMEOUT + RF_FSM1_TIMEOUT + RF_FSM1_TIMEOUT register + 0x04 + 0x20 + read-write + 0x00000006 + + + SYNTH_SETUP_TIMER + Timeout management for the RF regulator to stabilize after RF PLL power on + + 0 + 8 + read-write + + + + + RF_FSM2_TIMEOUT + RF_FSM2_TIMEOUT + RF_FSM2_TIMEOUT register + 0x08 + 0x20 + read-write + 0x00000050 + + + VCO_CALIB_LOCK_TIMER + Timeout for the RF PLL calibration + RF PLL lock (duration in CALIB_VCO+LOCKRXTX state) + + 0 + 8 + read-write + + + + + RF_FSM3_TIMEOUT + RF_FSM3_TIMEOUT + RF_FSM3_TIMEOUT register + 0x0C + 0x20 + read-write + 0x00000028 + + + VCO_LOCK_TIMER + Timeout for the RF PLL lock event when no calibration is requested (duration in LOCKRXTX state) + + 0 + 8 + read-write + + + + + RF_FSM4_TIMEOUT + RF_FSM4_TIMEOUT + RF_FSM4_TIMEOUT register + 0x10 + 0x20 + read-write + 0x0000000F + + + EN_RX_TIMER + Timeout for the analog RX chain setup (duration in EN_RX state) + + 0 + 8 + read-write + + + + + RF_FSM5_TIMEOUT + RF_FSM5_TIMEOUT + RF_FSM5_TIMEOUT register + 0x14 + 0x20 + read-write + 0x00000019 + + + EN_PA_TIMER + Timeout for the analog PA (DAC) setup (duration in EN_PA state) + + 0 + 8 + read-write + + + + + RF_FSM6_TIMEOUT + RF_FSM6_TIMEOUT + RF_FSM6_TIMEOUT register + 0x18 + 0x20 + read-write + 0x00000019 + + + PA_DWN_ANA_TIMER + Timeout for the analog PA (DAC) ramp down (duration in PA_DWN_ANA state) + + 0 + 8 + read-write + + + + + RF_FSM7_TIMEOUT + RF_FSM7_TIMEOUT + RF_FSM7_TIMEOUT register + 0x1C + 0x20 + read-write + 0x00000005 + + + EN_LNA_TIMER + Timeout for the analog RX chain signals settlement once PGA precharge is shut down (duration in EN_LNA state) + + 0 + 8 + read-write + + + + + AFC0_CONFIG + AFC0_CONFIG + AFC0_CONFIG register + 0x20 + 0x20 + read-write + 0x00000025 + + + AFC_SLOW_GAIN_LOG2 + AFC loop gain in slow mode (2's log) + 0 + 4 + read-write + + + AFC_FAST_GAIN_LOG2 + AFC loop gain in fast mode (2's log) + 4 + 4 + read-write + + + + + AFC1_CONFIG + AFC1_CONFIG + AFC1_CONFIG register + 0x24 + 0x20 + read-write + 0x00000018 + + + AFC_FAST_PERIOD + Length of the AFC fast period (in number of samples unit) + + 0 + 8 + read-write + + + + + AFC2_CONFIG + AFC2_CONFIG + AFC2_CONFIG register + 0x28 + 0x20 + read-write + 0x000000C8 + + + AFC_PD_LEAKAGE + AFC Peak Detection leakage. + 0 + 5 + read-write + + + AFC_MODE + Select AFC mode: + + 5 + 1 + read-write + + + AFC_EN + Enable AFC. + 6 + 1 + read-write + + + AFC_FREEZE_ON_SYNC + Freeze AFC correction upon SYNC word detection + 7 + 1 + read-write + + + + + AFC3_CONFIG + AFC3_CONFIG + AFC3_CONFIG register + 0x2C + 0x20 + read-write + 0x000000E8 + + + AFC_INIT_MODE + Control the initialization phase of the AFC and clock recovery algorithms: + + 0 + 1 + read-write + + + AFC_SIGN_PERM_CHECK + Enable the check of sign permanence of AFC corrected signal. + 1 + 1 + read-write + + + AFC_TH_SIGN_PERM + Threshold of chech sign permanence mechanism. + 2 + 4 + read-write + + + AFC_REINIT_OPTION + Select the AFC reinitialization option: + + 6 + 2 + read-write + + + + + CLKREC_CTRL0 + CLKREC_CTRL0 + CLKREC_CTRL0 register + 0x30 + 0x20 + read-write + 0x000000B8 + + + CLKREC_I_GAIN_FAST + Integral fast gain for the clock recovery loop (PLL mode only) + + 0 + 4 + read-write + + + CLKREC_P_GAIN_FAST + Clock recovery fast loop gain (log2) + + 4 + 3 + read-write + + + PSTFLT_LEN + Control the length of the demodulator post-filter + + 7 + 1 + read-write + + + + + CLKREC_CTRL1 + CLKREC_CTRL1 + CLKREC_CTRL1 register + 0x34 + 0x20 + read-write + 0x0000005C + + + CLKREC_I_GAIN_SLOW + Integral slow gain for the clock recovery loop (PLL mode only) + + 0 + 4 + read-write + + + CLKREC_P_GAIN_SLOW + Clock recovery slow loop gain (log2) + + 4 + 3 + read-write + + + CLKREC_ALGO_SEL + Symbol timing recovery algorithm selection + + 7 + 1 + read-write + + + + + DCREM_CTRL0 + DCREM_CTRL0 + DCREM_CTRL0 register + 0x38 + 0x20 + read-write + 0x000000E8 + + + START_GAIN + Filter gain in start mode for the DC removal block. + 0 + 5 + read-write + + + TRACK_GAIN + Filter gain in track mode for the DC removal block. + 7 + 1 + read-write + + + + + IQC_CTRL0 + IQC_CTRL0 + IQC_CTRL0 register + 0x40 + 0x20 + read-write + 0x000000E3 + + + FAST_GAIN + Gain of the correction loop in fast mode. + 0 + 4 + read-write + + + SLOW_GAIN + Gain of the correction loop in slow mode. + 4 + 4 + read-write + + + + + IQC_CTRL1 + IQC_CTRL1 + IQC_CTRL1 register + 0x44 + 0x20 + read-write + 0x00000008 + + + QPD_ATTACK + Attack coefficient for QPD: + + 0 + 8 + read-write + + + + + IQC_CTRL2 + IQC_CTRL2 + IQC_CTRL2 register + 0x48 + 0x20 + read-write + 0x00000008 + + + QPD_DECAY + Decay coefficient for QPD: + + 0 + 8 + read-write + + + + + IQC_CTRL3 + IQC_CTRL3 + IQC_CTRL3 register + 0x4C + 0x20 + read-write + 0x00000007 + + + FAST_TIME + Duration of the fast mode. + 0 + 4 + read-write + + + + + AGC_ANA_ENG + AGC_ANA_ENG + AGC_ANA_ENG register + 0x50 + 0x20 + read-write + 0x00000000 + + + FORCE_AGC_GAINS + Select the mode for AGC analog part: + + 0 + 1 + read-write + + + RFD_RX_ATTEN_AGCGAIN + Attenuation at LNA level by step of 6dB with thermometric code: + + 1 + 4 + read-write + + + RFD_RX_PGA_AGCGAIN + Attenuation at PGA level by step of 6dB with binary code: + + 5 + 3 + read-write + + + + + AGC0_CTRL + AGC0_CTRL + AGC0_CTRL register + 0x54 + 0x20 + read-write + 0x00000099 + + + AGC_HOLD_TIME + AGC hold time. + 0 + 6 + read-write + + + AGC_START_ONHOLD + Start the AGC with a hold phase. + 6 + 1 + read-write + + + AGC_EN + Enable the AGC + + 7 + 1 + read-write + + + + + AGC1_CTRL + AGC1_CTRL + AGC1_CTRL register + 0x58 + 0x20 + read-write + 0x00000062 + + + AGC_MIN_THR + Minimum signal threshold. + 0 + 4 + read-write + + + AGC_MAX_THR + Maximum signal threshold. + 4 + 4 + read-write + + + + + AGC2_CTRL + AGC2_CTRL + AGC2_CTRL register + 0x5C + 0x20 + read-write + 0x000000AF + + + AGC_MEAS_TIME + Measure time. + 0 + 4 + read-write + + + AGC_START_MAX_ATTEN + Start the AGC with maximum attenuation. + 4 + 1 + read-write + + + AGC_FREEZE_ON_SYNC + Enable the freeze on SYNC detection feature + 5 + 1 + read-write + + + AGC_FREEZE_ON_STEADY + Enable the autofreeze feature + 6 + 1 + read-write + + + AGC_HIGH_ATTEN_MODE + Enable the high attenuation mode. + 7 + 1 + read-write + + + + + AGC3_CTRL + AGC3_CTRL + AGC3_CTRL register + 0x60 + 0x20 + read-write + 0x00000090 + + + AGC_MIN_ATTEN + Minimum AGC attenuation. + 0 + 4 + read-write + + + AGC_MAX_ATTEN + Maximum AGC attenuation. + 4 + 4 + read-write + + + + + AGC4_CTRL + AGC4_CTRL + AGC4_CTRL register + 0x64 + 0x20 + read-write + 0x00000002 + + + AGC_FREEZE_THR + Signal threshold for the autofreeze feature. + 0 + 4 + read-write + + + + + AGC_PGA_HWTRIM_OUT + AGC_PGA_HWTRIM_OUT + AGC_PGA_HWTRIM_OUT register + 0xA0 + 0x20 + read-only + 0x00000008 + + + AGC_HW_PGA_TRIM + AGC PGA calibration information loaded by HW from the SoC flash. + 0 + 4 + read-only + + + + + PA_REG + PA_REG + PA_REG register + 0xA8 + 0x20 + read-write + 0x00000000 + + + CFG_FILT + FIR configuration: + + 0 + 2 + read-write + + + PA_DEGEN_ON + Enable a 'degeneration' mode, which introduces a pre-distortion to linearize the power control curve. + 3 + 1 + read-write + + + + + PA_HWTRIM_OUT + PA_HWTRIM_OUT + PA_HWTRIM_OUT register + 0xAC + 0x20 + read-only + 0x00000088 + + + PA_HW_DEGEN_TRIM + MSB part meaning: + + 4 + 4 + read-only + + + + + RSSI_FLT + RSSI_FLT + RSSI_FLT register + 0xBC + 0x20 + read-write + 0x000000E0 + + + OOK_PEAK_DECAY + Peak decay control for OOK: 3 slow decay; 0 fast decay + 0 + 4 + read-write + + + RSSI_FLT + Gain of the RSSI filter + 4 + 4 + read-write + + + + + SYNTH2_ANA_ENG + SYNTH2_ANA_ENG + SYNTH2_ANA_ENG register + 0xC8 + 0x20 + read-write + 0x0000004C + + + RFD_PLL_VCO_ALC_AMP + Select the level of max VCO amplitude in amplitude level control loop. + 0 + 3 + read-write + + + RFD_PLL_LD_WIN_ACC + Select the PLL lock detector window selection: + + 3 + 1 + read-write + + + + + RXADC_HWDELAYTRIM_OUT + RXADC_HWDELAYTRIM_OUT + RXADC_HWDELAYTRIM_OUT register + 0xE8 + 0x20 + read-only + 0x0000001B + + + RXADC_HW_DELAYTRIM_I + Control bits of the RX ADC loop delay for I channel (from SoC Flash). + 0 + 3 + read-only + + + RXADC_HW_DELAYTRIM_Q + Control bits of the RX ADC loop delay for Q channel (from SoC Flash). + 3 + 3 + read-only + + + + + RX_AAF_HWTRIM_OUT + RX_AAF_HWTRIM_OUT + RX_AAF_HWTRIM_OUT register + 0xF4 + 0x20 + read-only + 0x00000006 + + + AAF_HW_FCTRIM + AAF calibration information loaded by HW. + 0 + 4 + read-only + + + + + SINGEN_ANA_ENG + SINGEN_ANA_ENG + SINGEN_ANA_ENG register + 0x100 + 0x20 + read-write + 0x00000000 + + + RFD_SINGEN_ENA + Enable SINGEN signal for the RFSUBGanalog IP. + 0 + 1 + read-write + + + RFD_SINGEN_DIV2_PUP + This bit value is directly connected to the RFSUBG analog IP pin. + 1 + 1 + read-write + + + RFD_SINGEN_LBE + This bit value is directly connected to the RFSUBG analog IP pin. + 2 + 1 + read-write + + + + + RF_INFO_OUT + RF_INFO_OUT + RF_INFO_OUT register + 0x108 + 0x20 + read-only + 0x00000040 + + + FQCY_BAND_ID + FQCY_BAND_ID[3:0]: Indicates the version of the RFSUBG IP embedded in the device + + 0 + 4 + read-only + + + RFSUBG_ID + Indicate the version of the analog RFSUBG IP embedded in the device + + 4 + 4 + read-only + + + + + RF_FSM8_TIMEOUT + RF_FSM8_TIMEOUT + RF_FSM8_TIMEOUT register + 0x124 + 0x20 + read-write + 0x0000000A + + + SYNTH_PDWN_TIMER + Timeout management for the RF regulator to stabilize after PLL shut down + + 0 + 8 + read-write + + + + + RF_FSM9_TIMEOUT + RF_FSM9_TIMEOUT + RF_FSM9_TIMEOUT register + 0x128 + 0x20 + read-write + 0x00000006 + + + END_RX_TIMER + Timeout management for the RF regulator to stabilize after analog RX chain shut down + + 0 + 8 + read-write + + + + + RF_FSM10_TIMEOUT + RF_FSM10_TIMEOUT + RF_FSM10_TIMEOUT register + 0x12C + 0x20 + read-write + 0x00000006 + + + END_TX_TIMER + Timeout management for the RF regulator to stabilize after clock stops on the analog PA block + + 0 + 8 + read-write + + + + + SUBG_DIG_CTRL0 + SUBG_DIG_CTRL0 + SUBG_DIG_CTRL0 register + 0x144 + 0x20 + read-write + 0x00000000 + + + FORCE_GPIO_OUTPUT + Option for the direct GPIO signal output + + 0 + 1 + read-write + + + + + RX_CHAIN_ENG + RX_CHAIN_ENG + RX_CHAIN_ENG register + 0x148 + 0x20 + read-write + 0x00000003 + + + LNA_ISOL_ENA + Option for LNA during the EN_RX state of the Radio FSM: + + 0 + 1 + read-write + + + PGA_PRECH_ENA + Option for PGA precharge during the EN_RX state of the Radio FSM: + + 1 + 1 + read-write + + + + + DEMOD_DIG_ENG + DEMOD_DIG_ENG + DEMOD_DIG_ENG register + 0x14C + 0x20 + read-write + 0x00000003 + + + RX_BLANKING_LENGTH + Number of data samples at RX start for which the signal at the output of the channel filter is kept forced to zero: + + 0 + 3 + read-write + + + + + + + PWRC + PWRC + 0x48500000 + + 0x0 + 0xA8 + registers + + + PVD + PVD / BORH + 2 + + + + CR1 + CR1 + CR1 register + 0x0 + 0x20 + read-write + 0x114 + + + LPMS + LPMS Low Power Mode Selection +Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep. +- 0: Deep Stop mode (default) +- 1: Shutdown mode + 0 + 1 + read-write + + + ENSDNBOR + ENSDNBOR: Enable BOR supply monitoring during shutdown mode. +- 1: the PD_ALL_SHUTDOWN signal is not set during SHUTDOWN mode +- 0: the PD_ALL_SHUTDOWN signal is set during SHUTDOWN mode. + 1 + 1 + read-write + + + IBIAS_RUN_AUTO + IBIAS_RUN_AUTO: Enable automatic IBIAS control during RUN/DEEPSTOP mode. +- 0: IBIAS control is manual (and controlled by IBIAS_RUN_STATE register) +- 1: IBIAS control is automatic (default). + 2 + 1 + read-write + + + IBIAS_RUN_STATE + IBIAS_RUN_STATE: Enable/Disable IBIAS during RUN mode when automatic mode is +disabled. +- 0: IBIAS control is disabled (default). +- 1: IBIAS control is enabled. + 3 + 1 + read-write + + + APC + APC Apply Pull-up and pull-down configuration from CPU +- 1: the I/O pull-up and pull-down configurations defined in the PUCRx and PDCRx registers is applied. +- 0: the PUCRx and PDCRx are not used to control the I/O pull-up and pull-down configuration of the product I/Os. + 4 + 1 + read-write + + + ENBORH + ENBORH: enable BORH configuration +- 1: BORH is enabled, threshold level depends on SELBOR[1:0] +- 0: BORH off (VBOR0): threshold level for above 1.60V voltage operation. + 5 + 1 + read-write + + + SELBORH + SELBORH[1:0]: BORH selection of Vbor threshold +- 11: BORH Level 4(VBOR4): threshold level for above 2.81 V voltage operation. +- 10: BORH Level 3 (VBOR3): threshold level for above 2.52 V voltage operation +- 01: BORH Level 2 (VBOR2): threshold level for above 2.21 V voltage operation +- 00: BORH Level 1 (VBOR1): threshold level for above 2.0V voltage operation. + 6 + 2 + read-write + + + ENBORL + ENBORL: Enable BORL reset supervising during RUN mode. +- 0: No BORL is monitored during RUN mode. +- 1: BORL is monitored during RUN mode (a POR reset will happen if VDDIO goes below 1.6V during RUN mode) (default). +Note: Enabling this feature prevents blocking the device if VDDIO goes below supported voltages during RUN. + 8 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x4 + 0x20 + read-write + 0x0000 + + + PVDE + PVDE Programmable Voltage Detector Enable +When this bit is set the Power Voltage Detector is enabled + 0 + 1 + read-write + + + PVDLS + PVDLS[2:0] Programmable Voltage Detector Level selection +- 000: 2.05 V - Lowest level +- 001: 2.20 V +- 010: 2.36 V +- 011: 2.52 V +- 100: 2.64 V +- 101: 2.81 V +- 110: 2.91 V - Highest level +- 111: External input analog voltage (compare internally to VBGP; When external input VBGP +then PVDO=1) + 1 + 3 + read-write + + + DBGRET + DBGRET: PA2 and PA3 retention enable after DEEPSTOP +- 0: PA2, PA3 don't retain their status exiting from DEEPSTOP (default). +- 1: PA2, PA3 retain their status exiting from DEEPSTOP. + 4 + 1 + read-write + + + RAMRET1 + RAMRET1: RAM1 retention during low power mode +- 1: RAM1 bank is powered during low power mode +- 0: RAM1 bank is disabled during low power mode (by default) + 5 + 1 + read-write + + + LPREG_FORCE_VH + force LPREG=1.2V during DEEPSTOP +- 1: Force LPREG=1.2V during DEEPSTOP +- 0: No Force (Default) +Note LPREG= 1.2v can still apply when LCDEN or COMP.SCALEREN request it + 6 + 1 + read-write + + + LPREG_VH_STATUS + status LPREG VH (1.2v) during DEEPSTOP +- 1: LPREG=1.2V during DEEPSTOP +- 0: LPREG=1V during DEEPSTOP + 7 + 1 + read-only + + + GPIORET + GPIORET: GPIO retention enable. +- 0: Release GPIO retention after deepstop (Should be reset after restore Context) +- 1: Enable GPIO Retention during deepstop (Must be set before deepstop) + 8 + 1 + read-write + + + ENTS + ENTS: Enable Temperature Sensor +- 1: Temperature sensor is enabled +- 0: Temperature sensor is disabled + 9 + 1 + read-write + + + RFREGEN + RFREGEN: RF Regulator Enable +- 1: Enable RF Regulator +- 0: Disable RF Regulator (Note: RF Regulator can still be enabled by the RFSUGB or RCC_CR.HSEON) + 10 + 1 + read-write + + + RFREGCEXT + RFREGCEXT: RF Regulator External Supply Bypass +- 1: External supply bypass capability +- 0: Internal supply only + 11 + 1 + read-write + + + RFREGBYP + RFREGBYP: RF Regulator Bypass Enable +- 1: LDO output connected to VSMPS. +- 0: internally generated 1.2V + 12 + 1 + read-write + + + RFREGRDY + RFDREGRDY: RF Regulator Ready flag +- 1: RF Regulator is ready +- 0: RF Regulator is not ready + 13 + 1 + read-only + + + RFREGON_STATUS + RFREGON_STATUS: RF Regulator On Status +- 1: RF Regulator is enabled +- 0: RF Regulator is disabled + 14 + 1 + read-only + + + + + IEWU + IEWU + IEWU register + 0x8 + 0x20 + read-write + 0x0000 + + + EIWL0 + EWL0 Enable Internal WakeUp line LPUART +When this bit is set the internal wakeup line is enabled and a rising edge will trigger a CPU wakeup event. +- 0: wakeup disabled. +- 1: wakeup enabled. + 0 + 1 + read-write + + + EIWL1 + EIWL1 Enable Internal WakeUp line RTC +When this bit is set the internal wakeup line is enabled and a rising edge will trigger a CPU wakeup event. +- 0: wakeup disabled. +- 1: wakeup enabled. + 1 + 1 + read-write + + + EIWL2 + EIWL2 Enable Internal WakeUp line LCD +When this bit is set the internal wakeup line is enabled and a rising edge will trigger a CPU wakeup event. +- 0: wakeup disabled. +- 1: wakeup enabled. + 2 + 1 + read-write + + + EIWL3 + EIWL3 Enable Internal Wakeup line COMP +When this bit is set the COMP wakeup is enabled and an edge will trigger a COMP wakeup event +- 0: wakeup disabled. +- 1: wakeup enabled. + 3 + 1 + read-write + + + EIWL4 + EIWL4 Enable Internal Wakeup line LCSC +When this bit is set the LCSC wakeup is enabled and an edge will trigger a LCSC wakeup event +- 0: wakeup disabled. +- 1: wakeup enabled. + 4 + 1 + read-write + + + EWMRSUBG + EWMRSUB Wakeup MRSUBG Enable +When this bit is set the MRSUBG wakeup is enabled and a rising edge will trigger a MRSUBG wakeup event +- 0: MRSUBG wakeup disabled. +- 1: MRSUBG wakeup enabled. + 8 + 1 + read-write + + + EWMRSUBGHCPU + EWMRSUBGHCPU Wakeup MRSUBG Host CPU Enable +When this bit is set the MRSUBG HOST CPU wakeup is enabled and a rising edge will trigger a MRSUBG Host CPU wakeup event +- 0: MRSUBG Host CPU wakeup disabled. +- 1: MRSUBG Host CPU wakeup enabled. + 9 + 1 + read-write + + + EWLPAWUR + EWLPAWUR: Wakeup Bubble Enable +When this bit is set the Bubble wakeup is enabled and a rising edge will trigger a LPAWUR wakeup event +- 0: LPAWUR wakeup disabled. +- 1: LPAWUR wakeup enabled. + 10 + 1 + read-write + + + + + IWUP + IWUP + IWUP register + 0xc + 0x20 + read-write + 0x0 + + + IWUP0 + IWUP0: Wakeup polarity for internal wakeup line 0 event (LPUART). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 0 + 1 + read-write + + + IWUP1 + IWUP1: Wakeup polarity for internal wakeup line 1 event (RTC). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 1 + 1 + read-write + + + IWUP2 + IWUP2: Wakeup polarity for internal wakeup line 2 event (LCD). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 2 + 1 + read-write + + + IWUP3 + IWUP3: Wakeup polarity for internal wakeup line 3 event (COMP). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 3 + 1 + read-write + + + IWUP4 + IWUP4: Wakeup polarity for internal wakeup line 4 event (LCSC). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 4 + 1 + read-write + + + WMRSUBGHP + WMRSUBGHP: Wakeup polarity for internal wakeup MRSUBG event +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 8 + 1 + read-write + + + WMRSUBGHCPUP + WMRSUBGHCPUP: Wakeup polarity for internal wakeup MRSUBG Host CPU event +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 9 + 1 + read-write + + + WLPAWURP + WLPAWURP: Wakeup polarity for wakeup LPAWUR event. +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 10 + 1 + read-write + + + + + IWUF + IWUF + IWUF register + 0x10 + 0x20 + read-write + 0x0 + + + IWUF0 + IWUF0: Internal wakeup flag (LPUART). +- 0: no wakeup from LPUART occurred since last clear. +- 1: a wakeup from LPUART occurred since last clear. +Cleared by writing 1 in this bit. + 0 + 1 + read-write + + + IWUF1 + IWUF1: Internal wakeup flag (RTC). +- 0: no wakeup from RTC occurred since last clear. +- 1: a wakeup from RTC occurred + 1 + 1 + read-write + + + IWUF2 + IWUF2: Internal wakeup flag (LCD). +- 0: no wakeup from LCD occurred since last clear. +- 1: a wakeup from LCD occurred since last clear. +Cleared by writing 1 in this bit. + 2 + 1 + read-write + + + IWUF3 + IWUF3: Internal wakeup flag (COMP). +- 0: no wakeup from COMP occurred since last clear. +- 1: a wakeup from COMP occurred since last clear. +Cleared by writing 1 in this bit. + 3 + 1 + read-write + + + IWUF4 + IWUF4: Internal wakeup flag (LCSC). +- 0: no wakeup from LCSC occurred since last clear. +- 1: a wakeup from LCSC occurred since last clear. +Cleared by writing 1 in this bit. + 4 + 1 + read-write + + + WMRSUBGF + WMRSUBGF Wakeup MRSUBG Flag +This bit is set by hardware when a MRSUBG wakeup is detected +It is cleared by a reset pad or by software writing 1 in this bit field. +- 0: No MRSUBG Wakeup detected +- 1: MRSUBG Wakeup detected +writting 1 in this bit, clears the interrupt + 8 + 1 + read-write + + + WMRSUBGHCPUF + WMRSUBGHCPUF Wakeup MRSUBG HOST CPU Flag (cf. user manual) +This bit is set by hardware when a MRSUBG HOST CPU wakeup is detected +It is cleared by a reset pad or by software writing 1 in this bit field. +- 0: No MRSUBG Host CPU wakeup detected +- 1: MRSUBG Host CPU wakeup detected +writting 1 in this bit, clears the interrupt + 9 + 1 + read-write + + + WLPAWURF + WLPAWURF Wakeup LPAWUR Flag (cf. user manual) +This bit is set by hardware when a LPAWUR wakeup is detected +It is cleared by a reset pad or by software writing 1 in this bit field. +- 0: No LPAWUR wakeup detected +- 1: LPAWUR wakeup detected +writting 1 in this bit, clears the interrupt + 10 + 1 + read-write + + + + + SR2 + SR2 + SR2 register + 0x14 + 0x20 + read-only + 0xF3F6 + + + SMPSBYPR + SMPSBYPR: SMPS Force Bypass Control Replica +This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 0 + 1 + read-only + + + SMPSENR + SMPSENR: SMPS Enable Control Replica +This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 1 + 1 + read-only + + + SMPSRDY + SMPSRDY: SMPS Ready Status +This bit provides the information whether SMPS is ready. +- 0: SMPS regulator is not ready +- 1: SMPS regulator is ready. + 2 + 1 + read-only + + + IOBOOTVAL2 + Bit3: PB15 input value on VDD33 latched at POR +Bit2: PB14 input value on VDD33 latched at POR +Bit1: PB13 input value on VDD33 latched at POR +Bit0: PB12 input value on VDD33 latched at POR + 4 + 4 + read-only + + + REGLPS + REGLPS: Regulator Low Power Started +This bit provides the information whether low power regulator is ready. +- 0: LP regulator is not ready. +- 1: LP regulator is ready. + 8 + 1 + read-only + + + REGMS + REGMS: Main regulator ready status. +- 0: The Main regulator is not ready. +- 1: The Main regulator is ready. + 9 + 1 + read-only + + + PVDO + PVDO: Power Voltage Detector Output +When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is +lower than the selected PVD threshold (CR2.PVDLS) + 11 + 1 + read-only + + + IOBOOTVAL + Bit3: PA11 input value on VDD33 latched at POR +Bit2: PA10 input value on VDD33 latched at POR +Bit1: PA9 input value on VDD33 latched at POR +Bit0: PA8 input value on VDD33 latched at POR + 12 + 4 + read-only + + + + + CR5 + CR5 + CR5 register + 0x1c + 0x20 + read-write + 0x6014 + + + SMPSLVL + SMPSLVL[3:0] SMPS Output Level Voltage Selection +Select the SMPS output voltage with a granularity of 50mV. Default = '0100' (1.4V) +Vout = 1.2 + 0.05*SMPSOUT (V) + 0 + 4 + read-write + + + SMPSBOMSEL + SMPSBOMSEL: SMPS BOM Selection: +- 00: BOM1 +- 01: BOM2 (default) +- 10: BOM3 +- 11: n/a + 4 + 2 + read-write + + + SMPS_BOF_STATIC + SMPS_BOF_STATIC: SMPS Bypass on the Fly static +- 0 : disabled (by default) +- 1 : SMPS Bypass on the fly static is enabled (EN_SW=1) + 6 + 1 + read-write + + + NOSMPS_BOF + NOSMPS_BOF: No SMPS Mode to be used in accordance to SMPS_BOF_STATIC =1 +When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only SMPS_BOF_STATIC=1. +- 0 : No effect, SMPS is enabled. (default) +- 1 : SMPS is disabled; + 7 + 1 + read-write + + + SMPSLPOPEN + SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). +When this bit is set, when the chip is in Low power mode the SMPS regulator will be disabled (HZ) Documentation needed. +- 0 : in Low Power mode, SMPS is in PRECHARGE, output is connected to VDDIO. (default) +- 1 : in Low Power mode, SMPS is disabled, output is floating + 8 + 1 + read-write + + + SMPSFBYP + SMPSFB Force SMPS Regulator in bypass mode +When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. +- 0 : no effect (by default) +- 1 : SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1) + 9 + 1 + read-write + + + NOSMPS + NOSMPS: No SMPS Mode +When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only when SMPS_FB pad is directly connected to VBATT or Vext, without L/C BOM. +- 0 : No effect, SMPS is enabled. (Default) +- 1 : SMPS is disabled; + 10 + 1 + read-write + + + SMPS_ENA_DCM + SMPS_ENA_DCM: enable discontinuous conduction mode +- 0 : disable (Default) +- 1 : enable + 11 + 1 + read-write + + + CLKDETR_DISABLE + CLKDETR_DISABLE: disable SMPS clock detection +The SMPS clock detection enables an automatic SMPS bypass switching in case of unwanted loss of SMPS clock. +- 0 : SMPS clock detection enabled (default) +- 1 : SMPS clock detection disabled + 12 + 1 + read-write + + + SMPS_PRECH_CUR_SEL + SMPS_PRECH_CUR_SEL[1:0] Selection for SMPS PRECHARGE limit current +- 00: 2.5mA +- 01: 5mA +- 10: 10mA +- 11: 20mA (default) + 13 + 2 + read-write + + + SMPS_BOF_DYN + SMPS_BOF_DYN: SMPS Bypass on the Fly dynamic +- 0 : disabled (by default) +- 1 : SMPS Bypass on the fly dynamic is enabled (EN_LDO=1) + 15 + 1 + read-write + + + + + PUCRA + PUCRA + PUCRA register + 0x20 + 0x20 + read-write + 0xFFF7 + + + PUA + PUA[x] : Pull Up Port A +Pull up activation on port A[i] pad when APC bit of PWRC CR1 is set +- 1: Pull-Up activated on port A[i] when APC bit of PWRC CR1 bit is set and PWR_PDCRA[x] is reset +- 0: Pull-Up not activated on port A[i] + 0 + 16 + read-write + + + + + PDCRA + PDCRA + PDCRA register + 0x24 + 0x20 + read-write + 0x8 + + + PDA + PDA[x]: Pull Down Port A +Pull Down activation on port A[i] pad when APC bit of PWRC CR1 is set +- 1: Pull-Down activated on Port A[i] when APC bit of PWRC CR1 bit is set +- 0: Pull-Down not activated on Port A[i] + 0 + 16 + read-write + + + + + PUCRB + PUCRB + PUCRB register + 0x28 + 0x20 + read-write + 0xFFFF + + + PUB + PUB[x] : Pull Up Port B +Pull up activation on port B[i] pad when APC bit of PWRC CR1 is set +- 1: Pull-Up activated on port B[i] when APC bit of PWRC CR1 bit is set and PWR_PDCRB[x] is reset +- 0: Pull-Up not activated on port B[i] + 0 + 16 + read-write + + + + + PDCRB + PDCRB + PDCRB register + 0x2c + 0x20 + read-write + 0x0 + + + PDB + PDB[x]: Pull Down Port B +Pull Down activation on port B[i] pad when APC bit of PWRC CR1 is set +- 1: Pull-Down activated on Port B[i] when APC bit of PWRC CR1 bit is set +- 0: Pull-Down not activated on Port B[i] + 0 + 16 + read-write + + + + + EWUA + EWUA + EWUA register + 0x30 + 0x20 + read-write + 0x0 + + + EWUA + EWUA[x] Enable WakeUp line PA[x] +When this bit is set the PA[x] wakeup line is enabled and a rising or falling edge on wakeup line PA[x] will trigger a CPU wakeup event depending on CR7.WUPA[x] bit. + 0 + 16 + read-write + + + + + WUPA + WUPA + WUPA register + 0x34 + 0x20 + read-write + 0x0 + + + WUPA + WUPA[x] Wake-up Line PA[x] Polarity +This bit defines the polarity used for event detection on external wake-up line PA[x] +- 0: Detection on high level (rising edge) +- 1: Detection on low level (falling edge) + 0 + 16 + read-write + + + + + WUFA + WUFA + WUFA register + 0x38 + 0x20 + read-write + 0x0 + + + WUFA + WUFA[x] WakeUp Flag PA[x] +This bit is set when a wakeup is detected on wakeup line PA[x]. It is cleared by a reset pad or by writing 1 in this bit field. +Writing 1 this bit, clears the interrupt: + 0 + 16 + read-write + + + + + EWUB + EWUB + EWUB register + 0x40 + 0x20 + read-write + 0x0 + + + EWUB + EWUB[x] Enable WakeUp line PB[x] +When this bit is set the PB[x] wakeup line is enabled and a rising or falling edge on wakeup line PB[x] will trigger a CPU wakeup event depending on CR9.WUPB[x] bit. + 0 + 16 + read-write + + + + + WUPB + WUPB + WUPB register + 0x44 + 0x20 + read-write + 0x0 + + + WUPB + WUPB[x] Wake-up Line PB[x] Polarity +This bit defines the polarity used for event detection on external wake-up line PB[x] +- 0: Detection on high level (rising edge) +- 1: Detection on low level (falling edge) + 0 + 16 + read-write + + + + + WUFB + WUFB + WUFB register + 0x48 + 0x20 + read-write + 0x0 + + + WUFB + WUFB[x] WakeUp Flag PB[x] +This bit is set when a wakeup is detected on wakeup line PB[x]. It is cleared by a reset pad or by writing 1 in this bit field. +Writing 1 this bit, clears the interrupt: + 0 + 16 + read-write + + + + + SDWN_WUEN + SDWN_WUEN + SDWN_WUEN register + 0x4c + 0x20 + read-write + 0x0 + + + WUEN + WUEN PB0 I/O WakeUp from shutdown Enable +When this bit is set the PB0 wakeup from shutdown is enabled so that a rising or falling edge on PB0 (depending on SDWN_WUPOL..WUPOL bit) will trigger a CPU wakeup. It is cleared by a PORESETn. +- 0: PB0 wakeup from shutdown disabled +- 1: PB0 wakeup from shutdown enabled + 0 + 1 + read-write + + + + + SDWN_WUPOL + SDWN_WUPOL + SDWN_WUPOL register + 0x50 + 0x20 + read-write + 0x0 + + + WUPOL + WUPOL PB0 I/O WakeUp from shutdown Polarity +This bit defines the polarity used for wakeup from shutdown detection on PB0 pin. It is cleared by a PORESETn. +- 0: Detection on high level (rising edge) +- 1: Detection on low level (falling edge) + 0 + 1 + read-write + + + + + SDWN_WUF + SDWN_WUF + SDWN_WUF register + 0x54 + 0x20 + read-write + 0x0 + + + WUF + WUF PB0 I/O WakeUp from shutdown Flag +This bit is set when a wakeup from shutdown is detected on PB0 pin. It is cleared by a PORESETn or by writing 0 in this bit field. +- 0: Shutdown wakeup from PB0 not occurred +- 1: Shutdown wakeup from PB0 occurred + 0 + 1 + read-write + + + + + BOF_TUNE + BOF_TUNE + BOF_TUNE register + 0x58 + 0x20 + read-write + 0x4 + + + BOF_TUNE + BOF_TUNE: selection of the Bypass on the Fly LDO output voltage. +- 0: 1.2V +- 1: 1.2V +- 2: 1.2V +- 3: 1.3V +- 4: 1.4V (Default) +- 5: 1.5V +- 6: 1.6V +- 7: 1.7V +- 8: 1.8V +- 9: 1.9V +- 10: 2V +- 11: 2.1V +- 12: 2.2V +- 13: 2.3V +- 14: 2.4V +- 15: 2.4V + 0 + 4 + read-write + + + + + DBGR + DBGR + DBGR register + 0x84 + 0x20 + read-write + 0x0 + + + DEEPSTOP2 + DEEPSTOP2 low power saving mode emulation enable +this bit enable an emulated debug DEEPSTOP low power mode. +If emulation is enabled, entering in DEEPSTOP mode, the v12i power domain still enters power saving mode, but its clock and power are maintained. + 0 + 1 + read-write + + + SMPSFRDY + SMPSFB Force ready check +When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. +- 0 : no effect (by default) +- 1 : SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1) + 7 + 1 + read-write + + + KELVIN_TEST + KELVIN_TEST[2:0]: Enable TEST mode Kelvin for LDO_RF (Write protected by IFR3 key) +- 000: 0mA (open) (default 0x0) +- 001 for 1mA +- 010 for 3mA +- 011 for 5mA +- 100 for 8mA +- 101 for 10mA +else: 0mA (open) for other combinations. + 8 + 3 + read-write + + + DIS_PRECH + DIS_PRECH[2:0]: disable precharge during deepstop (debug) +allowed combination are: +- 111: precharge and SMPS monitoring are disabled (whatever CR5.SMPSLPOPEN) +- 101: precharge are activated only at deepstop exit (to be used only with CR5.SMPSLPOPEN=1) +else: No effect (default 0x0) + 13 + 3 + read-write + + + + + EXTSRR + EXTSRR + EXTSRR register + 0x88 + 0x20 + read-write + 0x0 + + + DEEPSTOPF + DEEPSTOPF System DeepStop Flag +This bit is set by hardware and cleared only by a POR reset or by writing '1' in this bit field +- 0: System has not been in DEEPSTOP mode +- 1: System has been in DEEPSTOP mode + 9 + 1 + read-write + + + RFPHASEF + RFPHASEF RFPHASE Flag +This bit is set by hardware after a S3LP wake-up event (S3LP activation); it +is cleared either by software, writing '1' in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP. +- 0: RF IP does not require attention +- 1: RF IP awake and requesting system attention + 10 + 1 + read-write + + + + + DBGSMPS + DBGSMPS + DBGSMPS register + 0x8c + 0x20 + read-write + 0x8000 + + + TESTDIG + TESTDIG: SMPS TEST_DIG_3V3[3:0] SMPS control signal + 0 + 4 + read-write + + + TESTKEL + TESTKEL: SMPS TEST_KEL_3V3[1:0] SMPS control signal + 4 + 2 + read-write + + + HOT_STUP + HOT_STUP_3V3 SMPS control signal + 6 + 1 + read-write + + + NO_STUP + NO_STUP_3V3 SMPS control signal + 7 + 1 + read-write + + + TESTILIM + TESTILIM: SMPS TEST_ILIM_3V3 SMPS control signal + 8 + 1 + read-write + + + CTLRES_RAMP + CTLRES_RAM_3V3 SMPS control signal + 9 + 1 + read-write + + + DIS_BIG_MOS + DIS_BIG_MOS_3V3 SMPS control signal + 10 + 1 + read-write + + + TEST_OL + TEST_OL_3V3 SMPS control signal + 11 + 1 + read-write + + + DIS_ILIM + DIS_ILIM_3V3 SMPS control signal + 12 + 1 + read-write + + + ILIM_BOOST + ILIM_BOOST_3V3 SMPS current limitation Boost +- 0: Max current = 110mA (Default) +- 1: Max current = 130mA + 13 + 1 + read-write + + + BOF_CUR_SEL + BOF_CUR_SEL Bypass On the Fly current limitation +- 00 : 20mA +- 01 : 40mA +- 10 : 60mA (default) +- 11 : no limit + 14 + 2 + read-write + + + + + TRIMR + TRIMR + TRIMR register + 0x90 + 0x20 + read-only + 0x2304 + + + RFD_REG_TRIM + RFD_REG_TRIM[2:0]: RF LDO Trimming +By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. +if associated ENGTRIM is enabled the RF LDO trimming can be controlled by the dedicated ENGTRIM register. Default= '100'. + 0 + 3 + read-only + + + SPARE + 3 + 1 + read-only + + + TRIM_MR + TRIM_MR[3:0]: Main Regulator Voltage Trimming +By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. +if associated ENGTRIM.TRIMMREN is enabled the Main Regulator Voltage can be controlled by the dedicated ENGTRIM.TRIM_MR register. Default= '0000'. + 4 + 4 + read-only + + + SMPS_TRIM + SMPS_TRIM[2:0]: SMPS Output Voltage Trimming +By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. +if associated ENGTRIM is enabled the SMPS output voltage can be controlled by the dedicated ENGTRIM register. Default= '011'. + 8 + 3 + read-only + + + BOF_TRIM + BOF_TRIM[2:0]: Bypass On the Fly Output Voltage Trimming +By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. +if associated ENGTRIM is enabled the SMPS output voltage can be controlled by the dedicated ENGTRIM register. Default= '100'. + 11 + 3 + read-only + + + + + ENGTRIM + ENGTRIM + ENGTRIM register + 0x94 + 0x20 + read-write + 0x0 + + + TRIMRFDREGEN + TRIMRFDREGEN: trimming RFREG enabled +- 1: trimming bit applied from ENGTRIM register +- 0: trimming bit applied from OBL (can be read on TRIMR register) + 0 + 1 + read-write + + + TRIM_RFDREG + TRIM_RFDREG: RF Regulator Trimming +By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.TRIMRFDREGEN=1, the startup current can be controlled by this register. + 1 + 3 + read-write + + + SPARE + 4 + 1 + read-write + + + TRIMMREN + TRIMMREN: trimming MR enabled +- 1: trimming bit applied from ENGTRIM register +- 0: trimming bit applied from OBL (can be read on TRIMR register) + 5 + 1 + read-write + + + TRIM_MR + TRIM_MR: Main Regulator Output Voltage Trimming +By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.TRIMMREN=1, the startup current can be controlled by this register. + 6 + 4 + read-write + + + SMPSTRIMEN + SMPSTRIMEN: trimming SMPS enabled +- 1: trimming bit applied from ENGTRIM register +- 0: trimming bit applied from OBL (can be read on TRIMR register) + 10 + 1 + read-write + + + SMPS_TRIM + SMPS_TRIM: SMPS Output Voltage Trimming +By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.SMPSTRIMEN=1, the SMPS output voltage can be controlled by this register. + 11 + 3 + read-write + + + + + DBG_STATUS_REG1 + DBG_STATUS_REG1 + DBG_STATUS_REG1 register + 0x98 + 0x20 + read-only + 0x202 + + + SMPS_FSM_STATE + SMPS_FSM_STATE[2:0]: Indicates the current state of the SMPS FSM inside the PWRC.: +- 000: STARTUP +- 001: SMPS_REQ +- 010: SMPS_RUN +- 011: STOP +- 100: NOSMPS +- 101: PRECHARGE +- 110: NOSMPS_BOF + 0 + 3 + read-only + + + FLASH_FSM_STATE + FLASH_FSM_STATE[2:0]: Indicates the current state of the FLASH FSM inside the PWRC: +- 000: STATE1: FLASH POR +- 001: STATE2: FLASH PWRUP +- 010: STATE3: FLASH READY +- 101: STATE4: FLASH SWITCH OFF +- 110: STATE5: FLASH PWR DOWN + 8 + 3 + read-only + + + + + DBG_STATUS_REG2 + DBG_STATUS_REG2 + DBG_STATUS_REG2 register + 0x9c + 0x20 + read-only + 0x201 + + + PMU_FSM_STATE + PMU_FSM_STATE[3:0]: Indicates the current state of the PMU FSM inside the PWRC. +- 0000: POR +- 0001: RUN +- 0010: DS ENTRY +- 0011: WAIT1 +- 0100: WAIT2 +- 0101: WAIT +- 0110: WAIT3 +- 0111: WAIT4 +- 1000: ISOLATION +- 1001: DEEPSTOP +- 1010: SHUTDOWN +- 1011: DEEPSTOP EXIT + 0 + 4 + read-only + + + RAM_FSM_STATE + RAM_FSM_STATE[1:0]: Indicates the current state of the RAM FSM inside the PWRC: +- 00: POR +- 01: POWER UP +- 10: READY +- 11: OFF + 8 + 2 + read-only + + + + + ENGTRIM2 + ENGTRIM2 + ENGTRIM2 register + 0xa0 + 0x20 + read-write + 0x0 + + + BOFTRIMEN + BOFTRIMEN: trimming BOF enabled +- 1: trimming bit applied from ENGTRIM2 register +- 0: trimming bit applied from OBL (can be read on TRIMR register) + 0 + 1 + read-write + + + BOF_TRIM + SMPS_TRIM: SMPS Output Voltage Trimming +By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.BOFTRIMEN=1, the SMPS output voltage can be controlled by this register. + 1 + 3 + read-write + + + + + + + RCC + RCC + 0x48400000 + + 0x0 + 0xB0 + registers + + + RCC + Reset and Clock Controller + 1 + + + + CR + CR + CR register + 0x0 + 0x20 + read-write + 0x00001400 + + + LSION + Internal Low Speed oscillator enable +Set and reset by software. +Reset source only for this field: PORESETn +0: LSI RC oscillator OFF +1: LSI RC oscillator ON + 2 + 1 + read-write + + + LSIRDY + Internal Low Speed oscillator Ready +Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. +Reset source only for this field: PORESETn +0: LSI RC oscillator not ready +1: LSI RC oscillator ready + 3 + 1 + read-only + + + LSEON + External Low Speed Clock enable. +Set and reset by software. +Reset source only for this field: PORESETn +0: LSE oscillator OFF +1: LSE oscillator ON +Note that enablng this bit, the configuration of PB12 and PB13 will be bypassed (whatever DFTMUX or AF selection) + 4 + 1 + read-write + + + LSERDY + External Low Speed Clock ready flag. +Set by hardware to indicate that LSE oscillator is stable. +0: LSE oscillator not ready +1: LSE oscillator ready + 5 + 1 + read-only + + + LSEBYP + External Low Speed Clock bypass. +Set and reset by software. +Reset source only for this field: PORESETn +0: LSE oscillator bypass OFF +1: LSE oscillator bypass ON +Note that enablng this bit, the configuration of PB13 will be bypassed (whatever DFTMUX or AF selection) + 6 + 1 + read-write + + + LOCKDET_NSTOP + Lock detector Nstop value +When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0. + 7 + 3 + read-write + + + HSIRDY + Internal High Speed clock ready flag. +Set by hardware to indicate that internal RC 64MHz oscillator is stable. +This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request). +0: internal RC 64 MHz oscillator not ready +1: internal RC 64 MHz oscillator ready + 10 + 1 + read-only + + + HSEPLLBUFON + External High Speed Clock Buffer for PLL RF enable. +Set and reset by software. +0: HSE PLL Buffer OFF +1: HSE PLL Buffer ON (default) + 12 + 1 + read-write + + + HSIPLLON + Internal High Speed Clock PLL enable +0: PLL is OFF +1: PLL is ON + 13 + 1 + read-write + + + HSIPLLRDY + Internal High Speed Clock PLL ready flag. +0: PLL is unlocked +1: PLL is locked + 14 + 1 + read-only + + + FMRAT + Force MRSUBG accurate clock ready status (for debug purpose) +0: no effect +1: active_transmission is force to '1' whatever the HSIPLLRDY/HSE status + 15 + 1 + read-write + + + HSEON + External High Speed Clock enable. +Set and reset by software. +in low power mode, HSE is turned off. +HSE is turned ON only when RFSUBG LDO is Ready +0: HSE oscillator OFF +1: HSE oscillator ON + 16 + 1 + read-write + + + HSERDY + External High Speed Clock ready flag. +Set by hardware to indicate that HSE oscillator is stable. +0: HSE oscillator not ready +1: HSE oscillator ready + 17 + 1 + read-only + + + + + ICSCR + ICSCR + ICSCR register + 0x4 + 0x20 + read-write + 0x3f000000 + + + LSITRIMEN + Low Speed oscillator trimming enable +Set and reset by software. +Reset source only for this field: PORESETn +0: LSI oscillator Bias trimming disabled +1: LSI oscillator Bias trimming enabled + 0 + 1 + read-write + + + LSITRIMOK + LSITRIMOK: Low Speed oscillator trimming OK +Set and reset by hardware to indicate when the Low Speed Internal RC oscillator has reached an optimal trimming of its bias current; this bit is only valid when LSITRIMEN is active. +0: LSI Bias trimming (LSIBW) is not good +1: LSI Bias trimming (LSIBW) value is OK + 1 + 1 + read-only + + + LSIBW + Trimming in test mode +The value stored is the correspondent Engi Byte and represents the actual value driving the input of the hardware macro. +This value is loaded soon after the completion of the Option Byte Loading procedure. +This field is directly writeable only in Test Mode. + 2 + 4 + read-only + + + HSITRIMOFFSET + ICSCR[18:16] = HSITRIMOFFSET[2:0]: High Speed oscillator signed trimming offset + 000: 0 (+ 0 MHz / default) + 001: 1 (-0.5 MHz) + 010: 2 (-1MHz) + 011: 3 (-1.5 MHz) + 100: -1 (+2 MHz) + 101: -2 (+1.5MHz) + 110: -3 (+1 MHz) + 111: -4 (+0.5 MHz) + 16 + 3 + read-write + + + HSITRIM + High Speed Internal clock trimming. +This value is loaded soon after the completion of the Option Byte Loading procedure. +When max value 0x3f is set, HSI is less than 64MHz + 24 + 6 + read-only + + + + + CFGR + CFGR + CFGR register + 0x8 + 0x20 + read-write + 0x00000240 + + + HSESEL + Clock source selection request: +0: HSI clock source is requested (default) +1: HSE clock source is requested + 1 + 1 + read-write + + + STOPHSI + Stop HSI clock source request +0: HSI is enabled (default) +1: disable HSI is requested + 2 + 1 + read-write + + + HSESEL_STATUS + Clock source selection Status +0: HSI clock source is selected +1: HSE clock source is selected +Mirror the actual system clock source, depending on clock switching mechanism and limitations + 3 + 1 + read-only + + + CLKSYSDIV + system clock frequency selection request +000: div1 (HSI 64M / HSE 48M) +001: div2 (HSI 32M / HSE 24M) +010: div4/div3 (HSI/HSE) (16M) +011: div8/div6 (HSI/HSE) (8M) * +100: div16/div12 (HSI/HSE) (4M) * +101: div32/div24 (HSI/HSE) (2M) * +110: div64/div48 (HSI/HSE) (1M) * +Note: behavior depends on depending on CFGR.HSESEL and (*) APB2ENR.MRSUBGEN or LPAWUREN register + 5 + 3 + read-write + + + CLKSYSDIV_STATUS + system clock frequency selection status +000: div1 (HSI 64M / HSE 48M) +001: div2 (HSI 32M / HSE 24M) +010: div4/div3 (HSI/HSE) (16M) +011: div8/div6 (HSI/HSE) (8M) +100: div16/div12 (HSI/HSE) (4M) +101: div32/div24 (HSI/HSE) (2M) +110: div64/div48 (HSI/HSE) (1M) +Note: behavior depends on depending on CFGR.HSESEL and APB2ENR.MRSUBGEN register + 8 + 3 + read-only + + + SMPSDIV + SMPS clock prescaling factor to generate 4MHz or 8MHz +0: SMPS clock 8MHz (default ) +1: SMPS clock 4MHz + 12 + 1 + read-write + + + LPUCLKSEL + LPUCLKSEL: Selection of LPUART clock +0: 16 MHz peripheral clock (default) +1: LSE clock (Mandatory in LPUART deepstop mode) + 13 + 1 + read-write + + + CLKSLOWSEL + slow clock source selection +Set by software to select the clock source. This is no glitch free mechanism +Reset source only for this field: PORESETn +00: '0' (default) +01: LSE oscillator clock used as slow clock +10: LSI oscillator clock used as slow clock +11:HSI_64M divided by 2048 used as slow clock + 15 + 2 + read-write + + + IOBOOSTEN + IOBOOSTEN: IO BOOSTER enable +0: IO BOOSTER block is disabled +1: IO BOOSTER block is enabled. + 17 + 1 + read-write + + + LCOEN + LCOEN: LCO enable on PA10 also in deepstop. +0: LCO output on PA10 is disabled +1: LCO output on PA10 is enabled. + 19 + 1 + read-write + + + SPI3I2SCLKSEL + SPI3I2SCLKSEL: Selection of I2S clock for SPI3 IP. +00: 32 MHz peripheral clock (default) +01: 16 MHz peripheral clock +10: CLK_SYS +11: CLK_SYS +Note: the I2S clock frequency must be higher or equal to the system clock (configured +through RCC_CFGR.CLKSYSDIV[2:0] bit field). + 22 + 2 + read-write + + + LCOSEL + Low speed Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. +Reset source only for this field: PORESETn +00: LCO output disabled, no clock on LCO +01: not used +10: internal 32 KHz (LSI) oscillator clock selected +11: external 32 KHz (LSE) oscillator clock selected + 24 + 2 + read-write + + + MCOSEL + Main Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. +000: MCO output disabled, no clock on MCO +001: system clock selected +010: na +011: internal RC 64 MHz (HSI) oscillator clock selected +100: external oscillator (HSE) clock selected +101: internal RC 64 MHz (HSI) oscillator divided by 2048 and used as slow clock selected +110: SMPS clock selected +111: AUX ADC ANA clock selected + 26 + 3 + read-write + + + CCOPRE + Configurable Clock Output Prescaler. +Set and reset by software. +Glitches propagation if CCOPRE is modified after CCO output is enabled. +000: CCO clock is divided by 1 +001: CCO clock is divided by 2 +010: CCO clock is divided by 4 +011: CCO clock is divided by 8 +100: CCO clock is divided by 16 +101: CCO clock is divided by 32 +Others: not used + 29 + 3 + read-write + + + + + CSSWCR + CSSWCR + CSSWCR register + 0xc + 0x20 + read-write + 0x00000000 + + + LSISWTRIMEN + Low Speed oscillator trimming by SW enable +Set and reset by software. +Reset source only for this field: PORESETn +0: LSI oscillator Bias trimming by SW disabled +1: LSI oscillator Bias trimming by SW enabled + 0 + 1 + read-write + + + LSISWBW + Low Speed Internal clock trimming value to set by SW +Reset source only for this field: PORESETn + 1 + 4 + read-write + + + LSEDRV + Maximum Crystal gm for Low Speed External XO +(to connect to XTDRV of 32kHz LSE XO => into IO V33?) to amplify drinving capacity modulation +Set by software. +Reset source only for this field: PORESETn +00: 0.0, low drive capability +01: 0.1, medium low drive capability +10: 1.0, medium high drive capability +11: 1.1, highdrive capability + 5 + 2 + read-write + + + HSISWTRIMEN + High Speed oscillator trimming by SW enable +Set and reset by software. +0: HSI oscillator Bias trimming by SW disabled +1: HSI oscillator Bias trimming by SW enabled + 23 + 1 + read-write + + + HSITRIMSW + High Speed Internal clock trimming value to set by SW. + 24 + 6 + read-write + + + + + KRMR + KRMR + KRMR register + 0x10 + 0x20 + read-write + 0x000000000 + + + KRM_EN + KRM_EN: Variable rate multiplier Enable +Reset source only for this field: PORESETn +0: KRM is disabled (default) +1: KRM is enabled. + 0 + 1 + read-write + + + KRM + KRM[4:0] :SMPS clock dividing Ratio (CLK_SPMS_KRM frequency= CLK_ROOT frequency +(depending on RCC_CFGR.HSESEL) divided by KRM when KRMEN=1) +Reset source only for this field: PORESETn +- 0x00 to 0x08: SMPS clock frequency equals CLK_ROOT/8 (8.00 MHz / 6.00 MHz) +- 0x09: SMPS clock frequency equals CLK_ROOT/9 (7.11 MHz / 5.33 MHz) +- 0x0A: SMPS clock frequency equals CLK_ROOT/10 (6.40 MHz / 4.80 MHz) +- 0x0B: SMPS clock frequency equals CLK_ROOT/11 (5.82 MHz / 4.36 MHz) +- 0x0C: SMPS clock frequency equals CLK_ROOT/12 (5.33 MHz / 4.00 MHz) +- 0x0D: SMPS clock frequency equals CLK_ROOT/13 (4.92 MHz / 3.69 MHz) +- 0x0E: SMPS clock frequency equals CLK_ROOT/14 (4.57 MHz / 3.43 MHz) +- 0x0F: SMPS clock frequency equals CLK_ROOT/15 (4.27 MHz / 3.20 MHz) +- 0x10: SMPS clock frequency equals CLK_ROOT/16 (4.00 MHz / 3.00 MHz) +- 0x1x: Reserved +Note: SMPS clock frequency must be selected in a range [4-8] MHz (depending on +RCC_KRMR.KRM and RCC_CFGR.HSESEL). + 1 + 5 + read-write + + + + + CIER + CIER + CIER register + 0x18 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization. +0: LSI ready interrupt disabled +1: LSI ready interrupt enabled + 0 + 1 + read-write + + + LSERDYIE + LSE Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. +0: LSE ready interrupt disabled +1: LSE ready interrupt enabled + 1 + 1 + read-write + + + HSIRDYIE + HSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization. +0: HSI ready interrupt disabled +1: HSI ready interrupt enabled + 3 + 1 + read-write + + + HSERDYIE + HSE Ready Interrupt Enable +Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization. +0: HSE ready interrupt disabled +1: HSE ready interrupt enabled + 4 + 1 + read-write + + + HSIPLLRDYIE + HSI PLL Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE. +0: HSI PLL ready interrupt disabled +1: HSI PLL ready interrupt enabled + 5 + 1 + read-write + + + HSIPLLUNLOCKDETIE + HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock. +0: HSI PLL unlock detection interrupt disabled +1: HSI PLL unlock detection interrupt enabled + 6 + 1 + read-write + + + RTCRSTIE + RTCRSTIE: RTC reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the RTC reset end. +0: HSI PLL unlock detection interrupt disabled +1: HSI PLL unlock detection interrupt enabled + 7 + 1 + read-write + + + WDGRSTIE + WDGRSTIE: Watchdog reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the watchdog reset end. +0: interrupt disabled +1: interrupt enabled + 8 + 1 + read-write + + + LPURSTIE + LPURSTIE: LPUART reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the LPUART reset end. +0: interrupt disabled +1: interrupt enabled + 9 + 1 + read-write + + + LCDRSTIE + LCDRSTIE: LCD reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the LCD reset end. +0: interrupt disabled +1: interrupt enabled + 10 + 1 + read-write + + + LCSCRSTIE + LCSCRSTIE: LCSC reset release interrupt enable. +0: LCSC reset release interrupt is disabled. +1: LCSC reset release interrupt is enabled. + 13 + 1 + read-write + + + + + CIFR + CIFR + CIFR register + 0x1c + 0x20 + read-write + 0x00000008 + + + LSIRDYIF + LSI Ready Interrupt flag +Set by hardware when LSI clock becomes stable. +0: No clock ready interrupt caused by the internal RC 32 KHz oscillator +1: Clock ready interrupt caused by the internal RC 32 kHz oscillator + 0 + 1 + read-write + + + LSERDYIF + LSE Ready Interrupt Flag. +Set by hardware when LSE clock becomes stable. +0: No clock ready interrupt caused by the LSE oscillator +1: Clock ready interrupt caused by the LSE oscillator + 1 + 1 + read-write + + + HSIRDYIF + HSI Ready Interrupt Flag. +Set by hardware when HSI becomes stable. +0: No clock ready interrupt caused by the HSI oscillator +1: Clock ready interrupt caused by the HSI oscillator + 3 + 1 + read-write + + + HSERDYIF + HSE Ready Interrupt Flag. +Set by hardware when HSE becomes stable. +0: No clock ready interrupt caused by the HSE oscillator +1: Clock ready interrupt caused by the HSE oscillator + 4 + 1 + read-write + + + HSIPLLRDYIF + HSI PLL Ready Interrupt Flag. +Set by hardware when HSI PLL 64MHz becomes stable. +0: No clock ready interrupt caused by the HSI PLL64 MHz oscillator +1: Clock ready interrupt caused by the HSI PLL64 MHz oscillator + 5 + 1 + read-write + + + HSIPLLUNLOCKDETIF + HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag. + 6 + 1 + read-write + + + RTCRSTIF + RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 7 + 1 + read-write + + + WDGRSTIF + WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 8 + 1 + read-write + + + LPURSTIF + LPUART reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 9 + 1 + read-write + + + LCDRSTIF + LCD reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 10 + 1 + read-write + + + LCSCRSTIF + LCSC reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 13 + 1 + read-write + + + + + CSCMDR + CSCMDR + CSCMDR register + 0x20 + 0x20 + read-write + 0x00000080 + + + REQUEST + Request for system clock switching +Cleared by hardware when system clock frequency switch is done +0: To cancel an ongiong request - still possible until IRQ assertion +1: To update the system clock frequency + 0 + 1 + read-write + + + CLKSYSDIV_REQ + system clock frequency selection request +000: div1 (HSI 64M / HSE) (48M) +001: div2 (HSI 32M / HSE (24M*) +010: div4/div3 (HSI/HSE) (16M) +011: div8/div6 (HSI/HSE) (8M) * +100: div16/div12 (HSI/HSE) (4M) * +101: div32/div24 (HSI/HSE) (2M) * +110: div64/div48 (HSI/HSE) (1M) * +Note: behavior depends on depending on CFGR.HSESEL and (*) APB2ENR.MRSUBGEN or LPAWUREN + 1 + 3 + read-write + + + STATUS + Status of clock switch sequence +00: IDLE no switch requested +01: ONGOING clock frequency switch is ongoing +10: DONE clock frequency switch done +11: Reserved + 4 + 2 + read-only + + + EOFSEQ_IE + End of sequence Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the clock system switch. +0: End of sequence interrupt disabled +1: End of sequence interrupt enabled + 6 + 1 + read-write + + + EOFSEQ_IRQ + End of Sequence flag +Set by hardware when clock system swtich is ended +0: No end of sequence event occured +1: End of sequece event occured + 7 + 1 + read-write + + + + + AHBRSTR + AHBRSTR + AHBRSTR register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMARST + DMA and DMAMUX reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 0 + 1 + read-write + + + GPIOARST + GPIOA reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 2 + 1 + read-write + + + GPIOBRST + GPIOB reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 3 + 1 + read-write + + + CRCRST + CRC reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 12 + 1 + read-write + + + RNGRST + RNG reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 18 + 1 + read-write + + + AESRST + AES reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 20 + 1 + read-write + + + + + APB0RSTR + APB0RSTR + APB0RSTR register + 0x34 + 0x20 + read-write + 0x00000000 + + + TIM2RST + TIM2RST: TIM2 reset. +0: TIM2 IP is not under reset. +1: TIM2 IP is under reset. + 0 + 1 + read-write + + + TIM16RST + TIM16RST: TIM16 reset. +0: TIM16 IP is not under reset. +1: TIM16 IP is under reset. + 1 + 1 + read-write + + + SYSCFGRST + SYSCFGRST: system controller reset. +0: system controller IP is not under reset. +1: system controller IP is under reset. + 8 + 1 + read-write + + + LCDCRST + LCDCRST: LCD controller reset. +0: LCD controller IP is not under reset. +1: LCD controller IP is under reset. + 9 + 1 + read-write + + + COMPRST + COMPRST: COMP reset. +0: COMP IP is not under reset. +1: COMP IP is under reset. + 10 + 1 + read-write + + + DACRST + DACRST: DAC reset. +0: DAC IP is not under reset. +1: DAC IP is under reset. + 11 + 1 + read-write + + + RTCRST + RTCRST: RTC reset. +0: RTC IP is not under reset. +1: RTC IP is under reset. + 12 + 1 + read-write + + + LCSCRST + LCSCRST: LCSC reset. +0: LCSC IP is not under reset. +1: LCSC IP is under reset. + 13 + 1 + read-write + + + WDGRST + WDGRST: Watchdog reset. +0: Watchdog IP is not under reset. +1: Watchdog IP is under reset. + 14 + 1 + read-write + + + DBGMCURST + DBGMCURST: DBGMCU reset. +0: DBGMCU IP is not under reset. +1: DBGMCU IP is under reset. + 15 + 1 + read-write + + + + + APB1RSTR + APB1RSTR + APB1RSTR register + 0x38 + 0x20 + read-write + 0x00000000 + + + SPI1RST + SPI1 reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 0 + 1 + read-write + + + ADCRST + ADC reset for Aux-ADC IP +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 4 + 1 + read-write + + + LPUARTRST + LPUART reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 8 + 1 + read-write + + + USARTRST + USART reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 10 + 1 + read-write + + + SPI3RST + SPI3 reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 14 + 1 + read-write + + + I2C1RST + I2C1 reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 21 + 1 + read-write + + + I2C2RST + I2C2 reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 23 + 1 + read-write + + + + + APB2RSTR + APB2RSTR + APB2RSTR register + 0x40 + 0x20 + read-write + 0x00000000 + + + MRSUBGRST + Radio MRSUBG reset. +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 0 + 1 + read-write + + + LPAWURRST + Bubble reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 3 + 1 + read-write + + + + + AHBENR + AHBENR + AHBENR register + 0x50 + 0x20 + read-write + 0x0000000C + + + DMAEN + DMA and DMAMUX enable +Set and enable by software. +0: does not enable +1: enable + 0 + 1 + read-write + + + GPIOAEN + GPIOA enable. It must be enabled by default + 2 + 1 + read-write + + + GPIOBEN + GPIOB enable. It must be enabled by default + 3 + 1 + read-write + + + CRCEN + CRC enable +Set and enable by software. +0: does not enable +1: enable + 12 + 1 + read-write + + + RNGEN + RNG clock enable +Set and enable by software. +0: does not enable +1: enable + 18 + 1 + read-write + + + AESEN + AESEN: AES clock enable. +0: AES IP is clock gated. +1: AES IP is clocked. + 20 + 1 + read-write + + + + + APB0ENR + APB0ENR + APB0ENR register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM2: Advanced Timer clock enable +Set and enable by software. +0: clock disable +1: clock enable + 0 + 1 + read-write + + + TIM16EN + TIM16: Advanced Timer clock enable +Set and enable by software. +0: clock disable +1: clock enable + 1 + 1 + read-write + + + SYSCFGEN + SYSTEM CONFIG clock enable +Set and enable by software. +0: clock disable +1: clock enable + 8 + 1 + read-write + + + LCDEN + LCD clock enable +Set and enable by software. +0: clock disable +1: clock enable + 9 + 1 + read-write + + + COMPEN + COMP clock enable +Set and enable by software. +0: clock disable +1: clock enable + 10 + 1 + read-write + + + DACEN + DAC clock enable +Set and enable by software. +0: clock disable +1: clock enable + 11 + 1 + read-write + + + RTCEN + RTC clock enable +Set and enable by software. +Reset source only for this field: PORESETn +0: clock disable +1: clock enable + 12 + 1 + read-write + + + LCSCEN + LCSC clock enable. +Set and enable by software. +0: clock disable +1: clock enable + 13 + 1 + read-write + + + WDGEN + Watchdog clock enable. +Set and enable by software. +0: clock disable +1: clock enable + 14 + 1 + read-write + + + DBGMCUEN + DBG MCU clock enable. +Set and enable by software. +0: clock disable +1: clock enable + 15 + 1 + read-write + + + + + APB1ENR + APB1ENR + APB1ENR register + 0x58 + 0x20 + read-write + 0x00000000 + + + SPI1EN + SPI1 clock enable +Set and enable by software. +0: clock disable +1: clock enable + 0 + 1 + read-write + + + ADCDIGEN + AUXADC clock enable for Aux-ADC digital clock +Set and enable by software. +0: clock disable +1: clock enable + 4 + 1 + read-write + + + ADCANAEN + ADC clock enable for Aux-ADC analog clock +Set and enable by software. +0: clock disable +1: clock enable + 5 + 1 + read-write + + + LPUARTEN + LPUART clock enable +Set and enable by software. +0: clock disable +1: clock enable + 8 + 1 + read-write + + + USARTEN + USART clock enable +Set and enable by software. +0: clock disable +1: clock enable + 10 + 1 + read-write + + + SPI3EN + SPI3 clock enable +Set and enable by software. +0: clock disable +1: clock enable + 14 + 1 + read-write + + + I2C1EN + I2C1 clock enable +Set and enable by software. +0: clock disable +1: clock enable + 21 + 1 + read-write + + + I2C2EN + I2C2 clock enable +Set and enable by software. +0: clock disable +1: clock enable + 23 + 1 + read-write + + + + + APB2ENR + APB2ENR + APB2ENR register + 0x60 + 0x20 + read-write + 0x00000000 + + + MRSUBGEN + MRSUBG clock enable. +Note: when this bit is '1', it must prevent clk_sys different from 16, 32, 64. If the configured clock is lower than 16MHz (1, 2, 4 or 8 MHz) or equal to 24MHz, clk_sys must be 16MHz +0: clock disable +1: clock enable + 0 + 1 + read-write + + + LPAWUREN + Bubble clock enable +Set and enable by software. +0: clock disable +1: clock enable + 3 + 1 + read-write + + + + + DBGR + DBGR + DBGR register + 0x80 + 0x20 + read-write + 0x00000000 + + + DBGHSIOFF + used for debug or test +0: No effect (default) +1: HSI forced off. + 19 + 1 + read-write + + + DBGBYPHSI + used for debug mode with HSI bypassed by HSE +0: No effect (default) +1: HSI bypassed HSE. + 20 + 1 + read-write + + + DBGXOEXT + used for debug mode with HSE bypassed by FXTAL_IN clock and ZIV12 output used. +0: No effect (default) +1: HSE bypassed by FXTAL_IN clock and ZIV12 output used. + 21 + 1 + read-write + + + FORCEXO48MREADY + FORCEXO48MREADY Force XO48M Ready input signal +This bit is for debug and force the XO48M ready input, in order to bypass XO48M comparators. +0: No effect (default) +1: Force XOREADY=1 + 22 + 1 + read-write + + + + + CSR + CSR + CSR register + 0x94 + 0x20 + read-write + 0x0C000000 + + + RMVF + Remove reset flag +Set by software to clear the value of the reset flags. +It auto clears by HW after clearing reason flags +0: Nothing done +1: Reset the value of the reset flags + 23 + 1 + write-only + + + PADRSTF + SYSTEM reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a reset from pad occurs. +0: No reset from pad occurred +1: Reset from pad occurred + 26 + 1 + read-only + + + PORRSTF + POWER reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a power reset occurs from LPMURESET block. +0: No POWER reset occurred +1: POWER reset occurred + 27 + 1 + read-only + + + SFTRSTF + Software reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a software reset occurs. +0: No software reset occurred +1: Software reset occurred + 28 + 1 + read-only + + + WDGRSTF + Watchdog reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a watchdog reset from V33 domain occurs. +0: No watchdog reset occurred +1: Watchdog reset occurred + 29 + 1 + read-only + + + LOCKUPRSTF + LOCK UP reset flag from CM0 +Reset by software by writing the RMVF bit. +Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals. +0: No lockup reset occurred +1: lockup reset occurred + 30 + 1 + read-only + + + + + RFSWHSECR + RFSWHSECR + RFSWHSECR register + 0x98 + 0x20 + read-write + 0x00000803F + + + GMC + GMC[6:5]: High speed external XO current control reference +00: 10 uA +01: 20 uA +1x: 40 uA +GMC[4:0]: High speed external XO current control multiplying factor +IcoreHSE= GMC[4:0] * GMC[6:5] +Example: GMC[6:0]=0x1111001 -> IcoreHSE=25*40uA / Default 3F: IcoreHSE= 10uA x 31 = 310uA +Note: this value is set only by software. + 0 + 7 + read-write + + + SWXOTUNEEN + RF-HSE capacitor bank tuning by SW enable +Set by software + 7 + 1 + read-write + + + SWXOTUNE + RF-HSE capacitor bank tuning value by SW +Set by software + 8 + 6 + read-write + + + ISTARTUP + RF-HSE Startup current +Set by software +Default value 2 + 14 + 2 + read-write + + + AMPLTHRESH + RF-HSE Amplitude Control threshold +Set by software +Default value 0 + 16 + 3 + read-write + + + + + RFHSECR + RFHSECR + RFHSECR register + 0x9c + 0x20 + read-only + 0x000000000 + + + XOTUNE + RF-HSE capacitor bank tuning +Set by option byte loading soon after Power On Reset. + 0 + 6 + read-only + + + AMPLREADY + RF-HSE Amplitude Control Ready output + 6 + 1 + read-only + + + + + AHBSMENR + AHBSMENR + AHBSMENR register + 0xa0 + 0x20 + read-write + 0x0014160F + + + DMASMEN + DMA clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: DMA clock disabled in Sleep mode +- 1: DMA clock enabled in Sleep mode (if enabled in DMAEN) + 0 + 1 + read-write + + + FLASHSMEN + Flash clocks enable during Flash Sleep PD and CPU Sleep mode bit +This bit is set and reset by software. +- 0: Flash clocks are disabled in Flash Sleep PD* and CPU Sleep mode +- 1: Flash clocks are enabled in Sleep mode +Note: Flash Sleep PD is enabled through nvm_control register CONFIG.SLEEP_PD + 1 + 1 + read-write + + + GPIOASMEN + GPIOA clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: GPIOA clock disabled in Sleep mode +- 1: GPIOA clock enabled in Sleep mode (if enabled by GPIOAEN) + 2 + 1 + read-write + + + GPIOBSMEN + GPIOB clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: GPIOB clock disabled in Sleep mode +- 1: GPIOB clock enabled in Sleep mode (if enabled in GPIOBEN) + 3 + 1 + read-write + + + SRAM0SMEN + SRAM0 clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SRAM0 clock disabled in Sleep mode +- 1: SRAM0 clock enabled in Sleep mode + 9 + 1 + read-write + + + SRAM1SMEN + SRAM1 clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SRAM1 clock disabled in Sleep mode +- 1: SRAM1 clock enabled in Sleep mode + 10 + 1 + read-write + + + CRCSMEN + CRC clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: CRC clock disabled in Sleep mode +- 1: CRC clock enabled in Sleep mode (if enabled in CRCEN) + 12 + 1 + read-write + + + RNGSMEN + RNG bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: RNG bus clock disabled in Sleep mode +- 1: RNG bus clock enabled in Sleep mode (if enabled in RNGEN) + 18 + 1 + read-write + + + AESSMEN + AES bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: AES bus clock disabled in Sleep mode +- 1: AES bus clock enabled in Sleep mode (if enabled in AESEN) + 20 + 1 + read-write + + + + + APB0SMENR + APB0SMENR + APB0SMENR register + 0xa4 + 0x20 + read-write + 0x0000FF03 + + + TIM2SMEN + TIM2 bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: TIM2 bus clock disabled in Sleep mode +- 1: TIM2 bus clock enabled in Sleep mode (if enabled in TIM2EN) + 0 + 1 + read-write + + + TIM16SMEN + TIM16 bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: TIM16 bus clock disabled in Sleep mode +- 1: TIM16 bus clock enabled in Sleep mode (if enabled in TIM16EN) + 1 + 1 + read-write + + + SYSCFGSMEN + SYSCFG bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SYSCFG bus clock disabled in Sleep mode +- 1: SYSCFG bus clock enabled in Sleep mode (if enabled in SYSCFGEN) + 8 + 1 + read-write + + + LCDCSMEN + LCDC bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: LCDC bus clock disabled in Sleep mode +- 1: LCDC bus clock enabled in Sleep mode (if enabled in LCDCEN) + 9 + 1 + read-write + + + COMPSMEN + COMP bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: COMP bus clock disabled in Sleep mode +- 1: COMP bus clock enabled in Sleep mode (if enabled in COMPEN) + 10 + 1 + read-write + + + DACSMEN + DAC bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: DAC bus clock disabled in Sleep mode +- 1: DAC bus clock enabled in Sleep mode (if enabled in DACEN) + 11 + 1 + read-write + + + RTCSMEN + RTC bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: RTC bus clock disabled in Sleep mode +- 1: RTC bus clock enabled in Sleep mode (if enabled in RTCEN) + 12 + 1 + read-write + + + LCSCSMEN + LCSC bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: LCSC bus clock disabled in Sleep mode +- 1: LCSC bus clock enabled in Sleep mode (if enabled in LCSCEN) + 13 + 1 + read-write + + + WDGSMEN + WDG clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: WDG clock disabled in Sleep mode +- 1: WDG clock enabled in Sleep mode (if enabled in WDGEN) + 14 + 1 + read-write + + + DBGMCUSMEN + DBGMCU clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: DBGMCU clock disabled in Sleep mode +- 1: DBGMCU clock enabled in Sleep mode (if enabled in DBGMCUEN) + 15 + 1 + read-write + + + + + APB1SMENR + APB1SMENR + APB1SMENR register + 0xa8 + 0x20 + read-write + 0x00A04511 + + + SPI1SMEN + SPI1 bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SPI1 bus clock disabled in Sleep mode +- 1: SPI1 bus clock enabled in Sleep mode (if enabled in SPI1EN) + 0 + 1 + read-write + + + ADCDIGSMEN + ADCDIG bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: ADCDIG bus clock disabled in Sleep mode +- 1: ADCDIG bus clock enabled in Sleep mode (if enabled by ADCDIGEN) + 4 + 1 + read-write + + + LPUARTSMEN + LPUART bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: LPUART bus clock disabled in Sleep mode +- 1: LPUART bus clock enabled in Sleep mode (if enabled in LPUARTEN) + 8 + 1 + read-write + + + USARTSMEN + USART bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: USART bus clock disabled in Sleep mode +- 1: USART bus clock enabled in Sleep mode (if enabled in USARTEN) + 10 + 1 + read-write + + + SPI3SMEN + SPI3 bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SPI3 bus clock disabled in Sleep mode +- 1: SPI3 bus clock enabled in Sleep mode (if enabled in SPI3EN) + 14 + 1 + read-write + + + I2C1SMEN + I2C1 clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: I2C1 clock disabled in Sleep mode +- 1: I2C1 clock enabled in Sleep mode (if enabled in I2C1EN) + 21 + 1 + read-write + + + I2C2SMEN + I2C2 clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: I2C2 clock disabled in Sleep mode +- 1: I2C2 clock enabled in Sleep mode (if enabled in I2C2EN) + 23 + 1 + read-write + + + + + + + RETAINED + RETAINED + 0x49000780 + + 0x0 + 0x80 + registers + + + + RFIP_WAKEUPTIME + RFIP_WAKEUPTIME + RFIP_WAKEUPTIME register + 0x0 + 0x20 + read-only + 0x00000000 + + + RFIP_WAKEUPTIME + (Absolute) Target time to wakeup the RFIP. + 0 + 32 + read-only + + + + + CPU_WAKEUPTIME + CPU_WAKEUPTIME + CPU_WAKEUPTIME register + 0x4 + 0x20 + read-write + 0x00000000 + + + CPU_WAKEUPTIME + (Absolute) Target time to wakeup the CPU. + 1 + 31 + read-write + + + + + WAKEUP_CTRL + WAKEUP_CTRL + WAKEUP_CTRL register + 0x8 + 0x20 + read-write + 0x00000000 + + + SOC_WAKEUP_OFFSET + Delay to be considered by the Wakeup block to anticipate the wakeup request to the PWRC of the SoC versus the target to wakeup the RFIP (or the CPU). + 0 + 8 + read-write + + + CPU_WAKEUP_EN + Indicates if the wakeup timer has to wakeup the SoC (match on CPU_WAKEUPTIME[31:4] bit field only) + set the CPU_WAKEUP_F in the WAKEUP_IRQ_STATUS Misc register when match on CPU_WAKEUPTIME[31:0] occurs. + 30 + 1 + read-write + + + RFIP_WAKEUP_EN + Indicates if the wakeup timer has to wakeup the SoC (match on RFIP_WAKEUPTIME[31:4] bit field only) + trigger an event on the Sequencer and set the RFIP_WAKEUP_F in the WAKEUP_IRQ_STATUS Misc register when match on RFIP_WAKEUPTIME[31:0] occurs. + 31 + 1 + read-only + + + + + RRM_CMDLIST_PTR + RRM_CMDLIST_PTR + RRM_CMDLIST_PTR register + 0xc + 0x20 + read-write + 0x00000000 + + + CMDLIST_PTR_OFFSET + Contain the offset versus the SoC RAM base address where to find the RRM-UDRA command list entry point. + 0 + 16 + read-write + + + CMDLIST_PTR_VALID + Indicate if a command list has to be executed or not + + 31 + 1 + read-write + + + + + SEQ_GLOBALTABLE_PTR + SEQ_GLOBALTABLE_PTR + SEQ_GLOBALTABLE_PTR register + 0x10 + 0x20 + read-write + 0x00000000 + + + SEQ_GLOBALTABLE_PTR + Contain the offset versus the SoC RAM base address of the GlobalConfiguration RAM table entry point. + 0 + 16 + read-write + + + + + + + RNG + RNG + 0x48600000 + + 0x0 + 0x1000 + registers + + + + RNG_CR + RNG_CR + RNG_CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + RNG_DIS + RNG Disable bit. + 2 + 1 + read-write + + + TST_CLK + RNG Test Clock bit. + 3 + 1 + read-write + + + + + RNG_SR + RNG_SR + RNG_SR register + 0x04 + 0x20 + read-write + 0x00000000 + + + RNGRDY + New Random Value Ready. + 0 + 1 + read-only + + + REVCLK + RNGCLK Clock Reveal bit. + 1 + 1 + read-only + + + FAULT + Fault Reveal bit. + 2 + 1 + read-write + + + + + RNG_VAL + RNG_VAL + RNG_VAL register + 0x08 + 0x20 + read-only + 0x00000000 + + + RANDOM_VALUE + Random Value + 0 + 16 + read-only + + + + + RNG_TCR + RNG_TCR + RNG_TCR register + 0x80 + 0x20 + read-write + 0x00000000 + + + TCR + Test-control register + 0 + 1 + read-write + + + + + RNG_ITIP + RNG_ITIP + RNG_ITIP register + 0x84 + 0x20 + read-write + 0x00000000 + + + ITIP + Integration-test input register + 0 + 1 + read-write + + + + + RNGPeriphID0 + RNGPeriphID0 + RNGPeriphID0 register + 0xFE0 + 0x20 + read-only + 0x000000E1 + + + PartNumber0 + These bits are read back as 0xE1 + 0 + 8 + read-only + + + + + RNGPeriphID1 + RNGPeriphID1 + RNGPeriphID1 register + 0xFE4 + 0x20 + read-only + 0x0000005 + + + PartNumber1 + These bits are read back as 0x05 + 0 + 4 + read-only + + + Designer0 + These bits are read back as 0x00 + 4 + 4 + read-only + + + + + RNGPeriphID2 + RNGPeriphID2 + RNGPeriphID2 register + 0xFE8 + 0x20 + read-only + 0x00000028 + + + Designer1 + These bits are read back as 0x08 + 0 + 4 + read-only + + + Revision + These bits are read back as 0x02 + 4 + 4 + read-only + + + + + RNGPeriphID3 + RNGPeriphID3 + RNGPeriphID3 register + 0xFEC + 0x20 + read-only + 0x00000000 + + + Configuration + These bits are read back as 0x00 + 0 + 8 + read-only + + + + + RNGPCellID0 + RNGPCellID0 + RNGPCellID0 register + 0xFF0 + 0x20 + read-only + 0x0000000D + + + RNGPCellID0 + These bits are read back as 0x0D + 0 + 8 + read-only + + + + + RNGPCellID1 + RNGPCellID1 + RNGPCellID1 register + 0xFF4 + 0x20 + read-only + 0x000000F0 + + + RNGPCellID1 + These bits are read back as 0xF0 + 0 + 8 + read-only + + + + + RNGPCellID2 + RNGPCellID2 + RNGPCellID2 register + 0xFF8 + 0x20 + read-only + 0x00000005 + + + RNGPCellID2 + These bits are read back as 0x05 + 0 + 8 + read-only + + + + + RNGPCellID3 + RNGPCellID3 + RNGPCellID3 register + 0xFFC + 0x20 + read-only + 0x000000B1 + + + RNGPCellID3 + These bits are read back as 0xB1 + 0 + 8 + read-only + + + + + + + RTC + RTC + 0x40004000 + + 0x0 + 0x58 + registers + + + RTC + RTC interrupt + 11 + + + + RTC_TR + RTC_TR + RTC_TR register + 0x00 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation. +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + + + RTC_DR + RTC_DR + RTC_DR register + 0x04 + 0x20 + read-write + 0x00002101 + + + DU + Date units in BCD format. + 0 + 4 + read-write + + + DT + Date tens in BCD format. + 4 + 2 + read-write + + + MU + Month units in BCD format. + 8 + 4 + read-write + + + MT + Month tens in BCD format. + 12 + 1 + read-write + + + WDU + Week day units +000: forbidden +001: Monday +010: Tuesday +011: Wednesday +100: Thursday +101: Friday +110: Saturday +111: Sunday + 13 + 3 + read-write + + + YU + Year units in BCD format. + 16 + 4 + read-write + + + YT + Year tens in BCD format. + 20 + 4 + read-write + + + + + RTC_CR + RTC_CR + RTC_CR register + 0x08 + 0x20 + read-write + 0x00000000 + + + WUCKSEL + Wakeup clock selection +000: RTC/16 clock is selected +001: RTC/8 clock is selected +010: RTC/4 clock is selected +011: RTC/2 clock is selected +10x: ck_spre (usually 1 Hz) clock is selected +11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value + 0 + 3 + read-write + + + TSEDGE + Time-stamp event active edge +0: RTC_TS input rising edge generates a time-stamp event +1: RTC_TS input falling edge generates a time-stamp event +TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. + 3 + 1 + read-write + + + BYPSHAD + Bypass the shadow registers +0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. +1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 5 + 1 + read-write + + + FMT + Hour format + + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + ALRAE + Alarm A enable +0: Alarm A disabled +1: Alarm A enabled + 8 + 1 + read-write + + + WUTE + Wakeup timer enable +0: Wakeup timer disabled +1: Wakeup timer enabled + 10 + 1 + read-write + + + TSE + Timestamp enable +0: Timestamp disable +1: Timestamp enable + 11 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable +0: Alarm A interrupt disabled +1: Alarm A interrupt enabled + 12 + 1 + read-write + + + WUTIE + Wakeup timer interrupt enable +0: Wakeup timer interrupt disabled +1: Wakeup timer interrupt enabled + 14 + 1 + read-write + + + TSIE + Time-stamp interrupt enable + + 15 + 1 + read-write + + + B_0x0 + Time-stamp Interrupt disable + + 0x0 + + + B_0x1 + Time-stamp Interrupt enable + 0x1 + + + + + ADD1H + Add 1 hour (summer time change) +When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. +0: No effect +1: Adds 1 hour to the current time. This can be used for summer time change + 16 + 1 + write-only + + + SUB1H + Subtract 1 hour (winter time change) +When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. +Setting this bit has no effect when current hour is 0. +0: No effect +1: Subtracts 1 hour to the current time. This can be used for winter time change. + 17 + 1 + write-only + + + BKP + Backup +This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection +When COE=1, this bit selects which signal is output on RTC_CALIB. +0: Calibration output is 512 Hz +1: Calibration output is 1 Hz +These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). + 19 + 1 + read-write + + + POL + Output polarity +This bit is used to configure the polarity of RTC_ALARM output +0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0]) +1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0]). + 20 + 1 + read-write + + + OSEL + Output selection +These bits are used to select the flag to be routed to RTC_ALARM output +00: Output disabled +01: Alarm A output enabled +10: Reserved +11: Wakeup output enabled + 21 + 2 + read-write + + + COE + Calibration output enable +This bit enables the RTC_CALIB output +0: Calibration output disabled +1: Calibration output enabled + 23 + 1 + read-write + + + ITSE + Timestamp on internal event enable +0: Internal event timestamp disable +1: Internal event timestamp enable + 24 + 1 + read-write + + + + + RTC_ISR + RTC_ISR + RTC_ISR register + 0x0C + 0x20 + read-write + 0x00000007 + + + ALRAWF + Alarm A write flag +This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. +It is cleared by hardware in initialization mode. +0: Alarm A update not allowed +1: Alarm A update allowed. + 0 + 1 + read-write + + + WUTWF + Wakeup timer write flag +This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. +0: Wakeup timer configuration update not allowed +1: Wakeup timer configuration update allowed. + 2 + 1 + read-write + + + SHPF + Shift operation pending +0: No shift operation is pending +1: A shift operation is pending +This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. + 3 + 1 + read-write + + + INITS + Initialization status flag +This bit is set by hardware when the calendar year field is different from 0 (power-on reset state). +0: Calendar has not been initialized +1: Calendar has been initialized + 4 + 1 + read-write + + + RSF + Registers synchronization flag +This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow regsiter mode (BYPSHAD=1). This bit can also be cleared by software. +It is cleared either by software or by hardware in initialization mode. +0: Calendar shadow registers not yet synchronized +1: Calendar shadow registers synchronized. + 5 + 1 + read-write + + + INITF + Initialization flag +When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. +0: Calendar registers update is not allowed +1: Calendar registers update is allowed. + 6 + 1 + read-write + + + INIT + Initialization mode +0: Free running mode +1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + 7 + 1 + read-write + + + ALRAF + Alarm A flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). +This flag is cleared by software by writing 0. + 8 + 1 + read-write + + + WUTF + Wakeup timer flag +This flag is set by hardware when the wakeup auto-reload counter reaches 0. +This flag is cleared by software by writing 0. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 10 + 1 + read-write + + + TSF + This flag is set by hardware when a time-stamp event occurs. +This flag is cleared by software by writing 0. If ITSF flag is set, TSF must be cleared together with ITSF by writing 0 in both bits. + 11 + 1 + read-write + + + TSOVF + This flag is set by hardware when a time-stamp event occurs while TSF is already set. +This flag is cleared by software by writing 0. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp +event occurs immediately before the TSF bit is cleared. + 12 + 1 + read-write + + + TAMP1F + RTC_TAMP1 detection flag +This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. +It is cleared by software writing 0 + 13 + 1 + read-write + + + RECALPF + Recalibration pending Flag +The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. + 16 + 1 + read-write + + + ITSF + Internal time-stamp flag +This flag is set by hardware when a time-stamp on the internal event occurs. +This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits. + 17 + 1 + read-write + + + + + RTC_PRER + RTC_PRER + RTC_PRER register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_S + Synchronous prescaler factor +This is the synchronous division factor: +ck_spre frequency = ck_apre frequency/(PREDIV_S+1) + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor +This is the asynchronous division factor: +ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + read-write + + + + + RTC_WUTR + RTC_WUTR + RTC_WUTR register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits +When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register +When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. +The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. + 0 + 16 + read-write + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC_ALRMAR register + 0x1C + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask +0: Alarm A set if the seconds match +1: Seconds dont care in Alarm A comparison + 7 + 1 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask +0: Alarm A set if the minutes match +1: Minutes dont care in Alarm A comparison + 15 + 1 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + MSK3 + Alarm A hours mask +0: Alarm A set if the hours match +1: Hours dont care in Alarm A comparison + 23 + 1 + read-write + + + DU + Date units or day in BCD format. + 24 + 4 + read-write + + + DT + Date tens in BCD format. + 28 + 2 + read-write + + + WDSEL + Week day selection +0: DU[3:0] represents the date units +1: DU[3:0] represents the week day. DT[1:0] is dont care. + 30 + 1 + read-write + + + MSK4 + Alarm A date mask +0: Alarm A set if the date/day match +1: Date/day dont care in Alarm A comparison + 31 + 1 + read-write + + + + + RTC_WPR + RTC_WPR + RTC_WPR register + 0x24 + 0x20 + read-write + 0x00000000 + + + KEY + Write protection key +This byte is written by software. +Reading this byte always returns 0x00 + 0 + 8 + write-only + + + + + RTC_SSR + RTC_SSR + RTC_SSR register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value +SS[15:0] is the value in the synchronous prescalers counter. The fraction of a second is given by the formula below: +Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 ) + 0 + 16 + read-only + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC_SHIFTR register + 0x2C + 0x20 + read-write + 0x00000000 + + + SUBFS + Subtract a fraction of a second +These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +The value which is written to SUBFS is added to the synchronous prescalers counter. +Since this counter counts down, this operation effectively subtracts from (delays) the clock by: +Delay (seconds) = SUBFS / ( PREDIV_S + 1 ) +A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by : +Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) . + 0 + 15 + write-only + + + ADD1S + Add one second +0: No effect +1: Add one second to the clock/calendar +This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. + 31 + 1 + write-only + + + + + RTC_TSTR + RTC_TSTR + RTC_TSTR register + 0x30 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + + + RTC_TSDR + RTC_TSDR + RTC_TSDR register + 0x34 + 0x20 + read-write + 0x00000000 + + + DU + Date units in BCD format. + 0 + 4 + read-write + + + DT + Date tens in BCD format. + 4 + 2 + read-write + + + MU + Month units in BCD format. + 8 + 4 + read-write + + + MT + Month tens in BCD format. + 12 + 1 + read-write + + + WDU + Week day units + 13 + 3 + read-write + + + + + RTC_TSSSR + RTC_TSSSR + RTC_TSSSR register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value +SS[15:0] is the value of the synchronous prescalers counter when the timestamp event occurred. + 0 + 16 + read-only + + + + + RTC_CALR + RTC_CALR + RTC_CALR register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALM + Calibration minus +The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. +To increase the frequency of the calendar, this feature should be used in conjunction with CALP. + 0 + 9 + read-write + + + CALW16 + Use a 16-second calibration cycle period +When CALW16 is set to 1 , the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. +Note: CALM[0] is stucked at 0 when CALW16=1. + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period +When CALW8 is set to 1 , the 8-second calibration cycle period is selected. +Note: CALM[1:0] are stucked at '00' when CALW8=1. + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488.5 ppm +0: No RTCCLK pulses are added. +1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency incresed by 488.5 ppm). +This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. + 15 + 1 + read-write + + + + + RTC_TAMPCR + RTC_TAMPCR + RTC_TAMPCR register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP1E + RTC_TAMP1 input detection enable +0: RTC_TAMP1 detection disabled +1: RTC_TAMP1 detection enabled. + 0 + 1 + read-write + + + TAMP1TRG + Active level for RTC_TAMP1 input +If TAMPFLT != 00 +0: RTC_TAMP1 input staying low triggers a tamper detection event. +1: RTC_TAMP1 input staying high triggers a tamper detection event. +if TAMPFLT = 00: +0: RTC_TAMP1 input rising edge triggers a tamper detection event. +1: RTC_TAMP1 input falling edge triggers a tamper detection event. + 1 + 1 + read-write + + + TAMPIE + Tamper interrupt enable +0: Tamper interrupt disabled +1: Tamper interrupt enabled. + 2 + 1 + read-write + + + TAMPTS + Activate timestamp on tamper detection event +0: Tamper detection event does not cause a timestamp to be saved +1: Save timestamp on tamper detection event +TAMPTS is valid even if TSE=0 in the RTC_CR register. + 7 + 1 + read-write + + + TAMPFREQ + Tamper sampling frequency +Determines the frequency at which each of the RTC_TAMPx inputs are sampled. +0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) +0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) +0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) +0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) +0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) +0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) +0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) +0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + 8 + 3 + read-write + + + TAMPFLT + RTC_TAMPx filter count +These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. +TAMPFLT is valid for each of the RTC_TAMPx inputs. +0x0: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input). +0x1: Tamper event is activated after 2 consecutive samples at the active level. +0x2: Tamper event is activated after 4 consecutive samples at the active level. +0x3: Tamper event is activated after 8 consecutive samples at the active level. + 11 + 2 + read-write + + + TAMPPRCH + RTC_TAMPx precharge duration +These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs. +0x0: 1 RTCCLK cycle +0x1: 2 RTCCLK cycles +0x2: 4 RTCCLK cycles +0x3: 8 RTCCLK cycles + 13 + 2 + read-write + + + TAMPPUDIS + RTC_TAMPx pull-up disable +This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample. +0: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) +1: Disable precharge of RTC_TAMPx pins. + 15 + 1 + read-write + + + TAMP1IE + Tamper 1 interrupt enable +0: Tamper 1 interrupt is disabled if TAMPIE = 0. +1: Tamper 1 interrupt enabled. + 16 + 1 + read-write + + + TAMP1NOERASE + Tamper 1 no erase +0: Tamper 1 event erases the backup registers. +1: Tamper 1 event does not erase the backup registers. + 17 + 1 + read-write + + + TAMP1MF + Tamper 1 mask flag +0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. +1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased. + 18 + 1 + read-write + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC_ALRMASSR register + 0x44 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value +This value is compared with the contents of the synchronous prescalers counter to +determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). +1: SS[14:1] are dont care in Alarm A comparison. Only SS[0] is compared. +2: SS[14:2] are dont care in Alarm A comparison. Only SS[1:0] are compared. +3: SS[14:3] are dont care in Alarm A comparison. Only SS[2:0] are compared. +... +12: SS[14:12] are dont care in Alarm A comparison. SS[11:0] are compared. +13: SS[14:13] are dont care in Alarm A comparison. SS[12:0] are compared. +14: SS[14] is dont care in Alarm A comparison. SS[13:0] are compared. +15: All 15 SS bits are compared and must match to activate alarm. +The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. + 24 + 4 + read-write + + + + + RTC_OR + RTC_OR + RTC_OR register + 0x4C + 0x20 + read-write + 0x00000000 + + + ALARMOUTTYPE + RTC_ALARM on PA8 output type + + 0 + 1 + read-write + + + B_0x0 + RTC_ALARM, when mapped on PA8, is open-drain output + + 0x0 + + + B_0x1 + RTC_ALARM, when mapped on PA8, is push-pull output + 0x1 + + + + + RTC_OUT_RMP + RTC_OUT remap +Setting this bit allows to remap the RTC outputs on PA9 as follows: +0 : +If OSEL/= '00' : RTC_ALARM is ouput on PA8 +If OSEL= '00' and COE = 1 : RTC_CALIB is output on PA8 +1 : +If OSEL /= '00' and COE = 0 : RTC_ALARM is output on PA9 +If OSEL = '00' and COE = 1: RTC_CALIB is output on PA9 +If OSEL /= '00' and COE = 1: RTC_CALIB is output on PA9 and RTC_ALARM is output on PA8. +Note: the RTC outputs are functional in DEEPSTOP mode only on PA8. + 1 + 1 + read-write + + + + + RTC_BKP0R + RTC_BKP0R + RTC_BKPxR register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + RTC_BKP1R + RTC_BKP1R + RTC_BKPxR register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + + + SPI3 + SPI3 + 0x41007000 + + 0x0 + 0x24 + registers + + + SPI3 + SPI3 interrupt + 7 + + + + SPI_SSPCR1 + SPI_SSPCR1 + SPI_SSPCR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + CPHA + Clock phase +- 0: The first clock transition is the first data capture edge +- 1: The second clock transition is the first data capture edge + 0 + 1 + read-write + + + CPOL + Clock polarity +- 0: CK to 0 when idle +- 1: CK to 1 when idle + 1 + 1 + read-write + + + MSTR + Master selection +- 0: Slave configuration +- 1: Master configuration + 2 + 1 + read-write + + + BR + Baud rate control +- 000: fPCLK/2 +- 001: fPCLK/4 +- 010: fPCLK/8 +- 011: fPCLK/16 +- 100: fPCLK/32 +- 101: fPCLK/64 +- 110: fPCLK/128 +- 111: fPCLK/256 + 3 + 3 + read-write + + + SPE + SPI enable +- 0: Peripheral disabled +- 1: Peripheral enabled + 6 + 1 + read-write + + + LSBFIRST + Frame format +- 0: data is transmitted / received with the MSB first +- 1: data is transmitted / received with the LSB first + 7 + 1 + read-write + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +- 0: Software slave management disabled +- 1: Software slave management enabled + 9 + 1 + read-write + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +- 0: Full duplex (Transmit and receive) +- 1: Output disabled (Receive-only mode) + 10 + 1 + read-write + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +- 0: 8-bit CRC length +- 1: 16-bit CRC length + 11 + 1 + read-write + + + CRCNEXT + Transmit CRC next +- 0: Next transmit value is from Tx buffer +- 1: Next transmit value is from Tx CRC register + 12 + 1 + read-write + + + CRCEN + Hardware CRC calculation enable +- 0: CRC calculation disabled +- 1: CRC calculation Enabled + 13 + 1 + read-write + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode +- 0: Output disabled (receive-only mode) +- 1: Output enabled (transmit-only mode) + 14 + 1 + read-write + + + BIDIMODE + Bidirectional data mode enable. This bit enables half-duplex communication using +common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is +active. +- 0: 2-line unidirectional data mode selected +- 1: 1-line bidirectional data mode selected + 15 + 1 + read-write + + + + + SPI_SSPCR2 + SPI_SSPCR2 + SPI_SSPCR2 register + 0x04 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. +- 0: Rx buffer DMA disabled +- 1: Rx buffer DMA enabled + 0 + 1 + read-write + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. +- 0: Tx buffer DMA disabled +- 1: Tx buffer DMA enabled + 1 + 1 + read-write + + + SSOE + SS output enable +- 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration +- 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 2 + 1 + read-write + + + NSSP + NSS pulse management +This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1, or FRF = 1. +- 0: No NSS pulse +- 1: NSS pulse generated + 3 + 1 + read-write + + + FRF + Frame format +- 0: SPI Motorola mode +- 1 SPI TI mode + 4 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). +- 0: Error interrupt is masked +- 1: Error interrupt is enabled + 5 + 1 + read-write + + + RXNEIE + RX buffer not empty interrupt enable +- 0: RXNE interrupt masked +- 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 6 + 1 + read-write + + + TXEIE + Tx buffer empty interrupt enable +- 0: TXE interrupt masked +- 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 7 + 1 + read-write + + + DS + Data size +These bits configure the data length for SPI transfers: +- 0000: Not used +- 0001: Not used +- 0010: Not used +- 0011: 4-bit +- 0100: 5-bit +- 0101: 6-bit +- 0110: 7-bit +- 0111: 8-bit +- 1000: 9-bit +- 1001: 10-bit +- 1010: 11-bit +- 1011: 12-bit +- 1100: 13-bit +- 1101: 14-bit +- 1110: 15-bit +- 1111: 16-bit +If software attempts to write one of the 'Not used' values, they are forced to the value '0111'(8-bit). + 8 + 4 + read-write + + + FRXTH + FIFO reception threshold +FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +- 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) +- 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 12 + 1 + read-write + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 13 + 1 + read-write + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 14 + 1 + read-write + + + + + SPI_SSPSR + SPI_SSPSR + SPI_SSPSR register + 0x08 + 0x20 + read-write + 0x00000002 + + + RXNE + Receive buffer not empty +- 0: Rx buffer empty +- 1: Rx buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty +- 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). +- 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer). + 1 + 1 + read-only + + + CHSIDE + Channel side +- 0: Channel Left has to be transmitted or has been received +- 1: Channel Right has to be transmitted or has been received + 2 + 1 + read-only + + + UDR + Underrun flag +- 0: No underrun occurred +- 1: Underrun occurred + 3 + 1 + read-only + + + CRCERR + CRC error flag +- 0: CRC value received matches the SPIx_RXCRCR value +- 1: CRC value received does not match the SPIx_RXCRCR value +This flag is set by hardware and cleared by software writing 0. + 4 + 1 + read-write + + + MODF + Mode fault +- 0: No mode fault occurred +- 1: Mode fault occurred + 5 + 1 + read-only + + + OVR + Overrun flag +- 0: No overrun occurred +- 1: Overrun occurred + 6 + 1 + read-only + + + BSY + Busy flag +- 0: SPI (or I2S) not busy +- 1: SPI (or I2S) is busy in communication or Tx buffer is not empty +This flag is set and cleared by hardware. + 7 + 1 + read-only + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. +- 0: No frame format error +- 1: A frame format error occurred + 8 + 1 + read-only + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full + 9 + 2 + read-only + + + FTLVL + FIFO Transmission Level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 11 + 2 + read-only + + + + + SPI_SSPDR + SPI_SSPDR + SPI_SSPDR register + 0x0C + 0x20 + read-write + 0x00000000 + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO +(See Section 18.5.8: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI_SSPCRCPR + SPI_SSPCRCPR + SPI_SSPCRCPR register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI_SSPRXCRCR + SPI_SSPRXCRCR + SPI_SSPRXCRCR register + 0x14 + 0x20 + read-only + 0x00000000 + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +A read to this register when the BSY Flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + SPI_SSPTXCRCR + SPI_SSPTXCRCR + SPI_SSPTXCRCR register + 0x18 + 0x20 + read-only + 0x00000000 + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode. + 0 + 1 + read-only + + + + + SPI2S_I2SCFGR + SPI2S_I2SCFGR + SPI2S_I2SCFGR register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHLEN + Channel length (number of bits per audio channel) +- 0: 16-bit wide +- 1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. + 0 + 1 + read-write + + + DATLEN + Data length to be transferred +- 00: 16-bit data length +- 01: 24-bit data length +- 10: 32-bit data length +- 11: Not allowed + 1 + 2 + read-write + + + CKPOL + Steady state clock polarity +- 0: I2S clock steady state is low level +- 1: I2S clock steady state is high level + 3 + 1 + read-write + + + I2SSTD + I2S standard selection +- 00: I2S Philips standard. +- 01: MSB justified standard (left justified) +- 10: LSB justified standard (right justified) +- 11: PCM standard + 4 + 2 + read-write + + + PCMSYNC + PCM frame synchronization +- 0: Short frame synchronization +- 1: Long frame synchronization +Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode. + 7 + 1 + read-write + + + I2SCFG + I2S configuration mode +- 00: Slave - transmit +- 01: Slave - receive +- 10: Master - transmit +- 11: Master - receive + 8 + 2 + read-write + + + I2SE + I2S enable +- 0: I2S peripheral is disabled +- 1: I2S peripheral is enabled +Note: This bit is not used in SPI mode. + 10 + 1 + read-write + + + I2SMOD + I2S mode selection +- 0: SPI mode is selected +- 1: I2S mode is selected +Note: This bit should be configured when the SPI is disabled. + 11 + 1 + read-write + + + ASTREN + Asynchronous start enable. +Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. + 12 + 1 + read-write + + + B_0x0 + The Asynchronous start is disabled. When the I2S is enabled in slave mode, the I2S slave starts the transfer when the I2S clock is received and an appropriate transition (depending on the protocol selected) is detected on the WS signal. + + 0x0 + + + B_0x1 + The Asynchronous start is enabled. When the I2S is enabled in slave mode, the I2S slave starts immediately the transfer when the I2S clock is received from the master without checking the expected transition of WS signal. + + 0x1 + + + + + + + SPI2S_I2SPR + SPI2S_I2SPR + SPI2S_I2SPR register + 0x20 + 0x20 + read-write + 0x00000002 + + + I2SDIV + I2S linear prescaler +I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. + 0 + 8 + read-write + + + ODD + Odd factor for the prescaler +- 0: Real divider value is = I2SDIV *2 +- 1: Real divider value is = (I2SDIV * 2)+1 + 8 + 1 + read-write + + + MCKOE + Master clock output enable +- 0: Master clock output is disabled +- 1: Master clock output is enabled + 9 + 1 + read-write + + + + + + + SYSTEM_CTRL + SYSTEM_CTRL + 0x40000000 + + 0x0 + 0x48 + registers + + + + DIE_ID + DIE_ID + DIE_ID register + 0x00 + 0x20 + read-only + 0x00000120 + + + REVISION + Cut revision (metal fix) + 0 + 4 + read-only + + + VERSION + Cut version + 4 + 4 + read-only + + + PRODUCT + Product version. +May be used to discriminate several version of a same digital BLE LPH device embedding +different analog versions + 8 + 4 + read-only + + + + + JTAG_ID + JTAG_ID + JTAG_ID register + 0x04 + 0x20 + read-only + 0x02027041 + + + MANUF_ID + Manufacturer ID + 1 + 11 + read-only + + + PART_NUMBER + Part number + 12 + 16 + read-only + + + VERSION_NUMBER + Version + 28 + 4 + read-only + + + + + I2C_FMP_CTRL + I2C_FMP_CTRL + I2C_FMP_CTRL register + 0x08 + 0x20 + read-write + 0x00000000 + + + I2C1_PA0_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. +0: PA0 pin operated in standard mode. +1: FM+ mode is enabled on PA0 pin, and speed control is bypassed + 0 + 1 + read-write + + + I2C1_PA1_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. +0: PA1 pin operated in standard mode. +1: FM+ mode is enabled on PA1 pin, and speed control is bypassed + 1 + 1 + read-write + + + I2C1_PB6_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O. +0: PB6 pin operated in standard mode. +1: FM+ mode is enabled on PB6 pin, and speed control is bypassed. + 2 + 1 + read-write + + + I2C1_PB7_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O. +0: PB7 pin operated in standard mode. +1: FM+ mode is enabled on PB7 pin, and speed control is bypassed + 3 + 1 + read-write + + + I2C1_PB10_FMP + I2C1_PB10_FMP: I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB10 I/O. +0: PB10 pin operated in standard mode. +1: FM+ mode is enabled on PB10 pin, and speed control is bypassed. + 4 + 1 + read-write + + + I2C1_PB11_FMP + I2C1_PB11_FMP: I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB11 I/O. +0: PB11 pin operated in standard mode. +1: FM+ mode is enabled on PB11 pin, and speed control is bypassed + 5 + 1 + read-write + + + I2C2_PA6_FMP + I2C2_PA6_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SCL on PA6 I/O. +0: PA6 pin operated in standard mode. +1: FM+ mode is enabled on PA6 pin, and speed control is bypassed. + 6 + 1 + read-write + + + I2C2_PA7_FMP + I2C2_PA7_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SDA on PA7 I/O. +0: PA7 pin operated in standard mode. +1: FM+ mode is enabled on PA7 pin, and speed control is bypassed + 7 + 1 + read-write + + + I2C2_PA13_FMP + I2C2_PA13_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SCL on PA13 I/O. +0: PA13 pin operated in standard mode. +1: FM+ mode is enabled on PA13 pin, and speed control is bypassed. + 8 + 1 + read-write + + + I2C2_PA14_FMP + I2C2_PA14_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SDA on PA14 I/O. +0: PA14 pin operated in standard mode. +1: FM+ mode is enabled on PA14 pin, and speed control is bypassed. + 9 + 1 + read-write + + + + + IO_DTR + IO_DTR + IO_DTR register + 0x0C + 0x20 + read-write + 0x00000000 + + + PA0_DT + PA0_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 0 + 1 + read-write + + + PA1_DT + PA1_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 1 + 1 + read-write + + + PA2_DT + PA2_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 2 + 1 + read-write + + + PA3_DT + PA3_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 3 + 1 + read-write + + + PA4_DT + PA4_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 4 + 1 + read-write + + + PA5_DT + PA5_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 5 + 1 + read-write + + + PA6_DT + PA6_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 6 + 1 + read-write + + + PA7_DT + PA7_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 7 + 1 + read-write + + + PA8_DT + PA8_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 8 + 1 + read-write + + + PA9_DT + PA9_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 9 + 1 + read-write + + + PA10_DT + PA10_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 10 + 1 + read-write + + + PA11_DT + PA11_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 11 + 1 + read-write + + + PA12_DT + PA12_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 12 + 1 + read-write + + + PA13_DT + PA13_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 13 + 1 + read-write + + + PA14_DT + PA14_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 14 + 1 + read-write + + + PA15_DT + PA15_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 15 + 1 + read-write + + + PB0_DT + PB0_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 16 + 1 + read-write + + + PB1_DT + PB1_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 17 + 1 + read-write + + + PB2_DT + PB2_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 18 + 1 + read-write + + + PB3_DT + PB3_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 19 + 1 + read-write + + + PB4_DT + PB4_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 20 + 1 + read-write + + + PB5_DT + PB5_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 21 + 1 + read-write + + + PB6_DT + PB6_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 22 + 1 + read-write + + + PB7_DT + PB7_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 23 + 1 + read-write + + + PB8_DT + PB8_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 24 + 1 + read-write + + + PB9_DT + PB9_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 25 + 1 + read-write + + + PB10_DT + PB10_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 26 + 1 + read-write + + + PB11_DT + PB11_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 27 + 1 + read-write + + + PB12_DT + PB12_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 28 + 1 + read-write + + + PB13_DT + PB13_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 29 + 1 + read-write + + + PB14_DT + PB14_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 30 + 1 + read-write + + + PB15_DT + PB15_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 31 + 1 + read-write + + + + + IO_IBER + IO_IBER + IO_IBER register + 0x10 + 0x20 + read-write + 0x000000000 + + + PA0_IBE + PA0_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 0 + 1 + read-write + + + PA1_IBE + PA1_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 1 + 1 + read-write + + + PA2_IBE + PA2_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 2 + 1 + read-write + + + PA3_IBE + PA3_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 3 + 1 + read-write + + + PA4_IBE + PA4_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 4 + 1 + read-write + + + PA5_IBE + PA5_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 5 + 1 + read-write + + + PA6_IBE + PA6_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 6 + 1 + read-write + + + PA7_IBE + PA7_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 7 + 1 + read-write + + + PA8_IBE + PA8_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 8 + 1 + read-write + + + PA9_IBE + PA9_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 9 + 1 + read-write + + + PA10_IBE + PA10_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 10 + 1 + read-write + + + PA11_IBE + PA11_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 11 + 1 + read-write + + + PA12_IBE + PA12_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 12 + 1 + read-write + + + PA13_IBE + PA13_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 13 + 1 + read-write + + + PA14_IBE + PA14_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 14 + 1 + read-write + + + PA15_IBE + PA15_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 15 + 1 + read-write + + + PB0_IBE + PB0_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 16 + 1 + read-write + + + PB1_IBE + PB1_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 17 + 1 + read-write + + + PB2_IBE + PB2_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 18 + 1 + read-write + + + PB3_IBE + PB3_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 19 + 1 + read-write + + + PB4_IBE + PB4_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 20 + 1 + read-write + + + PB5_IBE + PB5_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 21 + 1 + read-write + + + PB6_IBE + PB6_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 22 + 1 + read-write + + + PB7_IBE + PB7_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 23 + 1 + read-write + + + PB8_IBE + PB8_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 24 + 1 + read-write + + + PB9_IBE + PB9_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 25 + 1 + read-write + + + PB10_IBE + PB10_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 26 + 1 + read-write + + + PB11_IBE + PB11_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 27 + 1 + read-write + + + PB12_IBE + PB12_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 28 + 1 + read-write + + + PB13_IBE + PB13_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 29 + 1 + read-write + + + PB14_IBE + PB14_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 30 + 1 + read-write + + + PB15_IBE + PB15_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 31 + 1 + read-write + + + + + IO_IEVR + IO_IEVR + IO_IEVR register + 0x14 + 0x20 + read-write + 0x00000000 + + + PA0_IEV + PA0_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 0 + 1 + read-write + + + PA1_IEV + PA1_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 1 + 1 + read-write + + + PA2_IEV + PA2_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 2 + 1 + read-write + + + PA3_IEV + PA3_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 3 + 1 + read-write + + + PA4_IEV + PA4_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 4 + 1 + read-write + + + PA5_IEV + PA5_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 5 + 1 + read-write + + + PA6_IEV + PA6_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 6 + 1 + read-write + + + PA7_IEV + PA7_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 7 + 1 + read-write + + + PA8_IEV + PA8_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 8 + 1 + read-write + + + PA9_IEV + PA9_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 9 + 1 + read-write + + + PA10_IEV + PA10_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 10 + 1 + read-write + + + PA11_IEV + PA11_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 11 + 1 + read-write + + + PA12_IEV + PA12_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 12 + 1 + read-write + + + PA13_IEV + PA13_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 13 + 1 + read-write + + + PA14_IEV + PA14_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 14 + 1 + read-write + + + PA15_IEV + PA15_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 15 + 1 + read-write + + + PB0_IEV + PB0_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 16 + 1 + read-write + + + PB1_IEV + PB1_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 17 + 1 + read-write + + + PB2_IEV + PB2_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 18 + 1 + read-write + + + PB3_IEV + PB3_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 19 + 1 + read-write + + + PB4_IEV + PB4_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 20 + 1 + read-write + + + PB5_IEV + PB5_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 21 + 1 + read-write + + + PB6_IEV + PB6_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 22 + 1 + read-write + + + PB7_IEV + PB7_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 23 + 1 + read-write + + + PB8_IEV + PB8_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 24 + 1 + read-write + + + PB9_IEV + PB9_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 25 + 1 + read-write + + + PB10_IEV + PB10_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 26 + 1 + read-write + + + PB11_IEV + PB11_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 27 + 1 + read-write + + + PB12_IEV + PB12_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 28 + 1 + read-write + + + PB13_IEV + PB13_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 29 + 1 + read-write + + + PB14_IEV + PB14_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 30 + 1 + read-write + + + PB15_IEV + PB15_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 31 + 1 + read-write + + + + + IO_IER + IO_IER + IO_IER register + 0x18 + 0x20 + read-write + 0x000000000 + + + PA0_IE + PA0_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 0 + 1 + read-write + + + PA1_IE + PA1_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 1 + 1 + read-write + + + PA2_IE + PA2_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 2 + 1 + read-write + + + PA3_IE + PA3_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 3 + 1 + read-write + + + PA4_IE + PA4_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 4 + 1 + read-write + + + PA5_IE + PA5_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 5 + 1 + read-write + + + PA6_IE + PA6_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 6 + 1 + read-write + + + PA7_IE + PA7_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 7 + 1 + read-write + + + PA8_IE + PA8_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 8 + 1 + read-write + + + PA9_IE + PA9_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 9 + 1 + read-write + + + PA10_IE + PA10_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 10 + 1 + read-write + + + PA11_IE + PA11_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 11 + 1 + read-write + + + PA12_IE + PA12_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 12 + 1 + read-write + + + PA13_IE + PA13_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 13 + 1 + read-write + + + PA14_IE + PA14_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 14 + 1 + read-write + + + PA15_IE + PA15_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 15 + 1 + read-write + + + PB0_IE + PB0_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 16 + 1 + read-write + + + PB1_IE + PB1_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 17 + 1 + read-write + + + PB2_IE + PB2_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 18 + 1 + read-write + + + PB3_IE + PB3_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 19 + 1 + read-write + + + PB4_IE + PB4_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 20 + 1 + read-write + + + PB5_IE + PB5_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 21 + 1 + read-write + + + PB6_IE + PB6_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 22 + 1 + read-write + + + PB7_IE + PB7_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 23 + 1 + read-write + + + PB8_IE + PB8_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 24 + 1 + read-write + + + PB9_IE + PB9_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 25 + 1 + read-write + + + PB10_IE + PB10_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 26 + 1 + read-write + + + PB11_IE + PB11_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 27 + 1 + read-write + + + PB12_IE + PB12_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 28 + 1 + read-write + + + PB13_IE + PB13_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 29 + 1 + read-write + + + PB14_IE + PB14_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 30 + 1 + read-write + + + PB15_IE + PB15_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 31 + 1 + read-write + + + + + IO_ISCR + IO_ISCR + IO_ISCR register + 0x1C + 0x20 + read-write + 0x00000000 + + + PA0_ISC + PA0_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 0 + 1 + read-write + + + PA1_ISC + PA1_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + PA2_ISC + PA2_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 2 + 1 + read-write + + + PA3_ISC + PA3_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 3 + 1 + read-write + + + PA4_ISC + PA4_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 4 + 1 + read-write + + + PA5_ISC + PA5_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 5 + 1 + read-write + + + PA6_ISC + PA6_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 6 + 1 + read-write + + + PA7_ISC + PA7_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 7 + 1 + read-write + + + PA8_ISC + PA8_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 8 + 1 + read-write + + + PA9_ISC + PA9_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 9 + 1 + read-write + + + PA10_ISC + PA10_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 10 + 1 + read-write + + + PA11_ISC + PA11_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 11 + 1 + read-write + + + PA12_ISC + PA12_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 12 + 1 + read-write + + + PA13_ISC + PA13_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 13 + 1 + read-write + + + PA14_ISC + PA14_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 14 + 1 + read-write + + + PA15_ISC + PA15_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 15 + 1 + read-write + + + PB0_ISC + PB0_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 16 + 1 + read-write + + + PB1_ISC + PB1_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 17 + 1 + read-write + + + PB2_ISC + PB2_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 18 + 1 + read-write + + + PB3_ISC + PB3_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 19 + 1 + read-write + + + PB4_ISC + PB4_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 20 + 1 + read-write + + + PB5_ISC + PB5_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 21 + 1 + read-write + + + PB6_ISC + PB6_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 22 + 1 + read-write + + + PB7_ISC + PB7_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 23 + 1 + read-write + + + PB8_ISC + PB8_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 24 + 1 + read-write + + + PB9_ISC + PB9_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 25 + 1 + read-write + + + PB10_ISC + PB10_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 26 + 1 + read-write + + + PB11_ISC + PB11_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 27 + 1 + read-write + + + PB12_ISC + PB12_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 28 + 1 + read-write + + + PB13_ISC + PB13_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 29 + 1 + read-write + + + PB14_ISC + PB14_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 30 + 1 + read-write + + + PB15_ISC + PB15_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 31 + 1 + read-write + + + + + PWRC_IER + PWRC_IER + PWRC_IER register + 0x20 + 0x20 + read-write + 0x000000000 + + + BORH_IE + BORH_IE: BORH interrupt enable. +0: BORH interrupt is disabled. +1: BORH interrupt is enabled. + 0 + 1 + read-write + + + PVD_IE + PVD_IE: Programmable Voltage Detector interrupt enable. +0: PVD interrupt is disabled. +1: PVD interrupt is enabled. + 1 + 1 + read-write + + + WKUP_IE + WKUP_IE: Power Controller Wakeup event interrupt enable. +0: Interrupt on wakeup event seen by the PWRC is disabled. +1: Interrupt on wakeup event seen by the PWRC is enabled. + 2 + 1 + read-write + + + + + PWRC_ISCR + PWRC_ISCR + PWRC_ISCR register + 0x24 + 0x20 + read-write + 0x000000000 + + + BORH_ISC + BORH_ISC: BORH interrupt status. +0: no pending interrupt. +1: voltage went under BORH threshold / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 0 + 1 + read-write + + + PVD_ISC + PVD_ISC: Programmable Voltage Detector status. +0: no pending interrupt. +1: voltage went under programmed threshold / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + WKUP_ISC + WKUP_ISC: Indicates the Power Controller receives a Wakeup event. +0: no pending interrupt. +1: Wakeup event on PWRC occurred / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. +This flag will be read at 1 if a wakeup event arrives so close to the low power mode entry +requests that the PWRC aborts before shutting down the system. + 2 + 1 + read-write + + + + + GPIO_SWA_CTRL + GPIO_SWA_CTRL + GPIO_SWA_CTRL register + 0x28 + 0x20 + read-write + 0x000000000 + + + ATB1_nPVD + ATB1_nPVD: select the analog feature on PB14 between ATB1 and PVD when the PB14 I/O +is programmed in analog mode (in the associated GPIO_MODER register): +0: PVD external voltage feature is selected (default). +1: ATB1 feature is selected + 0 + 1 + read-write + + + + + INTAI_DTR + INTAI_DTR + INTAI_DTR register + 0x2C + 0x20 + read-write + 0x000000000 + + + TX_DT + TX_DT: detection type on TX_SEQUENCE signal: +0: detection on edge (default). +1: detection on level + 0 + 1 + read-write + + + RX_DT + RX_DT: detection type on RX_SEQUENCE signal: +0: detection on edge (default). +1: detection on level + 1 + 1 + read-write + + + COMP_DT + COMP_DT: detection type on COMP_OUT (after COMP_POL selection) signal: +0: detection on edge (default). +1: detection on level + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_DT + RFIP_BUSY_STATUS_DT: detection type on RFIP_BUSY_STATUS signal: +0: detection on edge (default). +1: detection on level + 5 + 1 + read-write + + + + + INTAI_IBER + INTAI_IBER + INTAI_IBER register + 0x30 + 0x20 + read-write + 0x000000000 + + + TX_IBE + TX_IBE: interrupt edge register on TX_SEQUENCE signal: +0: detection on single edge (default). +1: detection on both edges + 0 + 1 + read-write + + + RX_IBE + RX_IBE: interrupt edge register on RX_SEQUENCE signal: +0: detection on single edge (default). +1: detection on both edges + 1 + 1 + read-write + + + COMP_IBE + COMP_IBE: interrupt edge register on COMP_OUT signal: +0: detection on single edge (default). +1: detection on both edges + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_IBE + RFIP_BUSY_STATUS_IBE: interrupt edge register on RFIP_BUSY_STATUS signal: +0: detection on single edge (default). +1: detection on both edges + 5 + 1 + read-write + + + + + INTAI_IEVR + INTAI_IEVR + INTAI_IEVR register + 0x34 + 0x20 + read-write + 0x000000000 + + + TX_IEV + TX_IEV: interrupt polarity event on TX_SEQUENCE signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 0 + 1 + read-write + + + RX_IEV + RX_IEV: interrupt polarity event on RX_SEQUENCE signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 1 + 1 + read-write + + + COMP_IEV + COMP_IEV: interrupt polarity event on COMP_OUT signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_IEV + RFIP_BUSY_STATUS_IEV: interrupt polarity event on RFIP_BUSY_STATUS signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 5 + 1 + read-write + + + + + INTAI_IER + INTAI_IER + INTAI_IER register + 0x38 + 0x20 + read-write + 0x000000000 + + + TX_IE + TX_IE: interrupt enable on TX_SEQUENCE signal: +0: TX_SEQUENCE interrupt is disabled (default). +1: TX_SEQUENCE interrupt is enabled + 0 + 1 + read-write + + + RX_IE + RX_IE: interrupt enable on RX_SEQUENCE signal: +0: RX_SEQUENCE interrupt is disabled (default). +1: RX_SEQUENCE interrupt is enabled + 1 + 1 + read-write + + + COMP_IE + COMP_IE: interrupt enable on COMP_OUT signal: +0: COMP_OUT interrupt is disabled (default). +1: COMP_OUT interrupt is enabled + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_IE + RFIP_BUSY_STATUS_IE: interrupt enable on RFIP_BUSY_STATUS signal: +0: RFIP_BUSY_STATUS interrupt is disabled (default). +1: RFIP_BUSY_STATUS interrupt is enabled + 5 + 1 + read-write + + + + + INTAI_ISCR + INTAI_ISCR + INTAI_ISCR register + 0x3C + 0x20 + read-write + 0x000000000 + + + TX_ISC + TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): +0: no activity on TX_SEQUENCE detected. +1: activity on TX_SEQUENCE occurred + 0 + 1 + read-write + + + RX_ISC + RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): +0: no activity on RX_SEQUENCE detected. +1: activity on RX_SEQUENCE occurred + 1 + 1 + read-write + + + TX_ISEDGE + TX_ISEDGE: interrupt edge status on TX_SEQUENCE signal: +0: falling edge on TX_SEQUENCE detected. +1: rising edge on TX_SEQUENCE detected. + 2 + 1 + read-only + + + RX_ISEDGE + RX_ISEDGE: interrupt edge status on RX_SEQUENCE signal: +0: falling edge on RX_SEQUENCE detected. +1: rising edge on RX_SEQUENCE detected. + 3 + 1 + read-only + + + COMP_ISC + COMP_ISC: interrupt status on COMP_OUT (can be a rising or a falling edge depending on +INTAI_IEVR and INTAI_IBER): +0: no activity on COMP_OUT detected. +1: activity on COMP_OUT occurred + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_ISC + RFIP_BUSY_STATUS_ISC: interrupt status on RFIP_BUSY_STATUS (can be a rising or a +falling edge depending on INTAI_IEVR and INTAI_IBER): +0: no activity on RFIP_BUSY_STATUS detected. +1: activity on RFIP_BUSY_STATUS occurred + 5 + 1 + read-write + + + + + SYSCFG_SR1 + SYSCFG_SR1 + SYSCFG_SR1 register + 0x40 + 0x20 + read-only + 0x000000000 + + + RFIP_BUSY_STATUS + RFIP_BUSY_STATUS: MR_SUBG BUSY status: +Software should check that MR_SUBG IP is not busy (or relay on the related interrupt) before +to initiate any system clock frequency switch to operate the switching in a safe way. +0: MR_SUBG is not busy. +1: MR_SUBG is busy + 5 + 1 + read-only + + + + + RF_DTB_CONFIG + RF_DTB_CONFIG + RF_DTB_CONFIG register + 0x44 + 0x20 + read-write + 0x000000000 + + + RF_DTB_CONFIG + Controlling AF7 extended mode: +- 00 : MR_SUBG DTB default configuration +- 01 : MR_SUBG DTB shuffled configuration +- 10 : BUBBLE_DTB configuration +- 11 : MR_SUBG DTB default configuration (as per 00) + 0 + 2 + read-write + + + + + + + SWITCHABLE + SWITCHABLE + 0x49001040 + + 0x0 + 0x40 + registers + + + + RFIP_VERSION + RFIP_VERSION + RFIP_VERSION register + 0x0 + 0x20 + read-only + 0x00001100 + + + REVISION + Revision of the RFIP to be used for metal fixes) + 4 + 4 + read-only + + + VERSION + Version of the RFIP (to be used for cut upgrades) + 8 + 4 + read-only + + + PRODUCT + Used for major upgrades (new protocols support / new features) + 12 + 4 + read-only + + + + + IRQ_ENABLE + IRQ_ENABLE + IRQ_ENABLE register + 0x4 + 0x20 + read-write + 0x00000000 + + + BIT_SYNC_DETECTED_E + Preamble has been detected, the content of the PAYLOAD_X registers is not yet valid. + 0 + 1 + read-write + + + FRAME_SYNC_COMPLETE_E + Frame Sync has been detected, the content of the PAYLOAD_X registers is not yet valid. + 1 + 1 + read-write + + + FRAME_COMPLETE_E + Frame ( payload + CRC) received, the content of the PAYLOAD_X registers is valid. + 2 + 1 + read-write + + + FRAME_VALID_E + Frame ( payload + CRC) received wthout error (the CRC has been checked and is matching with the received CRC). + 3 + 1 + read-write + + + + + STATUS + STATUS + STATUS register + 0x8 + 0x20 + read-write + 0x00000000 + + + BIT_SYNC_DETECTED_F + Preamble has been detected, the content of the PAYLOAD_X registers is not yet valid. + 0 + 1 + read-write + + + FRAME_SYNC_COMPLETE_F + Frame Sync has been detected, the content of the PAYLOAD_X registers is not yet valid. + 1 + 1 + read-write + + + FRAME_COMPLETE_F + Frame ( payload + CRC) received, the content of the PAYLOAD_X registers is valid. + 2 + 1 + read-write + + + FRAME_VALID_F + Frame ( payload + CRC) received wthout error (the CRC has been checked and is matching with the received CRC). + 3 + 1 + read-write + + + ERROR_F + - 11 : CRC error + + 30 + 2 + read-write + + + + + + + STATUS + STATUS + 0x49000600 + + 0x0 + 0x40 + registers + + + + RFSEQ_IRQ_STATUS + RFSEQ_IRQ_STATUS + RFSEQ_IRQ_STATUS register + 0x0 + 0x20 + read-write + 0x00000000 + + + TX_DONE_F + Transmission done flag + 0 + 1 + + + RX_OK_F + Reception ended and OK flag + 1 + 1 + + + RX_TIMEOUT_F + Reception timeout flag + 2 + 1 + + + RX_CRC_FRROR_F + Reception with CRC error flag + 3 + 1 + + + FAST_RX_TERM_F + Fast RX Termination flag + 4 + 1 + + + RXTIMER_STOP_CDT_F + Enable interrupt on RXTIMER_STOP_CDT_F flag + 7 + 1 + + + SABORT_DONE_F + SABORT command treated and done flag + 8 + 1 + + + COMMAND_REJECTED_F + Command rejection flag. + 9 + 1 + + + CS_F + Carrier Sense (RSSI over threshold) flag + 12 + 1 + + + PREAMBLE_VALID_F + Valid PREAMBLE detection flag. + 13 + 1 + + + SYNC_VALID_F + Valid SYNC word detection flag. + 14 + 1 + + + DATABUFFER0_USED_F + Data Buffer 0 fully read in TX or fully written in RX flag + 16 + 1 + + + DATABUFFER1_USED_F + Data Buffer 1 fully read in TX or fully written in RX flag + 17 + 1 + + + RX_ALMOST_FULL_0_F + Data Buffer0 used (written during a RX) up to programmed thresold flag + 18 + 1 + + + RX_ALMOST_FULL_1_F + Data Buffer1 used (written during a RX) up to programmed thresold flag + 19 + 1 + + + TX_ALMOST_EMPTY_0_F + Data Buffer0 used (read during a TX) up to programmed thresold flag + 20 + 1 + + + TX_ALMOST_EMPTY_1_F + Data Buffer1 used (read during a TX) up to programmed thresold flag + 21 + 1 + + + AHB_ACCESS_ERROR_F + An AHB transfer issue occurred for one of the AHB masters (RRM, Data Buffer Manager, Sequencer). + 22 + 1 + + + HW_ANA_FAILURE_F + Analog HW failure flag (PLL lock / unlock error, calibration error) + + 24 + 1 + + + SEQ_F + Sequencer completion flag. + 26 + 1 + + + RRM_CMD_START_F + RRM-UDRA command list execution started flag. + 27 + 1 + + + RRM_CMD_END_F + RRM-UDRA command list execution ended flag. + 28 + 1 + + + SAFEASK_CALIB_DONE_F + End of Safe-ASK PA calibration flag. + 30 + 1 + + + AGC_CALIB_DONE_F + Valid RSSI value available in the RSSI_RUNNING bit field flag. + 31 + 1 + + + + + RFSEQ_STATUS_DETAIL + RFSEQ_STATUS_DETAIL + RFSEQ_STATUS_DETAIL register + 0x4 + 0x20 + read-write + 0x00000000 + + + DBM_FIFO_ERROR_F + Data Buffer Manager internal FIFO overflow/underflow flag. + 5 + 1 + + + PLL_LOCK_FAIL_F + PLL lock fail status flag + 8 + 1 + + + PLL_UNLOCK_F + PLL unlock event flag + 9 + 1 + + + PLL_CALFREQ_ERROR_F + VCO frequency calibration error flag + 10 + 1 + + + PLL_CALAMP_ERROR_F + VCO amplitude calibration error flag + 11 + 1 + + + SEQ_ACTIONTIMEOUT_F + The Sequencer has ended because the current SeqAction reached its ActionTimeout. + 14 + 1 + + + SEQ_COMPLETE_F + The Sequencer has ended the last defined SeqAction properly( NextAction math or null pointer) + 15 + 1 + + + + + RADIO_FSM_INFO + RADIO_FSM_INFO + RADIO_FSM_INFO register + 0x8 + 0x20 + read-only + 0x00000000 + + + RADIO_FSM_STATE + State of the Radio FSM + + 0 + 5 + read-only + + + + + RX_INDICATOR + RX_INDICATOR + RX_INDICATOR register + 0xc + 0x20 + read-only + 0x00000000 + + + RSSI_LEVEL_ON_SYNC + RSSI level captured at the end of the SYNC word detection of the received packet. + 0 + 9 + read-only + + + RSSI_LEVEL_RUN + Continuous level of the output of the measured RSSI value + 12 + 9 + read-only + + + AGC_WORD + AGC word of the received packet. + 24 + 4 + read-only + + + ANT_SELECT + Currently selected antenna + 31 + 1 + read-only + + + + + RX_INFO_REG + RX_INFO_REG + RX_INFO_REG register + 0x10 + 0x20 + read-only + 0x00000000 + + + RX_PCKTLEN_OUT + Indicates received packet length in bytes: + + 0 + 16 + read-only + + + + + RX_CRC_REG + RX_CRC_REG + RX_CRC_REG register + 0x14 + 0x20 + read-only + 0x00000000 + + + RX_CRC_OUT + CRC field of the received packet (read-only info) + 0 + 32 + read-only + + + + + QI_INFO + QI_INFO + QI_INFO register + 0x18 + 0x20 + read-only + 0x00000000 + + + PQI_INFO + Preamble Quality Indicator (PQI) value of the received packet. + 0 + 8 + read-only + + + SQI_INFO + SYNC Quality Indicator (SQI) value of the received packet. + 8 + 6 + read-only + + + SQI_SEC + Indicate if measured SQI refers to SYNC word or secondary SYNC word + + 14 + 1 + read-only + + + AFC_CORRECTION + AFC value frozen at sync reception. + 16 + 8 + read-only + + + + + DATABUFFER_INFO + DATABUFFER_INFO + DATABUFFER_INFO register + 0x1c + 0x20 + read-only + 0x00000000 + + + CURRENT_DATABUFFER_COUNT + Indicates the number of bytes used in the last used DATA BUFFER. + 0 + 16 + read-only + + + NB_DATABUFFER_USED + Provides the number of data buffers which have been fully used + + 16 + 15 + read-only + + + CURRENT_DATABUFFER + Indicates which Data Buffer is currently used by the HW + + 31 + 1 + read-only + + + + + TIME_CAPTURE + TIME_CAPTURE + TIME_CAPTURE register + 0x20 + 0x20 + read-only + 0x00000000 + + + TIME_CAPTURE + Interpolated absolute time value captured on specific programmable event through TIME_CAPTURESEL[2:0] bit field. + 0 + 32 + read-only + + + + + IQC_CORRECTION_OUT + IQC_CORRECTION_OUT + IQC_CORRECTION_OUT register + 0x24 + 0x20 + read-only + 0x00000000 + + + IQC_CORRECT_OUT + Final correction value output from IQC (compensation engine). + 0 + 24 + read-only + + + + + PA_SAFEASK_OUT + PA_SAFEASK_OUT + PA_SAFEASK_OUT register + 0x28 + 0x20 + read-only + 0x00000000 + + + PA_CODEMAX + Safe ASK level (provided after a CALIB_SAFEASK command), indicating the maximum PA Power to program before reaching ohmic saturation. + 0 + 8 + read-only + + + + + VCO_CALIB_OUT + VCO_CALIB_OUT + VCO_CALIB_OUT register + 0x2c + 0x20 + read-only + 0x0000FF40 + + + VCO_CALFREQ_OUT + VCO frequency calibration value currently output by the VCO calibration block (and applied on the VCO when ON) + + 0 + 7 + read-only + + + VCO_CALAMP_OUT + VCO amplitude calibration value currently output by the VCO calibration block (and applied on the VCO when ON) + + 8 + 14 + read-only + + + + + SEQ_INFO + SEQ_INFO + SEQ_INFO register + 0x30 + 0x20 + read-only + 0x00000000 + + + SEQ_FSM_STATE + Current state of the Sequencer + + 0 + 5 + read-only + + + + + SEQ_EVENT_STATUS + SEQ_EVENT_STATUS + SEQ_EVENT_STATUS register + 0x34 + 0x20 + read-only + 0x00000000 + + + SEQ_EVENT_STATUS + Current value of the seq_event_status used by the Sequencer for next action mask comparison. + 0 + 32 + read-only + + + + + + + STATIC + STATIC + 0x49000400 + + 0x0 + 0x40 + registers + + + + PCKT_CONFIG + PCKT_CONFIG + PCKT_CONFIG register + 0x0 + 0x20 + read-write + 0x000103F1 + + + CRC_MODE + CRC type (0, 8, 16, 16 802. + 0 + 3 + read-write + + + SECONDARY_SYNC_SEL + In TX mode: this bit selects which synchro word is sent on the frame between SYNC and SEC_SYNC + + 3 + 1 + read-write + + + SYNC_LEN + Length of the SYNC (and secondary) SYNC word in 1-bit granularity + + 4 + 5 + read-write + + + SYNC_PRESENT + Indicate if a SYNC word is present on the frame or not (null length) + + 9 + 1 + read-write + + + LEN_WIDTH + Indicates if the LENGTH field is defined on 1 byte or 2 bytes + + 10 + 1 + read-write + + + FIX_VAR_LEN + Select the length mode + + 11 + 1 + read-write + + + PREAMBLE_LENGTH + Length of the PREAMBLE in pairs of bits (0 to 2046) + 12 + 10 + read-write + + + PREAMBLE_SEQ + Select the PREAMBLE pattern to be applied + + 22 + 2 + read-write + + + POSTAMBLE_LENGTH + Length of the POSTAMBLE in pair of bits (0 to 126 bits) + 24 + 6 + read-write + + + POSTAMBLE_SEQ + Packet postamble control: postamble bit sequence selection + + 30 + 2 + read-write + + + + + SYNC + SYNC + SYNC register + 0x4 + 0x20 + read-write + 0x23232323 + + + SYNC + Synchro word. + 0 + 32 + read-write + + + + + SEC_SYNC + SEC_SYNC + SEC_SYNC register + 0x8 + 0x20 + read-write + 0x00000000 + + + SEC_SYNC + Secondary Synchro word. + 0 + 32 + read-write + + + + + CRC_INIT + CRC_INIT + CRC_INIT register + 0xc + 0x20 + read-write + 0x00000000 + + + CRC_INIT_VAL + CRC intialization value + 0 + 32 + read-write + + + + + PCKT_CTRL + PCKT_CTRL + PCKT_CTRL register + 0x10 + 0x20 + read-write + 0x00000000 + + + PCKT_FORMAT + Packet format + + 0 + 1 + read-write + + + BYTE_SWAP + Invert MSB-LSB transmission order (bitendianess) + + 2 + 1 + read-write + + + FOUR_FSK_SYM_SWAP + Invert bit to symbol mapping for 4-(G)FSK + + 3 + 1 + read-write + + + RX_MODE + RX mode + + 4 + 3 + read-write + + + TX_MODE + TX mode + + 7 + 2 + read-write + + + WHIT_BF_FEC + Whitening before FEC feature + + 10 + 1 + read-write + + + WHIT_EN + Whitening enable + + 11 + 1 + read-write + + + WHIT_INIT + Whitening initialization value. + 12 + 9 + read-write + + + CODING_SEL + Coding / decoding selection + + 21 + 2 + read-write + + + MANCHESTER_TYPE + Select the Manchester encoding polarity + + 24 + 1 + read-write + + + INT_EN_4G + This field is used as Interleaving enable for 802. + 25 + 1 + read-write + + + FEC_TYPE_4G + FEC type for 802. + 26 + 1 + read-write + + + FCS_TYPE_4G + FCS type value in header field for 802. + 27 + 1 + read-write + + + MOD_INTERP_EN + Enable frequency interpolator (for 2-GFSK and 4-GFSK) + + 28 + 1 + read-write + + + PN_SEL + Select the Pseudo Random Binary Sequence (PRBS) polynomial to apply when the selected transmission mode is PN mode (TX_MODE = '11') + + 29 + 1 + read-write + + + FORCE_2FSK_SYNC_MODE + Force SYNC word to be formatted as a 2-(G)FSK bit steam instead of 4-(G)FSK + + 31 + 1 + read-write + + + + + DATABUFFER0_PTR + DATABUFFER0_PTR + DATABUFFER0_PTR register + 0x14 + 0x20 + read-write + 0x00000000 + + + DATABUFFER0_PTR + Start address to be used by the Data Buffer0 + + 2 + 30 + read-write + + + + + DATABUFFER1_PTR + DATABUFFER1_PTR + DATABUFFER1_PTR register + 0x18 + 0x20 + read-write + 0x00000000 + + + DATABUFFER1_PTR + Start address to be used by the Data Buffer1 + + 2 + 30 + read-write + + + + + DATABUFFER_SIZE + DATABUFFER_SIZE + DATABUFFER_SIZE register + 0x1c + 0x20 + read-write + 0x00000000 + + + DATABUFFER_SIZE + Size of the Data Buffers (Data Buffer0 and Data Buffer1) expressed in byte unit. + 0 + 16 + read-write + + + + + PA_LEVEL_3_0 + PA_LEVEL_3_0 + PA_LEVEL_3_0 register + 0x20 + 0x20 + read-write + 0x230B0100 + + + PA_LEVEL0 + Output power level for first step + + 0 + 8 + read-write + + + PA_LEVEL1 + Output power level for second step + + 8 + 8 + read-write + + + PA_LEVEL2 + Output power level for third step + + 16 + 8 + read-write + + + PA_LEVEL3 + Output power level for fourth step + + 24 + 8 + read-write + + + + + PA_LEVEL_7_4 + PA_LEVEL_7_4 + PA_LEVEL_7_4 register + 0x24 + 0x20 + read-write + 0x51473B2F + + + PA_LEVEL4 + Output power level for fifth step + + 0 + 8 + read-write + + + PA_LEVEL5 + Output power level for sixth step + + 8 + 8 + read-write + + + PA_LEVEL6 + Output power level for seventh step + + 16 + 8 + read-write + + + PA_LEVEL7 + Output power level for eighth step + + 24 + 8 + read-write + + + + + PA_CONFIG + PA_CONFIG + PA_CONFIG register + 0x28 + 0x20 + read-write + 0x0000015C + + + PA_RAMP_STEP_WIDTH + Step width (unit: 1/8 of bit period). + 0 + 2 + read-write + + + PA_LEVEL_MAX_INDEX + Final level for power ramping (i. + 2 + 3 + read-write + + + PA_INTERP_EN + Enable power level interpolator. + 6 + 1 + read-write + + + ASK_OOK_EN + Enable the generation of the internal TXDATA signal provided to the FIR. + 7 + 1 + read-write + + + PA_DRV_MODE + Select the PA topology + + 8 + 2 + read-write + + + PA_MODE + Configure the Power Amplifier (PA) mode + + 10 + 2 + read-write + + + LIN_NLOG + Enable/disable the linear-to- log conversion of the PA code output from Safe-ASK calibrator + + 13 + 1 + read-write + + + PA_RAMP_ENABLE + Enable the power ramping + + 14 + 1 + read-write + + + + + IF_CTRL + IF_CTRL + IF_CTRL register + 0x2c + 0x20 + read-write + 0x04CD04CD + + + IF_OFFSET_DIG + Intermediate frequency setting for the digital shift-to-baseband circuits (default: 300 kHz) + + 0 + 13 + read-write + + + IF_OFFSET_ANA + Intermediate frequency setting for the synthesizer configuration (default: 300 kHz). + 16 + 13 + read-write + + + IF_MODE + Select the cutoff frequency of the AAF for the analog RFSUBG IP + + 31 + 1 + read-write + + + + + AS_QI_CTRL + AS_QI_CTRL + AS_QI_CTRL register + 0x30 + 0x20 + read-write + 0x58008028 + + + RSSI_THR + Signal detect threshold in 1 dB resolution. + 0 + 9 + read-write + + + PQI_THR + PQI threshold (if 0 then ). + 9 + 4 + read-write + + + CS_MODE + Carrier Sense mode selection + + 13 + 2 + read-write + + + SQI_EN + SQI enable + + 15 + 1 + read-write + + + SQI_THR + SQI threshold defining the precision requested to detect the SYNC word. + 16 + 3 + read-write + + + AS_EQU_CTRL + ISI cancellation equalizer + + 26 + 2 + read-write + + + AS_MEAS_TIME + Select the RSSI measurement duration during Antenna switching procedure + 28 + 3 + read-write + + + AS_CS_BLANKING + Blank received data if signal is below the CS threshold + + 31 + 1 + read-write + + + + + IQC_CONFIG + IQC_CONFIG + IQC_CONFIG register + 0x34 + 0x20 + read-write + 0xC0000000 + + + IQC_CORRECT_IN + Correction value Input for the IQ compensation engine (to be used as starting point or when the engine is disabled). + 0 + 24 + read-write + + + LOAD_IQC_INIT + Action bit to load the IQC_CORRECT_IN[23:0] bit field in the recirculation register when this bit is written to 1. + 29 + 1 + write-only + + + REUSE_CORRECTION + Reuse last correction value + 30 + 1 + read-write + + + IQC_ENABLE + Enable IQC + 31 + 1 + read-write + + + + + DSSS_CTRL + DSSS_CTRL + DSSS_CTRL register + 0x38 + 0x20 + read-write + 0x00000000 + + + ACQ_WINDOW + DSSS acquisition window + 0 + 4 + read-write + + + SPREADING_EXP + DSSS spreading exponent + 4 + 3 + read-write + + + DSSS_EN + DSSS mode enable + 7 + 1 + read-write + + + ACQ_HITS + DSSS acquisition hits + 8 + 2 + read-write + + + ACQ_THR + DSSS acquisition threshold + 10 + 6 + read-write + + + + + + + TIM16 + TIM16 address block description + TIM16 + 0x40005000 + + 0x0 + 0x6C + registers + + + TIM16 + TIM16 interrupt + 26 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIF_REMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + CCPC + CCPC: Capture/compare preloaded control + +0: CCxE, CCxNE and OCxM bits are not preloaded + +1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated + +only when COM bit is set. + +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + CCUS + CCUS: Capture/compare control update selection + +0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit only. + +1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit or when an rising edge occurs on TRGI. + +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + CCDS + CCDS: Capture/compare DMA selection + +0: CCx DMA request sent when CCx event occurs + +1: CCx DMA requests sent when update event occurs + 3 + 1 + read-write + + + MMS + MMS[2:0]: Master mode selection + +These bits allow to select the information to be sent in master mode to slave timers for + +synchronization (TRGO). The combination is as follows: + +000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the + +reset is generated by the trigger input (slave mode controller configured in reset mode) then + +the signal on TRGO is delayed compared to the actual reset. + +001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is + +useful to start several timers at the same time or to control a window in which a slave timer is + +enable. The Counter Enable signal is generated by a logic OR between CEN control bit and + +the trigger input when configured in gated mode. When the Counter Enable signal is + +controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is + +selected (see the MSM bit description in TIMx_SMCR register). + +010: Update - The update event is selected as trigger output (TRGO). For instance a master + +timer can then be used as a prescaler for a slave timer. + +011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be + +set (even if it was already high), as soon as a capture or a compare match occurred. + +(TRGO). + +100: Compare - OC1REF signal is used as trigger output (TRGO). + 4 + 3 + read-write + + + TI1S + TI1S: TI1 selection + +0: The TIMx_CH1 pin is connected to TI1 input + +1: Reserved + 7 + 1 + read-write + + + OIS1 + OIS1: Output Idle state 1 (OC1 output) + +0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + +1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 8 + 1 + read-write + + + OIS1N + OIS1N: Output Idle state 1 (OC1N output) + +0: OC1N=0 after a dead-time when MOE=0 + +1: OC1N=1 after a dead-time when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 9 + 1 + read-write + + + + + SMCR + SMCR + SMCR register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + SMS_2_0 + SMS[3:0]: Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to +the polarity selected on the external input (see Input Control register and Control Register +description. + 0 + 3 + read-write + + + TS_2_0 + TS[4:0]: Trigger selection + +This bitfield selects the trigger input to be used to synchronize the counter. + +00000: Internal Trigger 0 (ITR0) + +00001: Internal Trigger 1 (ITR1) + +00010: Internal Trigger 2 (ITR2) + +00011: Internal Trigger 3 (ITR3) + +00100: TI1 Edge Detector (TI1F_ED) + +00101: Filtered Timer Input 1 (TI1FP1) + +Other codes: Reserved + +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to + +avoid wrong edge detections at the transition. + +See Table 79 in IUM: TIM16 register map and reset values on page 469 for more details on ITRx + +meaning for each Timer. + 4 + 3 + read-write + + + MSM + MSM: Master/slave mode + +0: No action + +1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect + +synchronization between the current timer and its slaves (through TRGO). It is useful if we + +want to synchronize several timers on a single external event. + 7 + 1 + read-write + + + SMS_3 + SMS[3:0]: Slave mode selection. See SMS_LSB description + 16 + 1 + read-write + + + TS_4_3 + TS[4:0]: Trigger selection. See TS_LSB description + 20 + 2 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + COMIE + COMIE: COM interrupt enable + +0: COM interrupt disabled + +1: COM interrupt enabled + 5 + 1 + read-write + + + TIE + TIE: Trigger interrupt enable + +0: Trigger interrupt disabled + +1: Trigger interrupt enabled + 6 + 1 + read-write + + + BIE + BIE: Break interrupt enable + +0: Break interrupt disabled + +1: Break interrupt enabled + 7 + 1 + read-write + + + UDE + UDE: Update DMA request enable + +0: Update DMA request disabled + +1: Update DMA request enabled + 8 + 1 + read-write + + + CC1DE + CC1DE: Capture/Compare 1 DMA request enable + +0: CC1 DMA request disabled + +1: CC1 DMA request enabled + 9 + 1 + read-write + + + CCUDE + CCUDE: CC-Update DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: CC-Update DMA request disabled. + +1: CC-Update DMA request enabled. + 13 + 1 + read-write + + + TDE + TDE: Trigger DMA request enable + +0: Trigger DMA request disabled + +1: Trigger DMA request enabled + 14 + 1 + read-write + + + BDE + BDE: Break DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: Break DMA request disabled. + +1: Break DMA request enabled. + 15 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value. It is cleared by + +software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + COMIF + COMIF: COM interrupt flag + +This flag is set by hardware on a COM event (once the capture compare control bits CCxE, + +CCxNE, OCxMhave been updated). It is cleared by software. + +0: No COM event occurred + +1: COM interrupt pending + 5 + 1 + read-write + + + TIF + TIF: Trigger interrupt flag + +This flag is set by hardware on trigger event (active edge detected on TRGI input when the + +slave mode controller is enabled in all modes but gated mode, both edges in case gated + +mode is selected). It is cleared by software. + +0: No trigger event occurred + +1: Trigger interrupt pending + 6 + 1 + read-write + + + BIF + BIF: Break interrupt flag + +This flag is set by hardware as soon as the break input goes active. It can be cleared by + +software if the break input is not active. + +0: No break event occurred + +1: An active level has been detected on the break input + 7 + 1 + read-write + + + CC1OF + CC1OF: Capture_Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + COMG + COMG: Capture/Compare control update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action + +1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + +Note: This bit acts only on channels that have a complementary output. + 5 + 1 + write-only + + + TG + TG: Trigger generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action + +1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if + +enabled + 6 + 1 + write-only + + + BG + BG: Break generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or + +DMA transfer can occur if enabled. + 7 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately.. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M[2:0]: Output Compare 1 mode (bits 2 to 0) +These bits define the behavior of the output reference signal OC1REF from which OC1 and +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends +on CC1P and CC1NP bits. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable. + +Not used in Blue51. Not available in IUM + +0: OC1REF is not affected by the ocref_clr_int signal. + +1: OC1REF is cleared as soon as a high level is detected on the ocref_clr_int signal. + 7 + 1 + read-write + + + OC1M_3 + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1_in register + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x1 + Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + 0x1 + + + + + CC1NE + CC1NE: Capture/Compare 1 complementary output enable + +0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1E bits. + +1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1E bits. + 2 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 complementary output polarity + +CC1 channel configured as output: + +0: OC1N active high + +1: OC1N active low + +CC1 channel configured as input: + +This bit is used in conjunction with CC1P to define the polarity of TI1FP1. Refer + +to the description of CC1P. + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the + +preloaded bit only when a commutation event is generated. + 3 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIF_CPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0xFFFF + 0xFFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x0 + 0xF + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 8 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + CCR + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + BDTR + BDTR + BDTR register + 0x44 + 0x20 + read-write + 0x0 + 0xF + + + DTG + DTG[7:0]: Dead-time generator setup + +This bit-field defines the duration of the dead-time inserted between the complementary + +outputs. DT correspond to this duration. + +DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS + +DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS + +DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS + +DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS + +Example if TDTS=125ns (8MHz), dead-time possible values are: + +0 to 15875 ns by 125 ns steps, + +16 us to 31750 ns by 250 ns steps, + +32 us to 63 us by 1 us steps, + +64 us to 126 us by 2 us steps + +Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BDTR register). + 0 + 8 + read-write + + + LOCK + LOCK[1:0]: Lock configuration + +These bits offer a write protection against software errors. + +00: LOCK OFF - No bit is write protected + +01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 + +register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in + +TIMx_AF1 register can no longer be written. + +10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER + +register, as long as the related channel is configured in output through the CCxS bits) as well + +as OSSR and OSSI bits can no longer be written. + +11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in + +TIMx_CCMRx registers, as long as the related channel is configured in output through the + +CCxS bits) can no longer be written. + +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + +has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + OSSI + OSSI: Off-state selection for Idle mode + +This bit is used when MOE=0 on channels configured as outputs. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + +1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or + +CCxNE=1. OC/OCN enable output signal=1) + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 10 + 1 + read-write + + + OSSR + OSSR: Off-state selection for Run mode + +This bit is used when MOE=1 on channels that have a complementary output which are + +configured as outputs. OSSR is not implemented if no complementary output is implemented + +in the timer. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which + +is taken over by the AFIO logic, which forces a Hi-Z state) + +1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 + +or CCxNE=1 (the output is still controlled by the timer). + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 11 + 1 + read-write + + + BKE + BKE: Break enable + +1; Break inputs (BRK) enabled + +Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in + +TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK) disabled + 0x0 + + + + + BKP + BKP: Break polarity + +0: Break input BRK is active low. + +1: Break input BRK is active high + +Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + AOE + AOE: Automatic output enable + +not be active) + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is + 0x1 + + + + + MOE + MOE: Main output enable + +This bit is cleared asynchronously by hardware as soon as the break input is active. It is set + +by software or automatically depending on the AOE bit. It is acting only on the channels + +which are configured in output. + +0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + +1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in + +TIMx_CCER register) + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + 15 + 1 + read-write + + + BKDSRM + BKDSRM: Break Disarm + +0: Break input BRK is armed + +1: Break input BRK is disarmed + +This bit is cleared by hardware when no break source is active. + +The BKDSRM bit must be set by software to release the bidirectional output control (opendrain + +output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the + +fault condition has disappeared. + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + BKBID + BKBID: Break Bidirectional + +0: Break input BRK in input mode + +1: Break input BRK in bidirectional mode + +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input + +mode and in open drain output mode. Any active break event asserts a low logic level on the + +Break input to indicate an internal break event to external devices. + +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + + + DCR + DCR + DCR register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + DBA + DBA[4:0]: DMA base address + +This 5-bit field defines the base-address for DMA transfers (when read/write access are + +done through the TIMx_DMAR address). DBA is defined as an offset starting from the + +address of the TIMx_CR1 register. + +Example: + +00000: TIMx_CR1, + +00001: TIMx_CR2, + +00010: Reserved, + +... + +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In + +this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + DBL + DBL[4:0]: DMA burst length + +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when + +a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. + +Transfers can be in half-words or in bytes (see example below). + +00000: 1 transfer, + +00001: 2 transfers, + +00010: 3 transfers, + +... + +10001: 18 transfers. + 8 + 5 + read-write + + + + + DMAR + DMAR + DMAR register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + DMAB + DMAB[15:0]: DMA register for burst accesses + +A read or write operation to the DMAR register accesses the register located at the address + +(TIMx_CR1 address) + (DBA + DMA index) x 4 + +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base + +address configured in TIMx_DCR register, DMA index is automatically controlled by the + +DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 16 + read-write + + + + + OR1 + OR1 + OR1 register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + OR1_0 + Not used in Blue51. Not available in IUM + 0 + 1 + read-write + + + TI1_RMP + TI1_RMP[1:0]: Timer 16 input 1 connection + +This bit is set and cleared by software. + +00: TIM16 TI1 is connected to GPIO + +01: TIM16 TI1 is connected to LCO + +10: TIM16 TI1 is connected to COMP_OUT + +11: TIM16 TI1 is connected to MCO + 1 + 2 + read-write + + + + + AF1 + AF1 + AF1 register + 0x60 + 0x20 + read-write + 0x1 + 0xF + + + BKINE + BKINE: BRK BKIN enable. + +This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is + +ORed with the other enabled BRK sources. + +0: BKIN input disabled. + +1: BKIN input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 0 + 1 + read-write + + + BKCMP1E + BKCMP1E: BRK COMP1 enable. + +This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other + +enabled BRK sources. + +0: COMP1 input disabled. + +1: COMP1 input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 1 + 1 + read-write + + + BKINP + BKINP: BRK BKIN input polarity. + +This bit selects the BKIN alternate function input sensitivity. It must be programmed together + +with the BKP polarity bit. + +0: BKIN input is active low. + +1: BKIN input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 9 + 1 + read-write + + + BKCMP1P + BKCMP1P: BRK COMP1 input polarity. + +This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP + +polarity bit. + +0: COMP1 input is active low. + +1: COMP1 input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 10 + 1 + read-write + + + + + TISEL + TISEL + TISEL register + 0x68 + 0x20 + read-write + + + TI1SEL + TI1SEL[3:0]: selects TI1[0] to TI1[15] input + +0000: TIMx_CH1 input + +Others: Reserved + 0 + 4 + read-write + + + + + + + TIM2 + TIM2 address block description + TIM2 + 0x40002000 + + 0x0 + 0x6C + registers + + + TIM2 + TIM2 interrupt + 10 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + DIR + DIR: Direction + +0: Counter used as upcounter + +1: Counter used as downcounter + +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder + +mode. + 4 + 1 + read-write + + + CMS + CMS[1:0]: Center-aligned mode selection + +00: Edge-aligned mode. The counter counts up or down depending on the direction bit + +(DIR). + +01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting down. + +10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting up. + +11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +both when the counter is counting up or down. + +Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as + +the counter is enabled (CEN=1) + 5 + 2 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIF_REMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + CCDS + CCDS: Capture/compare DMA selection + +0: CCx DMA request sent when CCx event occurs + +1: CCx DMA requests sent when update event occurs + 3 + 1 + read-write + + + MMS + MMS[2:0]: Master mode selection + +These bits allow to select the information to be sent in master mode to slave timers for + +synchronization (TRGO). The combination is as follows: + +000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the + +reset is generated by the trigger input (slave mode controller configured in reset mode) then + +the signal on TRGO is delayed compared to the actual reset. + +001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is + +useful to start several timers at the same time or to control a window in which a slave timer is + +enabled. The Counter Enable signal is generated by a logic OR between CEN control bit + +and the trigger input when configured in gated mode. + +When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, + +except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR + +register). + +010: Update - The update event is selected as trigger output (TRGO). For instance a master + +timer can then be used as a prescaler for a slave timer. + +011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be + +set (even if it was already high), as soon as a capture or a compare match occurred. + +(TRGO) + +100: Compare - OC1REF signal is used as trigger output (TRGO) + +101: Compare - OC2REF signal is used as trigger output (TRGO) + +110: Compare - OC3REF signal is used as trigger output (TRGO) + +111: Compare - OC4REF signal is used as trigger output (TRGO) + +Note: The clock of the slave timer must be enabled prior to receive events from the master + +timer, and must not be changed on-the-fly while triggers are received from the master + +timer. + 4 + 3 + read-write + + + TI1S + TI1S: TI1 selection + +0: The TIMx_CH1 pin is connected to TI1 input. + +1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 7 + 1 + read-write + + + + + SMCR + SMCR + SMCR register + 0x08 + 0x20 + read-write + 0x0 + 0x0 + + + SMS_2_0 + SMS: Slave mode selection + +When external signals are selected the active edge of the trigger signal (TRGI) is linked to + +the polarity selected on the external input (see Input Control register and Control Register + +description. + +0000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal + +clock. + +0001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 + +level. + +0010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 + +level. + +0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges + +depending on the level of the other input. + +0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter + +and generates an update of the registers. + +0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The + +counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of + +the counter are controlled. + +0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not + +reset). Only the start of the counter is controlled. + +0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + +1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) + +reinitializes the counter, generates an update of the registers and starts the counter. + +Codes above 1000: Reserved. + +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input + +(TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the + +gated mode checks the level of the trigger signal. + 0 + 3 + read-write + + + OCCS + OCCS: OCREF clear selection + +This bit is used to select the OCREF clear source. + +0: OCREF_CLR_INT is connected to the OCREF_CLR input (stuck at 0 so no effect) + +1: OCREF_CLR_INT is connected to ETRF + 3 + 1 + read-write + + + TS_2_0 + TS[4:0]: Trigger selection + +This bit-field selects the trigger input to be used to synchronize the counter. + +00000: Internal Trigger 0 (ITR0) + +00001: Internal Trigger 1 (ITR1) + +00010: Internal Trigger 2 (ITR2) + +00011: Internal Trigger 3 (ITR3) + +00100: TI1 Edge Detector (TI1F_ED) + +00101: Filtered Timer Input 1 (TI1FP1) + +00110: Filtered Timer Input 2 (TI2FP2) + +00111: External Trigger input (ETRF) + +Others: Reserved + +See Table Note:: TIM2 internal trigger connection on page 395 for more details on ITRx + +meaning for each Timer. + +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to + +avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + MSM + MSM: Master/Slave mode + +0: No action + +1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect + +synchronization between the current timer and its slaves (through TRGO). It is useful if we + +want to synchronize several timers on a single external event. + 7 + 1 + read-write + + + ETF + ETF[3:0]: External trigger filter + +This bit-field then defines the frequency used to sample ETRP signal and the length of the + +digital filter applied to ETRP. The digital filter is made of an event counter in which N events + +are needed to validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N=6 + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 8 + 4 + read-write + + + ETPS + ETPS[1:0]: External trigger prescaler + +External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A + +prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external + +clocks. + +00: Prescaler OFF + +01: ETRP frequency divided by 2 + +10: ETRP frequency divided by 4 + +11: ETRP frequency divided by 8 + 12 + 2 + read-write + + + ECE + ECE: External clock enable + +This bit enables External clock mode 2. + +0: External clock mode 2 disabled + +1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF + +signal. + +Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with + +TRGI connected to ETRF (SMS=111 and TS=111). + +Note: 2: It is possible to simultaneously use external clock mode 2 with the following slave + +modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be + +connected to ETRF in this case (TS bits must not be 111). + +Note: 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, + +the external clock input is ETRF. + 14 + 1 + read-write + + + ETP + ETP: External trigger polarity + +This bit selects whether ETR or ETR is used for trigger operations + +0: ETR is non-inverted, active at high level or rising edge. + +1: ETR is inverted, active at low level or falling edge. + 15 + 1 + read-write + + + SMS_3 + SMS[3]: Slave mode selection - bit 3 + +Refer to SMS description - bits2:0 + 16 + 1 + read-write + + + TS_4_3 + Trigger selection. See TS_2_0_ description + 20 + 2 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + CC2IE + CC2IE: Capture/Compare 2 interrupt enable + +0: CC2 interrupt disabled + +1: CC2 interrupt enabled + 2 + 1 + read-write + + + CC3IE + CC3IE: Capture/Compare 3 interrupt enable + +0: CC3 interrupt disabled + +1: CC3 interrupt enabled + 3 + 1 + read-write + + + CC4IE + CC4IE: Capture/Compare 4 interrupt enable + +0: CC4 interrupt disabled + +1: CC4 interrupt enabled + 4 + 1 + read-write + + + TIE + TIE: Trigger interrupt enable + +0: Trigger interrupt disabled + +1: Trigger interrupt enabled + 6 + 1 + read-write + + + UDE + UDE: Update DMA request enable + +0: Update DMA request disabled + +1: Update DMA request enabled + 8 + 1 + read-write + + + CC1DE + CC1DE: Capture/Compare 1 DMA request enable + +0: CC1 DMA request disabled + +1: CC1 DMA request enabled + 9 + 1 + read-write + + + CC2DE + CC2DE: Capture/Compare 2 DMA request enable + +0: CC2 DMA request disabled + +1: CC2 DMA request enabled + 10 + 1 + read-write + + + CC3DE + CC3DE: Capture/Compare 3 DMA request enable + +0: CC3 DMA request disabled + +1: CC3 DMA request enabled + 11 + 1 + read-write + + + CC4DE + CC4DE: Capture/Compare 4 DMA request enable + +0: CC4 DMA request disabled + +1: CC4 DMA request enabled + 12 + 1 + read-write + + + TDE + TDE: Trigger DMA request enable + +0: Trigger DMA request disabled + +1: Trigger DMA request enabled + 14 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value, with some + +exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register + +description). It is cleared by software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow (in upcounting and up/down-counting modes) or + +underflow (in downcounting mode) + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + CC2IF + CC2IF: Capture/Compare 2 interrupt flag + +refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + CC3IF: Capture/Compare 3 interrupt flag + +refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + CC4IF: Capture/Compare 4 interrupt flag + +refer to CC1IF description + 4 + 1 + read-write + + + TIF + TIF: Trigger interrupt flag + +This flag is set by hardware on trigger event (active edge detected on TRGI input when the + +slave mode controller is enabled in all modes but gated mode. It is set when the counter + +starts or stops when gated mode is selected. It is cleared by software.. + +0: No trigger event occurred. + +1: Trigger interrupt pending. + 6 + 1 + read-write + + + CC1OF + CC1OF: Capture/Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + CC2OF + CC2OF: Capture/Compare 2 overcapture flag + +refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + CC3OF: Capture/Compare 3 overcapture flag + +refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + CC4OF: Capture/Compare 4 overcapture flag + +refer to CC1OF description + 12 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + CC2G + CC2G: Capture/Compare 2 generation + +refer to CC1G description + 2 + 1 + write-only + + + CC3G + CC3G: Capture/Compare 3 generation + +refer to CC1G description + 3 + 1 + write-only + + + CC4G + CC4G: Capture/Compare 4 generation + +refer to CC1G description + 4 + 1 + write-only + + + TG + TG: Trigger generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action + +1: The TIF flag is set in TIMx_SR register. Related interrupt can occur if enabled. + 6 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M: Output Compare 1 mode + +These bits define the behavior of the output reference signal OC1REF from which OC1 and + +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends + +on CC1P and CC1NP bits. + +0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the + +counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing + +base). + +0001: Set channel 1 to active level on match. OC1REF signal is forced high when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + +0100: Force inactive level - OC1REF is forced low. + +0101: Force active level - OC1REF is forced high. + +0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT TIMx_CCR1 + +else inactive. In downcounting, channel 1 is inactive (OC1REF='0') as long as + +TIMx_CNT>TIMx_CCR1 else active (OC1REF='1'). + +0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as + +TIMx_CNT TIMx_CCR1 else active. In downcounting, channel 1 is active as long as + +TIMx_CNT>TIMx_CCR1 else inactive. + +1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger + +event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 + +and the channels becomes active again at the next update. In down-counting mode, the + +channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is + +performed as in PWM mode 1 and the channels becomes inactive again at the next update. + +1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a + +trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM + +mode 2 and the channels becomes inactive again at the next update. In down-counting + +mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a + +comparison is performed as in PWM mode 1 and the channels becomes active again at the + +next update. + +1010: Reserved + +1011: Reserved + +1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. + +OC1REFC is the logical OR between OC1REF and OC2REF. + +1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. + +OC1REFC is the logical AND between OC1REF and OC2REF + +1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: In PWM mode, the OCREF level changes only when the result of the comparison + +changes or when the output compare mode switches from 'frozen' mode to 'PWM' + +mode. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable + +0: OC1Ref is not affected by the ETRF Input + +1: OC1Ref is cleared as soon as a High level is detected on ETRF input + 7 + 1 + read-write + + + CC2S + CC2S[1:0]: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through the TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC2FE + OC2FE: Output Compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + OC2PE: Output Compare 2 preload enable + 11 + 1 + read-write + + + OC2M_2_0 + OC2M[2:0]: Output Compare 2 mode + 12 + 3 + read-write + + + OC2CE + OC2CE: Output Compare 2 clear enable + 15 + 1 + read-write + + + OC1M_3 + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + OC2M_3 + OC2M[3]: Output Compare 2 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1_in register + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + CC2S + CC2S: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an + +internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC2PSC + IC2PSC[1:0]: Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + IC2F: Input capture 2 filter + 12 + 4 + read-write + + + + + CCMR2 + CCMR2 + CCMR2 register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/Compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC3FE + OC3FE: Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + OC3PE: Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M_2_0 + OC3M: Output compare 3 mode + 4 + 3 + read-write + + + OC3CE + OC3CE: Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC4FE + OC4FE: Output Compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + OC4PE: Output Compare 4 preload enable + 11 + 1 + read-write + + + OC4M_2_0 + OC4M[2:0]: Output Compare 4 mode + 12 + 3 + read-write + + + OC4CE + OC4CE: Output Compare 4 clear enable + 15 + 1 + read-write + + + OC3M_3 + OC3M[3]: Output Compare 3 mode (bit 3) + 16 + 1 + read-write + + + OC4M_3 + OC4M[3]: Output Compare 4 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR2_in + CCMR2_in + CCMR2_in register + CCMR2 + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC3PSC + IC3PSC: Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + IC3F: Input capture 3 filter + 4 + 4 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC4PSC + IC4PSC: Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + IC4F: Input capture 4 filter + 12 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +11: Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +Note: This bit is no longer writeable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in GPT_BDTR register) and CC1S='00' (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + CC2E: Capture/Compare 2 output enable + +refer to CC1E description + 4 + 1 + read-write + + + CC2P + CC2P: Capture/Compare 2 output polarity + +refer to CC1P description + 5 + 1 + read-write + + + CC2NP + CC2NP: Capture/Compare 2 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 7 + 1 + read-write + + + CC3E + CC3E: Capture/Compare 3 output enable + +refer to CC1E description + 8 + 1 + read-write + + + CC3P + CC3P: Capture/Compare 3 output polarity + +refer to CC1P description + 9 + 1 + read-write + + + CC3NP + CC3NP: Capture/Compare 3 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 11 + 1 + read-write + + + CC4E + CC4E: Capture/Compare 4 output enable + +refer to CC1E description + 12 + 1 + read-write + + + CC4P + CC4P: Capture/Compare 4 output polarity + +refer to CC1P description + 13 + 1 + read-write + + + CC4NP + CC4NP: Capture/Compare 4 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 15 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIF_CPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0xFFFF + 0xFFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x0 + 0xF + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 8 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + CCR1 + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + CCR2 + CCR2 + CCR2 register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + CCR2 + CCR2[15:0]: Capture/Compare 2 value + +If channel CC2 is configured as output: + +CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit + +OC2PE). Else the preload value is copied in the active capture/compare 2 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC2 output. + +If channel CC2 is configured as input: + +CCR2 is the counter value transferred by the last input capture 2 event (IC2). + 0 + 16 + read-write + + + + + CCR3 + CCR3 + CCR3 register + 0x3C + 0x20 + read-write + 0x0 + 0xF + + + CCR3 + CCR3[15:0]: Capture/Compare 3 value + +If channel CC3 is configured as output: + +CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit + +OC3PE). Else the preload value is copied in the active capture/compare 3 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC3 output. + +If channel CC3 is configured as input: + +CCR3 is the counter value transferred by the last input capture 3 event (IC3). + 0 + 16 + read-write + + + + + CCR4 + CCR4 + CCR4 register + 0x40 + 0x20 + read-write + 0x0 + 0xF + + + CCR4 + CCR4[15:0]: Capture/Compare 4 value + +If channel CC4 is configured as output: + +CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit + +OC4PE). Else the preload value is copied in the active capture/compare 4 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC4 output. + +If channel CC4 is configured as input: + +CCR4 is the counter value transferred by the last input capture 4 event (IC4). + 0 + 16 + read-write + + + + + DCR + DCR + DCR register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + DBA + DBA[4:0]: DMA base address + +This 5-bit field defines the base-address for DMA transfers (when read/write access are + +done through the TIMx_DMAR address). DBA is defined as an offset starting from the + +address of the TIMx_CR1 register. + +Example: + +00000: TIMx_CR1, + +00001: TIMx_CR2, + +00010: Reserved, + +... + +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In + +this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + DBL + DBL[4:0]: DMA burst length + +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when + +a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. + +Transfers can be in half-words or in bytes (see example below). + +00000: 1 transfer, + +00001: 2 transfers, + +00010: 3 transfers, + +... + +10001: 18 transfers. + 8 + 5 + read-write + + + + + DMAR + DMAR + DMAR register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + DMAB + DMAB[15:0]: DMA register for burst accesses + +A read or write operation to the DMAR register accesses the register located at the address + +(TIM2_CR1 address) + (DBA + DMA index) x 4 + +where TIM2_CR1 address is the address of the control register 1, DBA is the DMA base + +address configured in TIM2_DCR register, DMA index is automatically controlled by the + +DMA transfer, and ranges from 0 to DBL (DBL configured in TIM2_DCR). + 0 + 16 + read-write + + + + + OR1 + OR1 + OR1 register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + ETR_RMP + ETR_RMP: ETR remapping capability + +0: TIMx_ETR is not connected to ADC AWD (must be selected when the ETR comes from + +the ETR input pin) + +1: TIMx_ETR is connected to ADC AWD + +Note: ADC AWD source is 'ORed' with the TIMx_ETR input signals. When ADC AWD is used, + +it is necessary to make sure that the corresponding TIMx_ETR input pin is not enabled + +in the alternate function controller. + 0 + 1 + read-write + + + OR1_1 + This field is not used in Blue51. Not available in IUM + 1 + 1 + read-write + + + TI4_RMP + TI4_RMP: Input capture 4 remap + +0: TIM2 input capture 4 is connected to I/O + +1: TIM2 input capture 4 is connected to COMP1-OUT + 2 + 1 + read-write + + + + + AF1 + AF1 + AF1 register + 0x60 + 0x20 + read-write + 0x0 + 0xF + + + ETR_SEL + ETRSEL[2:0]: External trigger source selection + +000: TIMx External trigger legacy mode + +001: TIMx External trigger source select COMP1_OUT + +Other: Reserved + +Note: These bits can't be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 14 + 3 + read-write + + + ETR_SEL_3 + ETRSEL[2:0]: External trigger source selection + +This field is not used in Blue51. Not available in IUM + 17 + 1 + read-write + + + + + TISEL + TISEL + TISEL register + 0x68 + 0x20 + read-write + + + TI1SEL + TI1SEL[3:0]: selects TI1[0] to TI1[15] input + +0000: TIMx_CH1 input + +Others: Reserved + 0 + 4 + read-write + + + TI2SEL + TI2SEL[3:0]: selects TI2[0] to TI2[15] input + +0000: TIMx_CH2 input + +Others: Reserved + 8 + 4 + read-write + + + TI3SEL + TI3SEL[3:0]: selects TI3[0] to TI3[15] input + +0000: TIMx_CH3 input + +Others: Reserved + 16 + 4 + read-write + + + TI4SEL + TI4SEL[3:0]: selects TI4[0] to TI4[15] input + +0000: TIMx_CH4 input + +Others: Reserved + 24 + 4 + read-write + + + + + + + USART + USART + 0x41004000 + + 0x0 + 0x30 + registers + + + USART + USART interrupt + 8 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + UE + UE: USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and +current operations are discarded. The configuration of the USART is kept, but all the status +flags, in the USART_ISR are reset. This bit is set and cleared by software. +-0: USART prescaler and outputs disabled, low power mode +-1: USART enabled + 0 + 1 + read-write + + + RE + RE: Receiver enable +This bit enables the receiver. It is set and cleared by software. +-0: Receiver is disabled +-1: Receiver is enabled and begins searching for a start bit + 2 + 1 + read-write + + + TE + TE: Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +-0: Transmitter is disabled +-1: Transmitter is enabled + 3 + 1 + read-write + + + IDLEIE + IDLEIE: IDLE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register + 4 + 1 + read-write + + + RXNEIE_RXFNEIE + RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the +USART_ISR register + 5 + 1 + read-write + + + TCIE + TCIE: Transmission complete interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TC=1 in the USART_ISR register + 6 + 1 + read-write + + + TXEIE_TXFNFIE + TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register + 7 + 1 + read-write + + + PEIE + PEIE: PE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever PE=1 in the USART_ISR register + 8 + 1 + read-write + + + PS + PS: Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE +bit set). It is set and cleared by software. The parity will be selected after the current byte. +-0: Even parity +-1: Odd parity +This bit field can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + PCE + PCE: Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity +control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit +if M=0) and parity is checked on the received data. This bit is set and cleared by software. +Once it is set, PCE is active after the current byte (in reception and in transmission). +-0: Parity control disabled +-1: Parity control enabled +This bit field can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + WAKE + WAKE: Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by +software. +-0: Idle line +-1: Address mark +This bit field can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + M_0 + M0: Word length +This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit +-28 (M1)description. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + MME: Mute mode enable +This bit activates the mute mode function of the USART. When set, the USART can switch +between the active and mute modes, as defined by the WAKE bit. It is set and cleared by +software. +-0: Receiver in active mode permanently +-1: Receiver can switch between mute mode and active mode + 13 + 1 + read-write + + + CMIE + CMIE: Character match interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 14 + 1 + read-write + + + OVER8 + OVER8: Oversampling mode +-0: Oversampling by 16 +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + DEDT + DEDT[4:0]: Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted +message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample +time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only +when the DEDT and DEAT times have both elapsed. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + DEAT[4:0]: Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and +the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, +depending on the oversampling rate). +This bit field can only be written when the USART is disabled (UE=0). + 21 + 5 + read-write + + + RTOIE + RTOIE: Receiver timeout interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register + 26 + 1 + read-write + + + EOBIE + EOBIE: End of Block interrupt enable +This bit is set and cleared by software. + + 27 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + + 0x0 + + + B_0x1 + A USART interrupt is generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M_1 + Word length +This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0).s + 28 + 1 + read-write + + + FIFOEN + FIFOEN :FIFO mode enable +This bit is set and cleared by software. +-0: FIFO mode is disabled. +-1: FIFO mode is enabled. + 29 + 1 + read-write + + + TXFEIE + TXFEIE :TXFIFO empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFE=1 in the USART_ISR register + 30 + 1 + read-write + + + RXFFIE + RXFFIE :RXFIFO Full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when RXFF=1 in the USART_ISR register + 31 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + SLVEN + SLVEN: Synchronous Slave mode enable +When the SLVEN bit is set, the synchronous slave mode is enabled. +-0: Slave mode disabled. +-1: Slave mode enabled. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value + 0 + 1 + read-write + + + DIS_NSS + DIS_NSS +When the DSI_NSS bit is set, the NSS pin input will be ignored. +-0: SPI slave selection depends on NSS input pin. +-1: SPI slave will be always selected and NSS input pin will be ignored. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value + 3 + 1 + read-write + + + ADDM7 + ADDM7:7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +-0: 4-bit address detection +-1: 7-bit address detection (in 8-bit data mode) +This bit can only be written when the USART is disabled (UE=0) + 4 + 1 + read-write + + + LBDL + LBDL: LIN break detection length +This bit is for selection between 11 bit or 10 bit break detection. +-0: 10-bit break detection +-1: 11-bit break detection +This bit can only be written when the USART is disabled (UE=0). + 5 + 1 + read-write + + + LBDIE + LBDIE: LIN break detection interrupt enable +Break interrupt mask (break detection using break delimiter). +-0: Interrupt is inhibited +-1: An interrupt is generated whenever LBDF=1 in the USART_ISR register + 6 + 1 + read-write + + + LBCL + LBCL: Last bit clock pulse +This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) +has to be output on the SCLK pin in synchronous mode. +-0: The clock pulse of the last data bit is not output to the SCLK pin +-1: The clock pulse of the last data bit is output to the SCLK pin +Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit +format selected by the M bit in the USART_CR1 register. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CPHA + CPHA: Clock phase +This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It +works in conjunction with the CPOL bit to produce the desired clock/data relationship (see +Figure 137 and Figure 138) +-0: The first clock transition is the first data capture edge +-1: The second clock transition is the first data capture edge +This bit can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + CPOL + CPOL: Clock polarity +This bit allows the user to select the polarity of the clock output on the SCLK pin in synchronous +mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship +-0: Steady low value on SCLK pin outside transmission window +-1: Steady high value on SCLK pin outside transmission window +This bit can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + CLKEN + CLKEN: Clock enable +This bit allows the user to enable the SCLK pin. +-0: SCLK pin disabled +-1: SCLK pin enabled +This bit can only be written when the USART is disabled (UE=0). +Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and forced +by hardware to 0. Please refer to Section 23.4: USART implementation on page 483. +Note: In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps +below must be respected: +- UE = 0 +- SCEN = 1 +- GTPR configuration +- CLKEN= 1 +- UE = 1 + 11 + 1 + read-write + + + STOP + STOP[1:0]: STOP bits +These bits are used for programming the stop bits. +-00: 1 stop bit +-01: 0.5 stop bit. +-10: 2 stop bits +-11: 1.5 stop bits +This bit field can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + LINEN + LINEN: LIN mode enable +This bit is set and cleared by software. +-0: LIN mode disabled +-1: LIN mode enabled +The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBKRQ bit +in the USART_CR1 register, and to detect LIN Sync breaks. +This bit field can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + SWAP + SWAP: Swap TX/RX pins +This bit is set and cleared by software. +-0: TX/RX pins are used as defined in standard pinout +-1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired +connection to another UART. +This bit field can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + RXINV + RXINV: RX pin active level inversion +This bit is set and cleared by software. +-0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the RX line. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + TXINV + TXINV: TX pin active level inversion +This bit is set and cleared by software. +-0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the TX line. +This bit field can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + DATAINV + DATAINV: Binary data inversion +This bit is set and cleared by software. +-0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) +-1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The +parity bit is also inverted. +This bit field can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + MSBFIRST + MSBFIRST: Most significant bit first +This bit is set and cleared by software. +-0: data is transmitted/received with data bit 0 first, following the start bit. +-1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. +This bit field can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + ABREN + ABREN: Auto baud rate enable +This bit is set and cleared by software. +-0: Auto baud rate detection is disabled. +-1: Auto baud rate detection is enabled. + 20 + 1 + read-write + + + ABRMOD + ABRMOD[1:0]: Auto baud rate mode +These bits are set and cleared by software. +-00: Measurement of the start bit is used to detect the baud rate. +-01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 -> +Frame = Start10xxxxxx) +-10: 0x7F frame detection. +-11: 0x55 frame detection +This bit field can only be written when ABREN = 0 or the USART is disabled (UE=0). + 21 + 2 + read-write + + + RTOEN + RTOEN: Receiver timeout enable +This bit is set and cleared by software. +-0: Receiver timeout feature disabled. +-1: Receiver timeout feature enabled. +When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle +(no reception) for the duration programmed in the RTOR (receiver timeout register). + 23 + 1 + read-write + + + ADD + ADD[7:0]: Address of the USART node +This bit-field gives the address of the USART node or a character code to be recognized. +This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- +bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. +It may also be used for character detection during normal reception, Mute mode inactive (for +example, end of block detection in ModBus protocol). In this case, the whole received character (8- +bit) is compared to the ADD[7:0] value and CMF flag is set on match. +This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled +(UE=0) + 24 + 8 + read-write + + + + + CR3 + CR3 + CR3 register + 0x08 + 0x20 + read-write + 0x00000000 + + + EIE + EIE: Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing +error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR += 1 in the USART_ISR register). +-0: Interrupt is inhibited +-1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) +in the USART_ISR register. + 0 + 1 + read-write + + + IREN + IREN: IrDA mode enable +This bit is set and cleared by software. +-0: IrDA disabled +-1: IrDA enabled +This bit can only be written when the USART is disabled (UE=0). + 1 + 1 + read-write + + + IRLP + IRLP: IrDA low-power +This bit is used for selecting between normal and low-power IrDA modes +-0: Normal mode +-1: Low-power mode +This bit can only be written when the USART is disabled (UE=0). + 2 + 1 + read-write + + + HDSEL + HDSEL: Half-duplex selection +Selection of Single-wire Half-duplex mode +-0: Half duplex mode is not selected +-1: Half duplex mode is selected +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + NACK + NACK: Smartcard NACK enable +-0: NACK transmission in case of parity error is disabled +-1: NACK transmission during parity error is enabled +This bit field can only be written when the USART is disabled (UE=0). + 4 + 1 + read-write + + + SCEN + SCEN: Smartcard mode enable +This bit is used for enabling Smartcard mode. +-0: Smartcard Mode disabled +-1: Smartcard Mode enabled +This bit field can only be written when the USART is disabled (UE=0). + 5 + 1 + read-write + + + DMAR + DMAR: DMA enable receiver +This bit is set/reset by software +-1: DMA mode is enabled for reception +-0: DMA mode is disabled for reception + 6 + 1 + read-write + + + DMAT + DMAT: DMA enable transmitter +This bit is set/reset by software +-1: DMA mode is enabled for transmission +-0: DMA mode is disabled for transmission + 7 + 1 + read-write + + + RTSE + RTSE: RTS enable +-0: RTS hardware flow control disabled +-1: RTS output enabled, data is only requested when there is space in the receive buffer. The +transmission of data is expected to cease after the current character has been transmitted. +The nRTS output is asserted (pulled to 0) when data can be received. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CTSE + CTSE: CTS enable +-0: CTS hardware flow control disabled +-1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). +If the nCTS input is deasserted while data is being transmitted, then the transmission is +completed before stopping. If data is written into the data register while nCTS is asserted, +the transmission is postponed until nCTS is asserted. +This bit can only be written when the USART is disabled (UE=0) + 9 + 1 + read-write + + + CTSIE + CTSIE: CTS interrupt enable +-0: Interrupt is inhibited +-1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 10 + 1 + read-write + + + ONEBIT + ONEBIT: One sample bit method enable +This bit allows the user to select the sample method. When the one sample bit method is +selected the noise detection flag (NF) is disabled. +-0: Three sample bit method +-1: One sample bit method +This bit can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + OVRDIS + OVRDIS: Overrun Disable +This bit is used to disable the receive overrun detection. +-0: Overrun Error Flag, ORE, is set when received data is not read before receiving new +data. +-1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set +the ORE flag is not set and the new received data overwrites the previous content of the +USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data +will be written directly in USARTx_RDR register. Even when FIFO management is enabled, +the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + DDRE + DDRE: DMA Disable on Reception Error +-0: DMA is not disabled in case of reception error. The corresponding error flag is set but +RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not +asserted, so the erroneous data is not transferred (no DMA request), but next correct +received data will be transferred. (used for Smartcard mode) +-1: DMA is disabled following a reception error. The corresponding error flag is set, as well +as RXNE. The DMA request is masked until the error flag is cleared. This means that the +software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case +FIFO mode is enabled) before clearing the error flag. +This bit can only be written when the USART is disabled (UE=0). + 13 + 1 + read-write + + + DEM + DEM: Driver enable mode +This bit allows the user to activate the external transceiver control, through the DE signal. +-0: DE function is disabled. +-1: DE function is enabled. The DE signal is output on the RTS pin. +This bit can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + DEP + DEP: Driver enable polarity selection +-0: DE signal is active high. +-1: DE signal is active low. +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + SCARCNT + SCARCNT[2:0]: Smartcard auto-retry count +This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. +In transmission mode, it specifies the number of automatic retransmission retries, before +generating a transmission error (FE bit set). +In reception mode, it specifies the number or erroneous reception trials, before generating a +reception error (RXNE/RXFNE and PE bits set). +This bit field must be programmed only when the USART is disabled (UE=0). +When the USART is enabled (UE=1), this bit field may only be written to 0x0, in order to +stop retransmission. +-0x0: retransmission disabled - No automatic retransmission in transmit mode. +-0x1 to 0x7: number of automatic retransmission attempts (before signaling error) + 17 + 3 + read-write + + + TXFTIE + TXFTIE: TXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in +TXFTCFG. + 23 + 1 + read-write + + + TCBGTIE + TCBGTIE: Transmission Complete before guard time, interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever TCBGT=1 in the USARTx_ISR register + 24 + 1 + read-write + + + RXFTCFG + RXFTCFG: Receive FIFO threshold configuration +-000:Receive FIFO reaches 1/8 of its depth. +-001:Receive FIFO reaches 1/4 of its depth. +-010:Receive FIFO reaches 1/2 of its depth. +-011:Receive FIFO reaches 3/4 of its depth. +-100:Receive FIFO reaches 7/8 of its depth. +-101:Receive FIFO becomes full. +Remaining combinations: Reserved. + 25 + 3 + read-write + + + RXFTIE + RXFTIE: RXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when Receive FIFO reaches the threshold +programmed in RXFTCFG. + 28 + 1 + read-write + + + TXFTCFG + TXFTCFG: TXFIFO threshold configuration +-000:TXFIFO reaches 1/8 of its depth. +-001:TXFIFO reaches 1/4 of its depth. +-010:TXFIFO reaches 1/2 of its depth. +-011:TXFIFO reaches 3/4 of its depth. +-100:TXFIFO reaches 7/8 of its depth. +-101:TXFIFO becomes empty. +Remaining combinations: Reserved. + 29 + 3 + read-write + + + + + BRR + BRR + BRR register + 0x0C + 0x20 + read-write + 0x00000000 + + + BRR + BRR[15:4] +BRR[15:4] = USARTDIV[15:4]BRR[3:0] +When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. +When OVER8 = 1: +BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. +BRR[3] must be kept cleared + 0 + 16 + read-write + + + + + GTPR + GTPR + GTPR register + 0x10 + 0x20 + read-write + 0x00000000 + + + PSC + PSC[7:0]: Prescaler value +In IrDA Low-power and normal IrDA mode: +PSC[7:0] = IrDA Normal and Low-Power Baud Rate +Used for programming the prescaler for dividing the USART source clock to achieve the lowpower +frequency: +The source clock is divided by the value given in the register (8 significant bits): +-00000000: Reserved - do not program this value +-00000001: divides the source clock by 1 +-00000010: divides the source clock by 2 +... +In Smartcard mode: +PSC[4:0]: Prescaler value +Used for programming the prescaler for dividing the USART source clock to provide the +Smartcard clock. +The value given in the register (5 significant bits) is multiplied by 2 to give the division factor +of the source clock frequency: +-00000: Reserved - do not program this value +-00001: divides the source clock by 2 +-00010: divides the source clock by 4 +-00011: divides the source clock by 6 +... +This bit field can only be written when the USART is disabled (UE=0). + 0 + 8 + read-write + + + GT + GT[7:0]: Guard time value +This bit-field is used to program the Guard time value in terms of number of baud clock +periods. +This is used in Smartcard mode. The Transmission Complete flag is set after this guard time +value. +This bit field can only be written when the USART is disabled (UE=0). + 8 + 8 + read-write + + + + + RTOR + RTOR + RTOR register + 0x14 + 0x20 + read-write + 0x00000000 + + + RTO + RTO[23:0]: Receiver timeout value +This bit-field gives the Receiver timeout value in terms of number of baud clocks. +In standard mode, the RTOF flag is set if, after the last received character, no new start bit is +detected for more than the RTO value. +In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard +chapter for more details. In the standard, the CWT/BWT measurement is done starting from +the Start Bit of the last received character. + 0 + 24 + read-write + + + BLEN + BLEN[7:0]: Block Length +This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number +of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. +Examples: +BLEN = 0 -> 0 information characters + LEC +BLEN = 1 -> 0 information characters + CRC +BLEN = 255 -> 254 information characters + CRC (total 256 characters)) +In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO +mode is enabled). +This bit-field can be used also in other modes. In this case, the Block length counter is reset +when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. + 24 + 8 + read-write + + + + + RQR + RQR + RQR register + 0x18 + 0x20 + read-write + 0x00000000 + + + ABRRQ + ABRRQ: Auto baud rate request +Writing 1 to this bit resets the ABRF flag in the USART_ISR and request an automatic baud +rate measurement on the next received data frame. + 0 + 1 + write-only + + + SBKRQ + SBKRQ: Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as +the transmit machine is available. + 1 + 1 + write-only + + + MMRQ + MMRQ: Mute mode request +Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + RXFRQ: Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This allows to discard the received data without reading them, and avoid an overrun +condition. + 3 + 1 + write-only + + + TXFRQ + TXFRQ: Transmit data flush request +When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. +This allows to discard the transmit data. This bit must be used only in Smartcard mode, +when data has not been sent due to errors (NACK) and the FE flag is active in the +USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved +and forced by hardware to 0 +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE +(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is +supported in both UART and Smartcard modes. + 4 + 1 + write-only + + + + + ISR + ISR + ISR register + 0x1C + 0x20 + read-only + 0x000000C0 + + + PE + PE: Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by +software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +-0: No parity error +-1: Parity error + 0 + 1 + read-only + + + FE + FE: Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character +is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +In Smartcard mode, in transmission, this bit is set when the maximum number of transmit +attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR1 register. +-0: No Framing error is detected +-1: Framing error or break character is detected + 1 + 1 + read-only + + + NF + NF: START bit Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by +software, writing 1 to the NFCF bit in the USART_ICR register. +-0: No noise is detected +-1: Noise is detected + 2 + 1 + read-only + + + ORE + ORE: Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case +FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the +USARTx_ICR register. +An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. +-0: No overrun error +-1: Overrun error is detected + 3 + 1 + read-only + + + IDLE + IDLE: Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if +IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in +the USART_ICR register. +-0: No Idle line is detected +-1: Idle line is detected + 4 + 1 + read-only + + + RXNE_RXFNE + RXNE/RXFNE:Read data register not empty/RXFIFO not empty +RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been +transferred +to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from +the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It +is cleared when the RXFIFO is empty. +The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR +register. +An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. +-0: Data is not received +-1: Received data is ready to be read. + 5 + 1 + read-only + + + TC + TC: Transmission complete +This bit indicates when the last data written in the USART_TDR has been transmitted out of +the shift register. +It is set by hardware if the transmission of a frame containing data is complete and if +TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is +cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the +USART_TDR register. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +-0: Transmission is not complete +-1: Transmission is complete + 6 + 1 + read-only + + + TXE_TXFNF + TXE/TXFNF: Transmit data register empty/TXFIFO not full +When FIFO mode is disabled, TXE is set by hardware when the content of the +USARTx_TDR register has been transferred into the shift register. It is cleared by a write to +the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the +USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of +transmission failure). +When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so +data can be written in the USART_TDR. Every write in the USART_TDR places the data in +the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag +is cleared indicating that data can not be written into the USART_TDR. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After +sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to +writing in TXFIFO. (TXFNF and TXFE will be set at the same time). +An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. +-0: Data register is full/Transmit FIFO is full. +-1: Data register/Transmit FIFO is not full + 7 + 1 + read-only + + + LBDF + LBDF: LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by +writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +-0: LIN Break not detected +-1: LIN break detected + 8 + 1 + read-only + + + CTSIF + CTSIF: CTS interrupt flag +This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared +by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +-0: No change occurred on the nCTS status line +-1: A change occurred on the nCTS status line + 9 + 1 + read-only + + + CTS + CTS: CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. +-0: nCTS line set +-1: nCTS line reset + 10 + 1 + read-only + + + RTOF + RTOF: Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has +lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in +the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +-0: Timeout value not reached +-1: Timeout value reached without any data reception + 11 + 1 + read-only + + + EOBF + EOBF: End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 +Smartcard mode). The detection is done when the number of received bytes (from the start +of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if the EOBIE=1 in the USART_CR2 register. +It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. +-0: End of Block not reached +-1: End of Block (number of characters) reached + 12 + 1 + read-only + + + UDR + UDR: SPI slave underrun error flag +In slave transmission mode, this flag is set when the first clock for data transmission appears +while the software has not yet loaded any value into USARTx_DR. +-0: No underrun error +-1: underrun error + 13 + 1 + read-only + + + ABRE + ABRE: Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or +character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register + 14 + 1 + read-only + + + ABRF + ABRF: Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXNE will also be +set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was +completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to +the ABRRQ in the USART_RQR register. + 15 + 1 + read-only + + + BUSY + BUSY: Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the +RX line (successful start bit detected). It is reset at the end of the reception (successful or +not). +-0: USART is idle (no reception) +-1: Reception on going + 16 + 1 + read-only + + + CMF + CMF: Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is +cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. +-0: No Character match detected +-1: Character Match detected + 17 + 1 + read-only + + + SBKF + SBKF: Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing +1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during +the stop bit of break transmission. +-0: No break character is transmitted +-1: Break character will be transmitted + 18 + 1 + read-only + + + RWU + RWU: Receiver wakeup from Mute mode +This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a +wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) +is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the +MMRQ bit in the USART_RQR register. +-0: Receiver in active mode +-1: Receiver in mute mode + 19 + 1 + read-only + + + TEACK + TEACK: Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by +the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 +in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + REACK: Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by +the USART. +It can be used to verify that the USART is ready for reception before entering Stop mode. + 22 + 1 + read-only + + + TXFE + TXFE: TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one +data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in +the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. +-0: TXFIFO is not empty. +-1: TXFIFO is empty. + 23 + 1 + read-only + + + RXFF + RXFF: RXFIFO Full +This bit is set by hardware when RXFIFO is Full. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. +-0: RXFIFO is not Full. +-1: RXFIFO is Full. + 24 + 1 + read-only + + + TCBGT + TCBGT: Transmission complete before guard time flagl +This bit indicates when the last data written in the USART_TDR has been transmitted +correctly out of the shift register . +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is +complete and if there is no NACK from the smartcard. An interrupt is generated if +TCBGTIE=1 in the USART_CR3 register. It is cleared by software, writing 1 to the +TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +-0: Transmission is not complete or transmission is complete unsuccessfuly (i.e. a NACK is +received from the card) +-1: Transmission is complete successfully (before Guard time completion and there is no +NACK from the smart card). + 25 + 1 + read-only + + + RXFT + RXFT: RXFIFO threshold flag +This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 +register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and +one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in +the USART_CR3 register. +-0: Receive FIFO doesnt reach the programmed threshold. +-1: Receive FIFO reached the programmed threshold + 26 + 1 + read-only + + + TXFT + TXFT: TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG +in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is +generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. +-0: TXFIFO doesnt reach the programmed threshold. +-1: TXFIFO reached the programmed threshold + 27 + 1 + read-only + + + + + ICR + ICR + ICR register + 0x20 + 0x20 + read-write + 0x00000000 + + + PECF + PECF: Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + FECF: Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register + 1 + 1 + write-only + + + NECF + NECF: Noise detected clear flag +Writing 1 to this bit clears the NF flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + ORECF: Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + IDLECF: Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TXFECF + TXFECF: TXFIFO empty clear flag +Writing 1 to this bit clears the TXFE flag in the USART_ISR register + 5 + 1 + write-only + + + TCCF + TCCF: Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register + 6 + 1 + write-only + + + TCBGTCF + TCBGTCF: Transmission complete before Guard time clear flag +Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. + 7 + 1 + write-only + + + LBDCF + LBDCF: LIN break detection clear flag +Writing 1 to this bit clears the LBDF flag in the USART_ISR register. + 8 + 1 + write-only + + + CTSCF + CTSCF: CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register + 9 + 1 + write-only + + + RTOCF + RTOCF: Receiver timeout clear flag +Writing 1 to this bit clears the RTOF flag in the USART_ISR register. + 11 + 1 + write-only + + + EOBCF + EOBCF: End of block clear flag +Writing 1 to this bit clears the EOBF flag in the USART_ISR register + 12 + 1 + write-only + + + UDRCF + UDRCF:SPI slave underrun clear flag +Writing 1 to this bit clears the UDRF flag in the USART_ISR register + 13 + 1 + write-only + + + CMCF + CMCF: Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register + 17 + 1 + write-only + + + + + RDR + RDR + RDR register + 0x24 + 0x20 + read-only + 0x0 + + + RDR + RDR[8:0]: Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the +internal bus (see Figure 124). +When receiving with the parity enabled, the value read in the MSB bit is the received parity +bit. + 0 + 9 + read-only + + + + + TDR + TDR + TDR register + 0x28 + 0x20 + read-write + 0x0 + + + TDR + TDR[8:0]: Transmit data value +Contains the data character to be transmitted. +The USARTx_TDR register provides the parallel interface between the internal bus and the +output shift register (see Figure 124). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), +the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect +because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + PRESC + PRESC + PRESC register + 0x2C + 0x20 + read-write + 0x0 + + + PRESCALER + PRESCALER[3:0]: Clock prescaler +The USART input clock can be divided by a prescaler: +-0000: input clock not divided +-0001: input clock divided by 2 +-0010: input clock divided by 4 +-0011: input clock divided by 6 +-0100: input clock divided by 8 +-0101: input clock divided by 10 +-0110: input clock divided by 12 +-0111: input clock divided by 16 +-1000: input clock divided by 32 +-1001: input clock divided by 64 +-1010: input clock divided by 128 +-1011: input clock divided by 256 +Remaing combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, +programmed prescaler value will be '1011' i.e. input clock divided by 256 + 0 + 4 + read-write + + + + + + + diff --git a/svd/STM32WL3x/STM32WL31.svd b/svd/STM32WL3x/STM32WL31.svd new file mode 100644 index 0000000..a809e41 --- /dev/null +++ b/svd/STM32WL3x/STM32WL31.svd @@ -0,0 +1,28696 @@ + + + + STM32WL31 + 0.1 + STM32WL31 + + CM0+ + r0p0 + little + true + false + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC + ADC address block description + ADC + 0x41006000 + + 0x0 + 0x68 + registers + + + ADC + ADC interrupt + 12 + + + + VERSION_ID + VERSION_ID + VERSION_ID register + 0x00 + 0x20 + read-only + 0x21 + 0xFF + + + VERSION_ID + VERSION_ID[7:0]: version of the embedded IP. + 0 + 8 + read-only + + + + + CONF + CONF + CONF register + 0x04 + 0x20 + read-write + 0x20002 + 0xFFFFF + + + CONT + CONT: regular sequence runs continuously when ADC mode is enabled: + +0: enable the single conversion: when the sequence is over, the conversion stops + +1: enable the continuous conversion: when the sequence is over, the sequence starts again + +until the software sets the CTRL.STOP_OP_MODE bit. + 0 + 1 + read-write + + + SEQUENCE + SEQUENCE: enable the sequence mode (active by default): + +0: sequence mode is disabled, only SEQ0 is selected + +1: sequence mode is enabled, conversions from SEQ0 to SEQx with x=SEQ_LEN + +Note: clearing this bit is equivalent to SEQUENCE=1 and SEQ_LEN=0000. Ideally, this bit can + +be kept high as redundant with keeping high and setting SEQ_LEN=0000. + 1 + 1 + read-write + + + SEQ_LEN + SEQ_LEN[3:0]: number of conversions in a regular sequence: + +0000: 1 conversion, starting from SEQ0 + +0001: 2 conversions, starting from SEQ0 + +... + +1111: 16 conversions, starting from SEQ0 + 2 + 4 + read-write + + + SMPS_SYNCHRO_ENA + SMPS_SYNCHRO_ENA: synchronize the ADC start conversion with a pulse generated by the + +SMPS: + +0: SMPS synchronization is disabled for all ADC clock frequencies + +1: SMPS synchronization is enabled (only when ADC clock is 8 MHz or 16 MHz) + +Note: SMPS_SYNCHRO_ENA must be 0 when the ADC analog clock is 32 MHz or when + +PWRC_CR5.NOSMPS = 1. + 6 + 1 + read-write + + + SAMPLE_RATE_LSB + SAMPLE_RATE_LSB: Sample Rate LSB + +This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It + +impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description. + +When this field is set to a value different than 0, SMPS synchronization is not feasible. + +This value is hidden to the user + 9 + 2 + read-write + + + SAMPLE_RATE + SAMPLE_RATE[1:0]: conversion rate of ADC (F_ADC): + +F_ADC = F_ADC_CLK/(16 + 16*SAMPLE_RATE_MSB + 4*SAMPLE_RATE + SAMPLE_RATE_LSB),where + +F_ADC_CLK is the analog ADC clock frequency. By default F_ADC_CLK is 16MHz frequency. + 11 + 2 + read-write + + + DMA_DS_ENA + DMA_DS_EN: enable the DMA mode for the Down Sampler data path: + +0: DMA mode is disabled + +1: DMA mode is enabled + 13 + 1 + read-write + + + OVR_DS_CFG + OVR_DS_CFG: Down Sampler overrun configuration: + +0: the previous data is kept, the new one is lost + +1: the previous data is lost, the new one is kept + 15 + 1 + read-write + + + BIT_INVERT_SN + BIT_INVERT_SN: invert bit to bit the ADC data output (1's complement) when a single + +negative input is connected to the ADC: + +0: no inversion (default) + +1: enable the inversion + 17 + 1 + read-write + + + BIT_INVERT_DIFF + BIT_INVERT_DIFF: invert bit to bit the ADC data output (1's complement) when a differential + +input is connected to the ADC: + +0: no inversion (default) + +1: enable the inversion + 18 + 1 + read-write + + + ADC_CONT_1V2 + ADC_CONT_1V2: select the input sampling method: + +0: sampling only at conversion start (default) + +1: sampling starts at the end of conversion + 19 + 1 + read-write + + + SAMPLE_RATE_MSB + SAMPLE_RATE_MSB: Sample Rate MSB + +This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It + +impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description + 21 + 3 + read-write + + + + + CTRL + CTRL + CTRL register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + ADC_ON_OFF + ADC_ON_OFF: + +0: power off the ADC + +1: power on the ADC + 0 + 1 + read-write + + + START_CONV + START_CONV (1): generate a start pulse to initiate an ADC conversion: + +0: no effect + +1: start the ADC conversion + +Note: this bit is set by software and cleared by hardware. + 1 + 1 + write-only + + + STOP_OP_MODE + STOP_OP_MODE (1): stop the on-going OP_MODE (ADC mode, Analog audio mode, Full + +mode): + +0: no effect + +1: stop on-going ADC mode + +Note: this bit is set by software and cleared by hardware. + +When setting the STOP_MODE_OP, the user has to wait around 10 us before to start a new ADC conversion by setting the START_CONV bit. + 2 + 1 + write-only + + + TEST_MODE + TEST_MODE: select the functional or the test mode of the ADC: + +0: functional mode (one of the four main functional modes is used) + +1: test mode (for debug, test, calibration) + 4 + 1 + read-write + + + + + SWITCH + SWITCH + SWITCH register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + SE_VIN_0 + SE_VIN_0[1:0]: input voltage for VINM[0] / VINP[0]-VINM[0] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 0 + 2 + read-write + + + SE_VIN_1 + SE_VIN_1[1:0]: input voltage for VINM[1] / VINP[1]-VINM[1] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 2 + 2 + read-write + + + SE_VIN_2 + SE_VIN_2[1:0]: input voltage for VINM[2] / VINP[2]-VINM[2] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 4 + 2 + read-write + + + SE_VIN_3 + SE_VIN_3[1:0]: input voltage for VINM[3] / VINP[3]-VINM[3] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 6 + 2 + read-write + + + SE_VIN_4 + SE_VIN_4[1:0]: input voltage for VINP[0] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 8 + 2 + read-write + + + SE_VIN_5 + SE_VIN_5[1:0]: input voltage for VINP[1] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 10 + 2 + read-write + + + SE_VIN_6 + SE_VIN_6[1:0]: input voltage for VINP[2] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 12 + 2 + read-write + + + SE_VIN_7 + SE_VIN_7[1:0]: input voltage for VINP[3] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 14 + 2 + read-write + + + + + DS_CONF + DS_CONF + DS_CONF register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + DS_RATIO + DS_RATIO[2:0]: program the Down Sampler ratio (N factor) + +000: ratio = 1, no down sampling (default) + +001: ratio = 2 + +010: ratio = 4 + +011: ratio = 8 + +100: ratio = 16 + +101: ratio = 32 + +110: ratio = 64 + +111: ratio = 128 + 0 + 3 + read-write + + + DS_WIDTH + DS_WIDTH[2:0]: program the Down Sampler width of data output (DSDTATA) + +000: DS_DATA output on 12-bit (default) + +001: DS_DATA output on 13-bit + +010: DS_DATA output on 14-bit + +011: DS_DATA output on 15-bit + +100: DS_DATA output on 16-bit + +1xx: reserved + 3 + 3 + read-write + + + + + SEQ_1 + SEQ_1 + SEQ_1 register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + SEQ0 + SEQ0[3:0]: channel number code for first conversion of the sequence + +0000: VINM[0] to ADC single negative input + +0001: VINM[1] to ADC single negative input + +0010: VINM[2] to ADC single negative input + +0011: VINM[3] to ADC single negative input + +0100: VINP[0] to ADC single positive input + +0101: VINP[1] to ADC single positive input + +0110: VINP[2] to ADC single positive input + +0111: VINP[3] to ADC single positive input + +1000: VINP[0]-VINM[0] to ADC differential input + +1001: VINP[1]-VINM[1] to ADC differential input + +1010: VINP[2]-VINM[2] to ADC differential input + +1011: VINP[3]-VINM[3] to ADC differential input + +1100: VBAT - Battery level detector + +1101: Temperature sensor + +111x: reserved + 0 + 4 + read-write + + + SEQ1 + SEQ1[3:0]: channel number code for second conversion of the sequence. + +See SEQ0 for code detail. + 4 + 4 + read-write + + + SEQ2 + SEQ2[3:0]: channel number code for 3rd conversion of the sequence. + +See SEQ0 for code detail. + 8 + 4 + read-write + + + SEQ3 + SEQ3[3:0]: channel number code for 4th conversion of the sequence. + +See SEQ0 for code detail. + 12 + 4 + read-write + + + SEQ4 + SEQ4[3:0]: channel number code for 5th conversion of the sequence. + +See SEQ0 for code detail. + 16 + 4 + read-write + + + SEQ5 + SEQ5[3:0]: channel number code for 6th conversion of the sequence. + +See SEQ0 for code detail. + 20 + 4 + read-write + + + SEQ6 + SEQ6[3:0]: channel number code for 7th conversion of the sequence. + +See SEQ0 for code detail. + 24 + 4 + read-write + + + SEQ7 + SEQ7[3:0]: channel number code for 8th conversion of the sequence. + +See SEQ0 for code detail. + 28 + 4 + read-write + + + + + SEQ_2 + SEQ_2 + SEQ_2 register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + SEQ8 + SEQ8[3:0]: channel number code for 9th conversion of the sequence + +0000: VINM[0] to ADC single negative input + +0001: VINM[1] to ADC single negative input + +0010: VINM[2] to ADC single negative input + +0011: VINM[3] to ADC single negative input + +0100: VINP[0] to ADC single positive input + +0101: VINP[1] to ADC single positive input + +0110: VINP[2] to ADC single positive input + +0111: VINP[3] to ADC single positive input + +1000: VINP[0]-VINM[0] to ADC differential input + +1001: VINP[1]-VINM[1] to ADC differential input + +1010: VINP[2]-VINM[2] to ADC differential input + +1011: VINP[3]-VINM[3] to ADC differential input + +1100: VBAT - Battery level detector + +1101: Temperature sensor + +111x: reserved + 0 + 4 + read-write + + + SEQ9 + SEQ9[3:0]: channel number code for 10th conversion of the sequence. + +See SEQ0 for code detail. + 4 + 4 + read-write + + + SEQ10 + SEQ10[3:0]: channel number code for 11th conversion of the sequence. + +See SEQ0 for code detail. + 8 + 4 + read-write + + + SEQ11 + SEQ11[3:0]: channel number code for 12th conversion of the sequence. + +See SEQ0 for code detail. + 12 + 4 + read-write + + + SEQ12 + SEQ12[3:0]: channel number code for 13th conversion of the sequence. + +See SEQ0 for code detail. + 16 + 4 + read-write + + + SEQ13 + SEQ13[3:0]: channel number code for 14th conversion of the sequence. + +See SEQ0 for code detail. + 20 + 4 + read-write + + + SEQ14 + SEQ14[3:0]: channel number code for 15th conversion of the sequence. + +See SEQ0 for code detail. + 24 + 4 + read-write + + + SEQ15 + SEQ15[3:0]: channel number code for 16th conversion of the sequence. + +See SEQ0 for code detail. + 28 + 4 + read-write + + + + + COMP_1 + COMP_1 + COMP_1 register + 0x28 + 0x20 + read-write + 0x00555 + 0xFFFFF + + + GAIN1 + GAIN1[11:0]: first calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET1 + OFFSET1[7:0]: first calibration point + 12 + 8 + read-write + + + + + COMP_2 + COMP_2 + COMP_2 register + 0x2C + 0x20 + read-write + 0x00555 + 0xFFFFF + + + GAIN2 + GAIN2[11:0]: second calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET2 + OFFSET2[7:0]: second calibration point + 12 + 8 + read-write + + + + + COMP_3 + COMP_3 + COMP_3 register + 0x30 + 0x20 + read-write + 0x00555 + 0xFFFFF + + + GAIN3 + GAIN3[11:0]: third calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET3 + OFFSET3[7:0]: third calibration point + 12 + 8 + read-write + + + + + COMP_4 + COMP_4 + COMP_4 register + 0x34 + 0x20 + read-write + 0x00555 + 0xFFFFF + + + GAIN4 + GAIN4[11:0]: fourth calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET4 + OFFSET4[7:0]: fourth calibration point + 12 + 8 + read-write + + + + + COMP_SEL + COMP_SEL + COMP_SEL register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + OFFSET_GAIN0 + OFFSET_GAIN0[1:0]: gain / offset used in ADC single negative mode with Vinput range = + +1.2V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 0 + 2 + read-write + + + OFFSET_GAIN1 + OFFSET_GAIN1[1:0]: gain / offset used in ADC single positive mode with Vinput range = + +1.2V. This field also selects the gain/offset for Temperature Sensor input:: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 2 + 2 + read-write + + + OFFSET_GAIN2 + OFFSET_GAIN2[1:0]: gain / offset used in ADC differential mode with Vinput range = 1.2V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 4 + 2 + read-write + + + OFFSET_GAIN3 + OFFSET_GAIN3[1:0]: gain / offset used in ADC single negative mode with Vinput range = + +2.4V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 6 + 2 + read-write + + + OFFSET_GAIN4 + OFFSET_GAIN4[1:0]: gain / offset used in ADC single positive mode with Vinput range = + +2.4V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 8 + 2 + read-write + + + OFFSET_GAIN5 + OFFSET_GAIN5[1:0]: gain / offset used in ADC differential mode with Vinput range = 2.4V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 10 + 2 + read-write + + + OFFSET_GAIN6 + OFFSET_GAIN6[1:0]: gain / offset used in ADC single negative mode with Vinput range = + +3.6V. This field also selects the gain/offset for VBAT input:: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 12 + 2 + read-write + + + OFFSET_GAIN7 + OFFSET_GAIN7[1:0]: gain / offset used in ADC single positive mode with Vinput range = + +3.6V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 14 + 2 + read-write + + + OFFSET_GAIN8 + OFFSET_GAIN8[1:0]: gain / offset used in ADC differential mode with Vinput range = 3.6V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 16 + 2 + read-write + + + + + WD_TH + WD_TH + WD_TH register + 0x3C + 0x20 + read-write + 0xFFF0000 + 0xFFFFFFF + + + WD_LT + WD_LT[11:0]: analog watchdog low level threshold. + 0 + 12 + read-write + + + WD_HT + WD_HT[11:0]: analog watchdog high level threshold. + 16 + 12 + read-write + + + + + WD_CONF + WD_CONF + WD_CONF register + 0x40 + 0x20 + read-write + 0x0 + 0xF + + + AWD_CHX + AWD_CHX[15:0]: analog watchdog channel selection to define which input channel(s) need + +to be guarded by the watchdog. + +Bit0: VINM[0] to ADC negative input + +Bit1: VINM[1] to ADC negative input + +Bit2: VINM[2] to ADC negative input + +Bit3: VINM[3] to ADC negative input + +Bit4: Not used + +Bit5: VBAT to ADC negative input + +Bit6: GND to ADC negative input + +Bit7: VDDA to ADC negative input + +Bit8: VINP[0] to ADC positive input + +Bit9: VINP[1] to ADC positive input + +Bit10: VINP[2] to ADC positive input + +Bit11: VINP[3] to ADC positive input + +Bit12: Not used + +Bit13: TEMP to ADC positive input + +Bit14: GND to ADC positive input + +Bit15: VDDA to ADC positive input + 0 + 16 + read-write + + + + + DS_DATAOUT + DS_DATAOUT + DS_DATAOUT register + 0x44 + 0x20 + read-only + 0x0 + 0xF + + + DS_DATA + DS_DATA[15:0]: contain the converted data at the output of the Down Sampler. + 0 + 16 + read-only + + + + + IRQ_STATUS + IRQ_STATUS + IRQ_STATUS register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + EOC_IRQ + EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. + +When read, provide the status of the interrupt: + +0: ADC conversion is not completed + +1: ADC conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 0 + 1 + read-write + + + EODS_IRQ + EODS_IRQ: set when the Down Sampler conversion is completed. + +When read, provide the status of the interrupt: + +0: Down Sampler conversion is not completed + +1: Down Sampler conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 1 + 1 + read-write + + + EOS_IRQ + EOS_IRQ: set when a sequence of conversion is completed. + +When read, provide the status of the interrupt: + +0: sequence of conversion is not completed + +1: sequence of conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 3 + 1 + read-write + + + AWD_IRQ + AWD_IRQ: set when an analog watchdog event occurs. + +When read, provide the status of the interrupt: + +0: no analog watchdog event occurred + +1: analog watchdog event has occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 4 + 1 + read-write + + + OVR_DS_IRQ + OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) + +When read, provide the status of the interrupt: + +0: no overrun occurred + +1: overrun occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 5 + 1 + read-write + + + + + IRQ_ENABLE + IRQ_ENABLE + IRQ_ENABLE register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + EOC_IRQ + EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. + +When read, provide the status of the interrupt: + +0: ADC conversion is not completed + +1: ADC conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 0 + 1 + read-write + + + EODS_IRQ + EODS_IRQ: set when the Down Sampler conversion is completed. + +When read, provide the status of the interrupt: + +0: Down Sampler conversion is not completed + +1: Down Sampler conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 1 + 1 + read-write + + + EOS_IRQ + EOS_IRQ: set when a sequence of conversion is completed. + +When read, provide the status of the interrupt: + +0: sequence of conversion is not completed + +1: sequence of conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 3 + 1 + read-write + + + AWD_IRQ + AWD_IRQ: set when an analog watchdog event occurs. + +When read, provide the status of the interrupt: + +0: no analog watchdog event occurred + +1: analog watchdog event has occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 4 + 1 + read-write + + + OVR_DS_IRQ + OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) + +When read, provide the status of the interrupt: + +0: no overrun occurred + +1: overrun occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 5 + 1 + read-write + + + + + TEST_CONF + TEST_CONF + TEST_CONF register + 0x60 + 0x20 + read-write + 0x0 + 0xF + + + ADC_SWITCH_EN + ADC_SWITCH_EN[15:0]: enable individually each connection of the switching matrix at the + +ADC input. + +For each bit: + +0: switch X is ON + +1: switch X is OFF + +Bit mapping (corresponding to AUXADC_INSEL_1V2[15:0]): + +Bit 0: VINM[0] to ADC negative input + +Bit 1: VINM[1] to ADC negative input + +Bit 2: VINM[2] to ADC negative input + +Bit 3: VINM[3] to ADC negative input + +Bit4: GND to ADC negative input + +Bit5: VBAT to ADC negative input + +Bit6: GND to ADC negative input + +Bit7: VDDA to ADC negative input + +Bit8: VINP[0] to ADC positive input + +Bit9: VINP[1] to ADC positive input + +Bit10: VINP[2] to ADC positive input + +Bit11: VINP[3] to ADC positive input + +Bit12: VBAT to ADC positive input + +Bit13: TEMP to ADC positive input + +Bit14: GND to ADC positive input + +Bit15: VDDA to ADC positive input. + 0 + 16 + read-write + + + SEL_VIN_TYPE + SEL_VIN_TYPE[1:0]: operation mode of the selected VIN + +00: ADC single negative input + +01: ADC single positive input + +10: ADC differential input mode + +11: reserved + 18 + 2 + read-write + + + ADC_RUN + ADC_RUN: Start/stop ADC conversion. + +0: stop the ADC conversion, + +1: starts the ADC conversion. + 21 + 1 + read-write + + + ADC_ENABLE + ADC_ENABLE: + +0: disable the ADC (power OFF) + +1: enable the ADC (power ON) + 22 + 1 + read-write + + + + + DTB_CONF + DTB_CONF + DTB_CONF register + 0x64 + 0x20 + read-write + + + ADC_DBG_CONF + ADC_DBG_CONF[3:0]: use for debug purpose. + 0 + 4 + read-write + + + ADC_DTB_CONF + ADC_DTB_CONF[1:0]: configure the DTB output. + +00: DTB bus is all 0 + +01: output the ADC_BUSY, ADC_EOC, offset compensation data[11:0] on the ADC_DTB + +10: output the DS information on the ADC_DTB + +11: select states of the FSM and enable ADC serial output + +Note: detailed DTB configurations are available in the Table 38 in IUM + 8 + 2 + read-write + + + DTB_SER_SEL + DTB_SER_SEL: DTB serial output selection when ADC_DB_CONF[1:0]=3d + +0: pre down-sampler with offset compensation data + +1: post down-sampler data + 10 + 1 + read-write + + + FSM_STATE + FSM_STATE[7:0]: show the state of the state machine. + +Bit 0: IDLE + +Bit 1: Reserved + +Bit 2: ADC setup phase + +Bit 3: Reserved + +Bit 4: ADC_START_CONV resynchronization + +Bit 5: Reserved + +Bit 6: ADC mode + +Bit 7: sequence mode + 16 + 8 + read-only + + + FSM_CUR_STATE + FSM_CUR_STATE[2:0]: show the last executed state by the state machine. + +000: IDLE mode + +001: Reserved + +010: ADC setup phase + +011: Reserved + +100: ADC_START_CONV resynchronization + +101: Reserved + +110: ADC mode + +111: sequence mode + 24 + 3 + read-only + + + + + + + AES + AES + 0x48900000 + + 0x0 + 0x60 + registers + + + AES + AES interrupt + 13 + + + + AES_CR + AES_CR + AES_CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + EN + EN: AES IP enable + + 0 + 1 + read-write + + + DATATYPE + DATATYPE[1:0]: Data type selection + + 1 + 2 + read-write + + + MODE + MODE[1:0]: AES operating mode + + 3 + 2 + read-write + + + CHMOD_1_0 + CHMOD[1:0]: AES Chaining Mode selection + + 5 + 2 + read-write + + + CCFC + CCFC: Computation Complete Flag Clear + + 7 + 1 + read-write + + + ERRC + ERRC: Error clear + + 8 + 1 + read-write + + + CCFIE + CCFIE: CCF Flag Interrupt Enable + + 9 + 1 + read-write + + + ERRIE + ERRIE: Error Interrupt Enable + + 10 + 1 + read-write + + + DMAINEN + DMAINEN: DMA Input Enable + + 11 + 1 + read-write + + + DMAOUTEN + DMAOUTEN: DMA Output Enable + + 12 + 1 + read-write + + + GCMPH + GCMPH[1:0]: GCM or CCM Phase selection + + 13 + 2 + read-write + + + CHMOD_2 + CHMOD[2]: Chaining mode selection, bit [2] + + 16 + 1 + read-write + + + KEYSIZE + KEYSIZE: Key Size selection. + 18 + 1 + read-write + + + NPBLB + NPBLB: Number of Padding Bytes in Last Block of payload. + 20 + 4 + read-write + + + + + AES_SR + AES_SR + AES_SR register + 0x04 + 0x20 + read-only + 0x00000000 + + + CCF + CCF: Computation complete flag + + 0 + 1 + read-only + + + RDERR + RDERR: Read error flag + + 1 + 1 + read-only + + + WRERR + WRERR: Write error flag + + 2 + 1 + read-only + + + BUSY + BUSY: Busy flag + + 3 + 1 + read-only + + + + + AES_DINR + AES_DINR + AES_DINR register + 0x08 + 0x20 + read-write + 0x00000000 + + + DINR + DINR[x+31:x]: One of four 32-bit words of a 128-bit input data block being written into the peripheral + + 0 + 32 + read-write + + + + + AES_DOUTR + AES_DOUTR + AES_DOUTR register + 0x0C + 0x20 + read-only + 0x00000000 + + + DOUTR + DOUTR[x+31:x]: One of four 32-bit words of a 128-bit output data block being read from the + + 0 + 32 + read-only + + + + + AES_KEYR0 + AES_KEYR0 + AES_KEYRx register + 0x10 + 0x20 + read-write + 0x00000000 + + + KEY + KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)] + + 0 + 32 + read-write + + + + + AES_KEYR1 + AES_KEYR1 + AES_KEYRx register + 0x14 + 0x20 + read-write + 0x00000000 + + + KEY + KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)] + + 0 + 32 + read-write + + + + + AES_KEYR2 + AES_KEYR2 + AES_KEYRx register + 0x18 + 0x20 + read-write + 0x00000000 + + + KEY + KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)] + + 0 + 32 + read-write + + + + + AES_KEYR3 + AES_KEYR3 + AES_KEYRx register + 0x1C + 0x20 + read-write + 0x00000000 + + + KEY + KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)] + + 0 + 32 + read-write + + + + + AES_IVR0 + AES_IVR0 + AES_IVRx register + 0x20 + 0x20 + read-write + 0x00000000 + + + IVI + IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]) + + 0 + 32 + read-write + + + + + AES_IVR1 + AES_IVR1 + AES_IVRx register + 0x24 + 0x20 + read-write + 0x00000000 + + + IVI + IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]) + + 0 + 32 + read-write + + + + + AES_IVR2 + AES_IVR2 + AES_IVRx register + 0x28 + 0x20 + read-write + 0x00000000 + + + IVI + IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]) + + 0 + 32 + read-write + + + + + AES_IVR3 + AES_IVR3 + AES_IVRx register + 0x2C + 0x20 + read-write + 0x00000000 + + + IVI + IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]) + + 0 + 32 + read-write + + + + + + + CRC + CRC + 0x48200000 + + 0x0 + 0x18 + registers + + + + CRC_DR + CRC_DR + CRC_DR register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits. +This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. +If the data size is less than 32 bits, the least significant bits are used to write/read the +correct value. + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC_IDR register + 0x04 + 0x20 + read-write + 0x00000000 + + + IDR + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC_CR register + 0x08 + 0x20 + read-write + 0x00000000 + + + RESET + RESET bit +This bit is set by software to reset the CRC calculation unit and set the data register to the value +stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware + 0 + 1 + read-write + + + POLYSIZE + Polynomial size +These bits control the size of the polynomial. +-00: 32 bit polynomial +-01: 16 bit polynomial +-10: 8 bit polynomial +-11: 7 bit polynomial + 3 + 2 + read-write + + + REV_IN + Reverse input data +These bits control the reversal of the bit order of the input data +-00: Bit order not affected +-01: Bit reversal done by byte +-10: Bit reversal done by half-word +-11: Bit reversal done by word + 5 + 2 + read-write + + + REV_OUT + Reverse output data +This bit controls the reversal of the bit order of the output data. +-0: Bit order not affected +-1: Bit-reversed output format + 7 + 1 + read-write + + + + + CRC_INIT + CRC_INIT + CRC_INIT register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + INIT + Programmable initial CRC value +This register is used to write the CRC initial value. + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC_POL register + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + POL + POL[31:0]: Programmable polynomial +This register is used to write the coefficients of the polynomial to be used for CRC calculation. +If the polynomial size is less than 32 bits, the least significant bits have to be used to program the +correct value. + 0 + 32 + read-write + + + + + + + DBGMCU + DBGMCU + 0x40008000 + + 0x0 + 0xC + registers + + + + CR + CR + CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + DBG_SLEEP + Allow debug of the CPU in SLEEP mode +- 0: Normal operation. All clocks will be disabled automatically in SLEEP mode +- 1: Automatic clock stop disabled. All active CPU clocks and oscillators will continue to run during SLEEP mode, allowing full CPU debug capability. On exit from SLEEP mode, the clock settings will be set to the SLEEP mode exit state. + 0 + 1 + read-write + + + DBG_STOP + Allow debug of the CPU in DEEPSTOP mode +- 0: Normal operation. All clocks will be disabled automatically in STOP mode +- 1: Automatic clock stop disabled. All active CPU clocks and oscillators will continue to run during STOP mode, allowing full CPU debug capability. On exit from STOP mode, the clock settings will be set to the STOP mode exit state. + 1 + 1 + read-write + + + + + DBG_APB0_FZ + DBG_APB0_FZ + DBG_APB0_FZ register + 0x04 + 0x20 + read-write + 0x00000000 + + + DBG_TIM2_STOP + TIM2 stop in the CPU debug +- 0: Normal operation. TIM2 continues to operate while the CPU is in debug mode +- 1: Stop in debug. TIM2 is frozen while the CPU is in debug mode. + 0 + 1 + read-write + + + DBG_TIM16_STOP + TIM16 stop in the CPU debug +- 0: Normal operation. TIM16 continues to operate while the CPU is in debug mode +- 1: Stop in debug. TIM16 is frozen while the CPU is in debug mode. + 1 + 1 + read-write + + + DBG_RTC_STOP + RTC stop in CPU debug +- 0: Normal operation. RTC continues to operate while the CPU is in debug mode +- 1: Stop in debug. RTC is frozen while the CPU is in debug mode. + 12 + 1 + read-write + + + DBG_IWDG_STOP + IWDG stop in the CPU debug +- 0: Normal operation. IWDG continues to operate while the CPU is in debug mode +- 1: Stop in debug. IWDG is frozen while the CPU is in debug mode. + 14 + 1 + read-write + + + + + DBG_APB1_FZ + DBG_APB1_FZ + DBG_APB1_FZ register + 0x08 + 0x20 + read-write + 0x00000000 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout stop in CPU debug +- 0: Normal operation. I2C1 SMBUS timeout continues to operate while the CPU is in debug mode +- 1: Stop in debug. I2C1 SMBUS timeou is frozen while the CPU is in debug mode. + 21 + 1 + read-write + + + DBG_I2C2_STOP + I2C2 SMBUS timeout stop in CPU debug +- 0: Normal operation. I2C2 SMBUS timeout continues to operate while the CPU is in debug mode +- 1: Stop in debug. I2C2 SMBUS timeou is frozen while the CPU is in debug mode. + 23 + 1 + read-write + + + + + + + DMAMUX + DMAMUX address block description + DMAMUX + 0x48800000 + + 0x0 + 0x20 + registers + + + + C0CR + C0CR + CxCR register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C1CR + C1CR + CxCR register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C2CR + C2CR + CxCR register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C3CR + C3CR + CxCR register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C4CR + C4CR + CxCR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C5CR + C5CR + CxCR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C6CR + C6CR + CxCR register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C7CR + C7CR + CxCR register + 0x1C + 0x20 + read-write + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + + + DMA + DMA address block description + DMA + 0x48700000 + + 0x0 + 0xA4 + registers + + + DMA + DMA interrupt + 17 + + + + DMA_ISR + DMA_ISR + DMA_ISR register + 0x00 + 0x20 + read-only + 0x0000 + 0xFFFF + + + GIF1 + GIF1: Channel 1 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 1 + +1: A TE, HT or TC event occurred on channel 1 + 0 + 1 + read-only + + + TCIF1 + TCIF1: Channel 1 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 1 + +1: A transfer complete (TC) event occurred on channel 1 + 1 + 1 + read-only + + + HTIF1 + HTIF1: Channel 1 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 1 + +1: A half transfer (HT) event occurred on channel 1 + 2 + 1 + read-only + + + TE1F1 + TEIF1: Channel 1 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 1 + +1: A transfer error (TE) occurred on channel 1 + 3 + 1 + read-only + + + GIF2 + GIF2: Channel 2 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 2 + +1: A TE, HT or TC event occurred on channel 2 + 4 + 1 + read-only + + + TCIF2 + TCIF2: Channel 2 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 2 + +1: A transfer complete (TC) event occurred on channel 2 + 5 + 1 + read-only + + + HTIF2 + HTIF2: Channel 2 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 2 + +1: A half transfer (HT) event occurred on channel 2 + 6 + 1 + read-only + + + TE1F2 + TEIF2: Channel 2 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 2 + +1: A transfer error (TE) occurred on channel 2 + 7 + 1 + read-only + + + GIF3 + GIF3: Channel 3 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 3 + +1: A TE, HT or TC event occurred on channel 3 + 8 + 1 + read-only + + + TCIF3 + TCIF3: Channel 3 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 3 + +1: A transfer complete (TC) event occurred on channel 3 + 9 + 1 + read-only + + + HTIF3 + HTIF3: Channel 3 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 3 + +1: A half transfer (HT) event occurred on channel 3 + 10 + 1 + read-only + + + TE1F3 + TEIF3: Channel 3 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 3 + +1: A transfer error (TE) occurred on channel 3 + 11 + 1 + read-only + + + GIF4 + GIF4: Channel 4 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 4 + +1: A TE, HT or TC event occurred on channel 4 + 12 + 1 + read-only + + + TCIF4 + TCIF4: Channel 4 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 4 + +1: A transfer complete (TC) event occurred on channel 4 + 13 + 1 + read-only + + + HTIF4 + HTIF4: Channel 4 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 4 + +1: A half transfer (HT) event occurred on channel 4 + 14 + 1 + read-only + + + TE1F4 + TEIF4: Channel 4 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 4 + +1: A transfer error (TE) occurred on channel 4 + 15 + 1 + read-only + + + GIF5 + GIF5: Channel 5 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 5 + +1: A TE, HT or TC event occurred on channel 5 + 16 + 1 + read-only + + + TCIF5 + TCIF5: Channel 5 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 5 + +1: A transfer complete (TC) event occurred on channel 5 + 17 + 1 + read-only + + + HTIF5 + HTIF5: Channel 5 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 5 + +1: A half transfer (HT) event occurred on channel 5 + 18 + 1 + read-only + + + TE1F5 + TEIF5: Channel 5 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 5 + +1: A transfer error (TE) occurred on channel 5 + 19 + 1 + read-only + + + GIF6 + GIF6: Channel 6 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 6 + +1: A TE, HT or TC event occurred on channel 6 + 20 + 1 + read-only + + + TCIF6 + TCIF6: Channel 6 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 6 + +1: A transfer complete (TC) event occurred on channel 6 + 21 + 1 + read-only + + + HTIF6 + HTIF6: Channel 6 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 6 + +1: A half transfer (HT) event occurred on channel 6 + 22 + 1 + read-only + + + TE1F6 + TEIF6: Channel 6 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 6 + +1: A transfer error (TE) occurred on channel 6 + 23 + 1 + read-only + + + GIF7 + GIF7: Channel 7 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 7 + +1: A TE, HT or TC event occurred on channel 7 + 24 + 1 + read-only + + + TCIF7 + TCIF7: Channel 7 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 7 + +1: A transfer complete (TC) event occurred on channel 7 + 25 + 1 + read-only + + + HTIF7 + HTIF7: Channel 7 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 7 + +1: A half transfer (HT) event occurred on channel 7 + 26 + 1 + read-only + + + TE1F7 + TEIF7: Channel 7 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 7 + +1: A transfer error (TE) occurred on channel 7 + 27 + 1 + read-only + + + GIF8 + GIF8: Channel 8 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 8 + +1: A TE, HT or TC event occurred on channel 8 + 28 + 1 + read-only + + + TCIF8 + TCIF8: Channel 8 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 8 + +1: A transfer complete (TC) event occurred on channel 8 + 29 + 1 + read-only + + + HTIF8 + HTIF8: Channel 8 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 8 + +1: A half transfer (HT) event occurred on channel 8 + 30 + 1 + read-only + + + TE1F8 + TEIF8: Channel 8 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 8 + +1: A transfer error (TE) occurred on channel 8 + 31 + 1 + read-only + + + + + DMA_IFCR + DMA_IFCR + DMA_IFCR register + 0x04 + 0x20 + write-only + 0x0000 + 0xFFFF + + + CGIF1 + CGIF1: Channel 1 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 0 + 1 + write-only + + + CTCIF1 + CTCIF1: Channel 1 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 1 + 1 + write-only + + + CHTIF1 + CHTIF1: Channel 1 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 2 + 1 + write-only + + + CTEIF1 + CTEIF1: Channel 1 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 3 + 1 + write-only + + + CGIF2 + CGIF2: Channel 2 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 4 + 1 + write-only + + + CTCIF2 + CTCIF2: Channel 2 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 5 + 1 + write-only + + + CHTIF2 + CHTIF2: Channel 2 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 6 + 1 + write-only + + + CTEIF2 + CTEIF2: Channel 2 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 7 + 1 + write-only + + + CGIF3 + CGIF3: Channel 3 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 8 + 1 + write-only + + + CTCIF3 + CTCIF3: Channel 3 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 9 + 1 + write-only + + + CHTIF3 + CHTIF3: Channel 3 half transfer clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 10 + 1 + write-only + + + CTEIF3 + CTEIF3: Channel 3 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 11 + 1 + write-only + + + CGIF4 + CGIF4: Channel 4 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 12 + 1 + write-only + + + CTCIF4 + CTCIF4: Channel 4 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 13 + 1 + write-only + + + CHTIF4 + CHTIF4: Channel 4 half transfer clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 14 + 1 + write-only + + + CTEIF4 + CTEIF4: Channel 4 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 15 + 1 + write-only + + + CGIF5 + CGIF5: Channel 5 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 16 + 1 + write-only + + + CTCIF5 + CTCIF5: Channel 5 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 17 + 1 + write-only + + + CHTIF5 + CHTIF5: Channel 5 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 18 + 1 + write-only + + + CTEIF5 + CTEIF5: Channel 5 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 19 + 1 + write-only + + + CGIF6 + CGIF6: Channel 6 global interrupt clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 20 + 1 + write-only + + + CTCIF6 + CTCIF6: Channel 6 transfer complete clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 21 + 1 + write-only + + + CHTIF6 + CHTIF6: Channel 6 half transfer clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 22 + 1 + write-only + + + CTEIF6 + CTEIF6: Channel 6 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 23 + 1 + write-only + + + CGIF7 + CGIF7: Channel 7 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 24 + 1 + write-only + + + CTCIF7 + CTCIF7: Channel 7 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 25 + 1 + write-only + + + CHTIF7 + CHTIF7: Channel 7 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 26 + 1 + write-only + + + CTEIF7 + CTEIF7: Channel 7 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 27 + 1 + write-only + + + CGIF8 + CGIF8: Channel 8 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 28 + 1 + write-only + + + CTCIF8 + CTCIF8: Channel 8 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 29 + 1 + write-only + + + CHTIF8 + CHTIF8: Channel 8 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 30 + 1 + write-only + + + CTEIF8 + CTEIF8: Channel 8 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 31 + 1 + write-only + + + + + DMA_CCR1 + DMA_CCR1 + DMA_CCRx register + 0x08 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR1 + DMA_CNDTR1 + DMA_CNDTRx register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR1 + DMA_CPAR1 + DMA_CPARx register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR1 + DMA_CMAR1 + DMA_CMARx register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR2 + DMA_CCR2 + DMA_CCRx register + 0x1C + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR2 + DMA_CNDTR2 + DMA_CNDTRx register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR2 + DMA_CPAR2 + DMA_CPARx register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR2 + DMA_CMAR2 + DMA_CMARx register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR3 + DMA_CCR3 + DMA_CCRx register + 0x30 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR3 + DMA_CNDTR3 + DMA_CNDTRx register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR3 + DMA_CPAR3 + DMA_CPARx register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR3 + DMA_CMAR3 + DMA_CMARx register + 0x3C + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR4 + DMA_CCR4 + DMA_CCRx register + 0x44 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR4 + DMA_CNDTR4 + DMA_CNDTRx register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR4 + DMA_CPAR4 + DMA_CPARx register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR4 + DMA_CMAR4 + DMA_CMARx register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR5 + DMA_CCR5 + DMA_CCRx register + 0x58 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR5 + DMA_CNDTR5 + DMA_CNDTRx register + 0x5C + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR5 + DMA_CPAR5 + DMA_CPARx register + 0x60 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR5 + DMA_CMAR5 + DMA_CMARx register + 0x64 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR6 + DMA_CCR6 + DMA_CCRx register + 0x6C + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR6 + DMA_CNDTR6 + DMA_CNDTRx register + 0x70 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR6 + DMA_CPAR6 + DMA_CPARx register + 0x74 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR6 + DMA_CMAR6 + DMA_CMARx register + 0x78 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR7 + DMA_CCR7 + DMA_CCRx register + 0x80 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR7 + DMA_CNDTR7 + DMA_CNDTRx register + 0x84 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR7 + DMA_CPAR7 + DMA_CPARx register + 0x88 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR7 + DMA_CMAR7 + DMA_CMARx register + 0x8C + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR8 + DMA_CCR8 + DMA_CCRx register + 0x94 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR8 + DMA_CNDTR8 + DMA_CNDTRx register + 0x98 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR8 + DMA_CPAR8 + DMA_CPARx register + 0x9C + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR8 + DMA_CMAR8 + DMA_CMARx register + 0xA0 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + + + DYNAMIC_REG + DYNAMIC_REG + 0x49000500 + + 0x0 + 0x40 + registers + + + + PCKTLEN_CONFIG + PCKTLEN_CONFIG + PCKTLEN_CONFIG register + 0x0 + 0x20 + read-write + 0x00000014 + + + PCKTLEN + This bit field has different meanings/usages: + + 0 + 16 + read-write + + + + + MOD0_CONFIG + MOD0_CONFIG + MOD0_CONFIG register + 0x4 + 0x20 + read-write + 0x00083A93 + + + DATARATE_M + The mantissa of the specified data rate (default: 38. + 0 + 16 + read-write + + + DATARATE_E + The exponent of the specified data rate (default: 38. + 16 + 4 + read-write + + + MOD_TYPE + Select the modulation type + + 20 + 3 + read-write + + + CONST_MAP + Also known as FOUR_GFSK_CONST_MAP + + 24 + 2 + read-write + + + BT_SEL + Select BT value for GFSK + + 26 + 1 + read-write + + + PA_CLKON_LOCKONTX + Enable the clock on analog PA in LOCKONTX state + + 31 + 1 + read-write + + + + + MOD1_CONFIG + MOD1_CONFIG + MOD1_CONFIG register + 0x8 + 0x20 + read-write + 0x00400435 + + + FDEV_M + Mantissa of the frequency deviation (default: 28. + 0 + 8 + read-write + + + FDEV_E + Exponent of the frequency deviation (default: 28. + 8 + 4 + read-write + + + CHFLT_M + Mantissa of the channel filter BW (default: 100 kHz) + 16 + 4 + read-write + + + CHFLT_E + Exponent of the channel filter BW (default: 100 kHz) + 20 + 4 + read-write + + + + + SNYTH_FREQ + SNYTH_FREQ + SNYTH_FREQ register + 0xc + 0x20 + read-write + 0x04851615 + + + SYNTH_FRAC + Fractional part of the PLL fractional divide factor (default: 868 MHz, XTAL: 48 MHz) + 0 + 20 + read-write + + + SYNTH_INT + PLL integer divide factor (default: 868 MHz, XTAL: 48 MHz) + 20 + 8 + read-write + + + BS + Synthesizer band selector, i. + 30 + 1 + read-write + + + + + VCO_CAL_CONFIG + VCO_CAL_CONFIG + VCO_CAL_CONFIG register + 0x10 + 0x20 + read-write + 0x00400088 + + + VCO_CALAMP_EXT + VCO magnitude calibration word in thermometric code + + 0 + 14 + read-write + + + VCO_CALAMP_EXT_SEL + Select the mode to provide an external VCO amplitude calibration value through VCO_CALAMP_EXT bit field + + 15 + 1 + read-write + + + VCO_CALFREQ_EXT + VCO Cbank frequency calibration word. + 16 + 7 + read-write + + + VCO_CALFREQ_EXT_SEL + Select the mode to provide an external VCO frequency calibration value through VCO_CALFREQ_EXT bit field + + 23 + 1 + read-write + + + VCO_CALIB_REQ + Define if the Radio FSM must launch a VCO calibration request after VCO start-up + + 31 + 1 + read-write + + + + + RX_TIMER + RX_TIMER + RX_TIMER register + 0x14 + 0x20 + read-write + 0x00000000 + + + RX_TIMEOUT + RX timer timeout (relative duration in interpolated absolute time unit) + 0 + 23 + read-write + + + RX_CS_TIMEOUT_MASK + - 0: CS flag does not contribute to timeout disabling + + 28 + 1 + read-write + + + RX_PQI_TIMEOUT_MASK + - 0: PREAMBLE valid flag does not contribute to timeout disabling + + 29 + 1 + read-write + + + RX_SQI_TIMEOUT_MASK + - 0: SYNC valid flag does not contribute to timeout disabling + + 30 + 1 + read-write + + + RX_OR_nAND_SELECT + Select logical OR or logcial AND to apply on CS/PQI/SQI timeout mask + + 31 + 1 + read-write + + + + + DATABUFFER_THR + DATABUFFER_THR + DATABUFFER_THR register + 0x18 + 0x20 + read-write + 0x00000000 + + + RX_ALMOST_FULL_THR + Almost Full threshold for RX Data Buffers + + 0 + 16 + read-write + + + TX_ALMOST_EMPTY_THR + Almost Empty threshold for TX Data Buffers. + 16 + 16 + read-write + + + + + RFSEQ_IRQ_ENABLE + RFSEQ_IRQ_ENABLE + RFSEQ_IRQ_ENABLE register + 0x1c + 0x20 + read-write + 0x00000000 + + + TX_DONE_E + Enable interrupt on TX_DONE_F flag + 0 + 1 + read-write + + + RX_OK_E + Enable interrupt on RX_OK_F flag + 1 + 1 + read-write + + + RX_TIMEOUT_E + Enable interrupt on RX_TIMEOUT_F flag + 2 + 1 + read-write + + + RX_CRC_ERROR_E + Enable interrupt on RX_CRC_ERROR_F flag + 3 + 1 + read-write + + + FAST_RX_TERM_E + Enable interrupt on FAST_RX_TERM_F flag + 4 + 1 + read-write + + + RXTIMER_STOP_CDT_E + Enable interrupt on RXTIMER_STOP_CDT_F flag + 7 + 1 + read-write + + + SABORT_DONE_E + Enable interrupt on SABORT command treated and done flag + 8 + 1 + read-write + + + COMMAND_REJECTED_E + Enable interrupt on COMMAND_REJECTED flag + 9 + 1 + read-write + + + CS_E + Enable interrupt on CS_F flag + 12 + 1 + read-write + + + PREAMBLE_VALID_E + Enable interrupt on PREAMBLE_VALID_F flag + 13 + 1 + read-write + + + SYNC_VALID_E + Enable interrupt on SYNC_VALID_F flag + 14 + 1 + read-write + + + DATABUFFER0_USED_E + Enable interrupt on DATABUFFER0_USED_F flag + 16 + 1 + read-write + + + DATABUFFER1_USED_E + Enable interrupt on DATABUFFER1_USED_F flag + 17 + 1 + read-write + + + RX_ALMOST_FULL_0_E + Enable interrupt on RX_ALMOST_FULL_0_F flag + 18 + 1 + read-write + + + RX_ALMOST_FULL_1_E + Enable interrupt on RX_ALMOST_FULL_1_F flag + 19 + 1 + read-write + + + TX_ALMOST_EMPTY_0_E + Enable interrupt on TX_ALMOST_EMPTY_0_F flag + 20 + 1 + read-write + + + TX_ALMOST_EMPTY_1_E + Enable interrupt on TX_ALMOST_EMPTY_1_F flag + 21 + 1 + read-write + + + AHB_ACCESS_ERROR_E + Enable interrupt on AHB_ACCESS_ERROR_F flag + 22 + 1 + read-write + + + HW_ANA_FAILURE_E + Enable interrupt on HW_ANA_FAILURE_F flag + 24 + 1 + read-write + + + SEQ_E + Enable interrupt on SEQ_F flag + 26 + 1 + read-write + + + RRM_CMD_START_E + Enable interrupt on RRM_CMD_END_F flag + 27 + 1 + read-write + + + RRM_CMD_END_E + Enable interrupt on RRM_CMD_END_F flag + 28 + 1 + read-write + + + SAFEASK_CALIB_DONE_E + Enable interrupt on SAFEASK_CALIB_DONE_F flag + 30 + 1 + read-write + + + AGC_CALIB_DONE_E + Enable interrupt on AGC_CALIB_DONE_F flag + 31 + 1 + read-write + + + + + ADDITIONAL_CTRL + ADDITIONAL_CTRL + ADDITIONAL_CTRL register + 0x20 + 0x20 + read-write + 0x00038800 + + + CH_NUM + Channel number. + 0 + 8 + read-write + + + CH_SPACING + Channel spacing. + 8 + 8 + read-only + + + PA_FC + Power control bandwidth selection according data rate + + 16 + 2 + read-write + + + TIME_CAPTURESEL + Select the trigger event to capture the interpolated absolute time in the TIME_CAPTURE[31:0] register + + 20 + 3 + read-write + + + AS_ENABLE + Enable the antenna switching feature. + 31 + 1 + read-write + + + + + FAST_RX_TIMER + FAST_RX_TIMER + FAST_RX_TIMER register + 0x24 + 0x20 + read-write + 0x00000000 + + + FAST_RX_TIMEOUT + Fast RX termination timer value (corresponding to the delay to measure the RSSI and to let the HW check CS flag information) + + 0 + 8 + read-write + + + FAST_CS_TERM_EN + Enable the Fast RX Termination feature + + 8 + 1 + read-write + + + + + COMMAND + COMMAND + COMMAND register + 0x28 + 0x20 + read-write + 0x00000000 + + + COMMAND_ID + Opcode coresponding to a command: + + 0 + 4 + read-write + + + BACK2ACTIVE + Select the default/return state for the Radio FSM to be ACTIVE2 + + 25 + 1 + read-write + + + BACK2LOCKON + Request to the Radio FSM to stay in LOCKON state when exiting a RX or a TX + + 26 + 1 + read-write + + + + + + + FLASH_CTRL + 4kb addressable space + FLASH_CTRL + 0x40001000 + + 0x0 + 0x200 + registers + + + Flash + Non-volatile memory (flash) +controller + 0 + + + + COMMAND + COMMAND + COMMAND register + 0x00 + 0x20 + read-write + 0x00000000 + + + COMMAND + Macro commands for flash operations (may require DATA0...DATA3 to be set): +- 0x11 : ERASE +- 0x22 : MASSERASE +- 0x33 : WRITE +- 0x55 : MASSREAD +- 0xAA : SLEEP +- 0xBB : WAKEUP +- 0xCC : BURSTWRITE +- 0xEE : OTPWRITE +- 0xFF : KEYWRITE + 0 + 8 + read-write + + + + + CONFIG + CONFIG + CONFIG register + 0x04 + 0x20 + read-write + 0x00000010 + + + REMAP + CPU access routing (it supersedes PREMAP configuration): +- 0 : FLASH memory addressed +- 1 : SRAM0 memory addressed + 1 + 1 + read-write + + + DIS_GROUP_WRITE + Burst write Control: +- 0 : burst write allowed +- 1 : burst write forbidden + 2 + 1 + read-write + + + WAIT_STATE + Add latency to flash read opeations: +- 00 : no latency +- 01 : 1 clock cycle latency +- 10 : 2 clock cycles latency +- 11 : 3 clock cycles latency + 4 + 2 + read-write + + + SLEEP_SM + Flash memory power-down mode enable in SLEEP mode +This bit allows to have the Flash memory in power-down mode or in idle mode when the +device is in Sleep mode. +- 0: When the device is in Sleep mode, the NVM is in Idle mode. +- 1: When the device is in Sleep mode, the NVM is in power-down mode. + 6 + 1 + read-write + + + + + IRQSTAT + IRQSTAT + IRQSTAT register + 0x08 + 0x20 + read-write + 0x00000000 + + + CMDDONE_MIS + (1: clear, 0: inactive) CMDDONE_MIS flag + 0 + 1 + read-write + + + CMDSTART_MIS + (1: clear, 0: inactive) CMDSTART_MIS flag + 1 + 1 + read-write + + + CMDBUSYERR_MIS + (1: clear, 0: inactive) CMDBUSYERR_MIS flag + 2 + 1 + read-write + + + ILLCMD_MIS + (1: clear, 0: inactive) ILLCMD_MIS flag + 3 + 1 + read-write + + + READOK_MIS + (1: clear, 0: inactive) READOK_MIS flag + 4 + 1 + read-write + + + FNREADY_MIS + (1: clear, 0: inactive) FNREADY_MIS flag + 5 + 1 + read-write + + + + + IRQMASK + IRQMASK + IRQMASK register + 0x0C + 0x20 + read-write + 0x0000003F + + + CMDDONEM + (1: mask, 0: inactive) CMDDONE_MIS mask + 0 + 1 + read-write + + + CMDSTARTM + (1: mask, 0: inactive) CMDSTART_MIS mask + 1 + 1 + read-write + + + CMDBUSYERRM + (1: mask, 0: inactive) CMDBUSYERR_MIS mask + 2 + 1 + read-write + + + ILLCMDM + (1: mask, 0: inactive) ILLCMD_MIS mask + 3 + 1 + read-write + + + READOKM + (1: mask, 0: inactive) READOK_MIS mask + 4 + 1 + read-write + + + FNREADYM + (1: mask, 0: inactive) FNREADY_MIS mask + 5 + 1 + read-write + + + + + IRQRAW + IRQRAW + IRQRAW register + 0x10 + 0x20 + read-write + 0x00000001 + + + CMDDONE_RIS + (1: active, 0: inactive) COMMAND sequence ended + 0 + 1 + read-write + + + CMDSTART_RIS + (1: active, 0: inactive) COMMAND sequence started + 1 + 1 + read-write + + + CMDBUSYERR_RIS + (1: active, 0: inactive) COMMAND issued while flash busy + 2 + 1 + read-write + + + ILLCMD_RIS + (1: active, 0: inactive) Illegal command issued + 3 + 1 + read-write + + + READOK_RIS + (1: active, 0: inactive) READ COMMAND completed successfully + 4 + 1 + read-write + + + CMDSLEEPERR_RIS + (1: active, 0: inactive) COMMAND issued while flash in sleep-mode (SLM=1) + 5 + 1 + read-write + + + + + SIZE + SIZE + SIZE register + 0x14 + 0x20 + read-only + 0x0000FFFF + + + FLASH_SIZE + Maximum valid address for flash memory: +- 00 : 0x03FFF (64kb) +- 01 : 0x07FFF (128kb) +- 10 : 0x0BFFF (192kb) +- 11 : 0x0FFFF (256kb) + 0 + 17 + read-only + + + RAM_SIZE + RAM memory size selection: +- 0 : 16kb +- 1 : 32kb + 17 + 1 + read-only + + + FLASH_SECURE + Flash memory protection (0: no key present, 1: key present) + 19 + 1 + read-only + + + JTAG_DISABLE + Flash+JTAG protection (0: no JTAG protection - see FLASH_SECURE, 1: Flash and JTAG protected) + 20 + 1 + read-only + + + PACKAGE_SIZE + Package selection: +- 0- : CSP +- 10 : 32pins +- 11 : 48pins + 21 + 2 + read-only + + + + + ADDRESS + ADDRESS + ADDRESS register + 0x18 + 0x20 + read-write + 0x00000000 + + + YADDR + Flash column address offset to be used with some COMMAND + 0 + 6 + read-write + + + XADDR + Flash row address offset to be used with some COMMAND + 6 + 10 + read-write + + + + + LFSRVAL + LFSRVAL + LFSRVAL register + 0x24 + 0x20 + read-only + 0xFFFFFFFF + + + LFSRVAL + Flash read data CRC signature + 0 + 32 + read-only + + + + + PAGEPROT0 + PAGEPROT0 + PAGEPROT0 register + 0x34 + 0x20 + read-write + 0x00000000 + + + SEGSIZE0 + First segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 0 + 7 + read-write + + + SEGOFFSET0 + First segment, 7-bit page protection offset (first page number in protected segment) + 8 + 7 + read-write + + + SEGSIZE1 + Second segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 16 + 7 + read-write + + + SEGOFFSET1 + Second segment, 7-bit page protection offset (first page number in protected segment) + 24 + 7 + read-write + + + + + PAGEPROT1 + PAGEPROT1 + PAGEPROT1 register + 0x38 + 0x20 + read-write + 0x00000000 + + + SEGSIZE2 + Third segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 0 + 7 + read-write + + + SEGOFFSET2 + Third segment, 7-bit page protection offset (first page number in protected segment) + 8 + 7 + read-write + + + SEGSIZE3 + Fourth segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 16 + 7 + read-write + + + SEGOFFSET3 + Fourth segment, 7-bit page protection offset (first page number in protected segment) + 24 + 7 + read-write + + + + + DATA0 + DATA0 + DATA0 register + 0x40 + 0x20 + read-write + 0xFFFFFFFF + + + DATA0 + Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD + 0 + 32 + read-write + + + + + DATA1 + DATA1 + DATA1 register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + DATA1 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA2 + DATA2 + DATA2 register + 0x48 + 0x20 + read-write + 0xFFFFFFFF + + + DATA2 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA3 + DATA3 + DATA3 register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + DATA3 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + UNLOCK012 + UNLOCK012 + UNLOCK012 register + 0x50 + 0x20 + read-write + 0xFFFFFFFF + + + UNLOCK012 + (NOT TO BE DOCUMENTED) Remove read-write protection from IFR0, IFR1, IFR2 sectors + 0 + 32 + read-write + + + + + UNLOCK3 + UNLOCK3 + UNLOCK3 register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + UNLOCK3 + (NOT TO BE DOCUMENTED) Remove read-write protection from IFR3 sector + 0 + 32 + read-write + + + + + + + GPIOA + GPIOA + 0x48000000 + + 0x0 + 0x2C + registers + + + GPIOA + GPIOA interrupt + 15 + + + + MODER + MODER + MODER register + 0x00 + 0x20 + read-write + 0x000000A0 + + + MODE0 + MODE0[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 0 + 2 + read-write + + + MODE1 + MODE1[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 2 + 2 + read-write + + + MODE2 + MODE2[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 4 + 2 + read-write + + + MODE3 + MODE3[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 6 + 2 + read-write + + + MODE4 + MODE4[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 8 + 2 + read-write + + + MODE5 + MODE5[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 10 + 2 + read-write + + + MODE6 + MODE6[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 12 + 2 + read-write + + + MODE7 + MODE7[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 14 + 2 + read-write + + + MODE8 + MODE8[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 16 + 2 + read-write + + + MODE9 + MODE9[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 18 + 2 + read-write + + + MODE10 + MODE10[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 20 + 2 + read-write + + + MODE11 + MODE11[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 22 + 2 + read-write + + + MODE12 + MODE12[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 24 + 2 + read-write + + + MODE13 + MODE13[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 26 + 2 + read-write + + + MODE14 + MODE14[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 28 + 2 + read-write + + + MODE15 + MODE15[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 30 + 2 + read-write + + + + + OTYPER + OTYPER + OTYPER register + 0x04 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 0 + 1 + read-write + + + OT1 + OT1: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 1 + 1 + read-write + + + OT2 + OT2: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 2 + 1 + read-write + + + OT3 + OT3: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 3 + 1 + read-write + + + OT4 + OT4: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 4 + 1 + read-write + + + OT5 + OT5: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 5 + 1 + read-write + + + OT6 + OT6: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 6 + 1 + read-write + + + OT7 + OT7: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 7 + 1 + read-write + + + OT8 + OT8: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 8 + 1 + read-write + + + OT9 + OT9: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 9 + 1 + read-write + + + OT10 + OT10: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 10 + 1 + read-write + + + OT11 + OT11: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 11 + 1 + read-write + + + OT12 + OT12: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 12 + 1 + read-write + + + OT13 + OT13: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 13 + 1 + read-write + + + OT14 + OT14: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 14 + 1 + read-write + + + OT15 + OT15: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 15 + 1 + read-write + + + + + OSPEEDR + OSPEEDR + OSPEEDR register + 0x08 + 0x20 + read-write + 0x00000030 + + + OSPEED0 + OSPEED0[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 0 + 2 + read-write + + + OSPEED1 + OSPEED1[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 2 + 2 + read-write + + + OSPEED2 + OSPEED2[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 4 + 2 + read-write + + + OSPEED3 + OSPEED3[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 6 + 2 + read-write + + + OSPEED4 + OSPEED4[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 8 + 2 + read-write + + + OSPEED5 + OSPEED5[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 10 + 2 + read-write + + + OSPEED6 + OSPEED6[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 12 + 2 + read-write + + + OSPEED7 + OSPEED7[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 14 + 2 + read-write + + + OSPEED8 + OSPEED8[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 16 + 2 + read-write + + + OSPEED9 + OSPEED9[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 18 + 2 + read-write + + + OSPEED10 + OSPEED10[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 20 + 2 + read-write + + + OSPEED11 + OSPEED11[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 22 + 2 + read-write + + + OSPEED12 + OSPEED12[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 24 + 2 + read-write + + + OSPEED13 + OSPEED13[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 26 + 2 + read-write + + + OSPEED14 + OSPEED14[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 28 + 2 + read-write + + + OSPEED15 + OSPEED15[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 30 + 2 + read-write + + + + + PUPDR + PUPDR + PUPDR register + 0x0C + 0x20 + read-write + 0x55555595 + + + PUPD0 + PUPD0: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 0 + 2 + read-write + + + PUPD1 + PUPD1: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 2 + 2 + read-write + + + PUPD2 + PUPD2: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 4 + 2 + read-write + + + PUPD3 + PUPD3: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 6 + 2 + read-write + + + PUPD4 + PUPD4: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 8 + 2 + read-write + + + PUPD5 + PUPD5: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 10 + 2 + read-write + + + PUPD6 + PUPD6: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 12 + 2 + read-write + + + PUPD7 + PUPD7: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 14 + 2 + read-write + + + PUPD8 + PUPD8: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 16 + 2 + read-write + + + PUPD9 + PUPD9: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 18 + 2 + read-write + + + PUPD10 + PUPD10: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 20 + 2 + read-write + + + PUPD11 + PUPD11: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 22 + 2 + read-write + + + PUPD12 + PUPD12: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 24 + 2 + read-write + + + PUPD13 + PUPD13: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 26 + 2 + read-write + + + PUPD14 + PUPD14: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 28 + 2 + read-write + + + PUPD15 + PUPD15: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 30 + 2 + read-write + + + + + IDR + IDR + IDR register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + ID0: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 0 + 1 + read-only + + + ID1 + ID1: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 1 + 1 + read-only + + + ID2 + ID2: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 2 + 1 + read-only + + + ID3 + ID3: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 3 + 1 + read-only + + + ID4 + ID4: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 4 + 1 + read-only + + + ID5 + ID5: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 5 + 1 + read-only + + + ID6 + ID6: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 6 + 1 + read-only + + + ID7 + ID7: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 7 + 1 + read-only + + + ID8 + ID8: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 8 + 1 + read-only + + + ID9 + ID9: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 9 + 1 + read-only + + + ID10 + ID10: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 10 + 1 + read-only + + + ID11 + ID11: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 11 + 1 + read-only + + + ID12 + ID12: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 12 + 1 + read-only + + + ID13 + ID13: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 13 + 1 + read-only + + + ID14 + ID14: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 14 + 1 + read-only + + + ID15 + ID15: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 15 + 1 + read-only + + + + + ODR + ODR + ODR register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + OD0: Port A output data bit +These bits can be read and written by software + 0 + 1 + read-write + + + OD1 + OD1: Port A output data bit +These bits can be read and written by software + 1 + 1 + read-write + + + OD2 + OD2: Port A output data bit +These bits can be read and written by software + 2 + 1 + read-write + + + OD3 + OD3: Port A output data bit +These bits can be read and written by software + 3 + 1 + read-write + + + OD4 + OD4: Port A output data bit +These bits can be read and written by software + 4 + 1 + read-write + + + OD5 + OD5: Port A output data bit +These bits can be read and written by software + 5 + 1 + read-write + + + OD6 + OD6: Port A output data bit +These bits can be read and written by software + 6 + 1 + read-write + + + OD7 + OD7: Port A output data bit +These bits can be read and written by software + 7 + 1 + read-write + + + OD8 + OD8: Port A output data bit +These bits can be read and written by software + 8 + 1 + read-write + + + OD9 + OD9: Port A output data bit +These bits can be read and written by software + 9 + 1 + read-write + + + OD10 + OD10: Port A output data bit +These bits can be read and written by software + 10 + 1 + read-write + + + OD11 + OD11: Port A output data bit +These bits can be read and written by software + 11 + 1 + read-write + + + OD12 + OD12: Port A output data bit +These bits can be read and written by software + 12 + 1 + read-write + + + OD13 + OD13: Port A output data bit +These bits can be read and written by software + 13 + 1 + read-write + + + OD14 + OD14: Port A output data bit +These bits can be read and written by software + 14 + 1 + read-write + + + OD15 + OD15: Port A output data bit +These bits can be read and written by software + 15 + 1 + read-write + + + + + BSRR + BSRR + BSRR register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +0: No action on the corresponding ODx bit +1: Sets the corresponding ODx bit + 0 + 1 + write-only + + + BS1 + BS1: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +0: No action on the corresponding ODx bit +1: Sets the corresponding ODx bit + 1 + 1 + write-only + + + BS2 + BS2: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +0: No action on the corresponding ODx bit +1: Sets the corresponding ODx bit + 2 + 1 + write-only + + + BS3 + BS3: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + BS4 + BS4: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + BS5 + BS5: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000 + 5 + 1 + write-only + + + BS6 + BS6: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + BS7 + BS7: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000 + 7 + 1 + write-only + + + BS8 + BS8: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + BS9 + BS9: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + BS10 + BS10: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + BS11 + BS11: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + BS12 + BS12: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + BS13 + BS13: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + BS14 + BS14: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + BS15 + BS15: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + BR0 + BR0: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + BR1 + BR1: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + BR2 + BR2: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + BR3 + BR3: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + BR4 + BR4: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + BR5 + BR5: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + BR6 + BR6: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + BR7 + BR7: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + BR8 + BR8: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + BR9 + BR9: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + BR10 + BR10: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + BR11 + BR11: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + BR12 + BR12: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + BR13 + BR13: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + BR14 + BR14: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + BR15 + BR15: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + + + LCKR + LCKR + LCKR register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0: Port A lock bit 0 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 0 + 1 + read-write + + + LCK1 + LCK1: Port A lock bit 1 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 1 + 1 + read-write + + + LCK2 + LCK2: Port A lock bit 2 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 2 + 1 + read-write + + + LCK3 + LCK3: Port A lock bit 3 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 3 + 1 + read-write + + + LCK4 + LCK4: Port A lock bit 4 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 4 + 1 + read-write + + + LCK5 + LCK5: Port A lock bit 5 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 5 + 1 + read-write + + + LCK6 + LCK6: Port A lock bit 6 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 6 + 1 + read-write + + + LCK7 + LCK7: Port A lock bit 7 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 7 + 1 + read-write + + + LCK8 + LCK8: Port A lock bit 8 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 8 + 1 + read-write + + + LCK9 + LCK9: Port A lock bit 9 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 9 + 1 + read-write + + + LCK10 + LCK10: Port A lock bit 10 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 10 + 1 + read-write + + + LCK11 + LCK11: Port A lock bit 11 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 11 + 1 + read-write + + + LCK12 + LCK12: Port A lock bit 12 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 12 + 1 + read-write + + + LCK13 + LCK13: Port A lock bit 13 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 13 + 1 + read-write + + + LCK14 + LCK14: Port A lock bit 14 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 14 + 1 + read-write + + + LCK15 + LCK15: Port A lock bit 15 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 15 + 1 + read-write + + + LCKK + LCKK: Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +-0: Port configuration lock key not active +-1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU +reset or peripheral reset. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Any error in the lock sequence aborts the lock. +After the first lock sequence on any bit of the port, any read access on the LCKK bit will +return 1 until the next MCU reset or peripheral reset + 16 + 1 + read-write + + + + + AFRL + AFRL + AFRL register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL1 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL2 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL3 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL4 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL5 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL6 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL7 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + AFRH + AFRH + AFRH register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL9 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL10 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL11 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL12 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL13 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL14 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL15 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + BRR + BRR + BRR register + 0x28 + 0x20 + read-write + 0x00000000 + + + BR0 + BR0: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 0 + 1 + write-only + + + BR1 + BR1: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 1 + 1 + write-only + + + BR2 + BR2: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 2 + 1 + write-only + + + BR3 + BR3: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 3 + 1 + write-only + + + BR4 + BR4: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 4 + 1 + write-only + + + BR5 + BR5: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 5 + 1 + write-only + + + BR6 + BR6: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 6 + 1 + write-only + + + BR7 + BR7: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 7 + 1 + write-only + + + BR8 + BR8: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 8 + 1 + write-only + + + BR9 + BR9: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 9 + 1 + write-only + + + BR10 + BR10: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 10 + 1 + write-only + + + BR11 + BR11: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 11 + 1 + write-only + + + BR12 + BR12: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 12 + 1 + write-only + + + BR13 + BR13: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 13 + 1 + write-only + + + BR14 + BR14: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 14 + 1 + write-only + + + BR15 + BR15: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 15 + 1 + write-only + + + + + + + GPIOB + GPIOB + 0x48100000 + + 0x0 + 0x2C + registers + + + GPIOB + GPIOB interrupt + 16 + + + + MODER + MODER + MODER register + 0x00 + 0x20 + read-write + 0x00000000 + + + MODE0 + MODE0[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 0 + 2 + read-write + + + MODE1 + MODE1[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 2 + 2 + read-write + + + MODE2 + MODE2[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 4 + 2 + read-write + + + MODE3 + MODE3[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 6 + 2 + read-write + + + MODE4 + MODE4[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 8 + 2 + read-write + + + MODE5 + MODE5[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 10 + 2 + read-write + + + MODE6 + MODE6[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 12 + 2 + read-write + + + MODE7 + MODE7[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 14 + 2 + read-write + + + MODE8 + MODE8[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 16 + 2 + read-write + + + MODE9 + MODE9[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 18 + 2 + read-write + + + MODE10 + MODE10[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 20 + 2 + read-write + + + MODE11 + MODE11[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 22 + 2 + read-write + + + MODE12 + MODE12[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 24 + 2 + read-write + + + MODE13 + MODE13[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 26 + 2 + read-write + + + MODE14 + MODE14[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 28 + 2 + read-write + + + MODE15 + MODE15[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 30 + 2 + read-write + + + + + OTYPER + OTYPER + OTYPER register + 0x04 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 0 + 1 + read-write + + + OT1 + OT1: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 1 + 1 + read-write + + + OT2 + OT2: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 2 + 1 + read-write + + + OT3 + OT3: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 3 + 1 + read-write + + + OT4 + OT4: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 4 + 1 + read-write + + + OT5 + OT5: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 5 + 1 + read-write + + + OT6 + OT6: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 6 + 1 + read-write + + + OT7 + OT7: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 7 + 1 + read-write + + + OT8 + OT8: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 8 + 1 + read-write + + + OT9 + OT9: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 9 + 1 + read-write + + + OT10 + OT10: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 10 + 1 + read-write + + + OT11 + OT11: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 11 + 1 + read-write + + + OT12 + OT12: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 12 + 1 + read-write + + + OT13 + OT13: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 13 + 1 + read-write + + + OT14 + OT14: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 14 + 1 + read-write + + + OT15 + OT15: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 15 + 1 + read-write + + + + + OSPEEDR + OSPEEDR + OSPEEDR register + 0x08 + 0x20 + read-write + 0x00000000 + + + OSPEED0 + OSPEED0[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 0 + 2 + read-write + + + OSPEED1 + OSPEED1[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 2 + 2 + read-write + + + OSPEED2 + OSPEED2[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 4 + 2 + read-write + + + OSPEED3 + OSPEED3[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 6 + 2 + read-write + + + OSPEED4 + OSPEED4[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 8 + 2 + read-write + + + OSPEED5 + OSPEED5[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 10 + 2 + read-write + + + OSPEED6 + OSPEED6[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 12 + 2 + read-write + + + OSPEED7 + OSPEED7[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 14 + 2 + read-write + + + OSPEED8 + OSPEED8[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 16 + 2 + read-write + + + OSPEED9 + OSPEED9[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 18 + 2 + read-write + + + OSPEED10 + OSPEED10[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 20 + 2 + read-write + + + OSPEED11 + OSPEED11[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 22 + 2 + read-write + + + OSPEED12 + OSPEED12[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 24 + 2 + read-write + + + OSPEED13 + OSPEED13[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 26 + 2 + read-write + + + OSPEED14 + OSPEED14[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 28 + 2 + read-write + + + OSPEED15 + OSPEED15[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 30 + 2 + read-write + + + + + PUPDR + PUPDR + PUPDR register + 0x0C + 0x20 + read-write + 0x55555555 + + + PUPD0 + PUPD0: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 0 + 2 + read-write + + + PUPD1 + PUPD1: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 2 + 2 + read-write + + + PUPD2 + PUPD2: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 4 + 2 + read-write + + + PUPD3 + PUPD3: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 6 + 2 + read-write + + + PUPD4 + PUPD4: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 8 + 2 + read-write + + + PUPD5 + PUPD5: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 10 + 2 + read-write + + + PUPD6 + PUPD6: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 12 + 2 + read-write + + + PUPD7 + PUPD7: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 14 + 2 + read-write + + + PUPD8 + PUPD8: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 16 + 2 + read-write + + + PUPD9 + PUPD9: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 18 + 2 + read-write + + + PUPD10 + PUPD10: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 20 + 2 + read-write + + + PUPD11 + PUPD11: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 22 + 2 + read-write + + + PUPD12 + PUPD12: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 24 + 2 + read-write + + + PUPD13 + PUPD13: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 26 + 2 + read-write + + + PUPD14 + PUPD14: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 28 + 2 + read-write + + + PUPD15 + PUPD15: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 30 + 2 + read-write + + + + + IDR + IDR + IDR register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + ID0: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 0 + 1 + read-only + + + ID1 + ID1: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 1 + 1 + read-only + + + ID2 + ID2: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 2 + 1 + read-only + + + ID3 + ID3: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 3 + 1 + read-only + + + ID4 + ID4: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 4 + 1 + read-only + + + ID5 + ID5: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 5 + 1 + read-only + + + ID6 + ID6: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 6 + 1 + read-only + + + ID7 + ID7: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 7 + 1 + read-only + + + ID8 + ID8: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 8 + 1 + read-only + + + ID9 + ID9: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 9 + 1 + read-only + + + ID10 + ID10: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 10 + 1 + read-only + + + ID11 + ID11: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 11 + 1 + read-only + + + ID12 + ID12: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 12 + 1 + read-only + + + ID13 + ID13: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 13 + 1 + read-only + + + ID14 + ID14: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 14 + 1 + read-only + + + ID15 + ID15: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 15 + 1 + read-only + + + + + ODR + ODR + ODR register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + OD0: Port B output data bit +These bits can be read and written by software + 0 + 1 + read-write + + + OD1 + OD1: Port B output data bit +These bits can be read and written by software + 1 + 1 + read-write + + + OD2 + OD2: Port B output data bit +These bits can be read and written by software + 2 + 1 + read-write + + + OD3 + OD3: Port B output data bit +These bits can be read and written by software + 3 + 1 + read-write + + + OD4 + OD4: Port B output data bit +These bits can be read and written by software + 4 + 1 + read-write + + + OD5 + OD5: Port B output data bit +These bits can be read and written by software + 5 + 1 + read-write + + + OD6 + OD6: Port B output data bit +These bits can be read and written by software + 6 + 1 + read-write + + + OD7 + OD7: Port B output data bit +These bits can be read and written by software + 7 + 1 + read-write + + + OD8 + OD8: Port B output data bit +These bits can be read and written by software + 8 + 1 + read-write + + + OD9 + OD9: Port B output data bit +These bits can be read and written by software + 9 + 1 + read-write + + + OD10 + OD10: Port B output data bit +These bits can be read and written by software + 10 + 1 + read-write + + + OD11 + OD11: Port B output data bit +These bits can be read and written by software + 11 + 1 + read-write + + + OD12 + OD12: Port B output data bit +These bits can be read and written by software + 12 + 1 + read-write + + + OD13 + OD13: Port B output data bit +These bits can be read and written by software + 13 + 1 + read-write + + + OD14 + OD14: Port B output data bit +These bits can be read and written by software + 14 + 1 + read-write + + + OD15 + OD15: Port B output data bit +These bits can be read and written by software + 15 + 1 + read-write + + + + + BSRR + BSRR + BSRR register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + BS1 + BS1: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + BS2 + BS2: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + BS3 + BS3: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + BS4 + BS4: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + BS5 + BS5: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + BS6 + BS6: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + BS7 + BS7: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + BS8 + BS8: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + BS9 + BS9: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + BS10 + BS10: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + BS11 + BS11: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + BS12 + BS12: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + BS13 + BS13: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + BS14 + BS14: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + BS15 + BS15: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + BR0 + BR0: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + BR1 + BR1: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + BR2 + BR2: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + BR3 + BR3: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + BR4 + BR4: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + BR5 + BR5: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + BR6 + BR6: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + BR7 + BR7: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + BR8 + BR8: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + BR9 + BR9: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + BR10 + BR10: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + BR11 + BR11: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + BR12 + BR12: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + BR13 + BR13: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + BR14 + BR14: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + BR15 + BR15: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + + + LCKR + LCKR + LCKR register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0: Port B lock bit 0 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 0 + 1 + read-write + + + LCK1 + LCK1: Port B lock bit 1 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 1 + 1 + read-write + + + LCK2 + LCK2: Port B lock bit 2 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 2 + 1 + read-write + + + LCK3 + LCK3: Port B lock bit 3 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 3 + 1 + read-write + + + LCK4 + LCK4: Port B lock bit 4 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 4 + 1 + read-write + + + LCK5 + LCK5: Port B lock bit 5 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 5 + 1 + read-write + + + LCK6 + LCK6: Port B lock bit 6 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 6 + 1 + read-write + + + LCK7 + LCK7: Port B lock bit 7 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 7 + 1 + read-write + + + LCK8 + LCK8: Port B lock bit 8 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 8 + 1 + read-write + + + LCK9 + LCK9: Port B lock bit 9 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 9 + 1 + read-write + + + LCK10 + LCK10: Port B lock bit 10 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 10 + 1 + read-write + + + LCK11 + LCK11: Port B lock bit 11 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 11 + 1 + read-write + + + LCK12 + LCK12: Port B lock bit 12 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 12 + 1 + read-write + + + LCK13 + LCK13: Port B lock bit 13 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 13 + 1 + read-write + + + LCK14 + LCK14: Port B lock bit 14 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 14 + 1 + read-write + + + LCK15 + LCK15: Port B lock bit 15 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 15 + 1 + read-write + + + LCKK + LCKK: Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +-0: Port configuration lock key not active +-1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU +reset or peripheral reset. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Any error in the lock sequence aborts the lock. +After the first lock sequence on any bit of the port, any read access on the LCKK bit will +return 1 until the next MCU reset or peripheral reset + 16 + 1 + read-write + + + + + AFRL + AFRL + AFRL register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL1 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL2 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL3 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL4 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL5 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL6 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL7 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + AFRH + AFRH + AFRH register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL9 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL10 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL11 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL12 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL13 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL14 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL15 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + BRR + BRR + BRR register + 0x28 + 0x20 + read-write + + + BR0 + BR0: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 0 + 1 + write-only + + + BR1 + BR1: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 1 + 1 + write-only + + + BR2 + BR2: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 2 + 1 + write-only + + + BR3 + BR3: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 3 + 1 + write-only + + + BR4 + BR4: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 4 + 1 + write-only + + + BR5 + BR5: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 5 + 1 + write-only + + + BR6 + BR6: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 6 + 1 + write-only + + + BR7 + BR7: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 7 + 1 + write-only + + + BR8 + BR8: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 8 + 1 + write-only + + + BR9 + BR9: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 9 + 1 + write-only + + + BR10 + BR10: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 10 + 1 + write-only + + + BR11 + BR11: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 11 + 1 + write-only + + + BR12 + BR12: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 12 + 1 + write-only + + + BR13 + BR13: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 13 + 1 + write-only + + + BR14 + BR14: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 14 + 1 + write-only + + + BR15 + BR15: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 15 + 1 + write-only + + + + + + + I2C1 + I2C1 + 0x41000000 + + 0x0 + 0x2C + registers + + + I2C1 + I2C1 interrupt + 3 + + + + I2C_CR1 + I2C_CR1 + I2C_CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable +- 0: Peripheral disable +- 1: Peripheral enable + 0 + 1 + read-write + + + TXIE + TX Interrupt enable +- 0: Transmit (TXIS) interrupt disabled +- 1: Transmit (TXIS) interrupt enabled + 1 + 1 + read-write + + + RXIE + RX Interrupt enable +- 0: Receive (RXNE) interrupt disabled +- 1: Receive (RXNE) interrupt enabled + 2 + 1 + read-write + + + ADDRIE + Address match Interrupt enable (slave only) +- 0: Address match (ADDR) interrupts disabled +- 1: Address match (ADDR) interrupts enabled + 3 + 1 + read-write + + + NACKIE + Not acknowledge received Interrupt enable +- 0: Not acknowledge (NACKF) received interrupts disabled +- 1: Not acknowledge (NACKF) received interrupts enabled + 4 + 1 + read-write + + + STOPIE + STOP detection Interrupt enable +- 0: Stop detection (STOPF) interrupt disabled +- 1: Stop detection (STOPF) interrupt enabled + 5 + 1 + read-write + + + TCIE + Transfer Complete interrupt enable +- 0: Transfer Complete interrupt disabled +- 1: Transfer Complete interrupt enabled + 6 + 1 + read-write + + + ERRIE + Error interrupts enable +- 0: Error detection interrupts disabled +- 1: Error detection interrupts enabled +Note: Any of these errors generate an interrupt: +Arbitration Loss (ARLO) +Bus Error detection (BERR) +Overrun/Underrun (OVR) +Timeout detection (TIMEOUT) +PEC error detection (PECERR) +Alert pin event detection (ALERT) + 7 + 1 + read-write + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter +will filter spikes with a length of up to DNF[3:0] * tI2CCLK +- 0000: Digital filter disabled +- 0001: Digital filter enabled and filtering capability up to 1 tI2CCLK +- 1111: digital filter enabled and filtering capability up to15 tI2CCLK + 8 + 4 + read-write + + + ANFOFF + Analog noise filter OFF +- 0: Analog noise filter enabled +- 1: Analog noise filter disabled + 12 + 1 + read-write + + + TXDMAEN + DMA transmission requests enable +- 0: DMA mode disabled for transmission +- 1: DMA mode enabled for transmission + 14 + 1 + read-write + + + RXDMAEN + DMA reception requests enable +- 0: DMA mode disabled for reception +- 1: DMA mode enabled for reception + 15 + 1 + read-only + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. +- 0: Slave byte control disabled +- 1: Slave byte control enabled + 16 + 1 + read-write + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +- 0: Clock stretching enabled +- 1: Clock stretching disabled +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + GCEN + General call enable + + 19 + 1 + read-write + + + B_0x0 + General call disabled. Address 0b00000000 is NACKed. + + 0x0 + + + B_0x1 + General call enabled. Address 0b00000000 is ACKed. + 0x1 + + + + + SMBHEN + SMBus Host address enable +- 0: Host address disabled. Address 0b0001000x is NACKed. +- 1: Host address enabled. Address 0b0001000x is ACKed. + 20 + 1 + read-write + + + SMBDEN + SMBus Device Default address enable +- 0: Device default address disabled. Address 0b1100001x is NACKed. +- 1: Device default address enabled. Address 0b1100001x is ACKed. + 21 + 1 + read-write + + + ALERTEN + SMBus alert enable +Device mode (SMBHEN=0): +- 0: Releases SMBA pin high and Alert Response Address Header disabled: 0001100x followed by NACK. +- 1: Drives SMBA pin low and Alert Response Address Header enables: 0001100x followed by ACK. +Host mode (SMBHEN=1): +- 0: SMBus Alert pin (SMBA) not supported. +- 1: SMBus Alert pin (SMBA) supported. + 22 + 1 + read-write + + + PECEN + PEC enable +- 0: PEC calculation disabled +- 1: PEC calculation enabled + 23 + 1 + read-write + + + + + I2C_CR2 + I2C_CR2 + I2C_CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + SADD + Slave address + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +- 0: Master requests a write transfer. +- 1: Master requests a read transfer. + 10 + 1 + read-write + + + ADD10 + Ten-bit addressing mode (master mode) +- 0: The master operates in 7-bit addressing mode, +- 1: The master operates in 10-bit addressing mode + 11 + 1 + read-write + + + HEAD10R + Ten bit (10-bit) address header only read direction (master receiver mode) +- 0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. +- 1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction. + 12 + 1 + read-write + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. +- 0: No Start generation. +- 1: Restart/Start generation: +If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. +Otherwise setting this bit will generate a START condition once the bus is free. + 13 + 1 + read-write + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. +In Master Mode: +- 0: No Stop generation. +- 1: Stop generation after current byte transfer. + 14 + 1 + read-write + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP +condition or an Address matched is received, or when PE=0. +- 0: an ACK is sent after current received byte. +- 1: a NACK is sent after current received byte. + 15 + 1 + read-write + + + NBYTES + Number of bytes +The number of bytes to be transmitted/received is programmed there. This field is dont care in +slave mode with SBC=0. + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. +- 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). +- 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). +TCR flag is set when NBYTES data are transferred, stretching SCL low. + 24 + 1 + read-write + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +- 0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. +- 1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are +transferred. + 25 + 1 + read-write + + + PECBYTE + Packet error checking byte +This bit is set by software, and cleared by hardware when the PEC is transferred, or when a +STOP condition or an Address matched is received, also when PE=0. +- 0: No PEC transfer. +- 1: PEC transmission/reception is requested + 26 + 1 + read-write + + + + + I2C_OAR1 + I2C_OAR1 + I2C_OAR1 register + 0x08 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + read-write + + + OA1MODE + Own Address 1 10-bit mode +- 0: Own address 1 is a 7-bit address. +- 1: Own address 1 is a 10-bit address. + 10 + 1 + read-write + + + OA1EN + Own Address 1 enable +- 0: Own address 1 disabled. The received slave address OA1 is NACKed. +- 1: Own address 1 enabled. The received slave address OA1 is ACKed. + 15 + 1 + read-write + + + + + I2C_OAR2 + I2C_OAR2 + I2C_OAR2 register + 0x0C + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address +bits 7:1 of address +Note: These bits can be written only when OA2EN=0. + 1 + 7 + read-write + + + OA2MSK + Own Address 2 masks +- 000: No mask +- 001: OA2[1] is masked and dont care. Only OA2[7:2] are compared. +- 010: OA2[2:1] are masked and dont care. Only OA2[7:3] are compared. +- 011: OA2[3:1] are masked and dont care. Only OA2[7:4] are compared. +- 100: OA2[4:1] are masked and dont care. Only OA2[7:5] are compared. +- 101: OA2[5:1] are masked and dont care. Only OA2[7:6] are compared. +- 110: OA2[6:1] are masked and dont care. Only OA2[7] is compared. +- 111: OA2[7:1] are masked and dont care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 8 + 3 + read-write + + + OA2EN + Own Address 2 enable + + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. The received slave address OA2 is NACKed. + + 0x0 + + + B_0x1 + Own address 2 enabled. The received slave address OA2 is ACKed. + 0x1 + + + + + + + I2C_TIMING + I2C_TIMING + I2C_TIMING register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +tSCLL = (SCLL+1) x tPRESC +Note: SCLL is also used to generate tBUF and tSU:STA timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +tSCLH = (SCLH+1) x tPRESC +Note: SCLH is also used to generate tSU:STO and tHD:STA timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay tSDADEL between SCL falling edge SDA edge in +transmission mode. +tSDADEL= SDADEL x tPRESC +Note: SDADEL is used to generate tHD:DAT timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge in +transmission mode. +tSCLDEL = (SCLDEL+1) x tPRESC +Note: tSCLDEL is used to generate tSU:DAT timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler +This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data +setup and hold counters and for SCL high and low level +counters +tPRESC = (PRESC+1) x tI2CCLK + 28 + 4 + read-write + + + + + I2C_TIMEOUT + I2C_TIMEOUT + I2C_TIMEOUT register + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus Timeout A +This field is used to configure: +The SCL low timeout condition tTIMEOUT when TIDLE=0 +tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK +The bus idle condition (both SCL and SDA high) when TIDLE=1 +tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK +Note: These bits can be written only when TIMOUTEN=0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +- 0: TIMEOUTA is used to detect SCL low timeout +- 1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) +Note: This bit can be written only when TIMOUTEN=0. + 12 + 1 + read-write + + + TIMEOUTEN + Clock timeout enable +- 0: SCL timeout detection is disabled +- 1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or +high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1). + 15 + 1 + read-write + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected +In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected +tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK +Note: These bits can be written only when TEXTEN=0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable +- 0: Extended clock timeout detection is disabled +- 1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more +than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1). + 31 + 1 + read-write + + + + + I2C_ISR + I2C_ISR + I2C_ISR register + 0x18 + 0x20 + read-write + 0x00000000 + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE=0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). +Note: This bit is cleared by hardware when PE=0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE=0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE=0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE=0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: +either as a master, provided that the STOP condition is generated by the peripheral. +or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE=0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE=0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE=0. +This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE=0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE=0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE=0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception +This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 11 + 1 + read-only + + + TIMEOUT + Timeout or tLOW detection flag +This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 12 + 1 + read-only + + + ALERT + SMBus alert +This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 13 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) +This flag is updated when an address match event occurs (ADDR=1). +- 0: Write transfer, slave enters receiver mode. +- 1: Read transfer, slave enters transmitter mode. + 16 + 1 + read-only + + + ADDCODE + Address match code (Slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C_ICR register + 0x1C + 0x20 + read-write + 0x00000000 + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears +the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the ACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + Stop detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration Lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + PECCF + PEC Error flag clear +Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear +Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 12 + 1 + write-only + + + ALERTCF + Alert flag clear +Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 13 + 1 + write-only + + + + + I2C_PEC + I2C_PEC + I2C_PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE=0. + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C_RXDR register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + Eight bit (8-bit) receive data +Data byte received from the I2C bus. + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C_TXDR register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + Eight bits (8-bit) transmit data +Data byte to be transmitted to the I2C bus. +Note: These bits can be written only when TXE=1. + 0 + 8 + read-write + + + + + + + IWDG + IWDG + 0x40003000 + + 0x0 + 0x14 + registers + + + + IWDG_KR + IWDG_KR + IWDG_KR register + 0x00 + 0x20 + read-write + 0x00000000 + + + KEY + Key value. +Software can only write these bits. Reading returns the reset value. +These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. +Writing the key value 0x5555 to enables access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers. +Writing the key value CCCCh starts the watchdog + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG_PR register + 0x04 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider. +Set and reset by software. +These bits are write access protected. They are written by software to select the prescaler divider feeding the counter clock. +PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. +000: divider/4 +001: divider/8 +010: divider/16 +011: divider/32 +100: divider/64 +101: divider/128 +110: divider/256 +111: divider/256 + 0 + 3 + read-write + + + + + IWDG_RLR + IWDG_RLR + IWDG_RLR register + 0x08 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value. +Set and reset by software. +These bits are write access protected. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. +The timeout period is a function of this value and the clock prescaler. +The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG_SR register + 0x0C + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value update. +Read only bit. +This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is +reset by hardware when the prescaler update operation is completed in the VDD voltage +domain (takes up to 5 RC 40 kHz cycles). +Prescaler value can be updated only when PVU bit is reset + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update. +Read only bit. +This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Reload value can be updated only when RVU bit is reset + 1 + 1 + read-only + + + WVU + Watchdog counter window value update. +Read only bit. +This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Window value can be updated only when WVU bit is reset. +This bit is generated only if generic 'window' = 1 + 2 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG_WINR register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value. +Set and reset by software. +These bits are write access protected. These bits contain the high limit of the window value to be compared to the downcounter. +To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 +The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + + + LPUART + LPUART + 0x41005000 + + 0x0 + 0x30 + registers + + + LPUART + LPUART interrupt + 9 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + UE + UE: USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and +current operations are discarded. The configuration of the USART is kept, but all the status +flags, in the USART_ISR are reset. This bit is set and cleared by software. +-0: USART prescaler and outputs disabled, low power mode +-1: USART enabled + 0 + 1 + read-write + + + UESM + UESM: LPUART enable in Stop mode +When this bit is cleared, the LPUART is not able to wake up the MCU from Stop mode. +When this bit is set, the LPUART is able to wake up the MCU from Stop mode, provided that +the LPUART clock selection is LSE in the RCC. +This bit is set and cleared by software. +-0: LPUART not able to wake up the MCU from Stop mode. +-1: LPUART able to wake up the MCU from Stop mode. When this function is active, the +clock source for the LPUART must be LSE (see RCC chapter) + 1 + 1 + read-write + + + RE + RE: Receiver enable +This bit enables the receiver. It is set and cleared by software. +-0: Receiver is disabled +-1: Receiver is enabled and begins searching for a start bit + 2 + 1 + read-write + + + TE + TE: Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +-0: Transmitter is disabled +-1: Transmitter is enabled + 3 + 1 + read-write + + + IDLEIE + IDLEIE: IDLE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register + 4 + 1 + read-write + + + RXNEIE_RXFNEIE + RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the +USART_ISR register + 5 + 1 + read-write + + + TCIE + TCIE: Transmission complete interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TC=1 in the USART_ISR register + 6 + 1 + read-write + + + TXEIE_TXFNFIE + TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register + 7 + 1 + read-write + + + PEIE + PEIE: PE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever PE=1 in the USART_ISR register + 8 + 1 + read-write + + + PS + PS: Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE +bit set). It is set and cleared by software. The parity will be selected after the current byte. +-0: Even parity +-1: Odd parity +This bit field can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + PCE + PCE: Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity +control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit +if M=0) and parity is checked on the received data. This bit is set and cleared by software. +Once it is set, PCE is active after the current byte (in reception and in transmission). +-0: Parity control disabled +-1: Parity control enabled +This bit field can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + WAKE + WAKE: Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by +software. +-0: Idle line +-1: Address mark +This bit field can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + M_0 + M0: Word length +This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit +-28 (M1)description. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + MME: Mute mode enable +This bit activates the mute mode function of the USART. When set, the USART can switch +between the active and mute modes, as defined by the WAKE bit. It is set and cleared by +software. +-0: Receiver in active mode permanently +-1: Receiver can switch between mute mode and active mode + 13 + 1 + read-write + + + CMIE + CMIE: Character match interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 14 + 1 + read-write + + + DEDT + DEDT[4:0]: Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted +message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample +time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only +when the DEDT and DEAT times have both elapsed. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + DEAT[4:0]: Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and +the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, +depending on the oversampling rate). +This bit field can only be written when the USART is disabled (UE=0). + 21 + 5 + read-write + + + M_1 + Word length +This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0).s + 28 + 1 + read-write + + + FIFOEN + FIFOEN :FIFO mode enable +This bit is set and cleared by software. +-0: FIFO mode is disabled. +-1: FIFO mode is enabled. + 29 + 1 + read-write + + + TXFEIE + TXFEIE :TXFIFO empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFE=1 in the USART_ISR register + 30 + 1 + read-write + + + RXFFIE + RXFFIE :RXFIFO Full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when RXFF=1 in the USART_ISR register + 31 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + ADDM7 + ADDM7:7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +-0: 4-bit address detection +-1: 7-bit address detection (in 8-bit data mode) +This bit can only be written when the USART is disabled (UE=0) + 4 + 1 + read-write + + + STOP + STOP[1:0]: STOP bits +These bits are used for programming the stop bits. +-00: 1 stop bit +-01: 0.5 stop bit. +-10: 2 stop bits +-11: 1.5 stop bits +This bit field can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + SWAP + SWAP: Swap TX/RX pins +This bit is set and cleared by software. +-0: TX/RX pins are used as defined in standard pinout +-1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired +connection to another UART. +This bit field can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + RXINV + RXINV: RX pin active level inversion +This bit is set and cleared by software. +-0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the RX line. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + TXINV + TXINV: TX pin active level inversion +This bit is set and cleared by software. +-0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the TX line. +This bit field can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + DATAINV + DATAINV: Binary data inversion +This bit is set and cleared by software. +-0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) +-1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The +parity bit is also inverted. +This bit field can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + MSBFIRST + MSBFIRST: Most significant bit first +This bit is set and cleared by software. +-0: data is transmitted/received with data bit 0 first, following the start bit. +-1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. +This bit field can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + ADD + ADD[7:0]: Address of the USART node +This bit-field gives the address of the USART node or a character code to be recognized. +This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- +bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. +It may also be used for character detection during normal reception, Mute mode inactive (for +example, end of block detection in ModBus protocol). In this case, the whole received character (8- +bit) is compared to the ADD[7:0] value and CMF flag is set on match. +This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled +(UE=0) + 24 + 8 + read-write + + + + + CR3 + CR3 + CR3 register + 0x08 + 0x20 + read-write + 0x00000000 + + + EIE + EIE: Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing +error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR += 1 in the USART_ISR register). +-0: Interrupt is inhibited +-1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) +in the USART_ISR register. + 0 + 1 + read-write + + + HDSEL + HDSEL: Half-duplex selection +Selection of Single-wire Half-duplex mode +-0: Half duplex mode is not selected +-1: Half duplex mode is selected +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + DMAR + DMAR: DMA enable receiver +This bit is set/reset by software +-1: DMA mode is enabled for reception +-0: DMA mode is disabled for reception + 6 + 1 + read-write + + + DMAT + DMAT: DMA enable transmitter +This bit is set/reset by software +-1: DMA mode is enabled for transmission +-0: DMA mode is disabled for transmission + 7 + 1 + read-write + + + RTSE + RTSE: RTS enable +-0: RTS hardware flow control disabled +-1: RTS output enabled, data is only requested when there is space in the receive buffer. The +transmission of data is expected to cease after the current character has been transmitted. +The nRTS output is asserted (pulled to 0) when data can be received. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CTSE + CTSE: CTS enable +-0: CTS hardware flow control disabled +-1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). +If the nCTS input is deasserted while data is being transmitted, then the transmission is +completed before stopping. If data is written into the data register while nCTS is asserted, +the transmission is postponed until nCTS is asserted. +This bit can only be written when the USART is disabled (UE=0) + 9 + 1 + read-write + + + CTSIE + CTSIE: CTS interrupt enable +-0: Interrupt is inhibited +-1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 10 + 1 + read-write + + + OVRDIS + OVRDIS: Overrun Disable +This bit is used to disable the receive overrun detection. +-0: Overrun Error Flag, ORE, is set when received data is not read before receiving new +data. +-1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set +the ORE flag is not set and the new received data overwrites the previous content of the +USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data +will be written directly in USARTx_RDR register. Even when FIFO management is enabled, +the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + DDRE + DDRE: DMA Disable on Reception Error +-0: DMA is not disabled in case of reception error. The corresponding error flag is set but +RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not +asserted, so the erroneous data is not transferred (no DMA request), but next correct +received data will be transferred. (used for Smartcard mode) +-1: DMA is disabled following a reception error. The corresponding error flag is set, as well +as RXNE. The DMA request is masked until the error flag is cleared. This means that the +software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case +FIFO mode is enabled) before clearing the error flag. +This bit can only be written when the USART is disabled (UE=0). + 13 + 1 + read-write + + + DEM + DEM: Driver enable mode +This bit allows the user to activate the external transceiver control, through the DE signal. +-0: DE function is disabled. +-1: DE function is enabled. The DE signal is output on the RTS pin. +This bit can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + DEP + DEP: Driver enable polarity selection +-0: DE signal is active high. +-1: DE signal is active low. +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + WUS + WUS[1:0]: Wakeup from Stop mode interrupt flag selection +This bit-field specify the event which activates the WUF (Wakeup from Stop mode flag). +-00: WUF active on address match (as defined by ADD[7:0] and ADDM7) +-01:Reserved. +-10: WUF active on Start bit detection +-11: WUF active on RXNE. +This bit field can only be written when the LPUART is disabled (UE=0). + 20 + 2 + read-write + + + WUFIE + WUFIE: Wakeup from Stop mode interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An LPUART interrupt is generated whenever WUF=1 in the LPUART_ISR register + 22 + 1 + read-write + + + TXFTIE + TXFTIE: TXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in +TXFTCFG. + 23 + 1 + read-write + + + RXFTCFG + RXFTCFG: Receive FIFO threshold configuration +-000:Receive FIFO reaches 1/8 of its depth. +-001:Receive FIFO reaches 1/4 of its depth. +-010:Receive FIFO reaches 1/2 of its depth. +-011:Receive FIFO reaches 3/4 of its depth. +-100:Receive FIFO reaches 7/8 of its depth. +-101:Receive FIFO becomes full. +Remaining combinations: Reserved. + 25 + 3 + read-write + + + RXFTIE + RXFTIE: RXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when Receive FIFO reaches the threshold +programmed in RXFTCFG. + 28 + 1 + read-write + + + TXFTCFG + TXFTCFG: TXFIFO threshold configuration +-000:TXFIFO reaches 1/8 of its depth. +-001:TXFIFO reaches 1/4 of its depth. +-010:TXFIFO reaches 1/2 of its depth. +-011:TXFIFO reaches 3/4 of its depth. +-100:TXFIFO reaches 7/8 of its depth. +-101:TXFIFO becomes empty. +Remaining combinations: Reserved. + 29 + 3 + read-write + + + + + BRR + BRR + BRR register + 0x0C + 0x20 + read-write + 0x00000000 + + + BRR + BRR[19:0] + 0 + 20 + read-write + + + + + RQR + RQR + RQR register + 0x18 + 0x20 + read-write + 0x00000000 + + + SBKRQ + SBKRQ: Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as +the transmit machine is available. + 1 + 1 + write-only + + + MMRQ + MMRQ: Mute mode request +Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + RXFRQ: Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This allows to discard the received data without reading them, and avoid an overrun +condition. + 3 + 1 + write-only + + + TXFRQ + TXFRQ: Transmit data flush request +When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. +This allows to discard the transmit data. This bit must be used only in Smartcard mode, +when data has not been sent due to errors (NACK) and the FE flag is active in the +USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved +and forced by hardware to 0 +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE +(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is +supported in both UART and Smartcard modes. + 4 + 1 + write-only + + + + + ISR + ISR + ISR register + 0x1C + 0x20 + read-only + 0x000000C0 + + + PE + PE: Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by +software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +-0: No parity error +-1: Parity error + 0 + 1 + read-only + + + FE + FE: Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character +is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +In Smartcard mode, in transmission, this bit is set when the maximum number of transmit +attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR1 register. +-0: No Framing error is detected +-1: Framing error or break character is detected + 1 + 1 + read-only + + + NF + NF: START bit Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by +software, writing 1 to the NFCF bit in the USART_ICR register. +-0: No noise is detected +-1: Noise is detected + 2 + 1 + read-only + + + ORE + ORE: Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case +FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the +USARTx_ICR register. +An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. +-0: No overrun error +-1: Overrun error is detected + 3 + 1 + read-only + + + IDLE + IDLE: Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if +IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in +the USART_ICR register. +-0: No Idle line is detected +-1: Idle line is detected + 4 + 1 + read-only + + + RXNE_RXFNE + RXNE/RXFNE:Read data register not empty/RXFIFO not empty +RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been +transferred +to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from +the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It +is cleared when the RXFIFO is empty. +The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR +register. +An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. +-0: Data is not received +-1: Received data is ready to be read. + 5 + 1 + read-only + + + TC + TC: Transmission complete +This bit indicates when the last data written in the USART_TDR has been transmitted out of +the shift register. +It is set by hardware if the transmission of a frame containing data is complete and if +TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is +cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the +USART_TDR register. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +-0: Transmission is not complete +-1: Transmission is complete + 6 + 1 + read-only + + + TXE_TXFNF + TXE/TXFNF: Transmit data register empty/TXFIFO not full +When FIFO mode is disabled, TXE is set by hardware when the content of the +USARTx_TDR register has been transferred into the shift register. It is cleared by a write to +the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the +USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of +transmission failure). +When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so +data can be written in the USART_TDR. Every write in the USART_TDR places the data in +the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag +is cleared indicating that data can not be written into the USART_TDR. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After +sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to +writing in TXFIFO. (TXFNF and TXFE will be set at the same time). +An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. +-0: Data register is full/Transmit FIFO is full. +-1: Data register/Transmit FIFO is not full + 7 + 1 + read-only + + + CTSIF + CTSIF: CTS interrupt flag +This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared +by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +-0: No change occurred on the nCTS status line +-1: A change occurred on the nCTS status line + 9 + 1 + read-only + + + CTS + CTS: CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. +-0: nCTS line set +-1: nCTS line reset + 10 + 1 + read-only + + + BUSY + BUSY: Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the +RX line (successful start bit detected). It is reset at the end of the reception (successful or +not). +-0: USART is idle (no reception) +-1: Reception on going + 16 + 1 + read-only + + + CMF + CMF: Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is +cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. +-0: No Character match detected +-1: Character Match detected + 17 + 1 + read-only + + + SBKF + SBKF: Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing +1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during +the stop bit of break transmission. +-0: No break character is transmitted +-1: Break character will be transmitted + 18 + 1 + read-only + + + RWU + RWU: Receiver wakeup from Mute mode +This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a +wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) +is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the +MMRQ bit in the USART_RQR register. +-0: Receiver in active mode +-1: Receiver in mute mode + 19 + 1 + read-only + + + WUF + WUF: Wakeup from Stop mode flag +This bit is set by hardware, when a wakeup event is detected. The event is defined by the +WUS bit field. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. +An interrupt is generated if WUFIE=1 in the LPUART_CR3 register + 20 + 1 + read-only + + + TEACK + TEACK: Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by +the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 +in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + REACK: Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by +the USART. +It can be used to verify that the USART is ready for reception before entering Stop mode. + 22 + 1 + read-only + + + TXFE + TXFE: TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one +data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in +the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. +-0: TXFIFO is not empty. +-1: TXFIFO is empty. + 23 + 1 + read-only + + + RXFF + RXFF: RXFIFO Full +This bit is set by hardware when RXFIFO is Full. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. +-0: RXFIFO is not Full. +-1: RXFIFO is Full. + 24 + 1 + read-only + + + RXFT + RXFT: RXFIFO threshold flag +This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 +register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and +one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in +the USART_CR3 register. +-0: Receive FIFO doesnt reach the programmed threshold. +-1: Receive FIFO reached the programmed threshold + 26 + 1 + read-only + + + TXFT + TXFT: TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG +in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is +generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. +-0: TXFIFO doesnt reach the programmed threshold. +-1: TXFIFO reached the programmed threshold + 27 + 1 + read-only + + + + + ICR + ICR + ICR register + 0x20 + 0x20 + read-write + 0x00000000 + + + PECF + PECF: Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + FECF: Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register + 1 + 1 + write-only + + + NECF + NECF: Noise detected clear flag +Writing 1 to this bit clears the NF flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + ORECF: Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + IDLECF: Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TCCF + TCCF: Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register + 6 + 1 + write-only + + + CTSCF + CTSCF: CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register + 9 + 1 + write-only + + + CMCF + CMCF: Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register + 17 + 1 + write-only + + + WUCF + WUCF: Wakeup from Stop mode clear flag +Writing 1 to this bit clears the WUF flag in the LPUART_ISR register. + 20 + 1 + write-only + + + + + RDR + RDR + RDR register + 0x24 + 0x20 + read-only + 0x0 + + + RDR + RDR[8:0]: Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the +internal bus (see Figure 124). +When receiving with the parity enabled, the value read in the MSB bit is the received parity +bit. + 0 + 9 + read-only + + + + + TDR + TDR + TDR register + 0x28 + 0x20 + read-write + 0x0 + + + TDR + TDR[8:0]: Transmit data value +Contains the data character to be transmitted. +The USARTx_TDR register provides the parallel interface between the internal bus and the +output shift register (see Figure 124). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), +the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect +because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + PRESC + PRESC + PRESC register + 0x2C + 0x20 + read-write + 0x0 + + + PRESCALER + PRESCALER[3:0]: Clock prescaler +The USART input clock can be divided by a prescaler: +-0000: input clock not divided +-0001: input clock divided by 2 +-0010: input clock divided by 4 +-0011: input clock divided by 6 +-0100: input clock divided by 8 +-0101: input clock divided by 10 +-0110: input clock divided by 12 +-0111: input clock divided by 16 +-1000: input clock divided by 32 +-1001: input clock divided by 64 +-1010: input clock divided by 128 +-1011: input clock divided by 256 +Remaing combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, +programmed prescaler value will be '1011' i.e. input clock divided by 256 + 0 + 4 + read-write + + + + + + + MISC + MISC + 0x49000700 + + 0x0 + 0x80 + registers + + + + RFIP_VERSION + RFIP_VERSION + RFIP_VERSION register + 0x0 + 0x20 + read-only + 0x00001200 + + + REVISION + Revision of the MR_SubG (to be used for metal fixes) + 4 + 4 + read-only + + + VERSION + Version of the MR_SubG (to be used for cut upgrades) + 8 + 4 + read-only + + + PRODUCT + Used for major upgrades (new protocols support / new features) + 12 + 4 + read-only + + + + + RRM_UDRA_CTRL + RRM_UDRA_CTRL + RRM_UDRA_CTRL register + 0x4 + 0x20 + write-only + 0x00000000 + + + RRM_CMD_REQ + Action bit: write 1 to request a RRM-UDRA command. + 0 + 1 + write-only + + + + + SEQUENCER_CTRL + SEQUENCER_CTRL + SEQUENCER_CTRL register + 0x8 + 0x20 + read-write + 0x00000000 + + + GEN_SEQ_TRIGGER + Action bit: write 1 to generate a trigger event on Sequencer. + 0 + 1 + write-only + + + DISABLE_SEQ + Enable/disable the Sequencer + + 1 + 1 + read-write + + + + + ABSOLUTE_TIME + ABSOLUTE_TIME + ABSOLUTE_TIME register + 0xc + 0x20 + read-only + 0x00000000 + + + ABSOLUTE_TIME + Indicate the interpolated absolute. + 0 + 32 + read-only + + + + + SCM_COUNTER_VAL + SCM_COUNTER_VAL + SCM_COUNTER_VAL register + 0x10 + 0x20 + read-only + 0x00000000 + + + SCM_COUNTER_CURRVAL + Slow Clock Measurement: number of 16 MHz clock cycles contained in 32 slow clock periods. + 0 + 15 + read-only + + + + + SCM_MIN_MAX + SCM_MIN_MAX + SCM_MIN_MAX register + 0x14 + 0x20 + read-write + 0x00007FFF + + + SCM_COUNTER_MINVAL + Slow Clock Measurement: minimum SCM_COUNTER value seen since the counter is ON and since last clear request. + 0 + 15 + read-only + + + SCM_COUNTER_MAXVAL + Slow Clock Measurement: maximum SCM_COUNTER value seen since the counter is ON and since last clear request. + 16 + 15 + read-only + + + CLEAR_MIN_MAX + Write 1' to clear the SCM_COUNTER_MINVAL and SCM_COUNTER_MAXVAL bit fields. + 31 + 1 + write-only + + + + + WAKEUP_IRQ_STATUS + WAKEUP_IRQ_STATUS + WAKEUP_IRQ_STATUS register + 0x18 + 0x20 + read-write + 0x00000000 + + + CPU_WAKEUP_F + Set when the interpolated absolute time matches the CPU_WAKEUPTIME while WAKEUP_CTRL. + 0 + 1 + + + RFIP_WAKEUP_F + Set when the interpolated absolute time matches the RFIP_WAKEUPTIME while WAKEUP_CTRL. + 1 + 1 + + + + + + + MR_SUBG + MR_SUBG + 0x49000000 + + 0x0 + 0x400 + registers + + + MR_SUBG_BUSY + MR_SUBG Busy interrupt + 20 + + + MR_SUBG + MR_SUBG interrupt + 21 + + + TX_RX_SEQUENCE + MR_SUBG TX/RX Sequence +interrupt + 22 + + + + RF_FSM0_TIMEOUT + RF_FSM0_TIMEOUT + RF_FSM0_TIMEOUT register + 0x00 + 0x20 + read-write + 0x00000000 + + + ENA_RFREG_TIMER + Timeout for the RF regulator startup (duration in ENA_RF_REG state) + + 0 + 8 + read-write + + + + + RF_FSM1_TIMEOUT + RF_FSM1_TIMEOUT + RF_FSM1_TIMEOUT register + 0x04 + 0x20 + read-write + 0x00000006 + + + SYNTH_SETUP_TIMER + Timeout management for the RF regulator to stabilize after RF PLL power on + + 0 + 8 + read-write + + + + + RF_FSM2_TIMEOUT + RF_FSM2_TIMEOUT + RF_FSM2_TIMEOUT register + 0x08 + 0x20 + read-write + 0x00000050 + + + VCO_CALIB_LOCK_TIMER + Timeout for the RF PLL calibration + RF PLL lock (duration in CALIB_VCO+LOCKRXTX state) + + 0 + 8 + read-write + + + + + RF_FSM3_TIMEOUT + RF_FSM3_TIMEOUT + RF_FSM3_TIMEOUT register + 0x0C + 0x20 + read-write + 0x00000028 + + + VCO_LOCK_TIMER + Timeout for the RF PLL lock event when no calibration is requested (duration in LOCKRXTX state) + + 0 + 8 + read-write + + + + + RF_FSM4_TIMEOUT + RF_FSM4_TIMEOUT + RF_FSM4_TIMEOUT register + 0x10 + 0x20 + read-write + 0x0000000F + + + EN_RX_TIMER + Timeout for the analog RX chain setup (duration in EN_RX state) + + 0 + 8 + read-write + + + + + RF_FSM5_TIMEOUT + RF_FSM5_TIMEOUT + RF_FSM5_TIMEOUT register + 0x14 + 0x20 + read-write + 0x00000019 + + + EN_PA_TIMER + Timeout for the analog PA (DAC) setup (duration in EN_PA state) + + 0 + 8 + read-write + + + + + RF_FSM6_TIMEOUT + RF_FSM6_TIMEOUT + RF_FSM6_TIMEOUT register + 0x18 + 0x20 + read-write + 0x00000019 + + + PA_DWN_ANA_TIMER + Timeout for the analog PA (DAC) ramp down (duration in PA_DWN_ANA state) + + 0 + 8 + read-write + + + + + RF_FSM7_TIMEOUT + RF_FSM7_TIMEOUT + RF_FSM7_TIMEOUT register + 0x1C + 0x20 + read-write + 0x00000005 + + + EN_LNA_TIMER + Timeout for the analog RX chain signals settlement once PGA precharge is shut down (duration in EN_LNA state) + + 0 + 8 + read-write + + + + + AFC0_CONFIG + AFC0_CONFIG + AFC0_CONFIG register + 0x20 + 0x20 + read-write + 0x00000025 + + + AFC_SLOW_GAIN_LOG2 + AFC loop gain in slow mode (2's log) + 0 + 4 + read-write + + + AFC_FAST_GAIN_LOG2 + AFC loop gain in fast mode (2's log) + 4 + 4 + read-write + + + + + AFC1_CONFIG + AFC1_CONFIG + AFC1_CONFIG register + 0x24 + 0x20 + read-write + 0x00000018 + + + AFC_FAST_PERIOD + Length of the AFC fast period (in number of samples unit) + + 0 + 8 + read-write + + + + + AFC2_CONFIG + AFC2_CONFIG + AFC2_CONFIG register + 0x28 + 0x20 + read-write + 0x000000C8 + + + AFC_PD_LEAKAGE + AFC Peak Detection leakage. + 0 + 5 + read-write + + + AFC_MODE + Select AFC mode: + + 5 + 1 + read-write + + + AFC_EN + Enable AFC. + 6 + 1 + read-write + + + AFC_FREEZE_ON_SYNC + Freeze AFC correction upon SYNC word detection + 7 + 1 + read-write + + + + + AFC3_CONFIG + AFC3_CONFIG + AFC3_CONFIG register + 0x2C + 0x20 + read-write + 0x000000E8 + + + AFC_INIT_MODE + Control the initialization phase of the AFC and clock recovery algorithms: + + 0 + 1 + read-write + + + AFC_SIGN_PERM_CHECK + Enable the check of sign permanence of AFC corrected signal. + 1 + 1 + read-write + + + AFC_TH_SIGN_PERM + Threshold of chech sign permanence mechanism. + 2 + 4 + read-write + + + AFC_REINIT_OPTION + Select the AFC reinitialization option: + + 6 + 2 + read-write + + + + + CLKREC_CTRL0 + CLKREC_CTRL0 + CLKREC_CTRL0 register + 0x30 + 0x20 + read-write + 0x000000B8 + + + CLKREC_I_GAIN_FAST + Integral fast gain for the clock recovery loop (PLL mode only) + + 0 + 4 + read-write + + + CLKREC_P_GAIN_FAST + Clock recovery fast loop gain (log2) + + 4 + 3 + read-write + + + PSTFLT_LEN + Control the length of the demodulator post-filter + + 7 + 1 + read-write + + + + + CLKREC_CTRL1 + CLKREC_CTRL1 + CLKREC_CTRL1 register + 0x34 + 0x20 + read-write + 0x0000005C + + + CLKREC_I_GAIN_SLOW + Integral slow gain for the clock recovery loop (PLL mode only) + + 0 + 4 + read-write + + + CLKREC_P_GAIN_SLOW + Clock recovery slow loop gain (log2) + + 4 + 3 + read-write + + + CLKREC_ALGO_SEL + Symbol timing recovery algorithm selection + + 7 + 1 + read-write + + + + + DCREM_CTRL0 + DCREM_CTRL0 + DCREM_CTRL0 register + 0x38 + 0x20 + read-write + 0x000000E8 + + + START_GAIN + Filter gain in start mode for the DC removal block. + 0 + 5 + read-write + + + TRACK_GAIN + Filter gain in track mode for the DC removal block. + 7 + 1 + read-write + + + + + IQC_CTRL0 + IQC_CTRL0 + IQC_CTRL0 register + 0x40 + 0x20 + read-write + 0x000000E3 + + + FAST_GAIN + Gain of the correction loop in fast mode. + 0 + 4 + read-write + + + SLOW_GAIN + Gain of the correction loop in slow mode. + 4 + 4 + read-write + + + + + IQC_CTRL1 + IQC_CTRL1 + IQC_CTRL1 register + 0x44 + 0x20 + read-write + 0x00000008 + + + QPD_ATTACK + Attack coefficient for QPD: + + 0 + 8 + read-write + + + + + IQC_CTRL2 + IQC_CTRL2 + IQC_CTRL2 register + 0x48 + 0x20 + read-write + 0x00000008 + + + QPD_DECAY + Decay coefficient for QPD: + + 0 + 8 + read-write + + + + + IQC_CTRL3 + IQC_CTRL3 + IQC_CTRL3 register + 0x4C + 0x20 + read-write + 0x00000007 + + + FAST_TIME + Duration of the fast mode. + 0 + 4 + read-write + + + + + AGC_ANA_ENG + AGC_ANA_ENG + AGC_ANA_ENG register + 0x50 + 0x20 + read-write + 0x00000000 + + + FORCE_AGC_GAINS + Select the mode for AGC analog part: + + 0 + 1 + read-write + + + RFD_RX_ATTEN_AGCGAIN + Attenuation at LNA level by step of 6dB with thermometric code: + + 1 + 4 + read-write + + + RFD_RX_PGA_AGCGAIN + Attenuation at PGA level by step of 6dB with binary code: + + 5 + 3 + read-write + + + + + AGC0_CTRL + AGC0_CTRL + AGC0_CTRL register + 0x54 + 0x20 + read-write + 0x00000099 + + + AGC_HOLD_TIME + AGC hold time. + 0 + 6 + read-write + + + AGC_START_ONHOLD + Start the AGC with a hold phase. + 6 + 1 + read-write + + + AGC_EN + Enable the AGC + + 7 + 1 + read-write + + + + + AGC1_CTRL + AGC1_CTRL + AGC1_CTRL register + 0x58 + 0x20 + read-write + 0x00000062 + + + AGC_MIN_THR + Minimum signal threshold. + 0 + 4 + read-write + + + AGC_MAX_THR + Maximum signal threshold. + 4 + 4 + read-write + + + + + AGC2_CTRL + AGC2_CTRL + AGC2_CTRL register + 0x5C + 0x20 + read-write + 0x000000AF + + + AGC_MEAS_TIME + Measure time. + 0 + 4 + read-write + + + AGC_START_MAX_ATTEN + Start the AGC with maximum attenuation. + 4 + 1 + read-write + + + AGC_FREEZE_ON_SYNC + Enable the freeze on SYNC detection feature + 5 + 1 + read-write + + + AGC_FREEZE_ON_STEADY + Enable the autofreeze feature + 6 + 1 + read-write + + + AGC_HIGH_ATTEN_MODE + Enable the high attenuation mode. + 7 + 1 + read-write + + + + + AGC3_CTRL + AGC3_CTRL + AGC3_CTRL register + 0x60 + 0x20 + read-write + 0x00000090 + + + AGC_MIN_ATTEN + Minimum AGC attenuation. + 0 + 4 + read-write + + + AGC_MAX_ATTEN + Maximum AGC attenuation. + 4 + 4 + read-write + + + + + AGC4_CTRL + AGC4_CTRL + AGC4_CTRL register + 0x64 + 0x20 + read-write + 0x00000002 + + + AGC_FREEZE_THR + Signal threshold for the autofreeze feature. + 0 + 4 + read-write + + + + + AGC_PGA_HWTRIM_OUT + AGC_PGA_HWTRIM_OUT + AGC_PGA_HWTRIM_OUT register + 0xA0 + 0x20 + read-only + 0x00000008 + + + AGC_HW_PGA_TRIM + AGC PGA calibration information loaded by HW from the SoC flash. + 0 + 4 + read-only + + + + + PA_REG + PA_REG + PA_REG register + 0xA8 + 0x20 + read-write + 0x00000000 + + + CFG_FILT + FIR configuration: + + 0 + 2 + read-write + + + PA_DEGEN_ON + Enable a 'degeneration' mode, which introduces a pre-distortion to linearize the power control curve. + 3 + 1 + read-write + + + + + PA_HWTRIM_OUT + PA_HWTRIM_OUT + PA_HWTRIM_OUT register + 0xAC + 0x20 + read-only + 0x00000088 + + + PA_HW_DEGEN_TRIM + MSB part meaning: + + 4 + 4 + read-only + + + + + RSSI_FLT + RSSI_FLT + RSSI_FLT register + 0xBC + 0x20 + read-write + 0x000000E0 + + + OOK_PEAK_DECAY + Peak decay control for OOK: 3 slow decay; 0 fast decay + 0 + 4 + read-write + + + RSSI_FLT + Gain of the RSSI filter + 4 + 4 + read-write + + + + + SYNTH2_ANA_ENG + SYNTH2_ANA_ENG + SYNTH2_ANA_ENG register + 0xC8 + 0x20 + read-write + 0x0000004C + + + RFD_PLL_VCO_ALC_AMP + Select the level of max VCO amplitude in amplitude level control loop. + 0 + 3 + read-write + + + RFD_PLL_LD_WIN_ACC + Select the PLL lock detector window selection: + + 3 + 1 + read-write + + + + + RXADC_HWDELAYTRIM_OUT + RXADC_HWDELAYTRIM_OUT + RXADC_HWDELAYTRIM_OUT register + 0xE8 + 0x20 + read-only + 0x0000001B + + + RXADC_HW_DELAYTRIM_I + Control bits of the RX ADC loop delay for I channel (from SoC Flash). + 0 + 3 + read-only + + + RXADC_HW_DELAYTRIM_Q + Control bits of the RX ADC loop delay for Q channel (from SoC Flash). + 3 + 3 + read-only + + + + + RX_AAF_HWTRIM_OUT + RX_AAF_HWTRIM_OUT + RX_AAF_HWTRIM_OUT register + 0xF4 + 0x20 + read-only + 0x00000006 + + + AAF_HW_FCTRIM + AAF calibration information loaded by HW. + 0 + 4 + read-only + + + + + SINGEN_ANA_ENG + SINGEN_ANA_ENG + SINGEN_ANA_ENG register + 0x100 + 0x20 + read-write + 0x00000000 + + + RFD_SINGEN_ENA + Enable SINGEN signal for the RFSUBGanalog IP. + 0 + 1 + read-write + + + RFD_SINGEN_DIV2_PUP + This bit value is directly connected to the RFSUBG analog IP pin. + 1 + 1 + read-write + + + RFD_SINGEN_LBE + This bit value is directly connected to the RFSUBG analog IP pin. + 2 + 1 + read-write + + + + + RF_INFO_OUT + RF_INFO_OUT + RF_INFO_OUT register + 0x108 + 0x20 + read-only + 0x00000040 + + + FQCY_BAND_ID + FQCY_BAND_ID[3:0]: Indicates the version of the RFSUBG IP embedded in the device + + 0 + 4 + read-only + + + RFSUBG_ID + Indicate the version of the analog RFSUBG IP embedded in the device + + 4 + 4 + read-only + + + + + RF_FSM8_TIMEOUT + RF_FSM8_TIMEOUT + RF_FSM8_TIMEOUT register + 0x124 + 0x20 + read-write + 0x0000000A + + + SYNTH_PDWN_TIMER + Timeout management for the RF regulator to stabilize after PLL shut down + + 0 + 8 + read-write + + + + + RF_FSM9_TIMEOUT + RF_FSM9_TIMEOUT + RF_FSM9_TIMEOUT register + 0x128 + 0x20 + read-write + 0x00000006 + + + END_RX_TIMER + Timeout management for the RF regulator to stabilize after analog RX chain shut down + + 0 + 8 + read-write + + + + + RF_FSM10_TIMEOUT + RF_FSM10_TIMEOUT + RF_FSM10_TIMEOUT register + 0x12C + 0x20 + read-write + 0x00000006 + + + END_TX_TIMER + Timeout management for the RF regulator to stabilize after clock stops on the analog PA block + + 0 + 8 + read-write + + + + + SUBG_DIG_CTRL0 + SUBG_DIG_CTRL0 + SUBG_DIG_CTRL0 register + 0x144 + 0x20 + read-write + 0x00000000 + + + FORCE_GPIO_OUTPUT + Option for the direct GPIO signal output + + 0 + 1 + read-write + + + + + RX_CHAIN_ENG + RX_CHAIN_ENG + RX_CHAIN_ENG register + 0x148 + 0x20 + read-write + 0x00000003 + + + LNA_ISOL_ENA + Option for LNA during the EN_RX state of the Radio FSM: + + 0 + 1 + read-write + + + PGA_PRECH_ENA + Option for PGA precharge during the EN_RX state of the Radio FSM: + + 1 + 1 + read-write + + + + + DEMOD_DIG_ENG + DEMOD_DIG_ENG + DEMOD_DIG_ENG register + 0x14C + 0x20 + read-write + 0x00000003 + + + RX_BLANKING_LENGTH + Number of data samples at RX start for which the signal at the output of the channel filter is kept forced to zero: + + 0 + 3 + read-write + + + + + + + PWRC + PWRC + 0x48500000 + + 0x0 + 0xA8 + registers + + + PVD + PVD / BORH + 2 + + + + CR1 + CR1 + CR1 register + 0x0 + 0x20 + read-write + 0x114 + + + LPMS + LPMS Low Power Mode Selection +Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep. +- 0: Deep Stop mode (default) +- 1: Shutdown mode + 0 + 1 + read-write + + + ENSDNBOR + ENSDNBOR: Enable BOR supply monitoring during shutdown mode. +- 1: the PD_ALL_SHUTDOWN signal is not set during SHUTDOWN mode +- 0: the PD_ALL_SHUTDOWN signal is set during SHUTDOWN mode. + 1 + 1 + read-write + + + IBIAS_RUN_AUTO + IBIAS_RUN_AUTO: Enable automatic IBIAS control during RUN/DEEPSTOP mode. +- 0: IBIAS control is manual (and controlled by IBIAS_RUN_STATE register) +- 1: IBIAS control is automatic (default). + 2 + 1 + read-write + + + IBIAS_RUN_STATE + IBIAS_RUN_STATE: Enable/Disable IBIAS during RUN mode when automatic mode is +disabled. +- 0: IBIAS control is disabled (default). +- 1: IBIAS control is enabled. + 3 + 1 + read-write + + + APC + APC Apply Pull-up and pull-down configuration from CPU +- 1: the I/O pull-up and pull-down configurations defined in the PUCRx and PDCRx registers is applied. +- 0: the PUCRx and PDCRx are not used to control the I/O pull-up and pull-down configuration of the product I/Os. + 4 + 1 + read-write + + + ENBORH + ENBORH: enable BORH configuration +- 1: BORH is enabled, threshold level depends on SELBOR[1:0] +- 0: BORH off (VBOR0): threshold level for above 1.60V voltage operation. + 5 + 1 + read-write + + + SELBORH + SELBORH[1:0]: BORH selection of Vbor threshold +- 11: BORH Level 4(VBOR4): threshold level for above 2.81 V voltage operation. +- 10: BORH Level 3 (VBOR3): threshold level for above 2.52 V voltage operation +- 01: BORH Level 2 (VBOR2): threshold level for above 2.21 V voltage operation +- 00: BORH Level 1 (VBOR1): threshold level for above 2.0V voltage operation. + 6 + 2 + read-write + + + ENBORL + ENBORL: Enable BORL reset supervising during RUN mode. +- 0: No BORL is monitored during RUN mode. +- 1: BORL is monitored during RUN mode (a POR reset will happen if VDDIO goes below 1.6V during RUN mode) (default). +Note: Enabling this feature prevents blocking the device if VDDIO goes below supported voltages during RUN. + 8 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x4 + 0x20 + read-write + 0x0000 + + + PVDE + PVDE Programmable Voltage Detector Enable +When this bit is set the Power Voltage Detector is enabled + 0 + 1 + read-write + + + PVDLS + PVDLS[2:0] Programmable Voltage Detector Level selection +- 000: 2.05 V - Lowest level +- 001: 2.20 V +- 010: 2.36 V +- 011: 2.52 V +- 100: 2.64 V +- 101: 2.81 V +- 110: 2.91 V - Highest level +- 111: External input analog voltage (compare internally to VBGP; When external input VBGP +then PVDO=1) + 1 + 3 + read-write + + + DBGRET + DBGRET: PA2 and PA3 retention enable after DEEPSTOP +- 0: PA2, PA3 don't retain their status exiting from DEEPSTOP (default). +- 1: PA2, PA3 retain their status exiting from DEEPSTOP. + 4 + 1 + read-write + + + RAMRET1 + RAMRET1: RAM1 retention during low power mode +- 1: RAM1 bank is powered during low power mode +- 0: RAM1 bank is disabled during low power mode (by default) + 5 + 1 + read-write + + + LPREG_FORCE_VH + force LPREG=1.2V during DEEPSTOP +- 1: Force LPREG=1.2V during DEEPSTOP +- 0: No Force (Default) +Note LPREG= 1.2v can still apply when LCDEN or COMP.SCALEREN request it + 6 + 1 + read-write + + + LPREG_VH_STATUS + status LPREG VH (1.2v) during DEEPSTOP +- 1: LPREG=1.2V during DEEPSTOP +- 0: LPREG=1V during DEEPSTOP + 7 + 1 + read-only + + + GPIORET + GPIORET: GPIO retention enable. +- 0: Release GPIO retention after deepstop (Should be reset after restore Context) +- 1: Enable GPIO Retention during deepstop (Must be set before deepstop) + 8 + 1 + read-write + + + ENTS + ENTS: Enable Temperature Sensor +- 1: Temperature sensor is enabled +- 0: Temperature sensor is disabled + 9 + 1 + read-write + + + RFREGEN + RFREGEN: RF Regulator Enable +- 1: Enable RF Regulator +- 0: Disable RF Regulator (Note: RF Regulator can still be enabled by the RFSUGB or RCC_CR.HSEON) + 10 + 1 + read-write + + + RFREGCEXT + RFREGCEXT: RF Regulator External Supply Bypass +- 1: External supply bypass capability +- 0: Internal supply only + 11 + 1 + read-write + + + RFREGBYP + RFREGBYP: RF Regulator Bypass Enable +- 1: LDO output connected to VSMPS. +- 0: internally generated 1.2V + 12 + 1 + read-write + + + RFREGRDY + RFDREGRDY: RF Regulator Ready flag +- 1: RF Regulator is ready +- 0: RF Regulator is not ready + 13 + 1 + read-only + + + RFREGON_STATUS + RFREGON_STATUS: RF Regulator On Status +- 1: RF Regulator is enabled +- 0: RF Regulator is disabled + 14 + 1 + read-only + + + + + IEWU + IEWU + IEWU register + 0x8 + 0x20 + read-write + 0x0000 + + + EIWL0 + EWL0 Enable Internal WakeUp line LPUART +When this bit is set the internal wakeup line is enabled and a rising edge will trigger a CPU wakeup event. +- 0: wakeup disabled. +- 1: wakeup enabled. + 0 + 1 + read-write + + + EIWL1 + EIWL1 Enable Internal WakeUp line RTC +When this bit is set the internal wakeup line is enabled and a rising edge will trigger a CPU wakeup event. +- 0: wakeup disabled. +- 1: wakeup enabled. + 1 + 1 + read-write + + + EIWL2 + EIWL2 Enable Internal WakeUp line LCD +When this bit is set the internal wakeup line is enabled and a rising edge will trigger a CPU wakeup event. +- 0: wakeup disabled. +- 1: wakeup enabled. + 2 + 1 + read-write + + + EIWL3 + EIWL3 Enable Internal Wakeup line COMP +When this bit is set the COMP wakeup is enabled and an edge will trigger a COMP wakeup event +- 0: wakeup disabled. +- 1: wakeup enabled. + 3 + 1 + read-write + + + EIWL4 + EIWL4 Enable Internal Wakeup line LCSC +When this bit is set the LCSC wakeup is enabled and an edge will trigger a LCSC wakeup event +- 0: wakeup disabled. +- 1: wakeup enabled. + 4 + 1 + read-write + + + EWMRSUBG + EWMRSUB Wakeup MRSUBG Enable +When this bit is set the MRSUBG wakeup is enabled and a rising edge will trigger a MRSUBG wakeup event +- 0: MRSUBG wakeup disabled. +- 1: MRSUBG wakeup enabled. + 8 + 1 + read-write + + + EWMRSUBGHCPU + EWMRSUBGHCPU Wakeup MRSUBG Host CPU Enable +When this bit is set the MRSUBG HOST CPU wakeup is enabled and a rising edge will trigger a MRSUBG Host CPU wakeup event +- 0: MRSUBG Host CPU wakeup disabled. +- 1: MRSUBG Host CPU wakeup enabled. + 9 + 1 + read-write + + + EWLPAWUR + EWLPAWUR: Wakeup Bubble Enable +When this bit is set the Bubble wakeup is enabled and a rising edge will trigger a LPAWUR wakeup event +- 0: LPAWUR wakeup disabled. +- 1: LPAWUR wakeup enabled. + 10 + 1 + read-write + + + + + IWUP + IWUP + IWUP register + 0xc + 0x20 + read-write + 0x0 + + + IWUP0 + IWUP0: Wakeup polarity for internal wakeup line 0 event (LPUART). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 0 + 1 + read-write + + + IWUP1 + IWUP1: Wakeup polarity for internal wakeup line 1 event (RTC). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 1 + 1 + read-write + + + IWUP2 + IWUP2: Wakeup polarity for internal wakeup line 2 event (LCD). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 2 + 1 + read-write + + + IWUP3 + IWUP3: Wakeup polarity for internal wakeup line 3 event (COMP). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 3 + 1 + read-write + + + IWUP4 + IWUP4: Wakeup polarity for internal wakeup line 4 event (LCSC). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 4 + 1 + read-write + + + WMRSUBGHP + WMRSUBGHP: Wakeup polarity for internal wakeup MRSUBG event +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 8 + 1 + read-write + + + WMRSUBGHCPUP + WMRSUBGHCPUP: Wakeup polarity for internal wakeup MRSUBG Host CPU event +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 9 + 1 + read-write + + + WLPAWURP + WLPAWURP: Wakeup polarity for wakeup LPAWUR event. +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 10 + 1 + read-write + + + + + IWUF + IWUF + IWUF register + 0x10 + 0x20 + read-write + 0x0 + + + IWUF0 + IWUF0: Internal wakeup flag (LPUART). +- 0: no wakeup from LPUART occurred since last clear. +- 1: a wakeup from LPUART occurred since last clear. +Cleared by writing 1 in this bit. + 0 + 1 + read-write + + + IWUF1 + IWUF1: Internal wakeup flag (RTC). +- 0: no wakeup from RTC occurred since last clear. +- 1: a wakeup from RTC occurred + 1 + 1 + read-write + + + IWUF2 + IWUF2: Internal wakeup flag (LCD). +- 0: no wakeup from LCD occurred since last clear. +- 1: a wakeup from LCD occurred since last clear. +Cleared by writing 1 in this bit. + 2 + 1 + read-write + + + IWUF3 + IWUF3: Internal wakeup flag (COMP). +- 0: no wakeup from COMP occurred since last clear. +- 1: a wakeup from COMP occurred since last clear. +Cleared by writing 1 in this bit. + 3 + 1 + read-write + + + IWUF4 + IWUF4: Internal wakeup flag (LCSC). +- 0: no wakeup from LCSC occurred since last clear. +- 1: a wakeup from LCSC occurred since last clear. +Cleared by writing 1 in this bit. + 4 + 1 + read-write + + + WMRSUBGF + WMRSUBGF Wakeup MRSUBG Flag +This bit is set by hardware when a MRSUBG wakeup is detected +It is cleared by a reset pad or by software writing 1 in this bit field. +- 0: No MRSUBG Wakeup detected +- 1: MRSUBG Wakeup detected +writting 1 in this bit, clears the interrupt + 8 + 1 + read-write + + + WMRSUBGHCPUF + WMRSUBGHCPUF Wakeup MRSUBG HOST CPU Flag (cf. user manual) +This bit is set by hardware when a MRSUBG HOST CPU wakeup is detected +It is cleared by a reset pad or by software writing 1 in this bit field. +- 0: No MRSUBG Host CPU wakeup detected +- 1: MRSUBG Host CPU wakeup detected +writting 1 in this bit, clears the interrupt + 9 + 1 + read-write + + + WLPAWURF + WLPAWURF Wakeup LPAWUR Flag (cf. user manual) +This bit is set by hardware when a LPAWUR wakeup is detected +It is cleared by a reset pad or by software writing 1 in this bit field. +- 0: No LPAWUR wakeup detected +- 1: LPAWUR wakeup detected +writting 1 in this bit, clears the interrupt + 10 + 1 + read-write + + + + + SR2 + SR2 + SR2 register + 0x14 + 0x20 + read-only + 0xF3F6 + + + SMPSBYPR + SMPSBYPR: SMPS Force Bypass Control Replica +This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 0 + 1 + read-only + + + SMPSENR + SMPSENR: SMPS Enable Control Replica +This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 1 + 1 + read-only + + + SMPSRDY + SMPSRDY: SMPS Ready Status +This bit provides the information whether SMPS is ready. +- 0: SMPS regulator is not ready +- 1: SMPS regulator is ready. + 2 + 1 + read-only + + + IOBOOTVAL2 + Bit3: PB15 input value on VDD33 latched at POR +Bit2: PB14 input value on VDD33 latched at POR +Bit1: PB13 input value on VDD33 latched at POR +Bit0: PB12 input value on VDD33 latched at POR + 4 + 4 + read-only + + + REGLPS + REGLPS: Regulator Low Power Started +This bit provides the information whether low power regulator is ready. +- 0: LP regulator is not ready. +- 1: LP regulator is ready. + 8 + 1 + read-only + + + REGMS + REGMS: Main regulator ready status. +- 0: The Main regulator is not ready. +- 1: The Main regulator is ready. + 9 + 1 + read-only + + + PVDO + PVDO: Power Voltage Detector Output +When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is +lower than the selected PVD threshold (CR2.PVDLS) + 11 + 1 + read-only + + + IOBOOTVAL + Bit3: PA11 input value on VDD33 latched at POR +Bit2: PA10 input value on VDD33 latched at POR +Bit1: PA9 input value on VDD33 latched at POR +Bit0: PA8 input value on VDD33 latched at POR + 12 + 4 + read-only + + + + + CR5 + CR5 + CR5 register + 0x1c + 0x20 + read-write + 0x6014 + + + SMPSLVL + SMPSLVL[3:0] SMPS Output Level Voltage Selection +Select the SMPS output voltage with a granularity of 50mV. Default = '0100' (1.4V) +Vout = 1.2 + 0.05*SMPSOUT (V) + 0 + 4 + read-write + + + SMPSBOMSEL + SMPSBOMSEL: SMPS BOM Selection: +- 00: BOM1 +- 01: BOM2 (default) +- 10: BOM3 +- 11: n/a + 4 + 2 + read-write + + + SMPS_BOF_STATIC + SMPS_BOF_STATIC: SMPS Bypass on the Fly static +- 0 : disabled (by default) +- 1 : SMPS Bypass on the fly static is enabled (EN_SW=1) + 6 + 1 + read-write + + + NOSMPS_BOF + NOSMPS_BOF: No SMPS Mode to be used in accordance to SMPS_BOF_STATIC =1 +When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only SMPS_BOF_STATIC=1. +- 0 : No effect, SMPS is enabled. (default) +- 1 : SMPS is disabled; + 7 + 1 + read-write + + + SMPSLPOPEN + SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). +When this bit is set, when the chip is in Low power mode the SMPS regulator will be disabled (HZ) Documentation needed. +- 0 : in Low Power mode, SMPS is in PRECHARGE, output is connected to VDDIO. (default) +- 1 : in Low Power mode, SMPS is disabled, output is floating + 8 + 1 + read-write + + + SMPSFBYP + SMPSFB Force SMPS Regulator in bypass mode +When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. +- 0 : no effect (by default) +- 1 : SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1) + 9 + 1 + read-write + + + NOSMPS + NOSMPS: No SMPS Mode +When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only when SMPS_FB pad is directly connected to VBATT or Vext, without L/C BOM. +- 0 : No effect, SMPS is enabled. (Default) +- 1 : SMPS is disabled; + 10 + 1 + read-write + + + SMPS_ENA_DCM + SMPS_ENA_DCM: enable discontinuous conduction mode +- 0 : disable (Default) +- 1 : enable + 11 + 1 + read-write + + + CLKDETR_DISABLE + CLKDETR_DISABLE: disable SMPS clock detection +The SMPS clock detection enables an automatic SMPS bypass switching in case of unwanted loss of SMPS clock. +- 0 : SMPS clock detection enabled (default) +- 1 : SMPS clock detection disabled + 12 + 1 + read-write + + + SMPS_PRECH_CUR_SEL + SMPS_PRECH_CUR_SEL[1:0] Selection for SMPS PRECHARGE limit current +- 00: 2.5mA +- 01: 5mA +- 10: 10mA +- 11: 20mA (default) + 13 + 2 + read-write + + + SMPS_BOF_DYN + SMPS_BOF_DYN: SMPS Bypass on the Fly dynamic +- 0 : disabled (by default) +- 1 : SMPS Bypass on the fly dynamic is enabled (EN_LDO=1) + 15 + 1 + read-write + + + + + PUCRA + PUCRA + PUCRA register + 0x20 + 0x20 + read-write + 0xFFF7 + + + PUA + PUA[x] : Pull Up Port A +Pull up activation on port A[i] pad when APC bit of PWRC CR1 is set +- 1: Pull-Up activated on port A[i] when APC bit of PWRC CR1 bit is set and PWR_PDCRA[x] is reset +- 0: Pull-Up not activated on port A[i] + 0 + 16 + read-write + + + + + PDCRA + PDCRA + PDCRA register + 0x24 + 0x20 + read-write + 0x8 + + + PDA + PDA[x]: Pull Down Port A +Pull Down activation on port A[i] pad when APC bit of PWRC CR1 is set +- 1: Pull-Down activated on Port A[i] when APC bit of PWRC CR1 bit is set +- 0: Pull-Down not activated on Port A[i] + 0 + 16 + read-write + + + + + PUCRB + PUCRB + PUCRB register + 0x28 + 0x20 + read-write + 0xFFFF + + + PUB + PUB[x] : Pull Up Port B +Pull up activation on port B[i] pad when APC bit of PWRC CR1 is set +- 1: Pull-Up activated on port B[i] when APC bit of PWRC CR1 bit is set and PWR_PDCRB[x] is reset +- 0: Pull-Up not activated on port B[i] + 0 + 16 + read-write + + + + + PDCRB + PDCRB + PDCRB register + 0x2c + 0x20 + read-write + 0x0 + + + PDB + PDB[x]: Pull Down Port B +Pull Down activation on port B[i] pad when APC bit of PWRC CR1 is set +- 1: Pull-Down activated on Port B[i] when APC bit of PWRC CR1 bit is set +- 0: Pull-Down not activated on Port B[i] + 0 + 16 + read-write + + + + + EWUA + EWUA + EWUA register + 0x30 + 0x20 + read-write + 0x0 + + + EWUA + EWUA[x] Enable WakeUp line PA[x] +When this bit is set the PA[x] wakeup line is enabled and a rising or falling edge on wakeup line PA[x] will trigger a CPU wakeup event depending on CR7.WUPA[x] bit. + 0 + 16 + read-write + + + + + WUPA + WUPA + WUPA register + 0x34 + 0x20 + read-write + 0x0 + + + WUPA + WUPA[x] Wake-up Line PA[x] Polarity +This bit defines the polarity used for event detection on external wake-up line PA[x] +- 0: Detection on high level (rising edge) +- 1: Detection on low level (falling edge) + 0 + 16 + read-write + + + + + WUFA + WUFA + WUFA register + 0x38 + 0x20 + read-write + 0x0 + + + WUFA + WUFA[x] WakeUp Flag PA[x] +This bit is set when a wakeup is detected on wakeup line PA[x]. It is cleared by a reset pad or by writing 1 in this bit field. +Writing 1 this bit, clears the interrupt: + 0 + 16 + read-write + + + + + EWUB + EWUB + EWUB register + 0x40 + 0x20 + read-write + 0x0 + + + EWUB + EWUB[x] Enable WakeUp line PB[x] +When this bit is set the PB[x] wakeup line is enabled and a rising or falling edge on wakeup line PB[x] will trigger a CPU wakeup event depending on CR9.WUPB[x] bit. + 0 + 16 + read-write + + + + + WUPB + WUPB + WUPB register + 0x44 + 0x20 + read-write + 0x0 + + + WUPB + WUPB[x] Wake-up Line PB[x] Polarity +This bit defines the polarity used for event detection on external wake-up line PB[x] +- 0: Detection on high level (rising edge) +- 1: Detection on low level (falling edge) + 0 + 16 + read-write + + + + + WUFB + WUFB + WUFB register + 0x48 + 0x20 + read-write + 0x0 + + + WUFB + WUFB[x] WakeUp Flag PB[x] +This bit is set when a wakeup is detected on wakeup line PB[x]. It is cleared by a reset pad or by writing 1 in this bit field. +Writing 1 this bit, clears the interrupt: + 0 + 16 + read-write + + + + + SDWN_WUEN + SDWN_WUEN + SDWN_WUEN register + 0x4c + 0x20 + read-write + 0x0 + + + WUEN + WUEN PB0 I/O WakeUp from shutdown Enable +When this bit is set the PB0 wakeup from shutdown is enabled so that a rising or falling edge on PB0 (depending on SDWN_WUPOL..WUPOL bit) will trigger a CPU wakeup. It is cleared by a PORESETn. +- 0: PB0 wakeup from shutdown disabled +- 1: PB0 wakeup from shutdown enabled + 0 + 1 + read-write + + + + + SDWN_WUPOL + SDWN_WUPOL + SDWN_WUPOL register + 0x50 + 0x20 + read-write + 0x0 + + + WUPOL + WUPOL PB0 I/O WakeUp from shutdown Polarity +This bit defines the polarity used for wakeup from shutdown detection on PB0 pin. It is cleared by a PORESETn. +- 0: Detection on high level (rising edge) +- 1: Detection on low level (falling edge) + 0 + 1 + read-write + + + + + SDWN_WUF + SDWN_WUF + SDWN_WUF register + 0x54 + 0x20 + read-write + 0x0 + + + WUF + WUF PB0 I/O WakeUp from shutdown Flag +This bit is set when a wakeup from shutdown is detected on PB0 pin. It is cleared by a PORESETn or by writing 0 in this bit field. +- 0: Shutdown wakeup from PB0 not occurred +- 1: Shutdown wakeup from PB0 occurred + 0 + 1 + read-write + + + + + BOF_TUNE + BOF_TUNE + BOF_TUNE register + 0x58 + 0x20 + read-write + 0x4 + + + BOF_TUNE + BOF_TUNE: selection of the Bypass on the Fly LDO output voltage. +- 0: 1.2V +- 1: 1.2V +- 2: 1.2V +- 3: 1.3V +- 4: 1.4V (Default) +- 5: 1.5V +- 6: 1.6V +- 7: 1.7V +- 8: 1.8V +- 9: 1.9V +- 10: 2V +- 11: 2.1V +- 12: 2.2V +- 13: 2.3V +- 14: 2.4V +- 15: 2.4V + 0 + 4 + read-write + + + + + DBGR + DBGR + DBGR register + 0x84 + 0x20 + read-write + 0x0 + + + DEEPSTOP2 + DEEPSTOP2 low power saving mode emulation enable +this bit enable an emulated debug DEEPSTOP low power mode. +If emulation is enabled, entering in DEEPSTOP mode, the v12i power domain still enters power saving mode, but its clock and power are maintained. + 0 + 1 + read-write + + + SMPSFRDY + SMPSFB Force ready check +When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. +- 0 : no effect (by default) +- 1 : SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1) + 7 + 1 + read-write + + + KELVIN_TEST + KELVIN_TEST[2:0]: Enable TEST mode Kelvin for LDO_RF (Write protected by IFR3 key) +- 000: 0mA (open) (default 0x0) +- 001 for 1mA +- 010 for 3mA +- 011 for 5mA +- 100 for 8mA +- 101 for 10mA +else: 0mA (open) for other combinations. + 8 + 3 + read-write + + + DIS_PRECH + DIS_PRECH[2:0]: disable precharge during deepstop (debug) +allowed combination are: +- 111: precharge and SMPS monitoring are disabled (whatever CR5.SMPSLPOPEN) +- 101: precharge are activated only at deepstop exit (to be used only with CR5.SMPSLPOPEN=1) +else: No effect (default 0x0) + 13 + 3 + read-write + + + + + EXTSRR + EXTSRR + EXTSRR register + 0x88 + 0x20 + read-write + 0x0 + + + DEEPSTOPF + DEEPSTOPF System DeepStop Flag +This bit is set by hardware and cleared only by a POR reset or by writing '1' in this bit field +- 0: System has not been in DEEPSTOP mode +- 1: System has been in DEEPSTOP mode + 9 + 1 + read-write + + + RFPHASEF + RFPHASEF RFPHASE Flag +This bit is set by hardware after a S3LP wake-up event (S3LP activation); it +is cleared either by software, writing '1' in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP. +- 0: RF IP does not require attention +- 1: RF IP awake and requesting system attention + 10 + 1 + read-write + + + + + DBGSMPS + DBGSMPS + DBGSMPS register + 0x8c + 0x20 + read-write + 0x8000 + + + TESTDIG + TESTDIG: SMPS TEST_DIG_3V3[3:0] SMPS control signal + 0 + 4 + read-write + + + TESTKEL + TESTKEL: SMPS TEST_KEL_3V3[1:0] SMPS control signal + 4 + 2 + read-write + + + HOT_STUP + HOT_STUP_3V3 SMPS control signal + 6 + 1 + read-write + + + NO_STUP + NO_STUP_3V3 SMPS control signal + 7 + 1 + read-write + + + TESTILIM + TESTILIM: SMPS TEST_ILIM_3V3 SMPS control signal + 8 + 1 + read-write + + + CTLRES_RAMP + CTLRES_RAM_3V3 SMPS control signal + 9 + 1 + read-write + + + DIS_BIG_MOS + DIS_BIG_MOS_3V3 SMPS control signal + 10 + 1 + read-write + + + TEST_OL + TEST_OL_3V3 SMPS control signal + 11 + 1 + read-write + + + DIS_ILIM + DIS_ILIM_3V3 SMPS control signal + 12 + 1 + read-write + + + ILIM_BOOST + ILIM_BOOST_3V3 SMPS current limitation Boost +- 0: Max current = 110mA (Default) +- 1: Max current = 130mA + 13 + 1 + read-write + + + BOF_CUR_SEL + BOF_CUR_SEL Bypass On the Fly current limitation +- 00 : 20mA +- 01 : 40mA +- 10 : 60mA (default) +- 11 : no limit + 14 + 2 + read-write + + + + + TRIMR + TRIMR + TRIMR register + 0x90 + 0x20 + read-only + 0x2304 + + + RFD_REG_TRIM + RFD_REG_TRIM[2:0]: RF LDO Trimming +By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. +if associated ENGTRIM is enabled the RF LDO trimming can be controlled by the dedicated ENGTRIM register. Default= '100'. + 0 + 3 + read-only + + + SPARE + 3 + 1 + read-only + + + TRIM_MR + TRIM_MR[3:0]: Main Regulator Voltage Trimming +By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. +if associated ENGTRIM.TRIMMREN is enabled the Main Regulator Voltage can be controlled by the dedicated ENGTRIM.TRIM_MR register. Default= '0000'. + 4 + 4 + read-only + + + SMPS_TRIM + SMPS_TRIM[2:0]: SMPS Output Voltage Trimming +By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. +if associated ENGTRIM is enabled the SMPS output voltage can be controlled by the dedicated ENGTRIM register. Default= '011'. + 8 + 3 + read-only + + + BOF_TRIM + BOF_TRIM[2:0]: Bypass On the Fly Output Voltage Trimming +By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. +if associated ENGTRIM is enabled the SMPS output voltage can be controlled by the dedicated ENGTRIM register. Default= '100'. + 11 + 3 + read-only + + + + + ENGTRIM + ENGTRIM + ENGTRIM register + 0x94 + 0x20 + read-write + 0x0 + + + TRIMRFDREGEN + TRIMRFDREGEN: trimming RFREG enabled +- 1: trimming bit applied from ENGTRIM register +- 0: trimming bit applied from OBL (can be read on TRIMR register) + 0 + 1 + read-write + + + TRIM_RFDREG + TRIM_RFDREG: RF Regulator Trimming +By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.TRIMRFDREGEN=1, the startup current can be controlled by this register. + 1 + 3 + read-write + + + SPARE + 4 + 1 + read-write + + + TRIMMREN + TRIMMREN: trimming MR enabled +- 1: trimming bit applied from ENGTRIM register +- 0: trimming bit applied from OBL (can be read on TRIMR register) + 5 + 1 + read-write + + + TRIM_MR + TRIM_MR: Main Regulator Output Voltage Trimming +By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.TRIMMREN=1, the startup current can be controlled by this register. + 6 + 4 + read-write + + + SMPSTRIMEN + SMPSTRIMEN: trimming SMPS enabled +- 1: trimming bit applied from ENGTRIM register +- 0: trimming bit applied from OBL (can be read on TRIMR register) + 10 + 1 + read-write + + + SMPS_TRIM + SMPS_TRIM: SMPS Output Voltage Trimming +By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.SMPSTRIMEN=1, the SMPS output voltage can be controlled by this register. + 11 + 3 + read-write + + + + + DBG_STATUS_REG1 + DBG_STATUS_REG1 + DBG_STATUS_REG1 register + 0x98 + 0x20 + read-only + 0x202 + + + SMPS_FSM_STATE + SMPS_FSM_STATE[2:0]: Indicates the current state of the SMPS FSM inside the PWRC.: +- 000: STARTUP +- 001: SMPS_REQ +- 010: SMPS_RUN +- 011: STOP +- 100: NOSMPS +- 101: PRECHARGE +- 110: NOSMPS_BOF + 0 + 3 + read-only + + + FLASH_FSM_STATE + FLASH_FSM_STATE[2:0]: Indicates the current state of the FLASH FSM inside the PWRC: +- 000: STATE1: FLASH POR +- 001: STATE2: FLASH PWRUP +- 010: STATE3: FLASH READY +- 101: STATE4: FLASH SWITCH OFF +- 110: STATE5: FLASH PWR DOWN + 8 + 3 + read-only + + + + + DBG_STATUS_REG2 + DBG_STATUS_REG2 + DBG_STATUS_REG2 register + 0x9c + 0x20 + read-only + 0x201 + + + PMU_FSM_STATE + PMU_FSM_STATE[3:0]: Indicates the current state of the PMU FSM inside the PWRC. +- 0000: POR +- 0001: RUN +- 0010: DS ENTRY +- 0011: WAIT1 +- 0100: WAIT2 +- 0101: WAIT +- 0110: WAIT3 +- 0111: WAIT4 +- 1000: ISOLATION +- 1001: DEEPSTOP +- 1010: SHUTDOWN +- 1011: DEEPSTOP EXIT + 0 + 4 + read-only + + + RAM_FSM_STATE + RAM_FSM_STATE[1:0]: Indicates the current state of the RAM FSM inside the PWRC: +- 00: POR +- 01: POWER UP +- 10: READY +- 11: OFF + 8 + 2 + read-only + + + + + ENGTRIM2 + ENGTRIM2 + ENGTRIM2 register + 0xa0 + 0x20 + read-write + 0x0 + + + BOFTRIMEN + BOFTRIMEN: trimming BOF enabled +- 1: trimming bit applied from ENGTRIM2 register +- 0: trimming bit applied from OBL (can be read on TRIMR register) + 0 + 1 + read-write + + + BOF_TRIM + SMPS_TRIM: SMPS Output Voltage Trimming +By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.BOFTRIMEN=1, the SMPS output voltage can be controlled by this register. + 1 + 3 + read-write + + + + + + + RCC + RCC + 0x48400000 + + 0x0 + 0xB0 + registers + + + RCC + Reset and Clock Controller + 1 + + + + CR + CR + CR register + 0x0 + 0x20 + read-write + 0x00001400 + + + LSION + Internal Low Speed oscillator enable +Set and reset by software. +Reset source only for this field: PORESETn +0: LSI RC oscillator OFF +1: LSI RC oscillator ON + 2 + 1 + read-write + + + LSIRDY + Internal Low Speed oscillator Ready +Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. +Reset source only for this field: PORESETn +0: LSI RC oscillator not ready +1: LSI RC oscillator ready + 3 + 1 + read-only + + + LSEON + External Low Speed Clock enable. +Set and reset by software. +Reset source only for this field: PORESETn +0: LSE oscillator OFF +1: LSE oscillator ON +Note that enablng this bit, the configuration of PB12 and PB13 will be bypassed (whatever DFTMUX or AF selection) + 4 + 1 + read-write + + + LSERDY + External Low Speed Clock ready flag. +Set by hardware to indicate that LSE oscillator is stable. +0: LSE oscillator not ready +1: LSE oscillator ready + 5 + 1 + read-only + + + LSEBYP + External Low Speed Clock bypass. +Set and reset by software. +Reset source only for this field: PORESETn +0: LSE oscillator bypass OFF +1: LSE oscillator bypass ON +Note that enablng this bit, the configuration of PB13 will be bypassed (whatever DFTMUX or AF selection) + 6 + 1 + read-write + + + LOCKDET_NSTOP + Lock detector Nstop value +When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0. + 7 + 3 + read-write + + + HSIRDY + Internal High Speed clock ready flag. +Set by hardware to indicate that internal RC 64MHz oscillator is stable. +This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request). +0: internal RC 64 MHz oscillator not ready +1: internal RC 64 MHz oscillator ready + 10 + 1 + read-only + + + HSEPLLBUFON + External High Speed Clock Buffer for PLL RF enable. +Set and reset by software. +0: HSE PLL Buffer OFF +1: HSE PLL Buffer ON (default) + 12 + 1 + read-write + + + HSIPLLON + Internal High Speed Clock PLL enable +0: PLL is OFF +1: PLL is ON + 13 + 1 + read-write + + + HSIPLLRDY + Internal High Speed Clock PLL ready flag. +0: PLL is unlocked +1: PLL is locked + 14 + 1 + read-only + + + FMRAT + Force MRSUBG accurate clock ready status (for debug purpose) +0: no effect +1: active_transmission is force to '1' whatever the HSIPLLRDY/HSE status + 15 + 1 + read-write + + + HSEON + External High Speed Clock enable. +Set and reset by software. +in low power mode, HSE is turned off. +HSE is turned ON only when RFSUBG LDO is Ready +0: HSE oscillator OFF +1: HSE oscillator ON + 16 + 1 + read-write + + + HSERDY + External High Speed Clock ready flag. +Set by hardware to indicate that HSE oscillator is stable. +0: HSE oscillator not ready +1: HSE oscillator ready + 17 + 1 + read-only + + + + + ICSCR + ICSCR + ICSCR register + 0x4 + 0x20 + read-write + 0x3f000000 + + + LSITRIMEN + Low Speed oscillator trimming enable +Set and reset by software. +Reset source only for this field: PORESETn +0: LSI oscillator Bias trimming disabled +1: LSI oscillator Bias trimming enabled + 0 + 1 + read-write + + + LSITRIMOK + LSITRIMOK: Low Speed oscillator trimming OK +Set and reset by hardware to indicate when the Low Speed Internal RC oscillator has reached an optimal trimming of its bias current; this bit is only valid when LSITRIMEN is active. +0: LSI Bias trimming (LSIBW) is not good +1: LSI Bias trimming (LSIBW) value is OK + 1 + 1 + read-only + + + LSIBW + Trimming in test mode +The value stored is the correspondent Engi Byte and represents the actual value driving the input of the hardware macro. +This value is loaded soon after the completion of the Option Byte Loading procedure. +This field is directly writeable only in Test Mode. + 2 + 4 + read-only + + + HSITRIMOFFSET + ICSCR[18:16] = HSITRIMOFFSET[2:0]: High Speed oscillator signed trimming offset + 000: 0 (+ 0 MHz / default) + 001: 1 (-0.5 MHz) + 010: 2 (-1MHz) + 011: 3 (-1.5 MHz) + 100: -1 (+2 MHz) + 101: -2 (+1.5MHz) + 110: -3 (+1 MHz) + 111: -4 (+0.5 MHz) + 16 + 3 + read-write + + + HSITRIM + High Speed Internal clock trimming. +This value is loaded soon after the completion of the Option Byte Loading procedure. +When max value 0x3f is set, HSI is less than 64MHz + 24 + 6 + read-only + + + + + CFGR + CFGR + CFGR register + 0x8 + 0x20 + read-write + 0x00000240 + + + HSESEL + Clock source selection request: +0: HSI clock source is requested (default) +1: HSE clock source is requested + 1 + 1 + read-write + + + STOPHSI + Stop HSI clock source request +0: HSI is enabled (default) +1: disable HSI is requested + 2 + 1 + read-write + + + HSESEL_STATUS + Clock source selection Status +0: HSI clock source is selected +1: HSE clock source is selected +Mirror the actual system clock source, depending on clock switching mechanism and limitations + 3 + 1 + read-only + + + CLKSYSDIV + system clock frequency selection request +000: div1 (HSI 64M / HSE 48M) +001: div2 (HSI 32M / HSE 24M) +010: div4/div3 (HSI/HSE) (16M) +011: div8/div6 (HSI/HSE) (8M) * +100: div16/div12 (HSI/HSE) (4M) * +101: div32/div24 (HSI/HSE) (2M) * +110: div64/div48 (HSI/HSE) (1M) * +Note: behavior depends on depending on CFGR.HSESEL and (*) APB2ENR.MRSUBGEN or LPAWUREN register + 5 + 3 + read-write + + + CLKSYSDIV_STATUS + system clock frequency selection status +000: div1 (HSI 64M / HSE 48M) +001: div2 (HSI 32M / HSE 24M) +010: div4/div3 (HSI/HSE) (16M) +011: div8/div6 (HSI/HSE) (8M) +100: div16/div12 (HSI/HSE) (4M) +101: div32/div24 (HSI/HSE) (2M) +110: div64/div48 (HSI/HSE) (1M) +Note: behavior depends on depending on CFGR.HSESEL and APB2ENR.MRSUBGEN register + 8 + 3 + read-only + + + SMPSDIV + SMPS clock prescaling factor to generate 4MHz or 8MHz +0: SMPS clock 8MHz (default ) +1: SMPS clock 4MHz + 12 + 1 + read-write + + + LPUCLKSEL + LPUCLKSEL: Selection of LPUART clock +0: 16 MHz peripheral clock (default) +1: LSE clock (Mandatory in LPUART deepstop mode) + 13 + 1 + read-write + + + CLKSLOWSEL + slow clock source selection +Set by software to select the clock source. This is no glitch free mechanism +Reset source only for this field: PORESETn +00: '0' (default) +01: LSE oscillator clock used as slow clock +10: LSI oscillator clock used as slow clock +11:HSI_64M divided by 2048 used as slow clock + 15 + 2 + read-write + + + IOBOOSTEN + IOBOOSTEN: IO BOOSTER enable +0: IO BOOSTER block is disabled +1: IO BOOSTER block is enabled. + 17 + 1 + read-write + + + LCOEN + LCOEN: LCO enable on PA10 also in deepstop. +0: LCO output on PA10 is disabled +1: LCO output on PA10 is enabled. + 19 + 1 + read-write + + + SPI3I2SCLKSEL + SPI3I2SCLKSEL: Selection of I2S clock for SPI3 IP. +00: 32 MHz peripheral clock (default) +01: 16 MHz peripheral clock +10: CLK_SYS +11: CLK_SYS +Note: the I2S clock frequency must be higher or equal to the system clock (configured +through RCC_CFGR.CLKSYSDIV[2:0] bit field). + 22 + 2 + read-write + + + LCOSEL + Low speed Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. +Reset source only for this field: PORESETn +00: LCO output disabled, no clock on LCO +01: not used +10: internal 32 KHz (LSI) oscillator clock selected +11: external 32 KHz (LSE) oscillator clock selected + 24 + 2 + read-write + + + MCOSEL + Main Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. +000: MCO output disabled, no clock on MCO +001: system clock selected +010: na +011: internal RC 64 MHz (HSI) oscillator clock selected +100: external oscillator (HSE) clock selected +101: internal RC 64 MHz (HSI) oscillator divided by 2048 and used as slow clock selected +110: SMPS clock selected +111: AUX ADC ANA clock selected + 26 + 3 + read-write + + + CCOPRE + Configurable Clock Output Prescaler. +Set and reset by software. +Glitches propagation if CCOPRE is modified after CCO output is enabled. +000: CCO clock is divided by 1 +001: CCO clock is divided by 2 +010: CCO clock is divided by 4 +011: CCO clock is divided by 8 +100: CCO clock is divided by 16 +101: CCO clock is divided by 32 +Others: not used + 29 + 3 + read-write + + + + + CSSWCR + CSSWCR + CSSWCR register + 0xc + 0x20 + read-write + 0x00000000 + + + LSISWTRIMEN + Low Speed oscillator trimming by SW enable +Set and reset by software. +Reset source only for this field: PORESETn +0: LSI oscillator Bias trimming by SW disabled +1: LSI oscillator Bias trimming by SW enabled + 0 + 1 + read-write + + + LSISWBW + Low Speed Internal clock trimming value to set by SW +Reset source only for this field: PORESETn + 1 + 4 + read-write + + + LSEDRV + Maximum Crystal gm for Low Speed External XO +(to connect to XTDRV of 32kHz LSE XO => into IO V33?) to amplify drinving capacity modulation +Set by software. +Reset source only for this field: PORESETn +00: 0.0, low drive capability +01: 0.1, medium low drive capability +10: 1.0, medium high drive capability +11: 1.1, highdrive capability + 5 + 2 + read-write + + + HSISWTRIMEN + High Speed oscillator trimming by SW enable +Set and reset by software. +0: HSI oscillator Bias trimming by SW disabled +1: HSI oscillator Bias trimming by SW enabled + 23 + 1 + read-write + + + HSITRIMSW + High Speed Internal clock trimming value to set by SW. + 24 + 6 + read-write + + + + + KRMR + KRMR + KRMR register + 0x10 + 0x20 + read-write + 0x000000000 + + + KRM_EN + KRM_EN: Variable rate multiplier Enable +Reset source only for this field: PORESETn +0: KRM is disabled (default) +1: KRM is enabled. + 0 + 1 + read-write + + + KRM + KRM[4:0] :SMPS clock dividing Ratio (CLK_SPMS_KRM frequency= CLK_ROOT frequency +(depending on RCC_CFGR.HSESEL) divided by KRM when KRMEN=1) +Reset source only for this field: PORESETn +- 0x00 to 0x08: SMPS clock frequency equals CLK_ROOT/8 (8.00 MHz / 6.00 MHz) +- 0x09: SMPS clock frequency equals CLK_ROOT/9 (7.11 MHz / 5.33 MHz) +- 0x0A: SMPS clock frequency equals CLK_ROOT/10 (6.40 MHz / 4.80 MHz) +- 0x0B: SMPS clock frequency equals CLK_ROOT/11 (5.82 MHz / 4.36 MHz) +- 0x0C: SMPS clock frequency equals CLK_ROOT/12 (5.33 MHz / 4.00 MHz) +- 0x0D: SMPS clock frequency equals CLK_ROOT/13 (4.92 MHz / 3.69 MHz) +- 0x0E: SMPS clock frequency equals CLK_ROOT/14 (4.57 MHz / 3.43 MHz) +- 0x0F: SMPS clock frequency equals CLK_ROOT/15 (4.27 MHz / 3.20 MHz) +- 0x10: SMPS clock frequency equals CLK_ROOT/16 (4.00 MHz / 3.00 MHz) +- 0x1x: Reserved +Note: SMPS clock frequency must be selected in a range [4-8] MHz (depending on +RCC_KRMR.KRM and RCC_CFGR.HSESEL). + 1 + 5 + read-write + + + + + CIER + CIER + CIER register + 0x18 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization. +0: LSI ready interrupt disabled +1: LSI ready interrupt enabled + 0 + 1 + read-write + + + LSERDYIE + LSE Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. +0: LSE ready interrupt disabled +1: LSE ready interrupt enabled + 1 + 1 + read-write + + + HSIRDYIE + HSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization. +0: HSI ready interrupt disabled +1: HSI ready interrupt enabled + 3 + 1 + read-write + + + HSERDYIE + HSE Ready Interrupt Enable +Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization. +0: HSE ready interrupt disabled +1: HSE ready interrupt enabled + 4 + 1 + read-write + + + HSIPLLRDYIE + HSI PLL Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE. +0: HSI PLL ready interrupt disabled +1: HSI PLL ready interrupt enabled + 5 + 1 + read-write + + + HSIPLLUNLOCKDETIE + HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock. +0: HSI PLL unlock detection interrupt disabled +1: HSI PLL unlock detection interrupt enabled + 6 + 1 + read-write + + + RTCRSTIE + RTCRSTIE: RTC reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the RTC reset end. +0: HSI PLL unlock detection interrupt disabled +1: HSI PLL unlock detection interrupt enabled + 7 + 1 + read-write + + + WDGRSTIE + WDGRSTIE: Watchdog reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the watchdog reset end. +0: interrupt disabled +1: interrupt enabled + 8 + 1 + read-write + + + LPURSTIE + LPURSTIE: LPUART reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the LPUART reset end. +0: interrupt disabled +1: interrupt enabled + 9 + 1 + read-write + + + LCDRSTIE + LCDRSTIE: LCD reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the LCD reset end. +0: interrupt disabled +1: interrupt enabled + 10 + 1 + read-write + + + LCSCRSTIE + LCSCRSTIE: LCSC reset release interrupt enable. +0: LCSC reset release interrupt is disabled. +1: LCSC reset release interrupt is enabled. + 13 + 1 + read-write + + + + + CIFR + CIFR + CIFR register + 0x1c + 0x20 + read-write + 0x00000008 + + + LSIRDYIF + LSI Ready Interrupt flag +Set by hardware when LSI clock becomes stable. +0: No clock ready interrupt caused by the internal RC 32 KHz oscillator +1: Clock ready interrupt caused by the internal RC 32 kHz oscillator + 0 + 1 + read-write + + + LSERDYIF + LSE Ready Interrupt Flag. +Set by hardware when LSE clock becomes stable. +0: No clock ready interrupt caused by the LSE oscillator +1: Clock ready interrupt caused by the LSE oscillator + 1 + 1 + read-write + + + HSIRDYIF + HSI Ready Interrupt Flag. +Set by hardware when HSI becomes stable. +0: No clock ready interrupt caused by the HSI oscillator +1: Clock ready interrupt caused by the HSI oscillator + 3 + 1 + read-write + + + HSERDYIF + HSE Ready Interrupt Flag. +Set by hardware when HSE becomes stable. +0: No clock ready interrupt caused by the HSE oscillator +1: Clock ready interrupt caused by the HSE oscillator + 4 + 1 + read-write + + + HSIPLLRDYIF + HSI PLL Ready Interrupt Flag. +Set by hardware when HSI PLL 64MHz becomes stable. +0: No clock ready interrupt caused by the HSI PLL64 MHz oscillator +1: Clock ready interrupt caused by the HSI PLL64 MHz oscillator + 5 + 1 + read-write + + + HSIPLLUNLOCKDETIF + HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag. + 6 + 1 + read-write + + + RTCRSTIF + RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 7 + 1 + read-write + + + WDGRSTIF + WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 8 + 1 + read-write + + + LPURSTIF + LPUART reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 9 + 1 + read-write + + + LCDRSTIF + LCD reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 10 + 1 + read-write + + + LCSCRSTIF + LCSC reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 13 + 1 + read-write + + + + + CSCMDR + CSCMDR + CSCMDR register + 0x20 + 0x20 + read-write + 0x00000080 + + + REQUEST + Request for system clock switching +Cleared by hardware when system clock frequency switch is done +0: To cancel an ongiong request - still possible until IRQ assertion +1: To update the system clock frequency + 0 + 1 + read-write + + + CLKSYSDIV_REQ + system clock frequency selection request +000: div1 (HSI 64M / HSE) (48M) +001: div2 (HSI 32M / HSE (24M*) +010: div4/div3 (HSI/HSE) (16M) +011: div8/div6 (HSI/HSE) (8M) * +100: div16/div12 (HSI/HSE) (4M) * +101: div32/div24 (HSI/HSE) (2M) * +110: div64/div48 (HSI/HSE) (1M) * +Note: behavior depends on depending on CFGR.HSESEL and (*) APB2ENR.MRSUBGEN or LPAWUREN + 1 + 3 + read-write + + + STATUS + Status of clock switch sequence +00: IDLE no switch requested +01: ONGOING clock frequency switch is ongoing +10: DONE clock frequency switch done +11: Reserved + 4 + 2 + read-only + + + EOFSEQ_IE + End of sequence Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the clock system switch. +0: End of sequence interrupt disabled +1: End of sequence interrupt enabled + 6 + 1 + read-write + + + EOFSEQ_IRQ + End of Sequence flag +Set by hardware when clock system swtich is ended +0: No end of sequence event occured +1: End of sequece event occured + 7 + 1 + read-write + + + + + AHBRSTR + AHBRSTR + AHBRSTR register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMARST + DMA and DMAMUX reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 0 + 1 + read-write + + + GPIOARST + GPIOA reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 2 + 1 + read-write + + + GPIOBRST + GPIOB reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 3 + 1 + read-write + + + CRCRST + CRC reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 12 + 1 + read-write + + + RNGRST + RNG reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 18 + 1 + read-write + + + AESRST + AES reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 20 + 1 + read-write + + + + + APB0RSTR + APB0RSTR + APB0RSTR register + 0x34 + 0x20 + read-write + 0x00000000 + + + TIM2RST + TIM2RST: TIM2 reset. +0: TIM2 IP is not under reset. +1: TIM2 IP is under reset. + 0 + 1 + read-write + + + TIM16RST + TIM16RST: TIM16 reset. +0: TIM16 IP is not under reset. +1: TIM16 IP is under reset. + 1 + 1 + read-write + + + SYSCFGRST + SYSCFGRST: system controller reset. +0: system controller IP is not under reset. +1: system controller IP is under reset. + 8 + 1 + read-write + + + LCDCRST + LCDCRST: LCD controller reset. +0: LCD controller IP is not under reset. +1: LCD controller IP is under reset. + 9 + 1 + read-write + + + COMPRST + COMPRST: COMP reset. +0: COMP IP is not under reset. +1: COMP IP is under reset. + 10 + 1 + read-write + + + DACRST + DACRST: DAC reset. +0: DAC IP is not under reset. +1: DAC IP is under reset. + 11 + 1 + read-write + + + RTCRST + RTCRST: RTC reset. +0: RTC IP is not under reset. +1: RTC IP is under reset. + 12 + 1 + read-write + + + LCSCRST + LCSCRST: LCSC reset. +0: LCSC IP is not under reset. +1: LCSC IP is under reset. + 13 + 1 + read-write + + + WDGRST + WDGRST: Watchdog reset. +0: Watchdog IP is not under reset. +1: Watchdog IP is under reset. + 14 + 1 + read-write + + + DBGMCURST + DBGMCURST: DBGMCU reset. +0: DBGMCU IP is not under reset. +1: DBGMCU IP is under reset. + 15 + 1 + read-write + + + + + APB1RSTR + APB1RSTR + APB1RSTR register + 0x38 + 0x20 + read-write + 0x00000000 + + + SPI1RST + SPI1 reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 0 + 1 + read-write + + + ADCRST + ADC reset for Aux-ADC IP +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 4 + 1 + read-write + + + LPUARTRST + LPUART reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 8 + 1 + read-write + + + USARTRST + USART reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 10 + 1 + read-write + + + SPI3RST + SPI3 reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 14 + 1 + read-write + + + I2C1RST + I2C1 reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 21 + 1 + read-write + + + I2C2RST + I2C2 reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 23 + 1 + read-write + + + + + APB2RSTR + APB2RSTR + APB2RSTR register + 0x40 + 0x20 + read-write + 0x00000000 + + + MRSUBGRST + Radio MRSUBG reset. +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 0 + 1 + read-write + + + LPAWURRST + Bubble reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 3 + 1 + read-write + + + + + AHBENR + AHBENR + AHBENR register + 0x50 + 0x20 + read-write + 0x0000000C + + + DMAEN + DMA and DMAMUX enable +Set and enable by software. +0: does not enable +1: enable + 0 + 1 + read-write + + + GPIOAEN + GPIOA enable. It must be enabled by default + 2 + 1 + read-write + + + GPIOBEN + GPIOB enable. It must be enabled by default + 3 + 1 + read-write + + + CRCEN + CRC enable +Set and enable by software. +0: does not enable +1: enable + 12 + 1 + read-write + + + RNGEN + RNG clock enable +Set and enable by software. +0: does not enable +1: enable + 18 + 1 + read-write + + + AESEN + AESEN: AES clock enable. +0: AES IP is clock gated. +1: AES IP is clocked. + 20 + 1 + read-write + + + + + APB0ENR + APB0ENR + APB0ENR register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM2: Advanced Timer clock enable +Set and enable by software. +0: clock disable +1: clock enable + 0 + 1 + read-write + + + TIM16EN + TIM16: Advanced Timer clock enable +Set and enable by software. +0: clock disable +1: clock enable + 1 + 1 + read-write + + + SYSCFGEN + SYSTEM CONFIG clock enable +Set and enable by software. +0: clock disable +1: clock enable + 8 + 1 + read-write + + + LCDEN + LCD clock enable +Set and enable by software. +0: clock disable +1: clock enable + 9 + 1 + read-write + + + COMPEN + COMP clock enable +Set and enable by software. +0: clock disable +1: clock enable + 10 + 1 + read-write + + + DACEN + DAC clock enable +Set and enable by software. +0: clock disable +1: clock enable + 11 + 1 + read-write + + + RTCEN + RTC clock enable +Set and enable by software. +Reset source only for this field: PORESETn +0: clock disable +1: clock enable + 12 + 1 + read-write + + + LCSCEN + LCSC clock enable. +Set and enable by software. +0: clock disable +1: clock enable + 13 + 1 + read-write + + + WDGEN + Watchdog clock enable. +Set and enable by software. +0: clock disable +1: clock enable + 14 + 1 + read-write + + + DBGMCUEN + DBG MCU clock enable. +Set and enable by software. +0: clock disable +1: clock enable + 15 + 1 + read-write + + + + + APB1ENR + APB1ENR + APB1ENR register + 0x58 + 0x20 + read-write + 0x00000000 + + + SPI1EN + SPI1 clock enable +Set and enable by software. +0: clock disable +1: clock enable + 0 + 1 + read-write + + + ADCDIGEN + AUXADC clock enable for Aux-ADC digital clock +Set and enable by software. +0: clock disable +1: clock enable + 4 + 1 + read-write + + + ADCANAEN + ADC clock enable for Aux-ADC analog clock +Set and enable by software. +0: clock disable +1: clock enable + 5 + 1 + read-write + + + LPUARTEN + LPUART clock enable +Set and enable by software. +0: clock disable +1: clock enable + 8 + 1 + read-write + + + USARTEN + USART clock enable +Set and enable by software. +0: clock disable +1: clock enable + 10 + 1 + read-write + + + SPI3EN + SPI3 clock enable +Set and enable by software. +0: clock disable +1: clock enable + 14 + 1 + read-write + + + I2C1EN + I2C1 clock enable +Set and enable by software. +0: clock disable +1: clock enable + 21 + 1 + read-write + + + I2C2EN + I2C2 clock enable +Set and enable by software. +0: clock disable +1: clock enable + 23 + 1 + read-write + + + + + APB2ENR + APB2ENR + APB2ENR register + 0x60 + 0x20 + read-write + 0x00000000 + + + MRSUBGEN + MRSUBG clock enable. +Note: when this bit is '1', it must prevent clk_sys different from 16, 32, 64. If the configured clock is lower than 16MHz (1, 2, 4 or 8 MHz) or equal to 24MHz, clk_sys must be 16MHz +0: clock disable +1: clock enable + 0 + 1 + read-write + + + LPAWUREN + Bubble clock enable +Set and enable by software. +0: clock disable +1: clock enable + 3 + 1 + read-write + + + + + DBGR + DBGR + DBGR register + 0x80 + 0x20 + read-write + 0x00000000 + + + DBGHSIOFF + used for debug or test +0: No effect (default) +1: HSI forced off. + 19 + 1 + read-write + + + DBGBYPHSI + used for debug mode with HSI bypassed by HSE +0: No effect (default) +1: HSI bypassed HSE. + 20 + 1 + read-write + + + DBGXOEXT + used for debug mode with HSE bypassed by FXTAL_IN clock and ZIV12 output used. +0: No effect (default) +1: HSE bypassed by FXTAL_IN clock and ZIV12 output used. + 21 + 1 + read-write + + + FORCEXO48MREADY + FORCEXO48MREADY Force XO48M Ready input signal +This bit is for debug and force the XO48M ready input, in order to bypass XO48M comparators. +0: No effect (default) +1: Force XOREADY=1 + 22 + 1 + read-write + + + + + CSR + CSR + CSR register + 0x94 + 0x20 + read-write + 0x0C000000 + + + RMVF + Remove reset flag +Set by software to clear the value of the reset flags. +It auto clears by HW after clearing reason flags +0: Nothing done +1: Reset the value of the reset flags + 23 + 1 + write-only + + + PADRSTF + SYSTEM reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a reset from pad occurs. +0: No reset from pad occurred +1: Reset from pad occurred + 26 + 1 + read-only + + + PORRSTF + POWER reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a power reset occurs from LPMURESET block. +0: No POWER reset occurred +1: POWER reset occurred + 27 + 1 + read-only + + + SFTRSTF + Software reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a software reset occurs. +0: No software reset occurred +1: Software reset occurred + 28 + 1 + read-only + + + WDGRSTF + Watchdog reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a watchdog reset from V33 domain occurs. +0: No watchdog reset occurred +1: Watchdog reset occurred + 29 + 1 + read-only + + + LOCKUPRSTF + LOCK UP reset flag from CM0 +Reset by software by writing the RMVF bit. +Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals. +0: No lockup reset occurred +1: lockup reset occurred + 30 + 1 + read-only + + + + + RFSWHSECR + RFSWHSECR + RFSWHSECR register + 0x98 + 0x20 + read-write + 0x00000803F + + + GMC + GMC[6:5]: High speed external XO current control reference +00: 10 uA +01: 20 uA +1x: 40 uA +GMC[4:0]: High speed external XO current control multiplying factor +IcoreHSE= GMC[4:0] * GMC[6:5] +Example: GMC[6:0]=0x1111001 -> IcoreHSE=25*40uA / Default 3F: IcoreHSE= 10uA x 31 = 310uA +Note: this value is set only by software. + 0 + 7 + read-write + + + SWXOTUNEEN + RF-HSE capacitor bank tuning by SW enable +Set by software + 7 + 1 + read-write + + + SWXOTUNE + RF-HSE capacitor bank tuning value by SW +Set by software + 8 + 6 + read-write + + + ISTARTUP + RF-HSE Startup current +Set by software +Default value 2 + 14 + 2 + read-write + + + AMPLTHRESH + RF-HSE Amplitude Control threshold +Set by software +Default value 0 + 16 + 3 + read-write + + + + + RFHSECR + RFHSECR + RFHSECR register + 0x9c + 0x20 + read-only + 0x000000000 + + + XOTUNE + RF-HSE capacitor bank tuning +Set by option byte loading soon after Power On Reset. + 0 + 6 + read-only + + + AMPLREADY + RF-HSE Amplitude Control Ready output + 6 + 1 + read-only + + + + + AHBSMENR + AHBSMENR + AHBSMENR register + 0xa0 + 0x20 + read-write + 0x0014160F + + + DMASMEN + DMA clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: DMA clock disabled in Sleep mode +- 1: DMA clock enabled in Sleep mode (if enabled in DMAEN) + 0 + 1 + read-write + + + FLASHSMEN + Flash clocks enable during Flash Sleep PD and CPU Sleep mode bit +This bit is set and reset by software. +- 0: Flash clocks are disabled in Flash Sleep PD* and CPU Sleep mode +- 1: Flash clocks are enabled in Sleep mode +Note: Flash Sleep PD is enabled through nvm_control register CONFIG.SLEEP_PD + 1 + 1 + read-write + + + GPIOASMEN + GPIOA clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: GPIOA clock disabled in Sleep mode +- 1: GPIOA clock enabled in Sleep mode (if enabled by GPIOAEN) + 2 + 1 + read-write + + + GPIOBSMEN + GPIOB clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: GPIOB clock disabled in Sleep mode +- 1: GPIOB clock enabled in Sleep mode (if enabled in GPIOBEN) + 3 + 1 + read-write + + + SRAM0SMEN + SRAM0 clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SRAM0 clock disabled in Sleep mode +- 1: SRAM0 clock enabled in Sleep mode + 9 + 1 + read-write + + + SRAM1SMEN + SRAM1 clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SRAM1 clock disabled in Sleep mode +- 1: SRAM1 clock enabled in Sleep mode + 10 + 1 + read-write + + + CRCSMEN + CRC clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: CRC clock disabled in Sleep mode +- 1: CRC clock enabled in Sleep mode (if enabled in CRCEN) + 12 + 1 + read-write + + + RNGSMEN + RNG bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: RNG bus clock disabled in Sleep mode +- 1: RNG bus clock enabled in Sleep mode (if enabled in RNGEN) + 18 + 1 + read-write + + + AESSMEN + AES bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: AES bus clock disabled in Sleep mode +- 1: AES bus clock enabled in Sleep mode (if enabled in AESEN) + 20 + 1 + read-write + + + + + APB0SMENR + APB0SMENR + APB0SMENR register + 0xa4 + 0x20 + read-write + 0x0000FF03 + + + TIM2SMEN + TIM2 bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: TIM2 bus clock disabled in Sleep mode +- 1: TIM2 bus clock enabled in Sleep mode (if enabled in TIM2EN) + 0 + 1 + read-write + + + TIM16SMEN + TIM16 bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: TIM16 bus clock disabled in Sleep mode +- 1: TIM16 bus clock enabled in Sleep mode (if enabled in TIM16EN) + 1 + 1 + read-write + + + SYSCFGSMEN + SYSCFG bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SYSCFG bus clock disabled in Sleep mode +- 1: SYSCFG bus clock enabled in Sleep mode (if enabled in SYSCFGEN) + 8 + 1 + read-write + + + LCDCSMEN + LCDC bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: LCDC bus clock disabled in Sleep mode +- 1: LCDC bus clock enabled in Sleep mode (if enabled in LCDCEN) + 9 + 1 + read-write + + + COMPSMEN + COMP bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: COMP bus clock disabled in Sleep mode +- 1: COMP bus clock enabled in Sleep mode (if enabled in COMPEN) + 10 + 1 + read-write + + + DACSMEN + DAC bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: DAC bus clock disabled in Sleep mode +- 1: DAC bus clock enabled in Sleep mode (if enabled in DACEN) + 11 + 1 + read-write + + + RTCSMEN + RTC bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: RTC bus clock disabled in Sleep mode +- 1: RTC bus clock enabled in Sleep mode (if enabled in RTCEN) + 12 + 1 + read-write + + + LCSCSMEN + LCSC bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: LCSC bus clock disabled in Sleep mode +- 1: LCSC bus clock enabled in Sleep mode (if enabled in LCSCEN) + 13 + 1 + read-write + + + WDGSMEN + WDG clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: WDG clock disabled in Sleep mode +- 1: WDG clock enabled in Sleep mode (if enabled in WDGEN) + 14 + 1 + read-write + + + DBGMCUSMEN + DBGMCU clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: DBGMCU clock disabled in Sleep mode +- 1: DBGMCU clock enabled in Sleep mode (if enabled in DBGMCUEN) + 15 + 1 + read-write + + + + + APB1SMENR + APB1SMENR + APB1SMENR register + 0xa8 + 0x20 + read-write + 0x00A04511 + + + SPI1SMEN + SPI1 bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SPI1 bus clock disabled in Sleep mode +- 1: SPI1 bus clock enabled in Sleep mode (if enabled in SPI1EN) + 0 + 1 + read-write + + + ADCDIGSMEN + ADCDIG bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: ADCDIG bus clock disabled in Sleep mode +- 1: ADCDIG bus clock enabled in Sleep mode (if enabled by ADCDIGEN) + 4 + 1 + read-write + + + LPUARTSMEN + LPUART bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: LPUART bus clock disabled in Sleep mode +- 1: LPUART bus clock enabled in Sleep mode (if enabled in LPUARTEN) + 8 + 1 + read-write + + + USARTSMEN + USART bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: USART bus clock disabled in Sleep mode +- 1: USART bus clock enabled in Sleep mode (if enabled in USARTEN) + 10 + 1 + read-write + + + SPI3SMEN + SPI3 bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SPI3 bus clock disabled in Sleep mode +- 1: SPI3 bus clock enabled in Sleep mode (if enabled in SPI3EN) + 14 + 1 + read-write + + + I2C1SMEN + I2C1 clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: I2C1 clock disabled in Sleep mode +- 1: I2C1 clock enabled in Sleep mode (if enabled in I2C1EN) + 21 + 1 + read-write + + + I2C2SMEN + I2C2 clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: I2C2 clock disabled in Sleep mode +- 1: I2C2 clock enabled in Sleep mode (if enabled in I2C2EN) + 23 + 1 + read-write + + + + + + + RETAINED + RETAINED + 0x49000780 + + 0x0 + 0x80 + registers + + + + RFIP_WAKEUPTIME + RFIP_WAKEUPTIME + RFIP_WAKEUPTIME register + 0x0 + 0x20 + read-only + 0x00000000 + + + RFIP_WAKEUPTIME + (Absolute) Target time to wakeup the RFIP. + 0 + 32 + read-only + + + + + CPU_WAKEUPTIME + CPU_WAKEUPTIME + CPU_WAKEUPTIME register + 0x4 + 0x20 + read-write + 0x00000000 + + + CPU_WAKEUPTIME + (Absolute) Target time to wakeup the CPU. + 1 + 31 + read-write + + + + + WAKEUP_CTRL + WAKEUP_CTRL + WAKEUP_CTRL register + 0x8 + 0x20 + read-write + 0x00000000 + + + SOC_WAKEUP_OFFSET + Delay to be considered by the Wakeup block to anticipate the wakeup request to the PWRC of the SoC versus the target to wakeup the RFIP (or the CPU). + 0 + 8 + read-write + + + CPU_WAKEUP_EN + Indicates if the wakeup timer has to wakeup the SoC (match on CPU_WAKEUPTIME[31:4] bit field only) + set the CPU_WAKEUP_F in the WAKEUP_IRQ_STATUS Misc register when match on CPU_WAKEUPTIME[31:0] occurs. + 30 + 1 + read-write + + + RFIP_WAKEUP_EN + Indicates if the wakeup timer has to wakeup the SoC (match on RFIP_WAKEUPTIME[31:4] bit field only) + trigger an event on the Sequencer and set the RFIP_WAKEUP_F in the WAKEUP_IRQ_STATUS Misc register when match on RFIP_WAKEUPTIME[31:0] occurs. + 31 + 1 + read-only + + + + + RRM_CMDLIST_PTR + RRM_CMDLIST_PTR + RRM_CMDLIST_PTR register + 0xc + 0x20 + read-write + 0x00000000 + + + CMDLIST_PTR_OFFSET + Contain the offset versus the SoC RAM base address where to find the RRM-UDRA command list entry point. + 0 + 16 + read-write + + + CMDLIST_PTR_VALID + Indicate if a command list has to be executed or not + + 31 + 1 + read-write + + + + + SEQ_GLOBALTABLE_PTR + SEQ_GLOBALTABLE_PTR + SEQ_GLOBALTABLE_PTR register + 0x10 + 0x20 + read-write + 0x00000000 + + + SEQ_GLOBALTABLE_PTR + Contain the offset versus the SoC RAM base address of the GlobalConfiguration RAM table entry point. + 0 + 16 + read-write + + + + + + + RNG + RNG + 0x48600000 + + 0x0 + 0x1000 + registers + + + + RNG_CR + RNG_CR + RNG_CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + RNG_DIS + RNG Disable bit. + 2 + 1 + read-write + + + TST_CLK + RNG Test Clock bit. + 3 + 1 + read-write + + + + + RNG_SR + RNG_SR + RNG_SR register + 0x04 + 0x20 + read-write + 0x00000000 + + + RNGRDY + New Random Value Ready. + 0 + 1 + read-only + + + REVCLK + RNGCLK Clock Reveal bit. + 1 + 1 + read-only + + + FAULT + Fault Reveal bit. + 2 + 1 + read-write + + + + + RNG_VAL + RNG_VAL + RNG_VAL register + 0x08 + 0x20 + read-only + 0x00000000 + + + RANDOM_VALUE + Random Value + 0 + 16 + read-only + + + + + RNG_TCR + RNG_TCR + RNG_TCR register + 0x80 + 0x20 + read-write + 0x00000000 + + + TCR + Test-control register + 0 + 1 + read-write + + + + + RNG_ITIP + RNG_ITIP + RNG_ITIP register + 0x84 + 0x20 + read-write + 0x00000000 + + + ITIP + Integration-test input register + 0 + 1 + read-write + + + + + RNGPeriphID0 + RNGPeriphID0 + RNGPeriphID0 register + 0xFE0 + 0x20 + read-only + 0x000000E1 + + + PartNumber0 + These bits are read back as 0xE1 + 0 + 8 + read-only + + + + + RNGPeriphID1 + RNGPeriphID1 + RNGPeriphID1 register + 0xFE4 + 0x20 + read-only + 0x0000005 + + + PartNumber1 + These bits are read back as 0x05 + 0 + 4 + read-only + + + Designer0 + These bits are read back as 0x00 + 4 + 4 + read-only + + + + + RNGPeriphID2 + RNGPeriphID2 + RNGPeriphID2 register + 0xFE8 + 0x20 + read-only + 0x00000028 + + + Designer1 + These bits are read back as 0x08 + 0 + 4 + read-only + + + Revision + These bits are read back as 0x02 + 4 + 4 + read-only + + + + + RNGPeriphID3 + RNGPeriphID3 + RNGPeriphID3 register + 0xFEC + 0x20 + read-only + 0x00000000 + + + Configuration + These bits are read back as 0x00 + 0 + 8 + read-only + + + + + RNGPCellID0 + RNGPCellID0 + RNGPCellID0 register + 0xFF0 + 0x20 + read-only + 0x0000000D + + + RNGPCellID0 + These bits are read back as 0x0D + 0 + 8 + read-only + + + + + RNGPCellID1 + RNGPCellID1 + RNGPCellID1 register + 0xFF4 + 0x20 + read-only + 0x000000F0 + + + RNGPCellID1 + These bits are read back as 0xF0 + 0 + 8 + read-only + + + + + RNGPCellID2 + RNGPCellID2 + RNGPCellID2 register + 0xFF8 + 0x20 + read-only + 0x00000005 + + + RNGPCellID2 + These bits are read back as 0x05 + 0 + 8 + read-only + + + + + RNGPCellID3 + RNGPCellID3 + RNGPCellID3 register + 0xFFC + 0x20 + read-only + 0x000000B1 + + + RNGPCellID3 + These bits are read back as 0xB1 + 0 + 8 + read-only + + + + + + + RTC + RTC + 0x40004000 + + 0x0 + 0x58 + registers + + + RTC + RTC interrupt + 11 + + + + RTC_TR + RTC_TR + RTC_TR register + 0x00 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation. +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + + + RTC_DR + RTC_DR + RTC_DR register + 0x04 + 0x20 + read-write + 0x00002101 + + + DU + Date units in BCD format. + 0 + 4 + read-write + + + DT + Date tens in BCD format. + 4 + 2 + read-write + + + MU + Month units in BCD format. + 8 + 4 + read-write + + + MT + Month tens in BCD format. + 12 + 1 + read-write + + + WDU + Week day units +000: forbidden +001: Monday +010: Tuesday +011: Wednesday +100: Thursday +101: Friday +110: Saturday +111: Sunday + 13 + 3 + read-write + + + YU + Year units in BCD format. + 16 + 4 + read-write + + + YT + Year tens in BCD format. + 20 + 4 + read-write + + + + + RTC_CR + RTC_CR + RTC_CR register + 0x08 + 0x20 + read-write + 0x00000000 + + + WUCKSEL + Wakeup clock selection +000: RTC/16 clock is selected +001: RTC/8 clock is selected +010: RTC/4 clock is selected +011: RTC/2 clock is selected +10x: ck_spre (usually 1 Hz) clock is selected +11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value + 0 + 3 + read-write + + + TSEDGE + Time-stamp event active edge +0: RTC_TS input rising edge generates a time-stamp event +1: RTC_TS input falling edge generates a time-stamp event +TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. + 3 + 1 + read-write + + + BYPSHAD + Bypass the shadow registers +0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. +1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 5 + 1 + read-write + + + FMT + Hour format + + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + ALRAE + Alarm A enable +0: Alarm A disabled +1: Alarm A enabled + 8 + 1 + read-write + + + WUTE + Wakeup timer enable +0: Wakeup timer disabled +1: Wakeup timer enabled + 10 + 1 + read-write + + + TSE + Timestamp enable +0: Timestamp disable +1: Timestamp enable + 11 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable +0: Alarm A interrupt disabled +1: Alarm A interrupt enabled + 12 + 1 + read-write + + + WUTIE + Wakeup timer interrupt enable +0: Wakeup timer interrupt disabled +1: Wakeup timer interrupt enabled + 14 + 1 + read-write + + + TSIE + Time-stamp interrupt enable + + 15 + 1 + read-write + + + B_0x0 + Time-stamp Interrupt disable + + 0x0 + + + B_0x1 + Time-stamp Interrupt enable + 0x1 + + + + + ADD1H + Add 1 hour (summer time change) +When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. +0: No effect +1: Adds 1 hour to the current time. This can be used for summer time change + 16 + 1 + write-only + + + SUB1H + Subtract 1 hour (winter time change) +When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. +Setting this bit has no effect when current hour is 0. +0: No effect +1: Subtracts 1 hour to the current time. This can be used for winter time change. + 17 + 1 + write-only + + + BKP + Backup +This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection +When COE=1, this bit selects which signal is output on RTC_CALIB. +0: Calibration output is 512 Hz +1: Calibration output is 1 Hz +These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). + 19 + 1 + read-write + + + POL + Output polarity +This bit is used to configure the polarity of RTC_ALARM output +0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0]) +1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0]). + 20 + 1 + read-write + + + OSEL + Output selection +These bits are used to select the flag to be routed to RTC_ALARM output +00: Output disabled +01: Alarm A output enabled +10: Reserved +11: Wakeup output enabled + 21 + 2 + read-write + + + COE + Calibration output enable +This bit enables the RTC_CALIB output +0: Calibration output disabled +1: Calibration output enabled + 23 + 1 + read-write + + + ITSE + Timestamp on internal event enable +0: Internal event timestamp disable +1: Internal event timestamp enable + 24 + 1 + read-write + + + + + RTC_ISR + RTC_ISR + RTC_ISR register + 0x0C + 0x20 + read-write + 0x00000007 + + + ALRAWF + Alarm A write flag +This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. +It is cleared by hardware in initialization mode. +0: Alarm A update not allowed +1: Alarm A update allowed. + 0 + 1 + read-write + + + WUTWF + Wakeup timer write flag +This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. +0: Wakeup timer configuration update not allowed +1: Wakeup timer configuration update allowed. + 2 + 1 + read-write + + + SHPF + Shift operation pending +0: No shift operation is pending +1: A shift operation is pending +This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. + 3 + 1 + read-write + + + INITS + Initialization status flag +This bit is set by hardware when the calendar year field is different from 0 (power-on reset state). +0: Calendar has not been initialized +1: Calendar has been initialized + 4 + 1 + read-write + + + RSF + Registers synchronization flag +This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow regsiter mode (BYPSHAD=1). This bit can also be cleared by software. +It is cleared either by software or by hardware in initialization mode. +0: Calendar shadow registers not yet synchronized +1: Calendar shadow registers synchronized. + 5 + 1 + read-write + + + INITF + Initialization flag +When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. +0: Calendar registers update is not allowed +1: Calendar registers update is allowed. + 6 + 1 + read-write + + + INIT + Initialization mode +0: Free running mode +1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + 7 + 1 + read-write + + + ALRAF + Alarm A flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). +This flag is cleared by software by writing 0. + 8 + 1 + read-write + + + WUTF + Wakeup timer flag +This flag is set by hardware when the wakeup auto-reload counter reaches 0. +This flag is cleared by software by writing 0. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 10 + 1 + read-write + + + TSF + This flag is set by hardware when a time-stamp event occurs. +This flag is cleared by software by writing 0. If ITSF flag is set, TSF must be cleared together with ITSF by writing 0 in both bits. + 11 + 1 + read-write + + + TSOVF + This flag is set by hardware when a time-stamp event occurs while TSF is already set. +This flag is cleared by software by writing 0. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp +event occurs immediately before the TSF bit is cleared. + 12 + 1 + read-write + + + TAMP1F + RTC_TAMP1 detection flag +This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. +It is cleared by software writing 0 + 13 + 1 + read-write + + + RECALPF + Recalibration pending Flag +The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. + 16 + 1 + read-write + + + ITSF + Internal time-stamp flag +This flag is set by hardware when a time-stamp on the internal event occurs. +This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits. + 17 + 1 + read-write + + + + + RTC_PRER + RTC_PRER + RTC_PRER register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_S + Synchronous prescaler factor +This is the synchronous division factor: +ck_spre frequency = ck_apre frequency/(PREDIV_S+1) + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor +This is the asynchronous division factor: +ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + read-write + + + + + RTC_WUTR + RTC_WUTR + RTC_WUTR register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits +When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register +When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. +The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. + 0 + 16 + read-write + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC_ALRMAR register + 0x1C + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask +0: Alarm A set if the seconds match +1: Seconds dont care in Alarm A comparison + 7 + 1 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask +0: Alarm A set if the minutes match +1: Minutes dont care in Alarm A comparison + 15 + 1 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + MSK3 + Alarm A hours mask +0: Alarm A set if the hours match +1: Hours dont care in Alarm A comparison + 23 + 1 + read-write + + + DU + Date units or day in BCD format. + 24 + 4 + read-write + + + DT + Date tens in BCD format. + 28 + 2 + read-write + + + WDSEL + Week day selection +0: DU[3:0] represents the date units +1: DU[3:0] represents the week day. DT[1:0] is dont care. + 30 + 1 + read-write + + + MSK4 + Alarm A date mask +0: Alarm A set if the date/day match +1: Date/day dont care in Alarm A comparison + 31 + 1 + read-write + + + + + RTC_WPR + RTC_WPR + RTC_WPR register + 0x24 + 0x20 + read-write + 0x00000000 + + + KEY + Write protection key +This byte is written by software. +Reading this byte always returns 0x00 + 0 + 8 + write-only + + + + + RTC_SSR + RTC_SSR + RTC_SSR register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value +SS[15:0] is the value in the synchronous prescalers counter. The fraction of a second is given by the formula below: +Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 ) + 0 + 16 + read-only + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC_SHIFTR register + 0x2C + 0x20 + read-write + 0x00000000 + + + SUBFS + Subtract a fraction of a second +These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +The value which is written to SUBFS is added to the synchronous prescalers counter. +Since this counter counts down, this operation effectively subtracts from (delays) the clock by: +Delay (seconds) = SUBFS / ( PREDIV_S + 1 ) +A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by : +Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) . + 0 + 15 + write-only + + + ADD1S + Add one second +0: No effect +1: Add one second to the clock/calendar +This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. + 31 + 1 + write-only + + + + + RTC_TSTR + RTC_TSTR + RTC_TSTR register + 0x30 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + + + RTC_TSDR + RTC_TSDR + RTC_TSDR register + 0x34 + 0x20 + read-write + 0x00000000 + + + DU + Date units in BCD format. + 0 + 4 + read-write + + + DT + Date tens in BCD format. + 4 + 2 + read-write + + + MU + Month units in BCD format. + 8 + 4 + read-write + + + MT + Month tens in BCD format. + 12 + 1 + read-write + + + WDU + Week day units + 13 + 3 + read-write + + + + + RTC_TSSSR + RTC_TSSSR + RTC_TSSSR register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value +SS[15:0] is the value of the synchronous prescalers counter when the timestamp event occurred. + 0 + 16 + read-only + + + + + RTC_CALR + RTC_CALR + RTC_CALR register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALM + Calibration minus +The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. +To increase the frequency of the calendar, this feature should be used in conjunction with CALP. + 0 + 9 + read-write + + + CALW16 + Use a 16-second calibration cycle period +When CALW16 is set to 1 , the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. +Note: CALM[0] is stucked at 0 when CALW16=1. + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period +When CALW8 is set to 1 , the 8-second calibration cycle period is selected. +Note: CALM[1:0] are stucked at '00' when CALW8=1. + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488.5 ppm +0: No RTCCLK pulses are added. +1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency incresed by 488.5 ppm). +This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. + 15 + 1 + read-write + + + + + RTC_TAMPCR + RTC_TAMPCR + RTC_TAMPCR register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP1E + RTC_TAMP1 input detection enable +0: RTC_TAMP1 detection disabled +1: RTC_TAMP1 detection enabled. + 0 + 1 + read-write + + + TAMP1TRG + Active level for RTC_TAMP1 input +If TAMPFLT != 00 +0: RTC_TAMP1 input staying low triggers a tamper detection event. +1: RTC_TAMP1 input staying high triggers a tamper detection event. +if TAMPFLT = 00: +0: RTC_TAMP1 input rising edge triggers a tamper detection event. +1: RTC_TAMP1 input falling edge triggers a tamper detection event. + 1 + 1 + read-write + + + TAMPIE + Tamper interrupt enable +0: Tamper interrupt disabled +1: Tamper interrupt enabled. + 2 + 1 + read-write + + + TAMPTS + Activate timestamp on tamper detection event +0: Tamper detection event does not cause a timestamp to be saved +1: Save timestamp on tamper detection event +TAMPTS is valid even if TSE=0 in the RTC_CR register. + 7 + 1 + read-write + + + TAMPFREQ + Tamper sampling frequency +Determines the frequency at which each of the RTC_TAMPx inputs are sampled. +0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) +0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) +0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) +0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) +0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) +0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) +0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) +0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + 8 + 3 + read-write + + + TAMPFLT + RTC_TAMPx filter count +These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. +TAMPFLT is valid for each of the RTC_TAMPx inputs. +0x0: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input). +0x1: Tamper event is activated after 2 consecutive samples at the active level. +0x2: Tamper event is activated after 4 consecutive samples at the active level. +0x3: Tamper event is activated after 8 consecutive samples at the active level. + 11 + 2 + read-write + + + TAMPPRCH + RTC_TAMPx precharge duration +These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs. +0x0: 1 RTCCLK cycle +0x1: 2 RTCCLK cycles +0x2: 4 RTCCLK cycles +0x3: 8 RTCCLK cycles + 13 + 2 + read-write + + + TAMPPUDIS + RTC_TAMPx pull-up disable +This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample. +0: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) +1: Disable precharge of RTC_TAMPx pins. + 15 + 1 + read-write + + + TAMP1IE + Tamper 1 interrupt enable +0: Tamper 1 interrupt is disabled if TAMPIE = 0. +1: Tamper 1 interrupt enabled. + 16 + 1 + read-write + + + TAMP1NOERASE + Tamper 1 no erase +0: Tamper 1 event erases the backup registers. +1: Tamper 1 event does not erase the backup registers. + 17 + 1 + read-write + + + TAMP1MF + Tamper 1 mask flag +0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. +1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased. + 18 + 1 + read-write + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC_ALRMASSR register + 0x44 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value +This value is compared with the contents of the synchronous prescalers counter to +determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). +1: SS[14:1] are dont care in Alarm A comparison. Only SS[0] is compared. +2: SS[14:2] are dont care in Alarm A comparison. Only SS[1:0] are compared. +3: SS[14:3] are dont care in Alarm A comparison. Only SS[2:0] are compared. +... +12: SS[14:12] are dont care in Alarm A comparison. SS[11:0] are compared. +13: SS[14:13] are dont care in Alarm A comparison. SS[12:0] are compared. +14: SS[14] is dont care in Alarm A comparison. SS[13:0] are compared. +15: All 15 SS bits are compared and must match to activate alarm. +The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. + 24 + 4 + read-write + + + + + RTC_OR + RTC_OR + RTC_OR register + 0x4C + 0x20 + read-write + 0x00000000 + + + ALARMOUTTYPE + RTC_ALARM on PA8 output type + + 0 + 1 + read-write + + + B_0x0 + RTC_ALARM, when mapped on PA8, is open-drain output + + 0x0 + + + B_0x1 + RTC_ALARM, when mapped on PA8, is push-pull output + 0x1 + + + + + RTC_OUT_RMP + RTC_OUT remap +Setting this bit allows to remap the RTC outputs on PA9 as follows: +0 : +If OSEL/= '00' : RTC_ALARM is ouput on PA8 +If OSEL= '00' and COE = 1 : RTC_CALIB is output on PA8 +1 : +If OSEL /= '00' and COE = 0 : RTC_ALARM is output on PA9 +If OSEL = '00' and COE = 1: RTC_CALIB is output on PA9 +If OSEL /= '00' and COE = 1: RTC_CALIB is output on PA9 and RTC_ALARM is output on PA8. +Note: the RTC outputs are functional in DEEPSTOP mode only on PA8. + 1 + 1 + read-write + + + + + RTC_BKP0R + RTC_BKP0R + RTC_BKPxR register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + RTC_BKP1R + RTC_BKP1R + RTC_BKPxR register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + + + SPI + SPI + 0x41002000 + + 0x0 + 0x1C + registers + + + SPI1 + SPI1 interrupt + 5 + + + + SPI_SSPCR1 + SPI_SSPCR1 + SPI_SSPCR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + CPHA + Clock phase +- 0: The first clock transition is the first data capture edge +- 1: The second clock transition is the first data capture edge + 0 + 1 + read-write + + + CPOL + Clock polarity +- 0: CK to 0 when idle +- 1: CK to 1 when idle + 1 + 1 + read-write + + + MSTR + Master selection +- 0: Slave configuration +- 1: Master configuration + 2 + 1 + read-write + + + BR + Baud rate control +- 000: fPCLK/2 +- 001: fPCLK/4 +- 010: fPCLK/8 +- 011: fPCLK/16 +- 100: fPCLK/32 +- 101: fPCLK/64 +- 110: fPCLK/128 +- 111: fPCLK/256 + 3 + 3 + read-write + + + SPE + SPI enable +- 0: Peripheral disabled +- 1: Peripheral enabled + 6 + 1 + read-write + + + LSBFIRST + Frame format +- 0: data is transmitted / received with the MSB first +- 1: data is transmitted / received with the LSB first + 7 + 1 + read-write + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +- 0: Software slave management disabled +- 1: Software slave management enabled + 9 + 1 + read-write + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +- 0: Full duplex (Transmit and receive) +- 1: Output disabled (Receive-only mode) + 10 + 1 + read-write + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +- 0: 8-bit CRC length +- 1: 16-bit CRC length + 11 + 1 + read-write + + + CRCNEXT + Transmit CRC next +- 0: Next transmit value is from Tx buffer +- 1: Next transmit value is from Tx CRC register + 12 + 1 + read-write + + + CRCEN + Hardware CRC calculation enable +- 0: CRC calculation disabled +- 1: CRC calculation Enabled + 13 + 1 + read-write + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode +- 0: Output disabled (receive-only mode) +- 1: Output enabled (transmit-only mode) + 14 + 1 + read-write + + + BIDIMODE + Bidirectional data mode enable. This bit enables half-duplex communication using +common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is +active. +- 0: 2-line unidirectional data mode selected +- 1: 1-line bidirectional data mode selected + 15 + 1 + read-write + + + + + SPI_SSPCR2 + SPI_SSPCR2 + SPI_SSPCR2 register + 0x04 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. +- 0: Rx buffer DMA disabled +- 1: Rx buffer DMA enabled + 0 + 1 + read-write + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. +- 0: Tx buffer DMA disabled +- 1: Tx buffer DMA enabled + 1 + 1 + read-write + + + SSOE + SS output enable +- 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration +- 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 2 + 1 + read-write + + + NSSP + NSS pulse management +This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1, or FRF = 1. +- 0: No NSS pulse +- 1: NSS pulse generated + 3 + 1 + read-write + + + FRF + Frame format +- 0: SPI Motorola mode +- 1 SPI TI mode + 4 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). +- 0: Error interrupt is masked +- 1: Error interrupt is enabled + 5 + 1 + read-write + + + RXNEIE + RX buffer not empty interrupt enable +- 0: RXNE interrupt masked +- 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 6 + 1 + read-write + + + TXEIE + Tx buffer empty interrupt enable +- 0: TXE interrupt masked +- 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 7 + 1 + read-write + + + DS + Data size +These bits configure the data length for SPI transfers: +- 0000: Not used +- 0001: Not used +- 0010: Not used +- 0011: 4-bit +- 0100: 5-bit +- 0101: 6-bit +- 0110: 7-bit +- 0111: 8-bit +- 1000: 9-bit +- 1001: 10-bit +- 1010: 11-bit +- 1011: 12-bit +- 1100: 13-bit +- 1101: 14-bit +- 1110: 15-bit +- 1111: 16-bit +If software attempts to write one of the 'Not used' values, they are forced to the value '0111'(8-bit). + 8 + 4 + read-write + + + FRXTH + FIFO reception threshold +FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +- 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) +- 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 12 + 1 + read-write + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 13 + 1 + read-write + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 14 + 1 + read-write + + + + + SPI_SSPSR + SPI_SSPSR + SPI_SSPSR register + 0x08 + 0x20 + read-write + 0x00000002 + + + RXNE + Receive buffer not empty +- 0: Rx buffer empty +- 1: Rx buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty +- 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). +- 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer). + 1 + 1 + read-only + + + CHSIDE + Channel side +- 0: Channel Left has to be transmitted or has been received +- 1: Channel Right has to be transmitted or has been received + 2 + 1 + read-only + + + UDR + Underrun flag +- 0: No underrun occurred +- 1: Underrun occurred + 3 + 1 + read-only + + + CRCERR + CRC error flag +- 0: CRC value received matches the SPIx_RXCRCR value +- 1: CRC value received does not match the SPIx_RXCRCR value +This flag is set by hardware and cleared by software writing 0. + 4 + 1 + read-write + + + MODF + Mode fault +- 0: No mode fault occurred +- 1: Mode fault occurred + 5 + 1 + read-only + + + OVR + Overrun flag +- 0: No overrun occurred +- 1: Overrun occurred + 6 + 1 + read-only + + + BSY + Busy flag +- 0: SPI (or I2S) not busy +- 1: SPI (or I2S) is busy in communication or Tx buffer is not empty +This flag is set and cleared by hardware. + 7 + 1 + read-only + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. +- 0: No frame format error +- 1: A frame format error occurred + 8 + 1 + read-only + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full + 9 + 2 + read-only + + + FTLVL + FIFO Transmission Level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 11 + 2 + read-only + + + + + SPI_SSPDR + SPI_SSPDR + SPI_SSPDR register + 0x0C + 0x20 + read-write + 0x00000000 + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO +(See Section 18.5.8: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI_SSPCRCPR + SPI_SSPCRCPR + SPI_SSPCRCPR register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI_SSPRXCRCR + SPI_SSPRXCRCR + SPI_SSPRXCRCR register + 0x14 + 0x20 + read-only + 0x00000000 + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +A read to this register when the BSY Flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + SPI_SSPTXCRCR + SPI_SSPTXCRCR + SPI_SSPTXCRCR register + 0x18 + 0x20 + read-only + 0x00000000 + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode. + 0 + 1 + read-only + + + + + + + SPI3 + SPI3 + 0x41007000 + + 0x0 + 0x24 + registers + + + SPI3 + SPI3 interrupt + 7 + + + + SPI_SSPCR1 + SPI_SSPCR1 + SPI_SSPCR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + CPHA + Clock phase +- 0: The first clock transition is the first data capture edge +- 1: The second clock transition is the first data capture edge + 0 + 1 + read-write + + + CPOL + Clock polarity +- 0: CK to 0 when idle +- 1: CK to 1 when idle + 1 + 1 + read-write + + + MSTR + Master selection +- 0: Slave configuration +- 1: Master configuration + 2 + 1 + read-write + + + BR + Baud rate control +- 000: fPCLK/2 +- 001: fPCLK/4 +- 010: fPCLK/8 +- 011: fPCLK/16 +- 100: fPCLK/32 +- 101: fPCLK/64 +- 110: fPCLK/128 +- 111: fPCLK/256 + 3 + 3 + read-write + + + SPE + SPI enable +- 0: Peripheral disabled +- 1: Peripheral enabled + 6 + 1 + read-write + + + LSBFIRST + Frame format +- 0: data is transmitted / received with the MSB first +- 1: data is transmitted / received with the LSB first + 7 + 1 + read-write + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +- 0: Software slave management disabled +- 1: Software slave management enabled + 9 + 1 + read-write + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +- 0: Full duplex (Transmit and receive) +- 1: Output disabled (Receive-only mode) + 10 + 1 + read-write + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +- 0: 8-bit CRC length +- 1: 16-bit CRC length + 11 + 1 + read-write + + + CRCNEXT + Transmit CRC next +- 0: Next transmit value is from Tx buffer +- 1: Next transmit value is from Tx CRC register + 12 + 1 + read-write + + + CRCEN + Hardware CRC calculation enable +- 0: CRC calculation disabled +- 1: CRC calculation Enabled + 13 + 1 + read-write + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode +- 0: Output disabled (receive-only mode) +- 1: Output enabled (transmit-only mode) + 14 + 1 + read-write + + + BIDIMODE + Bidirectional data mode enable. This bit enables half-duplex communication using +common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is +active. +- 0: 2-line unidirectional data mode selected +- 1: 1-line bidirectional data mode selected + 15 + 1 + read-write + + + + + SPI_SSPCR2 + SPI_SSPCR2 + SPI_SSPCR2 register + 0x04 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. +- 0: Rx buffer DMA disabled +- 1: Rx buffer DMA enabled + 0 + 1 + read-write + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. +- 0: Tx buffer DMA disabled +- 1: Tx buffer DMA enabled + 1 + 1 + read-write + + + SSOE + SS output enable +- 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration +- 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 2 + 1 + read-write + + + NSSP + NSS pulse management +This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1, or FRF = 1. +- 0: No NSS pulse +- 1: NSS pulse generated + 3 + 1 + read-write + + + FRF + Frame format +- 0: SPI Motorola mode +- 1 SPI TI mode + 4 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). +- 0: Error interrupt is masked +- 1: Error interrupt is enabled + 5 + 1 + read-write + + + RXNEIE + RX buffer not empty interrupt enable +- 0: RXNE interrupt masked +- 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 6 + 1 + read-write + + + TXEIE + Tx buffer empty interrupt enable +- 0: TXE interrupt masked +- 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 7 + 1 + read-write + + + DS + Data size +These bits configure the data length for SPI transfers: +- 0000: Not used +- 0001: Not used +- 0010: Not used +- 0011: 4-bit +- 0100: 5-bit +- 0101: 6-bit +- 0110: 7-bit +- 0111: 8-bit +- 1000: 9-bit +- 1001: 10-bit +- 1010: 11-bit +- 1011: 12-bit +- 1100: 13-bit +- 1101: 14-bit +- 1110: 15-bit +- 1111: 16-bit +If software attempts to write one of the 'Not used' values, they are forced to the value '0111'(8-bit). + 8 + 4 + read-write + + + FRXTH + FIFO reception threshold +FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +- 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) +- 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 12 + 1 + read-write + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 13 + 1 + read-write + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 14 + 1 + read-write + + + + + SPI_SSPSR + SPI_SSPSR + SPI_SSPSR register + 0x08 + 0x20 + read-write + 0x00000002 + + + RXNE + Receive buffer not empty +- 0: Rx buffer empty +- 1: Rx buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty +- 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). +- 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer). + 1 + 1 + read-only + + + CHSIDE + Channel side +- 0: Channel Left has to be transmitted or has been received +- 1: Channel Right has to be transmitted or has been received + 2 + 1 + read-only + + + UDR + Underrun flag +- 0: No underrun occurred +- 1: Underrun occurred + 3 + 1 + read-only + + + CRCERR + CRC error flag +- 0: CRC value received matches the SPIx_RXCRCR value +- 1: CRC value received does not match the SPIx_RXCRCR value +This flag is set by hardware and cleared by software writing 0. + 4 + 1 + read-write + + + MODF + Mode fault +- 0: No mode fault occurred +- 1: Mode fault occurred + 5 + 1 + read-only + + + OVR + Overrun flag +- 0: No overrun occurred +- 1: Overrun occurred + 6 + 1 + read-only + + + BSY + Busy flag +- 0: SPI (or I2S) not busy +- 1: SPI (or I2S) is busy in communication or Tx buffer is not empty +This flag is set and cleared by hardware. + 7 + 1 + read-only + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. +- 0: No frame format error +- 1: A frame format error occurred + 8 + 1 + read-only + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full + 9 + 2 + read-only + + + FTLVL + FIFO Transmission Level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 11 + 2 + read-only + + + + + SPI_SSPDR + SPI_SSPDR + SPI_SSPDR register + 0x0C + 0x20 + read-write + 0x00000000 + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO +(See Section 18.5.8: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI_SSPCRCPR + SPI_SSPCRCPR + SPI_SSPCRCPR register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI_SSPRXCRCR + SPI_SSPRXCRCR + SPI_SSPRXCRCR register + 0x14 + 0x20 + read-only + 0x00000000 + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +A read to this register when the BSY Flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + SPI_SSPTXCRCR + SPI_SSPTXCRCR + SPI_SSPTXCRCR register + 0x18 + 0x20 + read-only + 0x00000000 + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode. + 0 + 1 + read-only + + + + + SPI2S_I2SCFGR + SPI2S_I2SCFGR + SPI2S_I2SCFGR register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHLEN + Channel length (number of bits per audio channel) +- 0: 16-bit wide +- 1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. + 0 + 1 + read-write + + + DATLEN + Data length to be transferred +- 00: 16-bit data length +- 01: 24-bit data length +- 10: 32-bit data length +- 11: Not allowed + 1 + 2 + read-write + + + CKPOL + Steady state clock polarity +- 0: I2S clock steady state is low level +- 1: I2S clock steady state is high level + 3 + 1 + read-write + + + I2SSTD + I2S standard selection +- 00: I2S Philips standard. +- 01: MSB justified standard (left justified) +- 10: LSB justified standard (right justified) +- 11: PCM standard + 4 + 2 + read-write + + + PCMSYNC + PCM frame synchronization +- 0: Short frame synchronization +- 1: Long frame synchronization +Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode. + 7 + 1 + read-write + + + I2SCFG + I2S configuration mode +- 00: Slave - transmit +- 01: Slave - receive +- 10: Master - transmit +- 11: Master - receive + 8 + 2 + read-write + + + I2SE + I2S enable +- 0: I2S peripheral is disabled +- 1: I2S peripheral is enabled +Note: This bit is not used in SPI mode. + 10 + 1 + read-write + + + I2SMOD + I2S mode selection +- 0: SPI mode is selected +- 1: I2S mode is selected +Note: This bit should be configured when the SPI is disabled. + 11 + 1 + read-write + + + ASTREN + Asynchronous start enable. +Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. + 12 + 1 + read-write + + + B_0x0 + The Asynchronous start is disabled. When the I2S is enabled in slave mode, the I2S slave starts the transfer when the I2S clock is received and an appropriate transition (depending on the protocol selected) is detected on the WS signal. + + 0x0 + + + B_0x1 + The Asynchronous start is enabled. When the I2S is enabled in slave mode, the I2S slave starts immediately the transfer when the I2S clock is received from the master without checking the expected transition of WS signal. + + 0x1 + + + + + + + SPI2S_I2SPR + SPI2S_I2SPR + SPI2S_I2SPR register + 0x20 + 0x20 + read-write + 0x00000002 + + + I2SDIV + I2S linear prescaler +I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. + 0 + 8 + read-write + + + ODD + Odd factor for the prescaler +- 0: Real divider value is = I2SDIV *2 +- 1: Real divider value is = (I2SDIV * 2)+1 + 8 + 1 + read-write + + + MCKOE + Master clock output enable +- 0: Master clock output is disabled +- 1: Master clock output is enabled + 9 + 1 + read-write + + + + + + + SYSTEM_CTRL + SYSTEM_CTRL + 0x40000000 + + 0x0 + 0x48 + registers + + + + DIE_ID + DIE_ID + DIE_ID register + 0x00 + 0x20 + read-only + 0x00000120 + + + REVISION + Cut revision (metal fix) + 0 + 4 + read-only + + + VERSION + Cut version + 4 + 4 + read-only + + + PRODUCT + Product version. +May be used to discriminate several version of a same digital BLE LPH device embedding +different analog versions + 8 + 4 + read-only + + + + + JTAG_ID + JTAG_ID + JTAG_ID register + 0x04 + 0x20 + read-only + 0x02027041 + + + MANUF_ID + Manufacturer ID + 1 + 11 + read-only + + + PART_NUMBER + Part number + 12 + 16 + read-only + + + VERSION_NUMBER + Version + 28 + 4 + read-only + + + + + I2C_FMP_CTRL + I2C_FMP_CTRL + I2C_FMP_CTRL register + 0x08 + 0x20 + read-write + 0x00000000 + + + I2C1_PA0_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. +0: PA0 pin operated in standard mode. +1: FM+ mode is enabled on PA0 pin, and speed control is bypassed + 0 + 1 + read-write + + + I2C1_PA1_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. +0: PA1 pin operated in standard mode. +1: FM+ mode is enabled on PA1 pin, and speed control is bypassed + 1 + 1 + read-write + + + I2C1_PB6_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O. +0: PB6 pin operated in standard mode. +1: FM+ mode is enabled on PB6 pin, and speed control is bypassed. + 2 + 1 + read-write + + + I2C1_PB7_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O. +0: PB7 pin operated in standard mode. +1: FM+ mode is enabled on PB7 pin, and speed control is bypassed + 3 + 1 + read-write + + + I2C1_PB10_FMP + I2C1_PB10_FMP: I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB10 I/O. +0: PB10 pin operated in standard mode. +1: FM+ mode is enabled on PB10 pin, and speed control is bypassed. + 4 + 1 + read-write + + + I2C1_PB11_FMP + I2C1_PB11_FMP: I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB11 I/O. +0: PB11 pin operated in standard mode. +1: FM+ mode is enabled on PB11 pin, and speed control is bypassed + 5 + 1 + read-write + + + I2C2_PA6_FMP + I2C2_PA6_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SCL on PA6 I/O. +0: PA6 pin operated in standard mode. +1: FM+ mode is enabled on PA6 pin, and speed control is bypassed. + 6 + 1 + read-write + + + I2C2_PA7_FMP + I2C2_PA7_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SDA on PA7 I/O. +0: PA7 pin operated in standard mode. +1: FM+ mode is enabled on PA7 pin, and speed control is bypassed + 7 + 1 + read-write + + + I2C2_PA13_FMP + I2C2_PA13_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SCL on PA13 I/O. +0: PA13 pin operated in standard mode. +1: FM+ mode is enabled on PA13 pin, and speed control is bypassed. + 8 + 1 + read-write + + + I2C2_PA14_FMP + I2C2_PA14_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SDA on PA14 I/O. +0: PA14 pin operated in standard mode. +1: FM+ mode is enabled on PA14 pin, and speed control is bypassed. + 9 + 1 + read-write + + + + + IO_DTR + IO_DTR + IO_DTR register + 0x0C + 0x20 + read-write + 0x00000000 + + + PA0_DT + PA0_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 0 + 1 + read-write + + + PA1_DT + PA1_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 1 + 1 + read-write + + + PA2_DT + PA2_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 2 + 1 + read-write + + + PA3_DT + PA3_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 3 + 1 + read-write + + + PA4_DT + PA4_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 4 + 1 + read-write + + + PA5_DT + PA5_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 5 + 1 + read-write + + + PA6_DT + PA6_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 6 + 1 + read-write + + + PA7_DT + PA7_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 7 + 1 + read-write + + + PA8_DT + PA8_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 8 + 1 + read-write + + + PA9_DT + PA9_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 9 + 1 + read-write + + + PA10_DT + PA10_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 10 + 1 + read-write + + + PA11_DT + PA11_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 11 + 1 + read-write + + + PA12_DT + PA12_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 12 + 1 + read-write + + + PA13_DT + PA13_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 13 + 1 + read-write + + + PA14_DT + PA14_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 14 + 1 + read-write + + + PA15_DT + PA15_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 15 + 1 + read-write + + + PB0_DT + PB0_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 16 + 1 + read-write + + + PB1_DT + PB1_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 17 + 1 + read-write + + + PB2_DT + PB2_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 18 + 1 + read-write + + + PB3_DT + PB3_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 19 + 1 + read-write + + + PB4_DT + PB4_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 20 + 1 + read-write + + + PB5_DT + PB5_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 21 + 1 + read-write + + + PB6_DT + PB6_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 22 + 1 + read-write + + + PB7_DT + PB7_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 23 + 1 + read-write + + + PB8_DT + PB8_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 24 + 1 + read-write + + + PB9_DT + PB9_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 25 + 1 + read-write + + + PB10_DT + PB10_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 26 + 1 + read-write + + + PB11_DT + PB11_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 27 + 1 + read-write + + + PB12_DT + PB12_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 28 + 1 + read-write + + + PB13_DT + PB13_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 29 + 1 + read-write + + + PB14_DT + PB14_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 30 + 1 + read-write + + + PB15_DT + PB15_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 31 + 1 + read-write + + + + + IO_IBER + IO_IBER + IO_IBER register + 0x10 + 0x20 + read-write + 0x000000000 + + + PA0_IBE + PA0_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 0 + 1 + read-write + + + PA1_IBE + PA1_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 1 + 1 + read-write + + + PA2_IBE + PA2_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 2 + 1 + read-write + + + PA3_IBE + PA3_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 3 + 1 + read-write + + + PA4_IBE + PA4_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 4 + 1 + read-write + + + PA5_IBE + PA5_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 5 + 1 + read-write + + + PA6_IBE + PA6_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 6 + 1 + read-write + + + PA7_IBE + PA7_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 7 + 1 + read-write + + + PA8_IBE + PA8_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 8 + 1 + read-write + + + PA9_IBE + PA9_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 9 + 1 + read-write + + + PA10_IBE + PA10_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 10 + 1 + read-write + + + PA11_IBE + PA11_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 11 + 1 + read-write + + + PA12_IBE + PA12_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 12 + 1 + read-write + + + PA13_IBE + PA13_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 13 + 1 + read-write + + + PA14_IBE + PA14_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 14 + 1 + read-write + + + PA15_IBE + PA15_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 15 + 1 + read-write + + + PB0_IBE + PB0_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 16 + 1 + read-write + + + PB1_IBE + PB1_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 17 + 1 + read-write + + + PB2_IBE + PB2_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 18 + 1 + read-write + + + PB3_IBE + PB3_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 19 + 1 + read-write + + + PB4_IBE + PB4_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 20 + 1 + read-write + + + PB5_IBE + PB5_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 21 + 1 + read-write + + + PB6_IBE + PB6_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 22 + 1 + read-write + + + PB7_IBE + PB7_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 23 + 1 + read-write + + + PB8_IBE + PB8_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 24 + 1 + read-write + + + PB9_IBE + PB9_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 25 + 1 + read-write + + + PB10_IBE + PB10_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 26 + 1 + read-write + + + PB11_IBE + PB11_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 27 + 1 + read-write + + + PB12_IBE + PB12_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 28 + 1 + read-write + + + PB13_IBE + PB13_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 29 + 1 + read-write + + + PB14_IBE + PB14_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 30 + 1 + read-write + + + PB15_IBE + PB15_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 31 + 1 + read-write + + + + + IO_IEVR + IO_IEVR + IO_IEVR register + 0x14 + 0x20 + read-write + 0x00000000 + + + PA0_IEV + PA0_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 0 + 1 + read-write + + + PA1_IEV + PA1_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 1 + 1 + read-write + + + PA2_IEV + PA2_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 2 + 1 + read-write + + + PA3_IEV + PA3_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 3 + 1 + read-write + + + PA4_IEV + PA4_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 4 + 1 + read-write + + + PA5_IEV + PA5_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 5 + 1 + read-write + + + PA6_IEV + PA6_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 6 + 1 + read-write + + + PA7_IEV + PA7_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 7 + 1 + read-write + + + PA8_IEV + PA8_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 8 + 1 + read-write + + + PA9_IEV + PA9_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 9 + 1 + read-write + + + PA10_IEV + PA10_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 10 + 1 + read-write + + + PA11_IEV + PA11_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 11 + 1 + read-write + + + PA12_IEV + PA12_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 12 + 1 + read-write + + + PA13_IEV + PA13_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 13 + 1 + read-write + + + PA14_IEV + PA14_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 14 + 1 + read-write + + + PA15_IEV + PA15_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 15 + 1 + read-write + + + PB0_IEV + PB0_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 16 + 1 + read-write + + + PB1_IEV + PB1_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 17 + 1 + read-write + + + PB2_IEV + PB2_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 18 + 1 + read-write + + + PB3_IEV + PB3_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 19 + 1 + read-write + + + PB4_IEV + PB4_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 20 + 1 + read-write + + + PB5_IEV + PB5_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 21 + 1 + read-write + + + PB6_IEV + PB6_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 22 + 1 + read-write + + + PB7_IEV + PB7_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 23 + 1 + read-write + + + PB8_IEV + PB8_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 24 + 1 + read-write + + + PB9_IEV + PB9_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 25 + 1 + read-write + + + PB10_IEV + PB10_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 26 + 1 + read-write + + + PB11_IEV + PB11_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 27 + 1 + read-write + + + PB12_IEV + PB12_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 28 + 1 + read-write + + + PB13_IEV + PB13_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 29 + 1 + read-write + + + PB14_IEV + PB14_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 30 + 1 + read-write + + + PB15_IEV + PB15_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 31 + 1 + read-write + + + + + IO_IER + IO_IER + IO_IER register + 0x18 + 0x20 + read-write + 0x000000000 + + + PA0_IE + PA0_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 0 + 1 + read-write + + + PA1_IE + PA1_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 1 + 1 + read-write + + + PA2_IE + PA2_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 2 + 1 + read-write + + + PA3_IE + PA3_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 3 + 1 + read-write + + + PA4_IE + PA4_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 4 + 1 + read-write + + + PA5_IE + PA5_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 5 + 1 + read-write + + + PA6_IE + PA6_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 6 + 1 + read-write + + + PA7_IE + PA7_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 7 + 1 + read-write + + + PA8_IE + PA8_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 8 + 1 + read-write + + + PA9_IE + PA9_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 9 + 1 + read-write + + + PA10_IE + PA10_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 10 + 1 + read-write + + + PA11_IE + PA11_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 11 + 1 + read-write + + + PA12_IE + PA12_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 12 + 1 + read-write + + + PA13_IE + PA13_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 13 + 1 + read-write + + + PA14_IE + PA14_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 14 + 1 + read-write + + + PA15_IE + PA15_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 15 + 1 + read-write + + + PB0_IE + PB0_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 16 + 1 + read-write + + + PB1_IE + PB1_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 17 + 1 + read-write + + + PB2_IE + PB2_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 18 + 1 + read-write + + + PB3_IE + PB3_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 19 + 1 + read-write + + + PB4_IE + PB4_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 20 + 1 + read-write + + + PB5_IE + PB5_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 21 + 1 + read-write + + + PB6_IE + PB6_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 22 + 1 + read-write + + + PB7_IE + PB7_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 23 + 1 + read-write + + + PB8_IE + PB8_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 24 + 1 + read-write + + + PB9_IE + PB9_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 25 + 1 + read-write + + + PB10_IE + PB10_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 26 + 1 + read-write + + + PB11_IE + PB11_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 27 + 1 + read-write + + + PB12_IE + PB12_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 28 + 1 + read-write + + + PB13_IE + PB13_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 29 + 1 + read-write + + + PB14_IE + PB14_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 30 + 1 + read-write + + + PB15_IE + PB15_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 31 + 1 + read-write + + + + + IO_ISCR + IO_ISCR + IO_ISCR register + 0x1C + 0x20 + read-write + 0x00000000 + + + PA0_ISC + PA0_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 0 + 1 + read-write + + + PA1_ISC + PA1_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + PA2_ISC + PA2_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 2 + 1 + read-write + + + PA3_ISC + PA3_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 3 + 1 + read-write + + + PA4_ISC + PA4_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 4 + 1 + read-write + + + PA5_ISC + PA5_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 5 + 1 + read-write + + + PA6_ISC + PA6_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 6 + 1 + read-write + + + PA7_ISC + PA7_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 7 + 1 + read-write + + + PA8_ISC + PA8_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 8 + 1 + read-write + + + PA9_ISC + PA9_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 9 + 1 + read-write + + + PA10_ISC + PA10_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 10 + 1 + read-write + + + PA11_ISC + PA11_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 11 + 1 + read-write + + + PA12_ISC + PA12_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 12 + 1 + read-write + + + PA13_ISC + PA13_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 13 + 1 + read-write + + + PA14_ISC + PA14_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 14 + 1 + read-write + + + PA15_ISC + PA15_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 15 + 1 + read-write + + + PB0_ISC + PB0_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 16 + 1 + read-write + + + PB1_ISC + PB1_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 17 + 1 + read-write + + + PB2_ISC + PB2_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 18 + 1 + read-write + + + PB3_ISC + PB3_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 19 + 1 + read-write + + + PB4_ISC + PB4_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 20 + 1 + read-write + + + PB5_ISC + PB5_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 21 + 1 + read-write + + + PB6_ISC + PB6_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 22 + 1 + read-write + + + PB7_ISC + PB7_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 23 + 1 + read-write + + + PB8_ISC + PB8_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 24 + 1 + read-write + + + PB9_ISC + PB9_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 25 + 1 + read-write + + + PB10_ISC + PB10_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 26 + 1 + read-write + + + PB11_ISC + PB11_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 27 + 1 + read-write + + + PB12_ISC + PB12_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 28 + 1 + read-write + + + PB13_ISC + PB13_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 29 + 1 + read-write + + + PB14_ISC + PB14_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 30 + 1 + read-write + + + PB15_ISC + PB15_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 31 + 1 + read-write + + + + + PWRC_IER + PWRC_IER + PWRC_IER register + 0x20 + 0x20 + read-write + 0x000000000 + + + BORH_IE + BORH_IE: BORH interrupt enable. +0: BORH interrupt is disabled. +1: BORH interrupt is enabled. + 0 + 1 + read-write + + + PVD_IE + PVD_IE: Programmable Voltage Detector interrupt enable. +0: PVD interrupt is disabled. +1: PVD interrupt is enabled. + 1 + 1 + read-write + + + WKUP_IE + WKUP_IE: Power Controller Wakeup event interrupt enable. +0: Interrupt on wakeup event seen by the PWRC is disabled. +1: Interrupt on wakeup event seen by the PWRC is enabled. + 2 + 1 + read-write + + + + + PWRC_ISCR + PWRC_ISCR + PWRC_ISCR register + 0x24 + 0x20 + read-write + 0x000000000 + + + BORH_ISC + BORH_ISC: BORH interrupt status. +0: no pending interrupt. +1: voltage went under BORH threshold / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 0 + 1 + read-write + + + PVD_ISC + PVD_ISC: Programmable Voltage Detector status. +0: no pending interrupt. +1: voltage went under programmed threshold / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + WKUP_ISC + WKUP_ISC: Indicates the Power Controller receives a Wakeup event. +0: no pending interrupt. +1: Wakeup event on PWRC occurred / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. +This flag will be read at 1 if a wakeup event arrives so close to the low power mode entry +requests that the PWRC aborts before shutting down the system. + 2 + 1 + read-write + + + + + GPIO_SWA_CTRL + GPIO_SWA_CTRL + GPIO_SWA_CTRL register + 0x28 + 0x20 + read-write + 0x000000000 + + + ATB1_nPVD + ATB1_nPVD: select the analog feature on PB14 between ATB1 and PVD when the PB14 I/O +is programmed in analog mode (in the associated GPIO_MODER register): +0: PVD external voltage feature is selected (default). +1: ATB1 feature is selected + 0 + 1 + read-write + + + + + INTAI_DTR + INTAI_DTR + INTAI_DTR register + 0x2C + 0x20 + read-write + 0x000000000 + + + TX_DT + TX_DT: detection type on TX_SEQUENCE signal: +0: detection on edge (default). +1: detection on level + 0 + 1 + read-write + + + RX_DT + RX_DT: detection type on RX_SEQUENCE signal: +0: detection on edge (default). +1: detection on level + 1 + 1 + read-write + + + COMP_DT + COMP_DT: detection type on COMP_OUT (after COMP_POL selection) signal: +0: detection on edge (default). +1: detection on level + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_DT + RFIP_BUSY_STATUS_DT: detection type on RFIP_BUSY_STATUS signal: +0: detection on edge (default). +1: detection on level + 5 + 1 + read-write + + + + + INTAI_IBER + INTAI_IBER + INTAI_IBER register + 0x30 + 0x20 + read-write + 0x000000000 + + + TX_IBE + TX_IBE: interrupt edge register on TX_SEQUENCE signal: +0: detection on single edge (default). +1: detection on both edges + 0 + 1 + read-write + + + RX_IBE + RX_IBE: interrupt edge register on RX_SEQUENCE signal: +0: detection on single edge (default). +1: detection on both edges + 1 + 1 + read-write + + + COMP_IBE + COMP_IBE: interrupt edge register on COMP_OUT signal: +0: detection on single edge (default). +1: detection on both edges + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_IBE + RFIP_BUSY_STATUS_IBE: interrupt edge register on RFIP_BUSY_STATUS signal: +0: detection on single edge (default). +1: detection on both edges + 5 + 1 + read-write + + + + + INTAI_IEVR + INTAI_IEVR + INTAI_IEVR register + 0x34 + 0x20 + read-write + 0x000000000 + + + TX_IEV + TX_IEV: interrupt polarity event on TX_SEQUENCE signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 0 + 1 + read-write + + + RX_IEV + RX_IEV: interrupt polarity event on RX_SEQUENCE signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 1 + 1 + read-write + + + COMP_IEV + COMP_IEV: interrupt polarity event on COMP_OUT signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_IEV + RFIP_BUSY_STATUS_IEV: interrupt polarity event on RFIP_BUSY_STATUS signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 5 + 1 + read-write + + + + + INTAI_IER + INTAI_IER + INTAI_IER register + 0x38 + 0x20 + read-write + 0x000000000 + + + TX_IE + TX_IE: interrupt enable on TX_SEQUENCE signal: +0: TX_SEQUENCE interrupt is disabled (default). +1: TX_SEQUENCE interrupt is enabled + 0 + 1 + read-write + + + RX_IE + RX_IE: interrupt enable on RX_SEQUENCE signal: +0: RX_SEQUENCE interrupt is disabled (default). +1: RX_SEQUENCE interrupt is enabled + 1 + 1 + read-write + + + COMP_IE + COMP_IE: interrupt enable on COMP_OUT signal: +0: COMP_OUT interrupt is disabled (default). +1: COMP_OUT interrupt is enabled + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_IE + RFIP_BUSY_STATUS_IE: interrupt enable on RFIP_BUSY_STATUS signal: +0: RFIP_BUSY_STATUS interrupt is disabled (default). +1: RFIP_BUSY_STATUS interrupt is enabled + 5 + 1 + read-write + + + + + INTAI_ISCR + INTAI_ISCR + INTAI_ISCR register + 0x3C + 0x20 + read-write + 0x000000000 + + + TX_ISC + TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): +0: no activity on TX_SEQUENCE detected. +1: activity on TX_SEQUENCE occurred + 0 + 1 + read-write + + + RX_ISC + RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): +0: no activity on RX_SEQUENCE detected. +1: activity on RX_SEQUENCE occurred + 1 + 1 + read-write + + + TX_ISEDGE + TX_ISEDGE: interrupt edge status on TX_SEQUENCE signal: +0: falling edge on TX_SEQUENCE detected. +1: rising edge on TX_SEQUENCE detected. + 2 + 1 + read-only + + + RX_ISEDGE + RX_ISEDGE: interrupt edge status on RX_SEQUENCE signal: +0: falling edge on RX_SEQUENCE detected. +1: rising edge on RX_SEQUENCE detected. + 3 + 1 + read-only + + + COMP_ISC + COMP_ISC: interrupt status on COMP_OUT (can be a rising or a falling edge depending on +INTAI_IEVR and INTAI_IBER): +0: no activity on COMP_OUT detected. +1: activity on COMP_OUT occurred + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_ISC + RFIP_BUSY_STATUS_ISC: interrupt status on RFIP_BUSY_STATUS (can be a rising or a +falling edge depending on INTAI_IEVR and INTAI_IBER): +0: no activity on RFIP_BUSY_STATUS detected. +1: activity on RFIP_BUSY_STATUS occurred + 5 + 1 + read-write + + + + + SYSCFG_SR1 + SYSCFG_SR1 + SYSCFG_SR1 register + 0x40 + 0x20 + read-only + 0x000000000 + + + RFIP_BUSY_STATUS + RFIP_BUSY_STATUS: MR_SUBG BUSY status: +Software should check that MR_SUBG IP is not busy (or relay on the related interrupt) before +to initiate any system clock frequency switch to operate the switching in a safe way. +0: MR_SUBG is not busy. +1: MR_SUBG is busy + 5 + 1 + read-only + + + + + RF_DTB_CONFIG + RF_DTB_CONFIG + RF_DTB_CONFIG register + 0x44 + 0x20 + read-write + 0x000000000 + + + RF_DTB_CONFIG + Controlling AF7 extended mode: +- 00 : MR_SUBG DTB default configuration +- 01 : MR_SUBG DTB shuffled configuration +- 10 : BUBBLE_DTB configuration +- 11 : MR_SUBG DTB default configuration (as per 00) + 0 + 2 + read-write + + + + + + + SWITCHABLE + SWITCHABLE + 0x49001040 + + 0x0 + 0x40 + registers + + + + RFIP_VERSION + RFIP_VERSION + RFIP_VERSION register + 0x0 + 0x20 + read-only + 0x00001100 + + + REVISION + Revision of the RFIP to be used for metal fixes) + 4 + 4 + read-only + + + VERSION + Version of the RFIP (to be used for cut upgrades) + 8 + 4 + read-only + + + PRODUCT + Used for major upgrades (new protocols support / new features) + 12 + 4 + read-only + + + + + IRQ_ENABLE + IRQ_ENABLE + IRQ_ENABLE register + 0x4 + 0x20 + read-write + 0x00000000 + + + BIT_SYNC_DETECTED_E + Preamble has been detected, the content of the PAYLOAD_X registers is not yet valid. + 0 + 1 + read-write + + + FRAME_SYNC_COMPLETE_E + Frame Sync has been detected, the content of the PAYLOAD_X registers is not yet valid. + 1 + 1 + read-write + + + FRAME_COMPLETE_E + Frame ( payload + CRC) received, the content of the PAYLOAD_X registers is valid. + 2 + 1 + read-write + + + FRAME_VALID_E + Frame ( payload + CRC) received wthout error (the CRC has been checked and is matching with the received CRC). + 3 + 1 + read-write + + + + + STATUS + STATUS + STATUS register + 0x8 + 0x20 + read-write + 0x00000000 + + + BIT_SYNC_DETECTED_F + Preamble has been detected, the content of the PAYLOAD_X registers is not yet valid. + 0 + 1 + read-write + + + FRAME_SYNC_COMPLETE_F + Frame Sync has been detected, the content of the PAYLOAD_X registers is not yet valid. + 1 + 1 + read-write + + + FRAME_COMPLETE_F + Frame ( payload + CRC) received, the content of the PAYLOAD_X registers is valid. + 2 + 1 + read-write + + + FRAME_VALID_F + Frame ( payload + CRC) received wthout error (the CRC has been checked and is matching with the received CRC). + 3 + 1 + read-write + + + ERROR_F + - 11 : CRC error + + 30 + 2 + read-write + + + + + + + STATUS + STATUS + 0x49000600 + + 0x0 + 0x40 + registers + + + + RFSEQ_IRQ_STATUS + RFSEQ_IRQ_STATUS + RFSEQ_IRQ_STATUS register + 0x0 + 0x20 + read-write + 0x00000000 + + + TX_DONE_F + Transmission done flag + 0 + 1 + + + RX_OK_F + Reception ended and OK flag + 1 + 1 + + + RX_TIMEOUT_F + Reception timeout flag + 2 + 1 + + + RX_CRC_FRROR_F + Reception with CRC error flag + 3 + 1 + + + FAST_RX_TERM_F + Fast RX Termination flag + 4 + 1 + + + RXTIMER_STOP_CDT_F + Enable interrupt on RXTIMER_STOP_CDT_F flag + 7 + 1 + + + SABORT_DONE_F + SABORT command treated and done flag + 8 + 1 + + + COMMAND_REJECTED_F + Command rejection flag. + 9 + 1 + + + CS_F + Carrier Sense (RSSI over threshold) flag + 12 + 1 + + + PREAMBLE_VALID_F + Valid PREAMBLE detection flag. + 13 + 1 + + + SYNC_VALID_F + Valid SYNC word detection flag. + 14 + 1 + + + DATABUFFER0_USED_F + Data Buffer 0 fully read in TX or fully written in RX flag + 16 + 1 + + + DATABUFFER1_USED_F + Data Buffer 1 fully read in TX or fully written in RX flag + 17 + 1 + + + RX_ALMOST_FULL_0_F + Data Buffer0 used (written during a RX) up to programmed thresold flag + 18 + 1 + + + RX_ALMOST_FULL_1_F + Data Buffer1 used (written during a RX) up to programmed thresold flag + 19 + 1 + + + TX_ALMOST_EMPTY_0_F + Data Buffer0 used (read during a TX) up to programmed thresold flag + 20 + 1 + + + TX_ALMOST_EMPTY_1_F + Data Buffer1 used (read during a TX) up to programmed thresold flag + 21 + 1 + + + AHB_ACCESS_ERROR_F + An AHB transfer issue occurred for one of the AHB masters (RRM, Data Buffer Manager, Sequencer). + 22 + 1 + + + HW_ANA_FAILURE_F + Analog HW failure flag (PLL lock / unlock error, calibration error) + + 24 + 1 + + + SEQ_F + Sequencer completion flag. + 26 + 1 + + + RRM_CMD_START_F + RRM-UDRA command list execution started flag. + 27 + 1 + + + RRM_CMD_END_F + RRM-UDRA command list execution ended flag. + 28 + 1 + + + SAFEASK_CALIB_DONE_F + End of Safe-ASK PA calibration flag. + 30 + 1 + + + AGC_CALIB_DONE_F + Valid RSSI value available in the RSSI_RUNNING bit field flag. + 31 + 1 + + + + + RFSEQ_STATUS_DETAIL + RFSEQ_STATUS_DETAIL + RFSEQ_STATUS_DETAIL register + 0x4 + 0x20 + read-write + 0x00000000 + + + DBM_FIFO_ERROR_F + Data Buffer Manager internal FIFO overflow/underflow flag. + 5 + 1 + + + PLL_LOCK_FAIL_F + PLL lock fail status flag + 8 + 1 + + + PLL_UNLOCK_F + PLL unlock event flag + 9 + 1 + + + PLL_CALFREQ_ERROR_F + VCO frequency calibration error flag + 10 + 1 + + + PLL_CALAMP_ERROR_F + VCO amplitude calibration error flag + 11 + 1 + + + SEQ_ACTIONTIMEOUT_F + The Sequencer has ended because the current SeqAction reached its ActionTimeout. + 14 + 1 + + + SEQ_COMPLETE_F + The Sequencer has ended the last defined SeqAction properly( NextAction math or null pointer) + 15 + 1 + + + + + RADIO_FSM_INFO + RADIO_FSM_INFO + RADIO_FSM_INFO register + 0x8 + 0x20 + read-only + 0x00000000 + + + RADIO_FSM_STATE + State of the Radio FSM + + 0 + 5 + read-only + + + + + RX_INDICATOR + RX_INDICATOR + RX_INDICATOR register + 0xc + 0x20 + read-only + 0x00000000 + + + RSSI_LEVEL_ON_SYNC + RSSI level captured at the end of the SYNC word detection of the received packet. + 0 + 9 + read-only + + + RSSI_LEVEL_RUN + Continuous level of the output of the measured RSSI value + 12 + 9 + read-only + + + AGC_WORD + AGC word of the received packet. + 24 + 4 + read-only + + + ANT_SELECT + Currently selected antenna + 31 + 1 + read-only + + + + + RX_INFO_REG + RX_INFO_REG + RX_INFO_REG register + 0x10 + 0x20 + read-only + 0x00000000 + + + RX_PCKTLEN_OUT + Indicates received packet length in bytes: + + 0 + 16 + read-only + + + + + RX_CRC_REG + RX_CRC_REG + RX_CRC_REG register + 0x14 + 0x20 + read-only + 0x00000000 + + + RX_CRC_OUT + CRC field of the received packet (read-only info) + 0 + 32 + read-only + + + + + QI_INFO + QI_INFO + QI_INFO register + 0x18 + 0x20 + read-only + 0x00000000 + + + PQI_INFO + Preamble Quality Indicator (PQI) value of the received packet. + 0 + 8 + read-only + + + SQI_INFO + SYNC Quality Indicator (SQI) value of the received packet. + 8 + 6 + read-only + + + SQI_SEC + Indicate if measured SQI refers to SYNC word or secondary SYNC word + + 14 + 1 + read-only + + + AFC_CORRECTION + AFC value frozen at sync reception. + 16 + 8 + read-only + + + + + DATABUFFER_INFO + DATABUFFER_INFO + DATABUFFER_INFO register + 0x1c + 0x20 + read-only + 0x00000000 + + + CURRENT_DATABUFFER_COUNT + Indicates the number of bytes used in the last used DATA BUFFER. + 0 + 16 + read-only + + + NB_DATABUFFER_USED + Provides the number of data buffers which have been fully used + + 16 + 15 + read-only + + + CURRENT_DATABUFFER + Indicates which Data Buffer is currently used by the HW + + 31 + 1 + read-only + + + + + TIME_CAPTURE + TIME_CAPTURE + TIME_CAPTURE register + 0x20 + 0x20 + read-only + 0x00000000 + + + TIME_CAPTURE + Interpolated absolute time value captured on specific programmable event through TIME_CAPTURESEL[2:0] bit field. + 0 + 32 + read-only + + + + + IQC_CORRECTION_OUT + IQC_CORRECTION_OUT + IQC_CORRECTION_OUT register + 0x24 + 0x20 + read-only + 0x00000000 + + + IQC_CORRECT_OUT + Final correction value output from IQC (compensation engine). + 0 + 24 + read-only + + + + + PA_SAFEASK_OUT + PA_SAFEASK_OUT + PA_SAFEASK_OUT register + 0x28 + 0x20 + read-only + 0x00000000 + + + PA_CODEMAX + Safe ASK level (provided after a CALIB_SAFEASK command), indicating the maximum PA Power to program before reaching ohmic saturation. + 0 + 8 + read-only + + + + + VCO_CALIB_OUT + VCO_CALIB_OUT + VCO_CALIB_OUT register + 0x2c + 0x20 + read-only + 0x0000FF40 + + + VCO_CALFREQ_OUT + VCO frequency calibration value currently output by the VCO calibration block (and applied on the VCO when ON) + + 0 + 7 + read-only + + + VCO_CALAMP_OUT + VCO amplitude calibration value currently output by the VCO calibration block (and applied on the VCO when ON) + + 8 + 14 + read-only + + + + + SEQ_INFO + SEQ_INFO + SEQ_INFO register + 0x30 + 0x20 + read-only + 0x00000000 + + + SEQ_FSM_STATE + Current state of the Sequencer + + 0 + 5 + read-only + + + + + SEQ_EVENT_STATUS + SEQ_EVENT_STATUS + SEQ_EVENT_STATUS register + 0x34 + 0x20 + read-only + 0x00000000 + + + SEQ_EVENT_STATUS + Current value of the seq_event_status used by the Sequencer for next action mask comparison. + 0 + 32 + read-only + + + + + + + STATIC + STATIC + 0x49000400 + + 0x0 + 0x40 + registers + + + + PCKT_CONFIG + PCKT_CONFIG + PCKT_CONFIG register + 0x0 + 0x20 + read-write + 0x000103F1 + + + CRC_MODE + CRC type (0, 8, 16, 16 802. + 0 + 3 + read-write + + + SECONDARY_SYNC_SEL + In TX mode: this bit selects which synchro word is sent on the frame between SYNC and SEC_SYNC + + 3 + 1 + read-write + + + SYNC_LEN + Length of the SYNC (and secondary) SYNC word in 1-bit granularity + + 4 + 5 + read-write + + + SYNC_PRESENT + Indicate if a SYNC word is present on the frame or not (null length) + + 9 + 1 + read-write + + + LEN_WIDTH + Indicates if the LENGTH field is defined on 1 byte or 2 bytes + + 10 + 1 + read-write + + + FIX_VAR_LEN + Select the length mode + + 11 + 1 + read-write + + + PREAMBLE_LENGTH + Length of the PREAMBLE in pairs of bits (0 to 2046) + 12 + 10 + read-write + + + PREAMBLE_SEQ + Select the PREAMBLE pattern to be applied + + 22 + 2 + read-write + + + POSTAMBLE_LENGTH + Length of the POSTAMBLE in pair of bits (0 to 126 bits) + 24 + 6 + read-write + + + POSTAMBLE_SEQ + Packet postamble control: postamble bit sequence selection + + 30 + 2 + read-write + + + + + SYNC + SYNC + SYNC register + 0x4 + 0x20 + read-write + 0x23232323 + + + SYNC + Synchro word. + 0 + 32 + read-write + + + + + SEC_SYNC + SEC_SYNC + SEC_SYNC register + 0x8 + 0x20 + read-write + 0x00000000 + + + SEC_SYNC + Secondary Synchro word. + 0 + 32 + read-write + + + + + CRC_INIT + CRC_INIT + CRC_INIT register + 0xc + 0x20 + read-write + 0x00000000 + + + CRC_INIT_VAL + CRC intialization value + 0 + 32 + read-write + + + + + PCKT_CTRL + PCKT_CTRL + PCKT_CTRL register + 0x10 + 0x20 + read-write + 0x00000000 + + + PCKT_FORMAT + Packet format + + 0 + 1 + read-write + + + BYTE_SWAP + Invert MSB-LSB transmission order (bitendianess) + + 2 + 1 + read-write + + + FOUR_FSK_SYM_SWAP + Invert bit to symbol mapping for 4-(G)FSK + + 3 + 1 + read-write + + + RX_MODE + RX mode + + 4 + 3 + read-write + + + TX_MODE + TX mode + + 7 + 2 + read-write + + + WHIT_BF_FEC + Whitening before FEC feature + + 10 + 1 + read-write + + + WHIT_EN + Whitening enable + + 11 + 1 + read-write + + + WHIT_INIT + Whitening initialization value. + 12 + 9 + read-write + + + CODING_SEL + Coding / decoding selection + + 21 + 2 + read-write + + + MANCHESTER_TYPE + Select the Manchester encoding polarity + + 24 + 1 + read-write + + + INT_EN_4G + This field is used as Interleaving enable for 802. + 25 + 1 + read-write + + + FEC_TYPE_4G + FEC type for 802. + 26 + 1 + read-write + + + FCS_TYPE_4G + FCS type value in header field for 802. + 27 + 1 + read-write + + + MOD_INTERP_EN + Enable frequency interpolator (for 2-GFSK and 4-GFSK) + + 28 + 1 + read-write + + + PN_SEL + Select the Pseudo Random Binary Sequence (PRBS) polynomial to apply when the selected transmission mode is PN mode (TX_MODE = '11') + + 29 + 1 + read-write + + + FORCE_2FSK_SYNC_MODE + Force SYNC word to be formatted as a 2-(G)FSK bit steam instead of 4-(G)FSK + + 31 + 1 + read-write + + + + + DATABUFFER0_PTR + DATABUFFER0_PTR + DATABUFFER0_PTR register + 0x14 + 0x20 + read-write + 0x00000000 + + + DATABUFFER0_PTR + Start address to be used by the Data Buffer0 + + 2 + 30 + read-write + + + + + DATABUFFER1_PTR + DATABUFFER1_PTR + DATABUFFER1_PTR register + 0x18 + 0x20 + read-write + 0x00000000 + + + DATABUFFER1_PTR + Start address to be used by the Data Buffer1 + + 2 + 30 + read-write + + + + + DATABUFFER_SIZE + DATABUFFER_SIZE + DATABUFFER_SIZE register + 0x1c + 0x20 + read-write + 0x00000000 + + + DATABUFFER_SIZE + Size of the Data Buffers (Data Buffer0 and Data Buffer1) expressed in byte unit. + 0 + 16 + read-write + + + + + PA_LEVEL_3_0 + PA_LEVEL_3_0 + PA_LEVEL_3_0 register + 0x20 + 0x20 + read-write + 0x230B0100 + + + PA_LEVEL0 + Output power level for first step + + 0 + 8 + read-write + + + PA_LEVEL1 + Output power level for second step + + 8 + 8 + read-write + + + PA_LEVEL2 + Output power level for third step + + 16 + 8 + read-write + + + PA_LEVEL3 + Output power level for fourth step + + 24 + 8 + read-write + + + + + PA_LEVEL_7_4 + PA_LEVEL_7_4 + PA_LEVEL_7_4 register + 0x24 + 0x20 + read-write + 0x51473B2F + + + PA_LEVEL4 + Output power level for fifth step + + 0 + 8 + read-write + + + PA_LEVEL5 + Output power level for sixth step + + 8 + 8 + read-write + + + PA_LEVEL6 + Output power level for seventh step + + 16 + 8 + read-write + + + PA_LEVEL7 + Output power level for eighth step + + 24 + 8 + read-write + + + + + PA_CONFIG + PA_CONFIG + PA_CONFIG register + 0x28 + 0x20 + read-write + 0x0000015C + + + PA_RAMP_STEP_WIDTH + Step width (unit: 1/8 of bit period). + 0 + 2 + read-write + + + PA_LEVEL_MAX_INDEX + Final level for power ramping (i. + 2 + 3 + read-write + + + PA_INTERP_EN + Enable power level interpolator. + 6 + 1 + read-write + + + ASK_OOK_EN + Enable the generation of the internal TXDATA signal provided to the FIR. + 7 + 1 + read-write + + + PA_DRV_MODE + Select the PA topology + + 8 + 2 + read-write + + + PA_MODE + Configure the Power Amplifier (PA) mode + + 10 + 2 + read-write + + + LIN_NLOG + Enable/disable the linear-to- log conversion of the PA code output from Safe-ASK calibrator + + 13 + 1 + read-write + + + PA_RAMP_ENABLE + Enable the power ramping + + 14 + 1 + read-write + + + + + IF_CTRL + IF_CTRL + IF_CTRL register + 0x2c + 0x20 + read-write + 0x04CD04CD + + + IF_OFFSET_DIG + Intermediate frequency setting for the digital shift-to-baseband circuits (default: 300 kHz) + + 0 + 13 + read-write + + + IF_OFFSET_ANA + Intermediate frequency setting for the synthesizer configuration (default: 300 kHz). + 16 + 13 + read-write + + + IF_MODE + Select the cutoff frequency of the AAF for the analog RFSUBG IP + + 31 + 1 + read-write + + + + + AS_QI_CTRL + AS_QI_CTRL + AS_QI_CTRL register + 0x30 + 0x20 + read-write + 0x58008028 + + + RSSI_THR + Signal detect threshold in 1 dB resolution. + 0 + 9 + read-write + + + PQI_THR + PQI threshold (if 0 then ). + 9 + 4 + read-write + + + CS_MODE + Carrier Sense mode selection + + 13 + 2 + read-write + + + SQI_EN + SQI enable + + 15 + 1 + read-write + + + SQI_THR + SQI threshold defining the precision requested to detect the SYNC word. + 16 + 3 + read-write + + + AS_EQU_CTRL + ISI cancellation equalizer + + 26 + 2 + read-write + + + AS_MEAS_TIME + Select the RSSI measurement duration during Antenna switching procedure + 28 + 3 + read-write + + + AS_CS_BLANKING + Blank received data if signal is below the CS threshold + + 31 + 1 + read-write + + + + + IQC_CONFIG + IQC_CONFIG + IQC_CONFIG register + 0x34 + 0x20 + read-write + 0xC0000000 + + + IQC_CORRECT_IN + Correction value Input for the IQ compensation engine (to be used as starting point or when the engine is disabled). + 0 + 24 + read-write + + + LOAD_IQC_INIT + Action bit to load the IQC_CORRECT_IN[23:0] bit field in the recirculation register when this bit is written to 1. + 29 + 1 + write-only + + + REUSE_CORRECTION + Reuse last correction value + 30 + 1 + read-write + + + IQC_ENABLE + Enable IQC + 31 + 1 + read-write + + + + + DSSS_CTRL + DSSS_CTRL + DSSS_CTRL register + 0x38 + 0x20 + read-write + 0x00000000 + + + ACQ_WINDOW + DSSS acquisition window + 0 + 4 + read-write + + + SPREADING_EXP + DSSS spreading exponent + 4 + 3 + read-write + + + DSSS_EN + DSSS mode enable + 7 + 1 + read-write + + + ACQ_HITS + DSSS acquisition hits + 8 + 2 + read-write + + + ACQ_THR + DSSS acquisition threshold + 10 + 6 + read-write + + + + + + + TIM16 + TIM16 address block description + TIM16 + 0x40005000 + + 0x0 + 0x6C + registers + + + TIM16 + TIM16 interrupt + 26 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIF_REMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + CCPC + CCPC: Capture/compare preloaded control + +0: CCxE, CCxNE and OCxM bits are not preloaded + +1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated + +only when COM bit is set. + +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + CCUS + CCUS: Capture/compare control update selection + +0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit only. + +1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit or when an rising edge occurs on TRGI. + +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + CCDS + CCDS: Capture/compare DMA selection + +0: CCx DMA request sent when CCx event occurs + +1: CCx DMA requests sent when update event occurs + 3 + 1 + read-write + + + MMS + MMS[2:0]: Master mode selection + +These bits allow to select the information to be sent in master mode to slave timers for + +synchronization (TRGO). The combination is as follows: + +000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the + +reset is generated by the trigger input (slave mode controller configured in reset mode) then + +the signal on TRGO is delayed compared to the actual reset. + +001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is + +useful to start several timers at the same time or to control a window in which a slave timer is + +enable. The Counter Enable signal is generated by a logic OR between CEN control bit and + +the trigger input when configured in gated mode. When the Counter Enable signal is + +controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is + +selected (see the MSM bit description in TIMx_SMCR register). + +010: Update - The update event is selected as trigger output (TRGO). For instance a master + +timer can then be used as a prescaler for a slave timer. + +011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be + +set (even if it was already high), as soon as a capture or a compare match occurred. + +(TRGO). + +100: Compare - OC1REF signal is used as trigger output (TRGO). + 4 + 3 + read-write + + + TI1S + TI1S: TI1 selection + +0: The TIMx_CH1 pin is connected to TI1 input + +1: Reserved + 7 + 1 + read-write + + + OIS1 + OIS1: Output Idle state 1 (OC1 output) + +0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + +1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 8 + 1 + read-write + + + OIS1N + OIS1N: Output Idle state 1 (OC1N output) + +0: OC1N=0 after a dead-time when MOE=0 + +1: OC1N=1 after a dead-time when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 9 + 1 + read-write + + + + + SMCR + SMCR + SMCR register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + SMS_2_0 + SMS[3:0]: Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to +the polarity selected on the external input (see Input Control register and Control Register +description. + 0 + 3 + read-write + + + TS_2_0 + TS[4:0]: Trigger selection + +This bitfield selects the trigger input to be used to synchronize the counter. + +00000: Internal Trigger 0 (ITR0) + +00001: Internal Trigger 1 (ITR1) + +00010: Internal Trigger 2 (ITR2) + +00011: Internal Trigger 3 (ITR3) + +00100: TI1 Edge Detector (TI1F_ED) + +00101: Filtered Timer Input 1 (TI1FP1) + +Other codes: Reserved + +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to + +avoid wrong edge detections at the transition. + +See Table 79 in IUM: TIM16 register map and reset values on page 469 for more details on ITRx + +meaning for each Timer. + 4 + 3 + read-write + + + MSM + MSM: Master/slave mode + +0: No action + +1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect + +synchronization between the current timer and its slaves (through TRGO). It is useful if we + +want to synchronize several timers on a single external event. + 7 + 1 + read-write + + + SMS_3 + SMS[3:0]: Slave mode selection. See SMS_LSB description + 16 + 1 + read-write + + + TS_4_3 + TS[4:0]: Trigger selection. See TS_LSB description + 20 + 2 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + COMIE + COMIE: COM interrupt enable + +0: COM interrupt disabled + +1: COM interrupt enabled + 5 + 1 + read-write + + + TIE + TIE: Trigger interrupt enable + +0: Trigger interrupt disabled + +1: Trigger interrupt enabled + 6 + 1 + read-write + + + BIE + BIE: Break interrupt enable + +0: Break interrupt disabled + +1: Break interrupt enabled + 7 + 1 + read-write + + + UDE + UDE: Update DMA request enable + +0: Update DMA request disabled + +1: Update DMA request enabled + 8 + 1 + read-write + + + CC1DE + CC1DE: Capture/Compare 1 DMA request enable + +0: CC1 DMA request disabled + +1: CC1 DMA request enabled + 9 + 1 + read-write + + + CCUDE + CCUDE: CC-Update DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: CC-Update DMA request disabled. + +1: CC-Update DMA request enabled. + 13 + 1 + read-write + + + TDE + TDE: Trigger DMA request enable + +0: Trigger DMA request disabled + +1: Trigger DMA request enabled + 14 + 1 + read-write + + + BDE + BDE: Break DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: Break DMA request disabled. + +1: Break DMA request enabled. + 15 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value. It is cleared by + +software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + COMIF + COMIF: COM interrupt flag + +This flag is set by hardware on a COM event (once the capture compare control bits CCxE, + +CCxNE, OCxMhave been updated). It is cleared by software. + +0: No COM event occurred + +1: COM interrupt pending + 5 + 1 + read-write + + + TIF + TIF: Trigger interrupt flag + +This flag is set by hardware on trigger event (active edge detected on TRGI input when the + +slave mode controller is enabled in all modes but gated mode, both edges in case gated + +mode is selected). It is cleared by software. + +0: No trigger event occurred + +1: Trigger interrupt pending + 6 + 1 + read-write + + + BIF + BIF: Break interrupt flag + +This flag is set by hardware as soon as the break input goes active. It can be cleared by + +software if the break input is not active. + +0: No break event occurred + +1: An active level has been detected on the break input + 7 + 1 + read-write + + + CC1OF + CC1OF: Capture_Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + COMG + COMG: Capture/Compare control update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action + +1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + +Note: This bit acts only on channels that have a complementary output. + 5 + 1 + write-only + + + TG + TG: Trigger generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action + +1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if + +enabled + 6 + 1 + write-only + + + BG + BG: Break generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or + +DMA transfer can occur if enabled. + 7 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately.. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M[2:0]: Output Compare 1 mode (bits 2 to 0) +These bits define the behavior of the output reference signal OC1REF from which OC1 and +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends +on CC1P and CC1NP bits. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable. + +Not used in Blue51. Not available in IUM + +0: OC1REF is not affected by the ocref_clr_int signal. + +1: OC1REF is cleared as soon as a high level is detected on the ocref_clr_int signal. + 7 + 1 + read-write + + + OC1M_3 + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1_in register + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x1 + Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + 0x1 + + + + + CC1NE + CC1NE: Capture/Compare 1 complementary output enable + +0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1E bits. + +1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1E bits. + 2 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 complementary output polarity + +CC1 channel configured as output: + +0: OC1N active high + +1: OC1N active low + +CC1 channel configured as input: + +This bit is used in conjunction with CC1P to define the polarity of TI1FP1. Refer + +to the description of CC1P. + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the + +preloaded bit only when a commutation event is generated. + 3 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIF_CPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0xFFFF + 0xFFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x0 + 0xF + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 8 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + CCR + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + BDTR + BDTR + BDTR register + 0x44 + 0x20 + read-write + 0x0 + 0xF + + + DTG + DTG[7:0]: Dead-time generator setup + +This bit-field defines the duration of the dead-time inserted between the complementary + +outputs. DT correspond to this duration. + +DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS + +DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS + +DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS + +DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS + +Example if TDTS=125ns (8MHz), dead-time possible values are: + +0 to 15875 ns by 125 ns steps, + +16 us to 31750 ns by 250 ns steps, + +32 us to 63 us by 1 us steps, + +64 us to 126 us by 2 us steps + +Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BDTR register). + 0 + 8 + read-write + + + LOCK + LOCK[1:0]: Lock configuration + +These bits offer a write protection against software errors. + +00: LOCK OFF - No bit is write protected + +01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 + +register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in + +TIMx_AF1 register can no longer be written. + +10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER + +register, as long as the related channel is configured in output through the CCxS bits) as well + +as OSSR and OSSI bits can no longer be written. + +11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in + +TIMx_CCMRx registers, as long as the related channel is configured in output through the + +CCxS bits) can no longer be written. + +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + +has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + OSSI + OSSI: Off-state selection for Idle mode + +This bit is used when MOE=0 on channels configured as outputs. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + +1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or + +CCxNE=1. OC/OCN enable output signal=1) + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 10 + 1 + read-write + + + OSSR + OSSR: Off-state selection for Run mode + +This bit is used when MOE=1 on channels that have a complementary output which are + +configured as outputs. OSSR is not implemented if no complementary output is implemented + +in the timer. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which + +is taken over by the AFIO logic, which forces a Hi-Z state) + +1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 + +or CCxNE=1 (the output is still controlled by the timer). + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 11 + 1 + read-write + + + BKE + BKE: Break enable + +1; Break inputs (BRK) enabled + +Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in + +TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK) disabled + 0x0 + + + + + BKP + BKP: Break polarity + +0: Break input BRK is active low. + +1: Break input BRK is active high + +Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + AOE + AOE: Automatic output enable + +not be active) + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is + 0x1 + + + + + MOE + MOE: Main output enable + +This bit is cleared asynchronously by hardware as soon as the break input is active. It is set + +by software or automatically depending on the AOE bit. It is acting only on the channels + +which are configured in output. + +0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + +1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in + +TIMx_CCER register) + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + 15 + 1 + read-write + + + BKDSRM + BKDSRM: Break Disarm + +0: Break input BRK is armed + +1: Break input BRK is disarmed + +This bit is cleared by hardware when no break source is active. + +The BKDSRM bit must be set by software to release the bidirectional output control (opendrain + +output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the + +fault condition has disappeared. + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + BKBID + BKBID: Break Bidirectional + +0: Break input BRK in input mode + +1: Break input BRK in bidirectional mode + +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input + +mode and in open drain output mode. Any active break event asserts a low logic level on the + +Break input to indicate an internal break event to external devices. + +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + + + DCR + DCR + DCR register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + DBA + DBA[4:0]: DMA base address + +This 5-bit field defines the base-address for DMA transfers (when read/write access are + +done through the TIMx_DMAR address). DBA is defined as an offset starting from the + +address of the TIMx_CR1 register. + +Example: + +00000: TIMx_CR1, + +00001: TIMx_CR2, + +00010: Reserved, + +... + +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In + +this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + DBL + DBL[4:0]: DMA burst length + +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when + +a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. + +Transfers can be in half-words or in bytes (see example below). + +00000: 1 transfer, + +00001: 2 transfers, + +00010: 3 transfers, + +... + +10001: 18 transfers. + 8 + 5 + read-write + + + + + DMAR + DMAR + DMAR register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + DMAB + DMAB[15:0]: DMA register for burst accesses + +A read or write operation to the DMAR register accesses the register located at the address + +(TIMx_CR1 address) + (DBA + DMA index) x 4 + +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base + +address configured in TIMx_DCR register, DMA index is automatically controlled by the + +DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 16 + read-write + + + + + OR1 + OR1 + OR1 register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + OR1_0 + Not used in Blue51. Not available in IUM + 0 + 1 + read-write + + + TI1_RMP + TI1_RMP[1:0]: Timer 16 input 1 connection + +This bit is set and cleared by software. + +00: TIM16 TI1 is connected to GPIO + +01: TIM16 TI1 is connected to LCO + +10: TIM16 TI1 is connected to COMP_OUT + +11: TIM16 TI1 is connected to MCO + 1 + 2 + read-write + + + + + AF1 + AF1 + AF1 register + 0x60 + 0x20 + read-write + 0x1 + 0xF + + + BKINE + BKINE: BRK BKIN enable. + +This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is + +ORed with the other enabled BRK sources. + +0: BKIN input disabled. + +1: BKIN input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 0 + 1 + read-write + + + BKCMP1E + BKCMP1E: BRK COMP1 enable. + +This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other + +enabled BRK sources. + +0: COMP1 input disabled. + +1: COMP1 input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 1 + 1 + read-write + + + BKINP + BKINP: BRK BKIN input polarity. + +This bit selects the BKIN alternate function input sensitivity. It must be programmed together + +with the BKP polarity bit. + +0: BKIN input is active low. + +1: BKIN input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 9 + 1 + read-write + + + BKCMP1P + BKCMP1P: BRK COMP1 input polarity. + +This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP + +polarity bit. + +0: COMP1 input is active low. + +1: COMP1 input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 10 + 1 + read-write + + + + + TISEL + TISEL + TISEL register + 0x68 + 0x20 + read-write + + + TI1SEL + TI1SEL[3:0]: selects TI1[0] to TI1[15] input + +0000: TIMx_CH1 input + +Others: Reserved + 0 + 4 + read-write + + + + + + + TIM2 + TIM2 address block description + TIM2 + 0x40002000 + + 0x0 + 0x6C + registers + + + TIM2 + TIM2 interrupt + 10 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + DIR + DIR: Direction + +0: Counter used as upcounter + +1: Counter used as downcounter + +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder + +mode. + 4 + 1 + read-write + + + CMS + CMS[1:0]: Center-aligned mode selection + +00: Edge-aligned mode. The counter counts up or down depending on the direction bit + +(DIR). + +01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting down. + +10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting up. + +11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +both when the counter is counting up or down. + +Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as + +the counter is enabled (CEN=1) + 5 + 2 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIF_REMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + CCDS + CCDS: Capture/compare DMA selection + +0: CCx DMA request sent when CCx event occurs + +1: CCx DMA requests sent when update event occurs + 3 + 1 + read-write + + + MMS + MMS[2:0]: Master mode selection + +These bits allow to select the information to be sent in master mode to slave timers for + +synchronization (TRGO). The combination is as follows: + +000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the + +reset is generated by the trigger input (slave mode controller configured in reset mode) then + +the signal on TRGO is delayed compared to the actual reset. + +001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is + +useful to start several timers at the same time or to control a window in which a slave timer is + +enabled. The Counter Enable signal is generated by a logic OR between CEN control bit + +and the trigger input when configured in gated mode. + +When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, + +except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR + +register). + +010: Update - The update event is selected as trigger output (TRGO). For instance a master + +timer can then be used as a prescaler for a slave timer. + +011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be + +set (even if it was already high), as soon as a capture or a compare match occurred. + +(TRGO) + +100: Compare - OC1REF signal is used as trigger output (TRGO) + +101: Compare - OC2REF signal is used as trigger output (TRGO) + +110: Compare - OC3REF signal is used as trigger output (TRGO) + +111: Compare - OC4REF signal is used as trigger output (TRGO) + +Note: The clock of the slave timer must be enabled prior to receive events from the master + +timer, and must not be changed on-the-fly while triggers are received from the master + +timer. + 4 + 3 + read-write + + + TI1S + TI1S: TI1 selection + +0: The TIMx_CH1 pin is connected to TI1 input. + +1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 7 + 1 + read-write + + + + + SMCR + SMCR + SMCR register + 0x08 + 0x20 + read-write + 0x0 + 0x0 + + + SMS_2_0 + SMS: Slave mode selection + +When external signals are selected the active edge of the trigger signal (TRGI) is linked to + +the polarity selected on the external input (see Input Control register and Control Register + +description. + +0000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal + +clock. + +0001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 + +level. + +0010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 + +level. + +0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges + +depending on the level of the other input. + +0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter + +and generates an update of the registers. + +0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The + +counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of + +the counter are controlled. + +0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not + +reset). Only the start of the counter is controlled. + +0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + +1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) + +reinitializes the counter, generates an update of the registers and starts the counter. + +Codes above 1000: Reserved. + +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input + +(TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the + +gated mode checks the level of the trigger signal. + 0 + 3 + read-write + + + OCCS + OCCS: OCREF clear selection + +This bit is used to select the OCREF clear source. + +0: OCREF_CLR_INT is connected to the OCREF_CLR input (stuck at 0 so no effect) + +1: OCREF_CLR_INT is connected to ETRF + 3 + 1 + read-write + + + TS_2_0 + TS[4:0]: Trigger selection + +This bit-field selects the trigger input to be used to synchronize the counter. + +00000: Internal Trigger 0 (ITR0) + +00001: Internal Trigger 1 (ITR1) + +00010: Internal Trigger 2 (ITR2) + +00011: Internal Trigger 3 (ITR3) + +00100: TI1 Edge Detector (TI1F_ED) + +00101: Filtered Timer Input 1 (TI1FP1) + +00110: Filtered Timer Input 2 (TI2FP2) + +00111: External Trigger input (ETRF) + +Others: Reserved + +See Table Note:: TIM2 internal trigger connection on page 395 for more details on ITRx + +meaning for each Timer. + +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to + +avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + MSM + MSM: Master/Slave mode + +0: No action + +1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect + +synchronization between the current timer and its slaves (through TRGO). It is useful if we + +want to synchronize several timers on a single external event. + 7 + 1 + read-write + + + ETF + ETF[3:0]: External trigger filter + +This bit-field then defines the frequency used to sample ETRP signal and the length of the + +digital filter applied to ETRP. The digital filter is made of an event counter in which N events + +are needed to validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N=6 + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 8 + 4 + read-write + + + ETPS + ETPS[1:0]: External trigger prescaler + +External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A + +prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external + +clocks. + +00: Prescaler OFF + +01: ETRP frequency divided by 2 + +10: ETRP frequency divided by 4 + +11: ETRP frequency divided by 8 + 12 + 2 + read-write + + + ECE + ECE: External clock enable + +This bit enables External clock mode 2. + +0: External clock mode 2 disabled + +1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF + +signal. + +Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with + +TRGI connected to ETRF (SMS=111 and TS=111). + +Note: 2: It is possible to simultaneously use external clock mode 2 with the following slave + +modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be + +connected to ETRF in this case (TS bits must not be 111). + +Note: 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, + +the external clock input is ETRF. + 14 + 1 + read-write + + + ETP + ETP: External trigger polarity + +This bit selects whether ETR or ETR is used for trigger operations + +0: ETR is non-inverted, active at high level or rising edge. + +1: ETR is inverted, active at low level or falling edge. + 15 + 1 + read-write + + + SMS_3 + SMS[3]: Slave mode selection - bit 3 + +Refer to SMS description - bits2:0 + 16 + 1 + read-write + + + TS_4_3 + Trigger selection. See TS_2_0_ description + 20 + 2 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + CC2IE + CC2IE: Capture/Compare 2 interrupt enable + +0: CC2 interrupt disabled + +1: CC2 interrupt enabled + 2 + 1 + read-write + + + CC3IE + CC3IE: Capture/Compare 3 interrupt enable + +0: CC3 interrupt disabled + +1: CC3 interrupt enabled + 3 + 1 + read-write + + + CC4IE + CC4IE: Capture/Compare 4 interrupt enable + +0: CC4 interrupt disabled + +1: CC4 interrupt enabled + 4 + 1 + read-write + + + TIE + TIE: Trigger interrupt enable + +0: Trigger interrupt disabled + +1: Trigger interrupt enabled + 6 + 1 + read-write + + + UDE + UDE: Update DMA request enable + +0: Update DMA request disabled + +1: Update DMA request enabled + 8 + 1 + read-write + + + CC1DE + CC1DE: Capture/Compare 1 DMA request enable + +0: CC1 DMA request disabled + +1: CC1 DMA request enabled + 9 + 1 + read-write + + + CC2DE + CC2DE: Capture/Compare 2 DMA request enable + +0: CC2 DMA request disabled + +1: CC2 DMA request enabled + 10 + 1 + read-write + + + CC3DE + CC3DE: Capture/Compare 3 DMA request enable + +0: CC3 DMA request disabled + +1: CC3 DMA request enabled + 11 + 1 + read-write + + + CC4DE + CC4DE: Capture/Compare 4 DMA request enable + +0: CC4 DMA request disabled + +1: CC4 DMA request enabled + 12 + 1 + read-write + + + TDE + TDE: Trigger DMA request enable + +0: Trigger DMA request disabled + +1: Trigger DMA request enabled + 14 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value, with some + +exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register + +description). It is cleared by software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow (in upcounting and up/down-counting modes) or + +underflow (in downcounting mode) + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + CC2IF + CC2IF: Capture/Compare 2 interrupt flag + +refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + CC3IF: Capture/Compare 3 interrupt flag + +refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + CC4IF: Capture/Compare 4 interrupt flag + +refer to CC1IF description + 4 + 1 + read-write + + + TIF + TIF: Trigger interrupt flag + +This flag is set by hardware on trigger event (active edge detected on TRGI input when the + +slave mode controller is enabled in all modes but gated mode. It is set when the counter + +starts or stops when gated mode is selected. It is cleared by software.. + +0: No trigger event occurred. + +1: Trigger interrupt pending. + 6 + 1 + read-write + + + CC1OF + CC1OF: Capture/Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + CC2OF + CC2OF: Capture/Compare 2 overcapture flag + +refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + CC3OF: Capture/Compare 3 overcapture flag + +refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + CC4OF: Capture/Compare 4 overcapture flag + +refer to CC1OF description + 12 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + CC2G + CC2G: Capture/Compare 2 generation + +refer to CC1G description + 2 + 1 + write-only + + + CC3G + CC3G: Capture/Compare 3 generation + +refer to CC1G description + 3 + 1 + write-only + + + CC4G + CC4G: Capture/Compare 4 generation + +refer to CC1G description + 4 + 1 + write-only + + + TG + TG: Trigger generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action + +1: The TIF flag is set in TIMx_SR register. Related interrupt can occur if enabled. + 6 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M: Output Compare 1 mode + +These bits define the behavior of the output reference signal OC1REF from which OC1 and + +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends + +on CC1P and CC1NP bits. + +0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the + +counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing + +base). + +0001: Set channel 1 to active level on match. OC1REF signal is forced high when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + +0100: Force inactive level - OC1REF is forced low. + +0101: Force active level - OC1REF is forced high. + +0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT TIMx_CCR1 + +else inactive. In downcounting, channel 1 is inactive (OC1REF='0') as long as + +TIMx_CNT>TIMx_CCR1 else active (OC1REF='1'). + +0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as + +TIMx_CNT TIMx_CCR1 else active. In downcounting, channel 1 is active as long as + +TIMx_CNT>TIMx_CCR1 else inactive. + +1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger + +event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 + +and the channels becomes active again at the next update. In down-counting mode, the + +channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is + +performed as in PWM mode 1 and the channels becomes inactive again at the next update. + +1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a + +trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM + +mode 2 and the channels becomes inactive again at the next update. In down-counting + +mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a + +comparison is performed as in PWM mode 1 and the channels becomes active again at the + +next update. + +1010: Reserved + +1011: Reserved + +1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. + +OC1REFC is the logical OR between OC1REF and OC2REF. + +1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. + +OC1REFC is the logical AND between OC1REF and OC2REF + +1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: In PWM mode, the OCREF level changes only when the result of the comparison + +changes or when the output compare mode switches from 'frozen' mode to 'PWM' + +mode. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable + +0: OC1Ref is not affected by the ETRF Input + +1: OC1Ref is cleared as soon as a High level is detected on ETRF input + 7 + 1 + read-write + + + CC2S + CC2S[1:0]: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through the TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC2FE + OC2FE: Output Compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + OC2PE: Output Compare 2 preload enable + 11 + 1 + read-write + + + OC2M_2_0 + OC2M[2:0]: Output Compare 2 mode + 12 + 3 + read-write + + + OC2CE + OC2CE: Output Compare 2 clear enable + 15 + 1 + read-write + + + OC1M_3 + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + OC2M_3 + OC2M[3]: Output Compare 2 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1_in register + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + CC2S + CC2S: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an + +internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC2PSC + IC2PSC[1:0]: Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + IC2F: Input capture 2 filter + 12 + 4 + read-write + + + + + CCMR2 + CCMR2 + CCMR2 register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/Compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC3FE + OC3FE: Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + OC3PE: Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M_2_0 + OC3M: Output compare 3 mode + 4 + 3 + read-write + + + OC3CE + OC3CE: Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC4FE + OC4FE: Output Compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + OC4PE: Output Compare 4 preload enable + 11 + 1 + read-write + + + OC4M_2_0 + OC4M[2:0]: Output Compare 4 mode + 12 + 3 + read-write + + + OC4CE + OC4CE: Output Compare 4 clear enable + 15 + 1 + read-write + + + OC3M_3 + OC3M[3]: Output Compare 3 mode (bit 3) + 16 + 1 + read-write + + + OC4M_3 + OC4M[3]: Output Compare 4 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR2_in + CCMR2_in + CCMR2_in register + CCMR2 + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC3PSC + IC3PSC: Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + IC3F: Input capture 3 filter + 4 + 4 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC4PSC + IC4PSC: Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + IC4F: Input capture 4 filter + 12 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +11: Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +Note: This bit is no longer writeable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in GPT_BDTR register) and CC1S='00' (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + CC2E: Capture/Compare 2 output enable + +refer to CC1E description + 4 + 1 + read-write + + + CC2P + CC2P: Capture/Compare 2 output polarity + +refer to CC1P description + 5 + 1 + read-write + + + CC2NP + CC2NP: Capture/Compare 2 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 7 + 1 + read-write + + + CC3E + CC3E: Capture/Compare 3 output enable + +refer to CC1E description + 8 + 1 + read-write + + + CC3P + CC3P: Capture/Compare 3 output polarity + +refer to CC1P description + 9 + 1 + read-write + + + CC3NP + CC3NP: Capture/Compare 3 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 11 + 1 + read-write + + + CC4E + CC4E: Capture/Compare 4 output enable + +refer to CC1E description + 12 + 1 + read-write + + + CC4P + CC4P: Capture/Compare 4 output polarity + +refer to CC1P description + 13 + 1 + read-write + + + CC4NP + CC4NP: Capture/Compare 4 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 15 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIF_CPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0xFFFF + 0xFFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x0 + 0xF + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 8 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + CCR1 + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + CCR2 + CCR2 + CCR2 register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + CCR2 + CCR2[15:0]: Capture/Compare 2 value + +If channel CC2 is configured as output: + +CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit + +OC2PE). Else the preload value is copied in the active capture/compare 2 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC2 output. + +If channel CC2 is configured as input: + +CCR2 is the counter value transferred by the last input capture 2 event (IC2). + 0 + 16 + read-write + + + + + CCR3 + CCR3 + CCR3 register + 0x3C + 0x20 + read-write + 0x0 + 0xF + + + CCR3 + CCR3[15:0]: Capture/Compare 3 value + +If channel CC3 is configured as output: + +CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit + +OC3PE). Else the preload value is copied in the active capture/compare 3 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC3 output. + +If channel CC3 is configured as input: + +CCR3 is the counter value transferred by the last input capture 3 event (IC3). + 0 + 16 + read-write + + + + + CCR4 + CCR4 + CCR4 register + 0x40 + 0x20 + read-write + 0x0 + 0xF + + + CCR4 + CCR4[15:0]: Capture/Compare 4 value + +If channel CC4 is configured as output: + +CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit + +OC4PE). Else the preload value is copied in the active capture/compare 4 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC4 output. + +If channel CC4 is configured as input: + +CCR4 is the counter value transferred by the last input capture 4 event (IC4). + 0 + 16 + read-write + + + + + DCR + DCR + DCR register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + DBA + DBA[4:0]: DMA base address + +This 5-bit field defines the base-address for DMA transfers (when read/write access are + +done through the TIMx_DMAR address). DBA is defined as an offset starting from the + +address of the TIMx_CR1 register. + +Example: + +00000: TIMx_CR1, + +00001: TIMx_CR2, + +00010: Reserved, + +... + +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In + +this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + DBL + DBL[4:0]: DMA burst length + +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when + +a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. + +Transfers can be in half-words or in bytes (see example below). + +00000: 1 transfer, + +00001: 2 transfers, + +00010: 3 transfers, + +... + +10001: 18 transfers. + 8 + 5 + read-write + + + + + DMAR + DMAR + DMAR register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + DMAB + DMAB[15:0]: DMA register for burst accesses + +A read or write operation to the DMAR register accesses the register located at the address + +(TIM2_CR1 address) + (DBA + DMA index) x 4 + +where TIM2_CR1 address is the address of the control register 1, DBA is the DMA base + +address configured in TIM2_DCR register, DMA index is automatically controlled by the + +DMA transfer, and ranges from 0 to DBL (DBL configured in TIM2_DCR). + 0 + 16 + read-write + + + + + OR1 + OR1 + OR1 register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + ETR_RMP + ETR_RMP: ETR remapping capability + +0: TIMx_ETR is not connected to ADC AWD (must be selected when the ETR comes from + +the ETR input pin) + +1: TIMx_ETR is connected to ADC AWD + +Note: ADC AWD source is 'ORed' with the TIMx_ETR input signals. When ADC AWD is used, + +it is necessary to make sure that the corresponding TIMx_ETR input pin is not enabled + +in the alternate function controller. + 0 + 1 + read-write + + + OR1_1 + This field is not used in Blue51. Not available in IUM + 1 + 1 + read-write + + + TI4_RMP + TI4_RMP: Input capture 4 remap + +0: TIM2 input capture 4 is connected to I/O + +1: TIM2 input capture 4 is connected to COMP1-OUT + 2 + 1 + read-write + + + + + AF1 + AF1 + AF1 register + 0x60 + 0x20 + read-write + 0x0 + 0xF + + + ETR_SEL + ETRSEL[2:0]: External trigger source selection + +000: TIMx External trigger legacy mode + +001: TIMx External trigger source select COMP1_OUT + +Other: Reserved + +Note: These bits can't be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 14 + 3 + read-write + + + ETR_SEL_3 + ETRSEL[2:0]: External trigger source selection + +This field is not used in Blue51. Not available in IUM + 17 + 1 + read-write + + + + + TISEL + TISEL + TISEL register + 0x68 + 0x20 + read-write + + + TI1SEL + TI1SEL[3:0]: selects TI1[0] to TI1[15] input + +0000: TIMx_CH1 input + +Others: Reserved + 0 + 4 + read-write + + + TI2SEL + TI2SEL[3:0]: selects TI2[0] to TI2[15] input + +0000: TIMx_CH2 input + +Others: Reserved + 8 + 4 + read-write + + + TI3SEL + TI3SEL[3:0]: selects TI3[0] to TI3[15] input + +0000: TIMx_CH3 input + +Others: Reserved + 16 + 4 + read-write + + + TI4SEL + TI4SEL[3:0]: selects TI4[0] to TI4[15] input + +0000: TIMx_CH4 input + +Others: Reserved + 24 + 4 + read-write + + + + + + + USART + USART + 0x41004000 + + 0x0 + 0x30 + registers + + + USART + USART interrupt + 8 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + UE + UE: USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and +current operations are discarded. The configuration of the USART is kept, but all the status +flags, in the USART_ISR are reset. This bit is set and cleared by software. +-0: USART prescaler and outputs disabled, low power mode +-1: USART enabled + 0 + 1 + read-write + + + RE + RE: Receiver enable +This bit enables the receiver. It is set and cleared by software. +-0: Receiver is disabled +-1: Receiver is enabled and begins searching for a start bit + 2 + 1 + read-write + + + TE + TE: Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +-0: Transmitter is disabled +-1: Transmitter is enabled + 3 + 1 + read-write + + + IDLEIE + IDLEIE: IDLE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register + 4 + 1 + read-write + + + RXNEIE_RXFNEIE + RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the +USART_ISR register + 5 + 1 + read-write + + + TCIE + TCIE: Transmission complete interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TC=1 in the USART_ISR register + 6 + 1 + read-write + + + TXEIE_TXFNFIE + TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register + 7 + 1 + read-write + + + PEIE + PEIE: PE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever PE=1 in the USART_ISR register + 8 + 1 + read-write + + + PS + PS: Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE +bit set). It is set and cleared by software. The parity will be selected after the current byte. +-0: Even parity +-1: Odd parity +This bit field can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + PCE + PCE: Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity +control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit +if M=0) and parity is checked on the received data. This bit is set and cleared by software. +Once it is set, PCE is active after the current byte (in reception and in transmission). +-0: Parity control disabled +-1: Parity control enabled +This bit field can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + WAKE + WAKE: Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by +software. +-0: Idle line +-1: Address mark +This bit field can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + M_0 + M0: Word length +This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit +-28 (M1)description. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + MME: Mute mode enable +This bit activates the mute mode function of the USART. When set, the USART can switch +between the active and mute modes, as defined by the WAKE bit. It is set and cleared by +software. +-0: Receiver in active mode permanently +-1: Receiver can switch between mute mode and active mode + 13 + 1 + read-write + + + CMIE + CMIE: Character match interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 14 + 1 + read-write + + + OVER8 + OVER8: Oversampling mode +-0: Oversampling by 16 +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + DEDT + DEDT[4:0]: Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted +message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample +time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only +when the DEDT and DEAT times have both elapsed. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + DEAT[4:0]: Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and +the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, +depending on the oversampling rate). +This bit field can only be written when the USART is disabled (UE=0). + 21 + 5 + read-write + + + RTOIE + RTOIE: Receiver timeout interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register + 26 + 1 + read-write + + + EOBIE + EOBIE: End of Block interrupt enable +This bit is set and cleared by software. + + 27 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + + 0x0 + + + B_0x1 + A USART interrupt is generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M_1 + Word length +This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0).s + 28 + 1 + read-write + + + FIFOEN + FIFOEN :FIFO mode enable +This bit is set and cleared by software. +-0: FIFO mode is disabled. +-1: FIFO mode is enabled. + 29 + 1 + read-write + + + TXFEIE + TXFEIE :TXFIFO empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFE=1 in the USART_ISR register + 30 + 1 + read-write + + + RXFFIE + RXFFIE :RXFIFO Full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when RXFF=1 in the USART_ISR register + 31 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + SLVEN + SLVEN: Synchronous Slave mode enable +When the SLVEN bit is set, the synchronous slave mode is enabled. +-0: Slave mode disabled. +-1: Slave mode enabled. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value + 0 + 1 + read-write + + + DIS_NSS + DIS_NSS +When the DSI_NSS bit is set, the NSS pin input will be ignored. +-0: SPI slave selection depends on NSS input pin. +-1: SPI slave will be always selected and NSS input pin will be ignored. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value + 3 + 1 + read-write + + + ADDM7 + ADDM7:7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +-0: 4-bit address detection +-1: 7-bit address detection (in 8-bit data mode) +This bit can only be written when the USART is disabled (UE=0) + 4 + 1 + read-write + + + LBDL + LBDL: LIN break detection length +This bit is for selection between 11 bit or 10 bit break detection. +-0: 10-bit break detection +-1: 11-bit break detection +This bit can only be written when the USART is disabled (UE=0). + 5 + 1 + read-write + + + LBDIE + LBDIE: LIN break detection interrupt enable +Break interrupt mask (break detection using break delimiter). +-0: Interrupt is inhibited +-1: An interrupt is generated whenever LBDF=1 in the USART_ISR register + 6 + 1 + read-write + + + LBCL + LBCL: Last bit clock pulse +This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) +has to be output on the SCLK pin in synchronous mode. +-0: The clock pulse of the last data bit is not output to the SCLK pin +-1: The clock pulse of the last data bit is output to the SCLK pin +Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit +format selected by the M bit in the USART_CR1 register. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CPHA + CPHA: Clock phase +This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It +works in conjunction with the CPOL bit to produce the desired clock/data relationship (see +Figure 137 and Figure 138) +-0: The first clock transition is the first data capture edge +-1: The second clock transition is the first data capture edge +This bit can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + CPOL + CPOL: Clock polarity +This bit allows the user to select the polarity of the clock output on the SCLK pin in synchronous +mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship +-0: Steady low value on SCLK pin outside transmission window +-1: Steady high value on SCLK pin outside transmission window +This bit can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + CLKEN + CLKEN: Clock enable +This bit allows the user to enable the SCLK pin. +-0: SCLK pin disabled +-1: SCLK pin enabled +This bit can only be written when the USART is disabled (UE=0). +Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and forced +by hardware to 0. Please refer to Section 23.4: USART implementation on page 483. +Note: In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps +below must be respected: +- UE = 0 +- SCEN = 1 +- GTPR configuration +- CLKEN= 1 +- UE = 1 + 11 + 1 + read-write + + + STOP + STOP[1:0]: STOP bits +These bits are used for programming the stop bits. +-00: 1 stop bit +-01: 0.5 stop bit. +-10: 2 stop bits +-11: 1.5 stop bits +This bit field can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + LINEN + LINEN: LIN mode enable +This bit is set and cleared by software. +-0: LIN mode disabled +-1: LIN mode enabled +The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBKRQ bit +in the USART_CR1 register, and to detect LIN Sync breaks. +This bit field can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + SWAP + SWAP: Swap TX/RX pins +This bit is set and cleared by software. +-0: TX/RX pins are used as defined in standard pinout +-1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired +connection to another UART. +This bit field can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + RXINV + RXINV: RX pin active level inversion +This bit is set and cleared by software. +-0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the RX line. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + TXINV + TXINV: TX pin active level inversion +This bit is set and cleared by software. +-0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the TX line. +This bit field can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + DATAINV + DATAINV: Binary data inversion +This bit is set and cleared by software. +-0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) +-1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The +parity bit is also inverted. +This bit field can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + MSBFIRST + MSBFIRST: Most significant bit first +This bit is set and cleared by software. +-0: data is transmitted/received with data bit 0 first, following the start bit. +-1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. +This bit field can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + ABREN + ABREN: Auto baud rate enable +This bit is set and cleared by software. +-0: Auto baud rate detection is disabled. +-1: Auto baud rate detection is enabled. + 20 + 1 + read-write + + + ABRMOD + ABRMOD[1:0]: Auto baud rate mode +These bits are set and cleared by software. +-00: Measurement of the start bit is used to detect the baud rate. +-01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 -> +Frame = Start10xxxxxx) +-10: 0x7F frame detection. +-11: 0x55 frame detection +This bit field can only be written when ABREN = 0 or the USART is disabled (UE=0). + 21 + 2 + read-write + + + RTOEN + RTOEN: Receiver timeout enable +This bit is set and cleared by software. +-0: Receiver timeout feature disabled. +-1: Receiver timeout feature enabled. +When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle +(no reception) for the duration programmed in the RTOR (receiver timeout register). + 23 + 1 + read-write + + + ADD + ADD[7:0]: Address of the USART node +This bit-field gives the address of the USART node or a character code to be recognized. +This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- +bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. +It may also be used for character detection during normal reception, Mute mode inactive (for +example, end of block detection in ModBus protocol). In this case, the whole received character (8- +bit) is compared to the ADD[7:0] value and CMF flag is set on match. +This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled +(UE=0) + 24 + 8 + read-write + + + + + CR3 + CR3 + CR3 register + 0x08 + 0x20 + read-write + 0x00000000 + + + EIE + EIE: Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing +error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR += 1 in the USART_ISR register). +-0: Interrupt is inhibited +-1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) +in the USART_ISR register. + 0 + 1 + read-write + + + IREN + IREN: IrDA mode enable +This bit is set and cleared by software. +-0: IrDA disabled +-1: IrDA enabled +This bit can only be written when the USART is disabled (UE=0). + 1 + 1 + read-write + + + IRLP + IRLP: IrDA low-power +This bit is used for selecting between normal and low-power IrDA modes +-0: Normal mode +-1: Low-power mode +This bit can only be written when the USART is disabled (UE=0). + 2 + 1 + read-write + + + HDSEL + HDSEL: Half-duplex selection +Selection of Single-wire Half-duplex mode +-0: Half duplex mode is not selected +-1: Half duplex mode is selected +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + NACK + NACK: Smartcard NACK enable +-0: NACK transmission in case of parity error is disabled +-1: NACK transmission during parity error is enabled +This bit field can only be written when the USART is disabled (UE=0). + 4 + 1 + read-write + + + SCEN + SCEN: Smartcard mode enable +This bit is used for enabling Smartcard mode. +-0: Smartcard Mode disabled +-1: Smartcard Mode enabled +This bit field can only be written when the USART is disabled (UE=0). + 5 + 1 + read-write + + + DMAR + DMAR: DMA enable receiver +This bit is set/reset by software +-1: DMA mode is enabled for reception +-0: DMA mode is disabled for reception + 6 + 1 + read-write + + + DMAT + DMAT: DMA enable transmitter +This bit is set/reset by software +-1: DMA mode is enabled for transmission +-0: DMA mode is disabled for transmission + 7 + 1 + read-write + + + RTSE + RTSE: RTS enable +-0: RTS hardware flow control disabled +-1: RTS output enabled, data is only requested when there is space in the receive buffer. The +transmission of data is expected to cease after the current character has been transmitted. +The nRTS output is asserted (pulled to 0) when data can be received. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CTSE + CTSE: CTS enable +-0: CTS hardware flow control disabled +-1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). +If the nCTS input is deasserted while data is being transmitted, then the transmission is +completed before stopping. If data is written into the data register while nCTS is asserted, +the transmission is postponed until nCTS is asserted. +This bit can only be written when the USART is disabled (UE=0) + 9 + 1 + read-write + + + CTSIE + CTSIE: CTS interrupt enable +-0: Interrupt is inhibited +-1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 10 + 1 + read-write + + + ONEBIT + ONEBIT: One sample bit method enable +This bit allows the user to select the sample method. When the one sample bit method is +selected the noise detection flag (NF) is disabled. +-0: Three sample bit method +-1: One sample bit method +This bit can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + OVRDIS + OVRDIS: Overrun Disable +This bit is used to disable the receive overrun detection. +-0: Overrun Error Flag, ORE, is set when received data is not read before receiving new +data. +-1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set +the ORE flag is not set and the new received data overwrites the previous content of the +USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data +will be written directly in USARTx_RDR register. Even when FIFO management is enabled, +the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + DDRE + DDRE: DMA Disable on Reception Error +-0: DMA is not disabled in case of reception error. The corresponding error flag is set but +RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not +asserted, so the erroneous data is not transferred (no DMA request), but next correct +received data will be transferred. (used for Smartcard mode) +-1: DMA is disabled following a reception error. The corresponding error flag is set, as well +as RXNE. The DMA request is masked until the error flag is cleared. This means that the +software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case +FIFO mode is enabled) before clearing the error flag. +This bit can only be written when the USART is disabled (UE=0). + 13 + 1 + read-write + + + DEM + DEM: Driver enable mode +This bit allows the user to activate the external transceiver control, through the DE signal. +-0: DE function is disabled. +-1: DE function is enabled. The DE signal is output on the RTS pin. +This bit can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + DEP + DEP: Driver enable polarity selection +-0: DE signal is active high. +-1: DE signal is active low. +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + SCARCNT + SCARCNT[2:0]: Smartcard auto-retry count +This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. +In transmission mode, it specifies the number of automatic retransmission retries, before +generating a transmission error (FE bit set). +In reception mode, it specifies the number or erroneous reception trials, before generating a +reception error (RXNE/RXFNE and PE bits set). +This bit field must be programmed only when the USART is disabled (UE=0). +When the USART is enabled (UE=1), this bit field may only be written to 0x0, in order to +stop retransmission. +-0x0: retransmission disabled - No automatic retransmission in transmit mode. +-0x1 to 0x7: number of automatic retransmission attempts (before signaling error) + 17 + 3 + read-write + + + TXFTIE + TXFTIE: TXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in +TXFTCFG. + 23 + 1 + read-write + + + TCBGTIE + TCBGTIE: Transmission Complete before guard time, interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever TCBGT=1 in the USARTx_ISR register + 24 + 1 + read-write + + + RXFTCFG + RXFTCFG: Receive FIFO threshold configuration +-000:Receive FIFO reaches 1/8 of its depth. +-001:Receive FIFO reaches 1/4 of its depth. +-010:Receive FIFO reaches 1/2 of its depth. +-011:Receive FIFO reaches 3/4 of its depth. +-100:Receive FIFO reaches 7/8 of its depth. +-101:Receive FIFO becomes full. +Remaining combinations: Reserved. + 25 + 3 + read-write + + + RXFTIE + RXFTIE: RXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when Receive FIFO reaches the threshold +programmed in RXFTCFG. + 28 + 1 + read-write + + + TXFTCFG + TXFTCFG: TXFIFO threshold configuration +-000:TXFIFO reaches 1/8 of its depth. +-001:TXFIFO reaches 1/4 of its depth. +-010:TXFIFO reaches 1/2 of its depth. +-011:TXFIFO reaches 3/4 of its depth. +-100:TXFIFO reaches 7/8 of its depth. +-101:TXFIFO becomes empty. +Remaining combinations: Reserved. + 29 + 3 + read-write + + + + + BRR + BRR + BRR register + 0x0C + 0x20 + read-write + 0x00000000 + + + BRR + BRR[15:4] +BRR[15:4] = USARTDIV[15:4]BRR[3:0] +When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. +When OVER8 = 1: +BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. +BRR[3] must be kept cleared + 0 + 16 + read-write + + + + + GTPR + GTPR + GTPR register + 0x10 + 0x20 + read-write + 0x00000000 + + + PSC + PSC[7:0]: Prescaler value +In IrDA Low-power and normal IrDA mode: +PSC[7:0] = IrDA Normal and Low-Power Baud Rate +Used for programming the prescaler for dividing the USART source clock to achieve the lowpower +frequency: +The source clock is divided by the value given in the register (8 significant bits): +-00000000: Reserved - do not program this value +-00000001: divides the source clock by 1 +-00000010: divides the source clock by 2 +... +In Smartcard mode: +PSC[4:0]: Prescaler value +Used for programming the prescaler for dividing the USART source clock to provide the +Smartcard clock. +The value given in the register (5 significant bits) is multiplied by 2 to give the division factor +of the source clock frequency: +-00000: Reserved - do not program this value +-00001: divides the source clock by 2 +-00010: divides the source clock by 4 +-00011: divides the source clock by 6 +... +This bit field can only be written when the USART is disabled (UE=0). + 0 + 8 + read-write + + + GT + GT[7:0]: Guard time value +This bit-field is used to program the Guard time value in terms of number of baud clock +periods. +This is used in Smartcard mode. The Transmission Complete flag is set after this guard time +value. +This bit field can only be written when the USART is disabled (UE=0). + 8 + 8 + read-write + + + + + RTOR + RTOR + RTOR register + 0x14 + 0x20 + read-write + 0x00000000 + + + RTO + RTO[23:0]: Receiver timeout value +This bit-field gives the Receiver timeout value in terms of number of baud clocks. +In standard mode, the RTOF flag is set if, after the last received character, no new start bit is +detected for more than the RTO value. +In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard +chapter for more details. In the standard, the CWT/BWT measurement is done starting from +the Start Bit of the last received character. + 0 + 24 + read-write + + + BLEN + BLEN[7:0]: Block Length +This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number +of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. +Examples: +BLEN = 0 -> 0 information characters + LEC +BLEN = 1 -> 0 information characters + CRC +BLEN = 255 -> 254 information characters + CRC (total 256 characters)) +In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO +mode is enabled). +This bit-field can be used also in other modes. In this case, the Block length counter is reset +when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. + 24 + 8 + read-write + + + + + RQR + RQR + RQR register + 0x18 + 0x20 + read-write + 0x00000000 + + + ABRRQ + ABRRQ: Auto baud rate request +Writing 1 to this bit resets the ABRF flag in the USART_ISR and request an automatic baud +rate measurement on the next received data frame. + 0 + 1 + write-only + + + SBKRQ + SBKRQ: Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as +the transmit machine is available. + 1 + 1 + write-only + + + MMRQ + MMRQ: Mute mode request +Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + RXFRQ: Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This allows to discard the received data without reading them, and avoid an overrun +condition. + 3 + 1 + write-only + + + TXFRQ + TXFRQ: Transmit data flush request +When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. +This allows to discard the transmit data. This bit must be used only in Smartcard mode, +when data has not been sent due to errors (NACK) and the FE flag is active in the +USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved +and forced by hardware to 0 +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE +(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is +supported in both UART and Smartcard modes. + 4 + 1 + write-only + + + + + ISR + ISR + ISR register + 0x1C + 0x20 + read-only + 0x000000C0 + + + PE + PE: Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by +software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +-0: No parity error +-1: Parity error + 0 + 1 + read-only + + + FE + FE: Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character +is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +In Smartcard mode, in transmission, this bit is set when the maximum number of transmit +attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR1 register. +-0: No Framing error is detected +-1: Framing error or break character is detected + 1 + 1 + read-only + + + NF + NF: START bit Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by +software, writing 1 to the NFCF bit in the USART_ICR register. +-0: No noise is detected +-1: Noise is detected + 2 + 1 + read-only + + + ORE + ORE: Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case +FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the +USARTx_ICR register. +An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. +-0: No overrun error +-1: Overrun error is detected + 3 + 1 + read-only + + + IDLE + IDLE: Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if +IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in +the USART_ICR register. +-0: No Idle line is detected +-1: Idle line is detected + 4 + 1 + read-only + + + RXNE_RXFNE + RXNE/RXFNE:Read data register not empty/RXFIFO not empty +RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been +transferred +to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from +the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It +is cleared when the RXFIFO is empty. +The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR +register. +An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. +-0: Data is not received +-1: Received data is ready to be read. + 5 + 1 + read-only + + + TC + TC: Transmission complete +This bit indicates when the last data written in the USART_TDR has been transmitted out of +the shift register. +It is set by hardware if the transmission of a frame containing data is complete and if +TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is +cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the +USART_TDR register. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +-0: Transmission is not complete +-1: Transmission is complete + 6 + 1 + read-only + + + TXE_TXFNF + TXE/TXFNF: Transmit data register empty/TXFIFO not full +When FIFO mode is disabled, TXE is set by hardware when the content of the +USARTx_TDR register has been transferred into the shift register. It is cleared by a write to +the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the +USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of +transmission failure). +When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so +data can be written in the USART_TDR. Every write in the USART_TDR places the data in +the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag +is cleared indicating that data can not be written into the USART_TDR. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After +sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to +writing in TXFIFO. (TXFNF and TXFE will be set at the same time). +An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. +-0: Data register is full/Transmit FIFO is full. +-1: Data register/Transmit FIFO is not full + 7 + 1 + read-only + + + LBDF + LBDF: LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by +writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +-0: LIN Break not detected +-1: LIN break detected + 8 + 1 + read-only + + + CTSIF + CTSIF: CTS interrupt flag +This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared +by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +-0: No change occurred on the nCTS status line +-1: A change occurred on the nCTS status line + 9 + 1 + read-only + + + CTS + CTS: CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. +-0: nCTS line set +-1: nCTS line reset + 10 + 1 + read-only + + + RTOF + RTOF: Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has +lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in +the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +-0: Timeout value not reached +-1: Timeout value reached without any data reception + 11 + 1 + read-only + + + EOBF + EOBF: End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 +Smartcard mode). The detection is done when the number of received bytes (from the start +of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if the EOBIE=1 in the USART_CR2 register. +It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. +-0: End of Block not reached +-1: End of Block (number of characters) reached + 12 + 1 + read-only + + + UDR + UDR: SPI slave underrun error flag +In slave transmission mode, this flag is set when the first clock for data transmission appears +while the software has not yet loaded any value into USARTx_DR. +-0: No underrun error +-1: underrun error + 13 + 1 + read-only + + + ABRE + ABRE: Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or +character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register + 14 + 1 + read-only + + + ABRF + ABRF: Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXNE will also be +set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was +completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to +the ABRRQ in the USART_RQR register. + 15 + 1 + read-only + + + BUSY + BUSY: Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the +RX line (successful start bit detected). It is reset at the end of the reception (successful or +not). +-0: USART is idle (no reception) +-1: Reception on going + 16 + 1 + read-only + + + CMF + CMF: Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is +cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. +-0: No Character match detected +-1: Character Match detected + 17 + 1 + read-only + + + SBKF + SBKF: Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing +1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during +the stop bit of break transmission. +-0: No break character is transmitted +-1: Break character will be transmitted + 18 + 1 + read-only + + + RWU + RWU: Receiver wakeup from Mute mode +This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a +wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) +is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the +MMRQ bit in the USART_RQR register. +-0: Receiver in active mode +-1: Receiver in mute mode + 19 + 1 + read-only + + + TEACK + TEACK: Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by +the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 +in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + REACK: Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by +the USART. +It can be used to verify that the USART is ready for reception before entering Stop mode. + 22 + 1 + read-only + + + TXFE + TXFE: TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one +data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in +the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. +-0: TXFIFO is not empty. +-1: TXFIFO is empty. + 23 + 1 + read-only + + + RXFF + RXFF: RXFIFO Full +This bit is set by hardware when RXFIFO is Full. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. +-0: RXFIFO is not Full. +-1: RXFIFO is Full. + 24 + 1 + read-only + + + TCBGT + TCBGT: Transmission complete before guard time flagl +This bit indicates when the last data written in the USART_TDR has been transmitted +correctly out of the shift register . +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is +complete and if there is no NACK from the smartcard. An interrupt is generated if +TCBGTIE=1 in the USART_CR3 register. It is cleared by software, writing 1 to the +TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +-0: Transmission is not complete or transmission is complete unsuccessfuly (i.e. a NACK is +received from the card) +-1: Transmission is complete successfully (before Guard time completion and there is no +NACK from the smart card). + 25 + 1 + read-only + + + RXFT + RXFT: RXFIFO threshold flag +This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 +register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and +one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in +the USART_CR3 register. +-0: Receive FIFO doesnt reach the programmed threshold. +-1: Receive FIFO reached the programmed threshold + 26 + 1 + read-only + + + TXFT + TXFT: TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG +in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is +generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. +-0: TXFIFO doesnt reach the programmed threshold. +-1: TXFIFO reached the programmed threshold + 27 + 1 + read-only + + + + + ICR + ICR + ICR register + 0x20 + 0x20 + read-write + 0x00000000 + + + PECF + PECF: Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + FECF: Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register + 1 + 1 + write-only + + + NECF + NECF: Noise detected clear flag +Writing 1 to this bit clears the NF flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + ORECF: Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + IDLECF: Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TXFECF + TXFECF: TXFIFO empty clear flag +Writing 1 to this bit clears the TXFE flag in the USART_ISR register + 5 + 1 + write-only + + + TCCF + TCCF: Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register + 6 + 1 + write-only + + + TCBGTCF + TCBGTCF: Transmission complete before Guard time clear flag +Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. + 7 + 1 + write-only + + + LBDCF + LBDCF: LIN break detection clear flag +Writing 1 to this bit clears the LBDF flag in the USART_ISR register. + 8 + 1 + write-only + + + CTSCF + CTSCF: CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register + 9 + 1 + write-only + + + RTOCF + RTOCF: Receiver timeout clear flag +Writing 1 to this bit clears the RTOF flag in the USART_ISR register. + 11 + 1 + write-only + + + EOBCF + EOBCF: End of block clear flag +Writing 1 to this bit clears the EOBF flag in the USART_ISR register + 12 + 1 + write-only + + + UDRCF + UDRCF:SPI slave underrun clear flag +Writing 1 to this bit clears the UDRF flag in the USART_ISR register + 13 + 1 + write-only + + + CMCF + CMCF: Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register + 17 + 1 + write-only + + + + + RDR + RDR + RDR register + 0x24 + 0x20 + read-only + 0x0 + + + RDR + RDR[8:0]: Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the +internal bus (see Figure 124). +When receiving with the parity enabled, the value read in the MSB bit is the received parity +bit. + 0 + 9 + read-only + + + + + TDR + TDR + TDR register + 0x28 + 0x20 + read-write + 0x0 + + + TDR + TDR[8:0]: Transmit data value +Contains the data character to be transmitted. +The USARTx_TDR register provides the parallel interface between the internal bus and the +output shift register (see Figure 124). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), +the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect +because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + PRESC + PRESC + PRESC register + 0x2C + 0x20 + read-write + 0x0 + + + PRESCALER + PRESCALER[3:0]: Clock prescaler +The USART input clock can be divided by a prescaler: +-0000: input clock not divided +-0001: input clock divided by 2 +-0010: input clock divided by 4 +-0011: input clock divided by 6 +-0100: input clock divided by 8 +-0101: input clock divided by 10 +-0110: input clock divided by 12 +-0111: input clock divided by 16 +-1000: input clock divided by 32 +-1001: input clock divided by 64 +-1010: input clock divided by 128 +-1011: input clock divided by 256 +Remaing combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, +programmed prescaler value will be '1011' i.e. input clock divided by 256 + 0 + 4 + read-write + + + + + + + diff --git a/svd/STM32WL3x/STM32WL33.svd b/svd/STM32WL3x/STM32WL33.svd new file mode 100644 index 0000000..0cf22ae --- /dev/null +++ b/svd/STM32WL3x/STM32WL33.svd @@ -0,0 +1,31298 @@ + + + + STM32WL33 + 1.0 + STM32WL33 + + CM0+ + r0p0 + little + true + false + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC + ADC address block description + ADC + 0x41006000 + + 0x0 + 0x68 + registers + + + ADC + ADC interrupt + 12 + + + + VERSION_ID + VERSION_ID + VERSION_ID register + 0x00 + 0x20 + read-only + 0x21 + 0xFF + + + VERSION_ID + VERSION_ID[7:0]: version of the embedded IP. + 0 + 8 + read-only + + + + + CONF + CONF + CONF register + 0x04 + 0x20 + read-write + 0x20002 + 0xFFFFF + + + CONT + CONT: regular sequence runs continuously when ADC mode is enabled: + +0: enable the single conversion: when the sequence is over, the conversion stops + +1: enable the continuous conversion: when the sequence is over, the sequence starts again + +until the software sets the CTRL.STOP_OP_MODE bit. + 0 + 1 + read-write + + + SEQUENCE + SEQUENCE: enable the sequence mode (active by default): + +0: sequence mode is disabled, only SEQ0 is selected + +1: sequence mode is enabled, conversions from SEQ0 to SEQx with x=SEQ_LEN + +Note: clearing this bit is equivalent to SEQUENCE=1 and SEQ_LEN=0000. Ideally, this bit can + +be kept high as redundant with keeping high and setting SEQ_LEN=0000. + 1 + 1 + read-write + + + SEQ_LEN + SEQ_LEN[3:0]: number of conversions in a regular sequence: + +0000: 1 conversion, starting from SEQ0 + +0001: 2 conversions, starting from SEQ0 + +... + +1111: 16 conversions, starting from SEQ0 + 2 + 4 + read-write + + + SMPS_SYNCHRO_ENA + SMPS_SYNCHRO_ENA: synchronize the ADC start conversion with a pulse generated by the + +SMPS: + +0: SMPS synchronization is disabled for all ADC clock frequencies + +1: SMPS synchronization is enabled (only when ADC clock is 8 MHz or 16 MHz) + +Note: SMPS_SYNCHRO_ENA must be 0 when the ADC analog clock is 32 MHz or when + +PWRC_CR5.NOSMPS = 1. + 6 + 1 + read-write + + + SAMPLE_RATE_LSB + SAMPLE_RATE_LSB: Sample Rate LSB + +This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It + +impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description. + +When this field is set to a value different than 0, SMPS synchronization is not feasible. + +This value is hidden to the user + 9 + 2 + read-write + + + SAMPLE_RATE + SAMPLE_RATE[1:0]: conversion rate of ADC (F_ADC): + +F_ADC = F_ADC_CLK/(16 + 16*SAMPLE_RATE_MSB + 4*SAMPLE_RATE + SAMPLE_RATE_LSB),where + +F_ADC_CLK is the analog ADC clock frequency. By default F_ADC_CLK is 16MHz frequency. + 11 + 2 + read-write + + + DMA_DS_ENA + DMA_DS_EN: enable the DMA mode for the Down Sampler data path: + +0: DMA mode is disabled + +1: DMA mode is enabled + 13 + 1 + read-write + + + OVR_DS_CFG + OVR_DS_CFG: Down Sampler overrun configuration: + +0: the previous data is kept, the new one is lost + +1: the previous data is lost, the new one is kept + 15 + 1 + read-write + + + BIT_INVERT_SN + BIT_INVERT_SN: invert bit to bit the ADC data output (1's complement) when a single + +negative input is connected to the ADC: + +0: no inversion (default) + +1: enable the inversion + 17 + 1 + read-write + + + BIT_INVERT_DIFF + BIT_INVERT_DIFF: invert bit to bit the ADC data output (1's complement) when a differential + +input is connected to the ADC: + +0: no inversion (default) + +1: enable the inversion + 18 + 1 + read-write + + + ADC_CONT_1V2 + ADC_CONT_1V2: select the input sampling method: + +0: sampling only at conversion start (default) + +1: sampling starts at the end of conversion + 19 + 1 + read-write + + + SAMPLE_RATE_MSB + SAMPLE_RATE_MSB: Sample Rate MSB + +This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It + +impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description + 21 + 3 + read-write + + + + + CTRL + CTRL + CTRL register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + ADC_ON_OFF + ADC_ON_OFF: + +0: power off the ADC + +1: power on the ADC + 0 + 1 + read-write + + + START_CONV + START_CONV (1): generate a start pulse to initiate an ADC conversion: + +0: no effect + +1: start the ADC conversion + +Note: this bit is set by software and cleared by hardware. + 1 + 1 + write-only + + + STOP_OP_MODE + STOP_OP_MODE (1): stop the on-going OP_MODE (ADC mode, Analog audio mode, Full + +mode): + +0: no effect + +1: stop on-going ADC mode + +Note: this bit is set by software and cleared by hardware. + +When setting the STOP_MODE_OP, the user has to wait around 10 us before to start a new ADC conversion by setting the START_CONV bit. + 2 + 1 + write-only + + + TEST_MODE + TEST_MODE: select the functional or the test mode of the ADC: + +0: functional mode (one of the four main functional modes is used) + +1: test mode (for debug, test, calibration) + 4 + 1 + read-write + + + + + SWITCH + SWITCH + SWITCH register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + SE_VIN_0 + SE_VIN_0[1:0]: input voltage for VINM[0] / VINP[0]-VINM[0] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 0 + 2 + read-write + + + SE_VIN_1 + SE_VIN_1[1:0]: input voltage for VINM[1] / VINP[1]-VINM[1] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 2 + 2 + read-write + + + SE_VIN_2 + SE_VIN_2[1:0]: input voltage for VINM[2] / VINP[2]-VINM[2] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 4 + 2 + read-write + + + SE_VIN_3 + SE_VIN_3[1:0]: input voltage for VINM[3] / VINP[3]-VINM[3] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 6 + 2 + read-write + + + SE_VIN_4 + SE_VIN_4[1:0]: input voltage for VINP[0] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 8 + 2 + read-write + + + SE_VIN_5 + SE_VIN_5[1:0]: input voltage for VINP[1] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 10 + 2 + read-write + + + SE_VIN_6 + SE_VIN_6[1:0]: input voltage for VINP[2] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 12 + 2 + read-write + + + SE_VIN_7 + SE_VIN_7[1:0]: input voltage for VINP[3] + +00: Vinput = 1.2V + +01: reserved (not used for this cut) + +10: Vinput = 2.4V + +11: Vinput = 3.6V + 14 + 2 + read-write + + + + + DS_CONF + DS_CONF + DS_CONF register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + DS_RATIO + DS_RATIO[2:0]: program the Down Sampler ratio (N factor) + +000: ratio = 1, no down sampling (default) + +001: ratio = 2 + +010: ratio = 4 + +011: ratio = 8 + +100: ratio = 16 + +101: ratio = 32 + +110: ratio = 64 + +111: ratio = 128 + 0 + 3 + read-write + + + DS_WIDTH + DS_WIDTH[2:0]: program the Down Sampler width of data output (DSDTATA) + +000: DS_DATA output on 12-bit (default) + +001: DS_DATA output on 13-bit + +010: DS_DATA output on 14-bit + +011: DS_DATA output on 15-bit + +100: DS_DATA output on 16-bit + +1xx: reserved + 3 + 3 + read-write + + + + + SEQ_1 + SEQ_1 + SEQ_1 register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + SEQ0 + SEQ0[3:0]: channel number code for first conversion of the sequence + +0000: VINM[0] to ADC single negative input + +0001: VINM[1] to ADC single negative input + +0010: VINM[2] to ADC single negative input + +0011: VINM[3] to ADC single negative input + +0100: VINP[0] to ADC single positive input + +0101: VINP[1] to ADC single positive input + +0110: VINP[2] to ADC single positive input + +0111: VINP[3] to ADC single positive input + +1000: VINP[0]-VINM[0] to ADC differential input + +1001: VINP[1]-VINM[1] to ADC differential input + +1010: VINP[2]-VINM[2] to ADC differential input + +1011: VINP[3]-VINM[3] to ADC differential input + +1100: VBAT - Battery level detector + +1101: Temperature sensor + +111x: reserved + 0 + 4 + read-write + + + SEQ1 + SEQ1[3:0]: channel number code for second conversion of the sequence. + +See SEQ0 for code detail. + 4 + 4 + read-write + + + SEQ2 + SEQ2[3:0]: channel number code for 3rd conversion of the sequence. + +See SEQ0 for code detail. + 8 + 4 + read-write + + + SEQ3 + SEQ3[3:0]: channel number code for 4th conversion of the sequence. + +See SEQ0 for code detail. + 12 + 4 + read-write + + + SEQ4 + SEQ4[3:0]: channel number code for 5th conversion of the sequence. + +See SEQ0 for code detail. + 16 + 4 + read-write + + + SEQ5 + SEQ5[3:0]: channel number code for 6th conversion of the sequence. + +See SEQ0 for code detail. + 20 + 4 + read-write + + + SEQ6 + SEQ6[3:0]: channel number code for 7th conversion of the sequence. + +See SEQ0 for code detail. + 24 + 4 + read-write + + + SEQ7 + SEQ7[3:0]: channel number code for 8th conversion of the sequence. + +See SEQ0 for code detail. + 28 + 4 + read-write + + + + + SEQ_2 + SEQ_2 + SEQ_2 register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + SEQ8 + SEQ8[3:0]: channel number code for 9th conversion of the sequence + +0000: VINM[0] to ADC single negative input + +0001: VINM[1] to ADC single negative input + +0010: VINM[2] to ADC single negative input + +0011: VINM[3] to ADC single negative input + +0100: VINP[0] to ADC single positive input + +0101: VINP[1] to ADC single positive input + +0110: VINP[2] to ADC single positive input + +0111: VINP[3] to ADC single positive input + +1000: VINP[0]-VINM[0] to ADC differential input + +1001: VINP[1]-VINM[1] to ADC differential input + +1010: VINP[2]-VINM[2] to ADC differential input + +1011: VINP[3]-VINM[3] to ADC differential input + +1100: VBAT - Battery level detector + +1101: Temperature sensor + +111x: reserved + 0 + 4 + read-write + + + SEQ9 + SEQ9[3:0]: channel number code for 10th conversion of the sequence. + +See SEQ0 for code detail. + 4 + 4 + read-write + + + SEQ10 + SEQ10[3:0]: channel number code for 11th conversion of the sequence. + +See SEQ0 for code detail. + 8 + 4 + read-write + + + SEQ11 + SEQ11[3:0]: channel number code for 12th conversion of the sequence. + +See SEQ0 for code detail. + 12 + 4 + read-write + + + SEQ12 + SEQ12[3:0]: channel number code for 13th conversion of the sequence. + +See SEQ0 for code detail. + 16 + 4 + read-write + + + SEQ13 + SEQ13[3:0]: channel number code for 14th conversion of the sequence. + +See SEQ0 for code detail. + 20 + 4 + read-write + + + SEQ14 + SEQ14[3:0]: channel number code for 15th conversion of the sequence. + +See SEQ0 for code detail. + 24 + 4 + read-write + + + SEQ15 + SEQ15[3:0]: channel number code for 16th conversion of the sequence. + +See SEQ0 for code detail. + 28 + 4 + read-write + + + + + COMP_1 + COMP_1 + COMP_1 register + 0x28 + 0x20 + read-write + 0x00555 + 0xFFFFF + + + GAIN1 + GAIN1[11:0]: first calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET1 + OFFSET1[7:0]: first calibration point + 12 + 8 + read-write + + + + + COMP_2 + COMP_2 + COMP_2 register + 0x2C + 0x20 + read-write + 0x00555 + 0xFFFFF + + + GAIN2 + GAIN2[11:0]: second calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET2 + OFFSET2[7:0]: second calibration point + 12 + 8 + read-write + + + + + COMP_3 + COMP_3 + COMP_3 register + 0x30 + 0x20 + read-write + 0x00555 + 0xFFFFF + + + GAIN3 + GAIN3[11:0]: third calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET3 + OFFSET3[7:0]: third calibration point + 12 + 8 + read-write + + + + + COMP_4 + COMP_4 + COMP_4 register + 0x34 + 0x20 + read-write + 0x00555 + 0xFFFFF + + + GAIN4 + GAIN4[11:0]: fourth calibration point: gain AUXADC_GAIN_1V2[11:0] + 0 + 12 + read-write + + + OFFSET4 + OFFSET4[7:0]: fourth calibration point + 12 + 8 + read-write + + + + + COMP_SEL + COMP_SEL + COMP_SEL register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + OFFSET_GAIN0 + OFFSET_GAIN0[1:0]: gain / offset used in ADC single negative mode with Vinput range = + +1.2V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 0 + 2 + read-write + + + OFFSET_GAIN1 + OFFSET_GAIN1[1:0]: gain / offset used in ADC single positive mode with Vinput range = + +1.2V. This field also selects the gain/offset for Temperature Sensor input:: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 2 + 2 + read-write + + + OFFSET_GAIN2 + OFFSET_GAIN2[1:0]: gain / offset used in ADC differential mode with Vinput range = 1.2V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 4 + 2 + read-write + + + OFFSET_GAIN3 + OFFSET_GAIN3[1:0]: gain / offset used in ADC single negative mode with Vinput range = + +2.4V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 6 + 2 + read-write + + + OFFSET_GAIN4 + OFFSET_GAIN4[1:0]: gain / offset used in ADC single positive mode with Vinput range = + +2.4V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 8 + 2 + read-write + + + OFFSET_GAIN5 + OFFSET_GAIN5[1:0]: gain / offset used in ADC differential mode with Vinput range = 2.4V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 10 + 2 + read-write + + + OFFSET_GAIN6 + OFFSET_GAIN6[1:0]: gain / offset used in ADC single negative mode with Vinput range = + +3.6V. This field also selects the gain/offset for VBAT input:: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 12 + 2 + read-write + + + OFFSET_GAIN7 + OFFSET_GAIN7[1:0]: gain / offset used in ADC single positive mode with Vinput range = + +3.6V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 14 + 2 + read-write + + + OFFSET_GAIN8 + OFFSET_GAIN8[1:0]: gain / offset used in ADC differential mode with Vinput range = 3.6V: + +00: OFFSET1 and GAIN1 from COMP_1 + +01: OFFSET2 and GAIN2 from COMP_2 + +10: OFFSET3 and GAIN3 from COMP_3 + +11: OFFSET4 and GAIN4 from COMP_4 + 16 + 2 + read-write + + + + + WD_TH + WD_TH + WD_TH register + 0x3C + 0x20 + read-write + 0xFFF0000 + 0xFFFFFFF + + + WD_LT + WD_LT[11:0]: analog watchdog low level threshold. + 0 + 12 + read-write + + + WD_HT + WD_HT[11:0]: analog watchdog high level threshold. + 16 + 12 + read-write + + + + + WD_CONF + WD_CONF + WD_CONF register + 0x40 + 0x20 + read-write + 0x0 + 0xF + + + AWD_CHX + AWD_CHX[15:0]: analog watchdog channel selection to define which input channel(s) need + +to be guarded by the watchdog. + +Bit0: VINM[0] to ADC negative input + +Bit1: VINM[1] to ADC negative input + +Bit2: VINM[2] to ADC negative input + +Bit3: VINM[3] to ADC negative input + +Bit4: Not used + +Bit5: VBAT to ADC negative input + +Bit6: GND to ADC negative input + +Bit7: VDDA to ADC negative input + +Bit8: VINP[0] to ADC positive input + +Bit9: VINP[1] to ADC positive input + +Bit10: VINP[2] to ADC positive input + +Bit11: VINP[3] to ADC positive input + +Bit12: Not used + +Bit13: TEMP to ADC positive input + +Bit14: GND to ADC positive input + +Bit15: VDDA to ADC positive input + 0 + 16 + read-write + + + + + DS_DATAOUT + DS_DATAOUT + DS_DATAOUT register + 0x44 + 0x20 + read-only + 0x0 + 0xF + + + DS_DATA + DS_DATA[15:0]: contain the converted data at the output of the Down Sampler. + 0 + 16 + read-only + + + + + IRQ_STATUS + IRQ_STATUS + IRQ_STATUS register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + EOC_IRQ + EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. + +When read, provide the status of the interrupt: + +0: ADC conversion is not completed + +1: ADC conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 0 + 1 + read-write + + + EODS_IRQ + EODS_IRQ: set when the Down Sampler conversion is completed. + +When read, provide the status of the interrupt: + +0: Down Sampler conversion is not completed + +1: Down Sampler conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 1 + 1 + read-write + + + EOS_IRQ + EOS_IRQ: set when a sequence of conversion is completed. + +When read, provide the status of the interrupt: + +0: sequence of conversion is not completed + +1: sequence of conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 3 + 1 + read-write + + + AWD_IRQ + AWD_IRQ: set when an analog watchdog event occurs. + +When read, provide the status of the interrupt: + +0: no analog watchdog event occurred + +1: analog watchdog event has occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 4 + 1 + read-write + + + OVR_DS_IRQ + OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) + +When read, provide the status of the interrupt: + +0: no overrun occurred + +1: overrun occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 5 + 1 + read-write + + + + + IRQ_ENABLE + IRQ_ENABLE + IRQ_ENABLE register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + EOC_IRQ + EOC_IRQ (Used in test mode only): set when the ADC conversion is completed. + +When read, provide the status of the interrupt: + +0: ADC conversion is not completed + +1: ADC conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 0 + 1 + read-write + + + EODS_IRQ + EODS_IRQ: set when the Down Sampler conversion is completed. + +When read, provide the status of the interrupt: + +0: Down Sampler conversion is not completed + +1: Down Sampler conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 1 + 1 + read-write + + + EOS_IRQ + EOS_IRQ: set when a sequence of conversion is completed. + +When read, provide the status of the interrupt: + +0: sequence of conversion is not completed + +1: sequence of conversion is completed + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 3 + 1 + read-write + + + AWD_IRQ + AWD_IRQ: set when an analog watchdog event occurs. + +When read, provide the status of the interrupt: + +0: no analog watchdog event occurred + +1: analog watchdog event has occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 4 + 1 + read-write + + + OVR_DS_IRQ + OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost) + +When read, provide the status of the interrupt: + +0: no overrun occurred + +1: overrun occurred + +Writing this bit clears the status of the interrupt: + +0: no effect + +1: clear the interrupt + 5 + 1 + read-write + + + + + TEST_CONF + TEST_CONF + TEST_CONF register + 0x60 + 0x20 + read-write + 0x0 + 0xF + + + ADC_SWITCH_EN + ADC_SWITCH_EN[15:0]: enable individually each connection of the switching matrix at the + +ADC input. + +For each bit: + +0: switch X is ON + +1: switch X is OFF + +Bit mapping (corresponding to AUXADC_INSEL_1V2[15:0]): + +Bit 0: VINM[0] to ADC negative input + +Bit 1: VINM[1] to ADC negative input + +Bit 2: VINM[2] to ADC negative input + +Bit 3: VINM[3] to ADC negative input + +Bit4: GND to ADC negative input + +Bit5: VBAT to ADC negative input + +Bit6: GND to ADC negative input + +Bit7: VDDA to ADC negative input + +Bit8: VINP[0] to ADC positive input + +Bit9: VINP[1] to ADC positive input + +Bit10: VINP[2] to ADC positive input + +Bit11: VINP[3] to ADC positive input + +Bit12: VBAT to ADC positive input + +Bit13: TEMP to ADC positive input + +Bit14: GND to ADC positive input + +Bit15: VDDA to ADC positive input. + 0 + 16 + read-write + + + SEL_VIN_TYPE + SEL_VIN_TYPE[1:0]: operation mode of the selected VIN + +00: ADC single negative input + +01: ADC single positive input + +10: ADC differential input mode + +11: reserved + 18 + 2 + read-write + + + ADC_RUN + ADC_RUN: Start/stop ADC conversion. + +0: stop the ADC conversion, + +1: starts the ADC conversion. + 21 + 1 + read-write + + + ADC_ENABLE + ADC_ENABLE: + +0: disable the ADC (power OFF) + +1: enable the ADC (power ON) + 22 + 1 + read-write + + + + + DTB_CONF + DTB_CONF + DTB_CONF register + 0x64 + 0x20 + read-write + + + ADC_DBG_CONF + ADC_DBG_CONF[3:0]: use for debug purpose. + 0 + 4 + read-write + + + ADC_DTB_CONF + ADC_DTB_CONF[1:0]: configure the DTB output. + +00: DTB bus is all 0 + +01: output the ADC_BUSY, ADC_EOC, offset compensation data[11:0] on the ADC_DTB + +10: output the DS information on the ADC_DTB + +11: select states of the FSM and enable ADC serial output + +Note: detailed DTB configurations are available in the Table 38 in IUM + 8 + 2 + read-write + + + DTB_SER_SEL + DTB_SER_SEL: DTB serial output selection when ADC_DB_CONF[1:0]=3d + +0: pre down-sampler with offset compensation data + +1: post down-sampler data + 10 + 1 + read-write + + + FSM_STATE + FSM_STATE[7:0]: show the state of the state machine. + +Bit 0: IDLE + +Bit 1: Reserved + +Bit 2: ADC setup phase + +Bit 3: Reserved + +Bit 4: ADC_START_CONV resynchronization + +Bit 5: Reserved + +Bit 6: ADC mode + +Bit 7: sequence mode + 16 + 8 + read-only + + + FSM_CUR_STATE + FSM_CUR_STATE[2:0]: show the last executed state by the state machine. + +000: IDLE mode + +001: Reserved + +010: ADC setup phase + +011: Reserved + +100: ADC_START_CONV resynchronization + +101: Reserved + +110: ADC mode + +111: sequence mode + 24 + 3 + read-only + + + + + + + AES + AES + 0x48900000 + + 0x0 + 0x60 + registers + + + AES + AES interrupt + 13 + + + + AES_CR + AES_CR + AES_CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + EN + EN: AES IP enable + + 0 + 1 + read-write + + + DATATYPE + DATATYPE[1:0]: Data type selection + + 1 + 2 + read-write + + + MODE + MODE[1:0]: AES operating mode + + 3 + 2 + read-write + + + CHMOD_1_0 + CHMOD[1:0]: AES Chaining Mode selection + + 5 + 2 + read-write + + + CCFC + CCFC: Computation Complete Flag Clear + + 7 + 1 + read-write + + + ERRC + ERRC: Error clear + + 8 + 1 + read-write + + + CCFIE + CCFIE: CCF Flag Interrupt Enable + + 9 + 1 + read-write + + + ERRIE + ERRIE: Error Interrupt Enable + + 10 + 1 + read-write + + + DMAINEN + DMAINEN: DMA Input Enable + + 11 + 1 + read-write + + + DMAOUTEN + DMAOUTEN: DMA Output Enable + + 12 + 1 + read-write + + + GCMPH + GCMPH[1:0]: GCM or CCM Phase selection + + 13 + 2 + read-write + + + CHMOD_2 + CHMOD[2]: Chaining mode selection, bit [2] + + 16 + 1 + read-write + + + KEYSIZE + KEYSIZE: Key Size selection. + 18 + 1 + read-write + + + NPBLB + NPBLB: Number of Padding Bytes in Last Block of payload. + 20 + 4 + read-write + + + + + AES_SR + AES_SR + AES_SR register + 0x04 + 0x20 + read-only + 0x00000000 + + + CCF + CCF: Computation complete flag + + 0 + 1 + read-only + + + RDERR + RDERR: Read error flag + + 1 + 1 + read-only + + + WRERR + WRERR: Write error flag + + 2 + 1 + read-only + + + BUSY + BUSY: Busy flag + + 3 + 1 + read-only + + + + + AES_DINR + AES_DINR + AES_DINR register + 0x08 + 0x20 + read-write + 0x00000000 + + + DINR + DINR[x+31:x]: One of four 32-bit words of a 128-bit input data block being written into the peripheral + + 0 + 32 + read-write + + + + + AES_DOUTR + AES_DOUTR + AES_DOUTR register + 0x0C + 0x20 + read-only + 0x00000000 + + + DOUTR + DOUTR[x+31:x]: One of four 32-bit words of a 128-bit output data block being read from the + + 0 + 32 + read-only + + + + + AES_KEYR0 + AES_KEYR0 + AES_KEYRx register + 0x10 + 0x20 + read-write + 0x00000000 + + + KEY + KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)] + + 0 + 32 + read-write + + + + + AES_KEYR1 + AES_KEYR1 + AES_KEYRx register + 0x14 + 0x20 + read-write + 0x00000000 + + + KEY + KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)] + + 0 + 32 + read-write + + + + + AES_KEYR2 + AES_KEYR2 + AES_KEYRx register + 0x18 + 0x20 + read-write + 0x00000000 + + + KEY + KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)] + + 0 + 32 + read-write + + + + + AES_KEYR3 + AES_KEYR3 + AES_KEYRx register + 0x1C + 0x20 + read-write + 0x00000000 + + + KEY + KEY [((32*x)+31):((32*x)+0)]: Cryptographic key, bits [((32*x)+31):((32*x)+0)] + + 0 + 32 + read-write + + + + + AES_IVR0 + AES_IVR0 + AES_IVRx register + 0x20 + 0x20 + read-write + 0x00000000 + + + IVI + IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]) + + 0 + 32 + read-write + + + + + AES_IVR1 + AES_IVR1 + AES_IVRx register + 0x24 + 0x20 + read-write + 0x00000000 + + + IVI + IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]) + + 0 + 32 + read-write + + + + + AES_IVR2 + AES_IVR2 + AES_IVRx register + 0x28 + 0x20 + read-write + 0x00000000 + + + IVI + IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]) + + 0 + 32 + read-write + + + + + AES_IVR3 + AES_IVR3 + AES_IVRx register + 0x2C + 0x20 + read-write + 0x00000000 + + + IVI + IVI [((32*x)+31):((32*x)+0)]: Initialization vector register (LSB IVR[((32*x)+31):((32*x)+0)]) + + 0 + 32 + read-write + + + + + + + CRC + CRC + 0x48200000 + + 0x0 + 0x18 + registers + + + + CRC_DR + CRC_DR + CRC_DR register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits. +This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. +If the data size is less than 32 bits, the least significant bits are used to write/read the +correct value. + 0 + 32 + read-write + + + + + CRC_IDR + CRC_IDR + CRC_IDR register + 0x04 + 0x20 + read-write + 0x00000000 + + + IDR + 0 + 32 + read-write + + + + + CRC_CR + CRC_CR + CRC_CR register + 0x08 + 0x20 + read-write + 0x00000000 + + + RESET + RESET bit +This bit is set by software to reset the CRC calculation unit and set the data register to the value +stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware + 0 + 1 + read-write + + + POLYSIZE + Polynomial size +These bits control the size of the polynomial. +-00: 32 bit polynomial +-01: 16 bit polynomial +-10: 8 bit polynomial +-11: 7 bit polynomial + 3 + 2 + read-write + + + REV_IN + Reverse input data +These bits control the reversal of the bit order of the input data +-00: Bit order not affected +-01: Bit reversal done by byte +-10: Bit reversal done by half-word +-11: Bit reversal done by word + 5 + 2 + read-write + + + REV_OUT + Reverse output data +This bit controls the reversal of the bit order of the output data. +-0: Bit order not affected +-1: Bit-reversed output format + 7 + 1 + read-write + + + + + CRC_INIT + CRC_INIT + CRC_INIT register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + INIT + Programmable initial CRC value +This register is used to write the CRC initial value. + 0 + 32 + read-write + + + + + CRC_POL + CRC_POL + CRC_POL register + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + POL + POL[31:0]: Programmable polynomial +This register is used to write the coefficients of the polynomial to be used for CRC calculation. +If the polynomial size is less than 32 bits, the least significant bits have to be used to program the +correct value. + 0 + 32 + read-write + + + + + + + COMP + COMP address block description + COMP + 0x40009000 + + 0x0 + 0x4 + registers + + + COMP + Comp interrupt through SYSCFG + 19 + + + + CSR + CSR + CSR register + 0x00 + 0x20 + read-write + + + EN + EN: Comparator enable bit + +This bit is set and cleared by software (only if LOCK not set). It switches on Comparator. + +0: Comparator switched OFF + +1: Comparator switched ON + 0 + 1 + read-write + + + PWRMODE + PWRMODE[1:0]: Power Mode of the comparator + +These bits are set and cleared by software (only if LOCK not set). They control the + +power/speed of the Comparator. + +00:High speed + +01 or 10:Medium speed + +11:Ultra low power + 2 + 2 + read-write + + + INMSEL + INMSEL: Comparator input minus selection bits + +These bits are set and cleared by software (only if LOCK not set). They select which input is + +connected to the input minus of comparator. + +000: 1/4 VREFINT + +001: 1/2 VREFINT + +010: 3/4VREFINT + +011: VREFINT + +100: DAC OUT + +101: PA13 + +110: PB0 + +111: PB3 + 4 + 3 + read-write + + + INPSEL + INPSEL[1:0]: Comparator input plus selection bit + +This bit is set and cleared by software (only if LOCK not set). + +00: PA14 + +01: PB1 + +1x: PB2 + 7 + 2 + read-write + + + POLARITY + POLARITY: Comparator polarity selection bit + +This bit is set and cleared by software (only if LOCK not set). It inverts Comparator polarity. + +0: Comparator output value not inverted + +1: Comparator output value inverted + 15 + 1 + read-write + + + HYST + HYST[1:0]: Comparator hysteresis selection bits + +These bits are set and cleared by software (only if LOCK not set). They select the + +Hysteresis voltage of the comparator . + +00: No hysteresis + +01: Low hysteresis + +10: Medium hysteresis + +11: High hysteresis + 16 + 2 + read-write + + + BLANKING + BLANKING[2:0]: Comparator blanking source selection bits + +These bits select which timer output controls the comparator output blanking. + +000: No blanking + +001: TIM2 OC4 selected as blanking source + +010: TIM16 OC1 selected as blanking source + +All other values: reserved + 18 + 3 + read-write + + + BRGEN + BRGEN: Scaler bridge enable + +This bit is set and cleared by software (only if LOCK not set). This bit enable the bridge of + +the scaler. + +0: Scaler resistor bridge disable + +1: Scaler resistor bridge enable + +If SCALEN is set and BRGEN is reset, BG voltage reference is available but not 1/4BGAP, 1/2BGAP, 3/4 BGAP. BGAP value is sent instead of 1/4BGAP, 1/2BGAP, 3/4 BGAP. + +If SCALEN and BRGEN are set, 1/4 BGAP 1/2BGAP 3/4BGAP and BGAP voltage + +references are available. + 22 + 1 + read-write + + + SCALEN + SCALEN: Voltage scaler enable bit + +This bit is set and cleared by software. This bit enable the outputs of the VREFINT divider + +available on the minus input of the Comparator + +0: scaler disable + +1: scaler enable + 23 + 1 + read-write + + + VALUE + VALUE: Comparator output status bit + +This bit is read-only. It reflects the current comparator output taking into account POLARITY + +bit effect. + 30 + 1 + read-only + + + LOCK + LOCK: COMP_CSR register lock bit + +This bit is set by software and cleared by a hardware system reset. It locks the whole + +content of the comparator control register, COMP1_CSR[31:0]. + +0: COMP1_CSR[31:0] are read/write + +1: COMP1_CSR[31:0] are read-only + 31 + 1 + read-only + + + + + + + DAC + DAC address block description + DAC + 0x40006000 + + 0x0 + 0xA0 + registers + + + DAC + DAC interrupt + 25 + + + + CR + CR + CR register + 0x00 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: DAC channel enable This bit is set and cleared by software to enable/disable DAC + +channel. + +0: DAC channel disabled + +1: DAC channel enabled + 0 + 1 + read-write + + + BON + BON: DAC channel output buffer enable. This bit is set and cleared by software to + +enable/disable DAC channel output buffer. + +0: DAC channel output buffer disabled + +1: DAC channel output buffer enabled + 1 + 1 + read-write + + + TEN + TEN: DAC channel trigger enable This bit is set and cleared by software to enable/disable + +DAC channel trigger. + +0: DAC channel trigger disabled and data written into the DAC_DHR register are transferred + + one APB0 clock cycle later to the DAC_DOR register + +1: DAC channel trigger enabled and data from the DAC_DHR register are transferred three + + APB0 clock cycles later to the DAC_DOR register + +Note: When software trigger is selected, the transfer from the DAC_DHR + +register to the DAC_DOR register takes only one APB0 clock cycle. + 2 + 1 + read-write + + + TSEL + TSEL[2:0]: DAC channel trigger selection These bits select the external event used to trigger + +DAC channel. + +000: Timer 16 TRGO event + +001: PA8 pin event from SYSCFG + +010 to 011: Reserved + +111: Software trigger + +Only used if bit TEN = 1 (DAC channel trigger enabled). + 3 + 3 + read-write + + + WAVE + WAVE[1:0]: DAC channel noise/triangle wave generation enable These bits are set and + +cleared by software. + +00: wave generation disabled + +01: Noise wave generation enabled + +1x: Triangle wave generation enabled + +Note: Only used if bit TEN = 1 (DAC channel trigger enabled). + 6 + 2 + read-write + + + MAMP + MAMP[3:0]: DAC channel mask amplitude selector These bits are written by software to + +select mask in wave generation mode or amplitude in triangle generation mode. + +0000: Unmask bit0 of LFSR triangle amplitude equal to 1 + +0001: Unmask bits[1:0] of LFSR triangle amplitude equal to 3 + +0010: Unmask bits[2:0] of LFSR triangle amplitude equal to 7 + +0011: Unmask bits[3:0] of LFSR triangle amplitude equal to 15 + +0100: Unmask bits[4:0] of LFSR triangle amplitude equal to 31 + +greater than or equal to 0101: Unmask bits[5:0] of LFSR triangle amplitude equal to 63 + 8 + 4 + read-write + + + DMAEN + DMAEN: DAC channel DMA enable This bit is set and cleared by software. + +0: DAC channel DMA mode disabled + +1: DAC channel DMA mode enabled + 12 + 1 + read-write + + + DMAUDRIE + DMAUDRIE: DAC channel DMA Underrun Interrupt enable This bit is set and cleared by + +software. + +0: DAC channel DMA Underrun Interrupt disabled + +1: DAC channel DMA Underrun Interrupt enabled + 13 + 1 + read-write + + + CMPEN + CMPEN: DAC channel output to COMP INMINUS enable. This bit is set and cleared by + +software. + +0: DAC channel output to COMP INMINUS disabled + +1: DAC channel output to COMP INMINUS enabled + 14 + 1 + read-write + + + VCMEN + VCMEN: DAC channel output to VCM BUFFER enable. This bit is set and cleared by + +software. + +0: DAC channel output to VCM BUFFER disabled + +1: DAC channel output to VCM BUFFER enabled + 15 + 1 + read-write + + + VCMON + VCMON: VCMBUFF power-up. This bit is set and cleared by software. + +0: VCM BUFFER OFF + +1: VCM BUFFER ON + 16 + 1 + read-write + + + + + SWTRIGR + SWTRIGR + SWTRIGR register + 0x04 + 0x20 + read-write + 0x0000 + 0xFFFF + + + SWTRIG + SWTRIG: DAC channel software trigger This bit is set by software to enable/disable the + +software trigger. + +0: Software trigger disabled + +1: Software trigger enabled + +Note: This bit is cleared by hardware (one APB0 clock cycle later) once the + +DAC_DHR register value has been loaded into the DAC_DOR register. + 0 + 1 + write-only + + + + + DHR + DHR + DHR register + 0x10 + 0x20 + read-write + 0x0000 + 0xFFFF + + + DACDHR + DACDHR[5:0]: DAC channel 6-bit data These bits are written by software which + +specifies 6-bit data for DAC channel. + 0 + 6 + read-write + + + + + DOR + DOR + DOR register + 0x2C + 0x20 + read-only + 0x0 + 0xF + + + DACDOR + DACDOR[5:0]: DAC channel data output These bits are read-only, they contain data output + +for DAC channel. + 0 + 6 + read-only + + + + + SR + SR + SR register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + DMAUDR + DMAUDR: DAC channel DMA underrun flag This bit is set by hardware and cleared by + +software (by writing it to 1). + +0: No DMA underrun error condition occurred for DAC channel + +1: DMA underrun error condition occurred for DAC channel (the currently selected trigger is + + driving DAC channel conversion at a frequency higher than the DMA service capability rate) + 13 + 1 + read-write + + + + + + + DBGMCU + DBGMCU + 0x40008000 + + 0x0 + 0xC + registers + + + + CR + CR + CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + DBG_SLEEP + Allow debug of the CPU in SLEEP mode +- 0: Normal operation. All clocks will be disabled automatically in SLEEP mode +- 1: Automatic clock stop disabled. All active CPU clocks and oscillators will continue to run during SLEEP mode, allowing full CPU debug capability. On exit from SLEEP mode, the clock settings will be set to the SLEEP mode exit state. + 0 + 1 + read-write + + + DBG_STOP + Allow debug of the CPU in DEEPSTOP mode +- 0: Normal operation. All clocks will be disabled automatically in STOP mode +- 1: Automatic clock stop disabled. All active CPU clocks and oscillators will continue to run during STOP mode, allowing full CPU debug capability. On exit from STOP mode, the clock settings will be set to the STOP mode exit state. + 1 + 1 + read-write + + + + + DBG_APB0_FZ + DBG_APB0_FZ + DBG_APB0_FZ register + 0x04 + 0x20 + read-write + 0x00000000 + + + DBG_TIM2_STOP + TIM2 stop in the CPU debug +- 0: Normal operation. TIM2 continues to operate while the CPU is in debug mode +- 1: Stop in debug. TIM2 is frozen while the CPU is in debug mode. + 0 + 1 + read-write + + + DBG_TIM16_STOP + TIM16 stop in the CPU debug +- 0: Normal operation. TIM16 continues to operate while the CPU is in debug mode +- 1: Stop in debug. TIM16 is frozen while the CPU is in debug mode. + 1 + 1 + read-write + + + DBG_RTC_STOP + RTC stop in CPU debug +- 0: Normal operation. RTC continues to operate while the CPU is in debug mode +- 1: Stop in debug. RTC is frozen while the CPU is in debug mode. + 12 + 1 + read-write + + + DBG_IWDG_STOP + IWDG stop in the CPU debug +- 0: Normal operation. IWDG continues to operate while the CPU is in debug mode +- 1: Stop in debug. IWDG is frozen while the CPU is in debug mode. + 14 + 1 + read-write + + + + + DBG_APB1_FZ + DBG_APB1_FZ + DBG_APB1_FZ register + 0x08 + 0x20 + read-write + 0x00000000 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout stop in CPU debug +- 0: Normal operation. I2C1 SMBUS timeout continues to operate while the CPU is in debug mode +- 1: Stop in debug. I2C1 SMBUS timeou is frozen while the CPU is in debug mode. + 21 + 1 + read-write + + + DBG_I2C2_STOP + I2C2 SMBUS timeout stop in CPU debug +- 0: Normal operation. I2C2 SMBUS timeout continues to operate while the CPU is in debug mode +- 1: Stop in debug. I2C2 SMBUS timeou is frozen while the CPU is in debug mode. + 23 + 1 + read-write + + + + + + + DMAMUX + DMAMUX address block description + DMAMUX + 0x48800000 + + 0x0 + 0x20 + registers + + + + C0CR + C0CR + CxCR register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C1CR + C1CR + CxCR register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C2CR + C2CR + CxCR register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C3CR + C3CR + CxCR register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C4CR + C4CR + CxCR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C5CR + C5CR + CxCR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C6CR + C6CR + CxCR register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + C7CR + C7CR + CxCR register + 0x1C + 0x20 + read-write + + + DMAREQ_ID + DMAREQ_ID[4:0]: DMA REQuest IDentification + +Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer + +inputs to resources. + 0 + 5 + read-write + + + + + + + DMA + DMA address block description + DMA + 0x48700000 + + 0x0 + 0xA4 + registers + + + DMA + DMA interrupt + 17 + + + + DMA_ISR + DMA_ISR + DMA_ISR register + 0x00 + 0x20 + read-only + 0x0000 + 0xFFFF + + + GIF1 + GIF1: Channel 1 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 1 + +1: A TE, HT or TC event occurred on channel 1 + 0 + 1 + read-only + + + TCIF1 + TCIF1: Channel 1 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 1 + +1: A transfer complete (TC) event occurred on channel 1 + 1 + 1 + read-only + + + HTIF1 + HTIF1: Channel 1 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 1 + +1: A half transfer (HT) event occurred on channel 1 + 2 + 1 + read-only + + + TE1F1 + TEIF1: Channel 1 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 1 + +1: A transfer error (TE) occurred on channel 1 + 3 + 1 + read-only + + + GIF2 + GIF2: Channel 2 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 2 + +1: A TE, HT or TC event occurred on channel 2 + 4 + 1 + read-only + + + TCIF2 + TCIF2: Channel 2 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 2 + +1: A transfer complete (TC) event occurred on channel 2 + 5 + 1 + read-only + + + HTIF2 + HTIF2: Channel 2 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 2 + +1: A half transfer (HT) event occurred on channel 2 + 6 + 1 + read-only + + + TE1F2 + TEIF2: Channel 2 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 2 + +1: A transfer error (TE) occurred on channel 2 + 7 + 1 + read-only + + + GIF3 + GIF3: Channel 3 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 3 + +1: A TE, HT or TC event occurred on channel 3 + 8 + 1 + read-only + + + TCIF3 + TCIF3: Channel 3 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 3 + +1: A transfer complete (TC) event occurred on channel 3 + 9 + 1 + read-only + + + HTIF3 + HTIF3: Channel 3 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 3 + +1: A half transfer (HT) event occurred on channel 3 + 10 + 1 + read-only + + + TE1F3 + TEIF3: Channel 3 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 3 + +1: A transfer error (TE) occurred on channel 3 + 11 + 1 + read-only + + + GIF4 + GIF4: Channel 4 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 4 + +1: A TE, HT or TC event occurred on channel 4 + 12 + 1 + read-only + + + TCIF4 + TCIF4: Channel 4 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 4 + +1: A transfer complete (TC) event occurred on channel 4 + 13 + 1 + read-only + + + HTIF4 + HTIF4: Channel 4 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 4 + +1: A half transfer (HT) event occurred on channel 4 + 14 + 1 + read-only + + + TE1F4 + TEIF4: Channel 4 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 4 + +1: A transfer error (TE) occurred on channel 4 + 15 + 1 + read-only + + + GIF5 + GIF5: Channel 5 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 5 + +1: A TE, HT or TC event occurred on channel 5 + 16 + 1 + read-only + + + TCIF5 + TCIF5: Channel 5 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 5 + +1: A transfer complete (TC) event occurred on channel 5 + 17 + 1 + read-only + + + HTIF5 + HTIF5: Channel 5 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 5 + +1: A half transfer (HT) event occurred on channel 5 + 18 + 1 + read-only + + + TE1F5 + TEIF5: Channel 5 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 5 + +1: A transfer error (TE) occurred on channel 5 + 19 + 1 + read-only + + + GIF6 + GIF6: Channel 6 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 6 + +1: A TE, HT or TC event occurred on channel 6 + 20 + 1 + read-only + + + TCIF6 + TCIF6: Channel 6 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 6 + +1: A transfer complete (TC) event occurred on channel 6 + 21 + 1 + read-only + + + HTIF6 + HTIF6: Channel 6 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 6 + +1: A half transfer (HT) event occurred on channel 6 + 22 + 1 + read-only + + + TE1F6 + TEIF6: Channel 6 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 6 + +1: A transfer error (TE) occurred on channel 6 + 23 + 1 + read-only + + + GIF7 + GIF7: Channel 7 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 7 + +1: A TE, HT or TC event occurred on channel 7 + 24 + 1 + read-only + + + TCIF7 + TCIF7: Channel 7 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 7 + +1: A transfer complete (TC) event occurred on channel 7 + 25 + 1 + read-only + + + HTIF7 + HTIF7: Channel 7 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 7 + +1: A half transfer (HT) event occurred on channel 7 + 26 + 1 + read-only + + + TE1F7 + TEIF7: Channel 7 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 7 + +1: A transfer error (TE) occurred on channel 7 + 27 + 1 + read-only + + + GIF8 + GIF8: Channel 8 global interrupt flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No TE, HT or TC event on channel 8 + +1: A TE, HT or TC event occurred on channel 8 + 28 + 1 + read-only + + + TCIF8 + TCIF8: Channel 8 transfer complete flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer complete (TC) event on channel 8 + +1: A transfer complete (TC) event occurred on channel 8 + 29 + 1 + read-only + + + HTIF8 + HTIF8: Channel 8 half transfer flag + +This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No half transfer (HT) event on channel 8 + +1: A half transfer (HT) event occurred on channel 8 + 30 + 1 + read-only + + + TE1F8 + TEIF8: Channel 8 transfer error flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. + +0: No transfer error (TE) on channel 8 + +1: A transfer error (TE) occurred on channel 8 + 31 + 1 + read-only + + + + + DMA_IFCR + DMA_IFCR + DMA_IFCR register + 0x04 + 0x20 + write-only + 0x0000 + 0xFFFF + + + CGIF1 + CGIF1: Channel 1 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 0 + 1 + write-only + + + CTCIF1 + CTCIF1: Channel 1 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 1 + 1 + write-only + + + CHTIF1 + CHTIF1: Channel 1 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 2 + 1 + write-only + + + CTEIF1 + CTEIF1: Channel 1 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 3 + 1 + write-only + + + CGIF2 + CGIF2: Channel 2 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 4 + 1 + write-only + + + CTCIF2 + CTCIF2: Channel 2 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 5 + 1 + write-only + + + CHTIF2 + CHTIF2: Channel 2 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 6 + 1 + write-only + + + CTEIF2 + CTEIF2: Channel 2 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 7 + 1 + write-only + + + CGIF3 + CGIF3: Channel 3 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 8 + 1 + write-only + + + CTCIF3 + CTCIF3: Channel 3 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 9 + 1 + write-only + + + CHTIF3 + CHTIF3: Channel 3 half transfer clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 10 + 1 + write-only + + + CTEIF3 + CTEIF3: Channel 3 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 11 + 1 + write-only + + + CGIF4 + CGIF4: Channel 4 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 12 + 1 + write-only + + + CTCIF4 + CTCIF4: Channel 4 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 13 + 1 + write-only + + + CHTIF4 + CHTIF4: Channel 4 half transfer clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 14 + 1 + write-only + + + CTEIF4 + CTEIF4: Channel 4 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 15 + 1 + write-only + + + CGIF5 + CGIF5: Channel 5 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 16 + 1 + write-only + + + CTCIF5 + CTCIF5: Channel 5 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 17 + 1 + write-only + + + CHTIF5 + CHTIF5: Channel 5 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 18 + 1 + write-only + + + CTEIF5 + CTEIF5: Channel 5 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 19 + 1 + write-only + + + CGIF6 + CGIF6: Channel 6 global interrupt clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 20 + 1 + write-only + + + CTCIF6 + CTCIF6: Channel 6 transfer complete clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 21 + 1 + write-only + + + CHTIF6 + CHTIF6: Channel 6 half transfer clear + +This bit is set and cleared by software. + +0: No effect. + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 22 + 1 + write-only + + + CTEIF6 + CTEIF6: Channel 6 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 23 + 1 + write-only + + + CGIF7 + CGIF7: Channel 7 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 24 + 1 + write-only + + + CTCIF7 + CTCIF7: Channel 7 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 25 + 1 + write-only + + + CHTIF7 + CHTIF7: Channel 7 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 26 + 1 + write-only + + + CTEIF7 + CTEIF7: Channel 7 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 27 + 1 + write-only + + + CGIF8 + CGIF8: Channel 8 global interrupt clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register + 28 + 1 + write-only + + + CTCIF8 + CTCIF8: Channel 8 transfer complete clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TCIF flag in the DMA_ISR register + 29 + 1 + write-only + + + CHTIF8 + CHTIF8: Channel 8 half transfer clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding HTIF flag in the DMA_ISR register + 30 + 1 + write-only + + + CTEIF8 + CTEIF8: Channel 8 transfer error clear + +This bit is set and cleared by software. + +0: No effect + +1: Clears the corresponding TEIF flag in the DMA_ISR register + 31 + 1 + write-only + + + + + DMA_CCR1 + DMA_CCR1 + DMA_CCRx register + 0x08 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR1 + DMA_CNDTR1 + DMA_CNDTRx register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR1 + DMA_CPAR1 + DMA_CPARx register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR1 + DMA_CMAR1 + DMA_CMARx register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR2 + DMA_CCR2 + DMA_CCRx register + 0x1C + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR2 + DMA_CNDTR2 + DMA_CNDTRx register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR2 + DMA_CPAR2 + DMA_CPARx register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR2 + DMA_CMAR2 + DMA_CMARx register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR3 + DMA_CCR3 + DMA_CCRx register + 0x30 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR3 + DMA_CNDTR3 + DMA_CNDTRx register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR3 + DMA_CPAR3 + DMA_CPARx register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR3 + DMA_CMAR3 + DMA_CMARx register + 0x3C + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR4 + DMA_CCR4 + DMA_CCRx register + 0x44 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR4 + DMA_CNDTR4 + DMA_CNDTRx register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR4 + DMA_CPAR4 + DMA_CPARx register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR4 + DMA_CMAR4 + DMA_CMARx register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR5 + DMA_CCR5 + DMA_CCRx register + 0x58 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR5 + DMA_CNDTR5 + DMA_CNDTRx register + 0x5C + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR5 + DMA_CPAR5 + DMA_CPARx register + 0x60 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR5 + DMA_CMAR5 + DMA_CMARx register + 0x64 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR6 + DMA_CCR6 + DMA_CCRx register + 0x6C + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR6 + DMA_CNDTR6 + DMA_CNDTRx register + 0x70 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR6 + DMA_CPAR6 + DMA_CPARx register + 0x74 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR6 + DMA_CMAR6 + DMA_CMARx register + 0x78 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR7 + DMA_CCR7 + DMA_CCRx register + 0x80 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR7 + DMA_CNDTR7 + DMA_CNDTRx register + 0x84 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR7 + DMA_CPAR7 + DMA_CPARx register + 0x88 + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR7 + DMA_CMAR7 + DMA_CMARx register + 0x8C + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CCR8 + DMA_CCR8 + DMA_CCRx register + 0x94 + 0x20 + read-write + 0x0000 + 0xFFFF + + + EN + EN: Channel enable + +This bit is set and cleared by software. + +0: Channel disabled + +1: Channel enabled + 0 + 1 + read-write + + + TCIE + TCIE: Transfer complete interrupt enable + +This bit is set and cleared by software. + +0: TC interrupt disabled + +1: TC interrupt enabled + 1 + 1 + read-write + + + HTIE + HTIE: Half transfer interrupt enable + +This bit is set and cleared by software. + +0: HT interrupt disabled + +1: HT interrupt enabled + 2 + 1 + read-write + + + TEIE + TEIE: Transfer error interrupt enable + +This bit is set and cleared by software. + +0: TE interrupt disabled + +1: TE interrupt enabled + 3 + 1 + read-write + + + DIR + DIR: Data transfer direction + +This bit is set and cleared by software. + +0: Read from peripheral. + +1: Read from memory + 4 + 1 + read-write + + + CIRC + CIRC: Circular mode + +This bit is set and cleared by software. + +0: Circular mode disabled + +1: Circular mode enabled + 5 + 1 + read-write + + + PINC + PINC: Peripheral increment mode + +This bit is set and cleared by software. + +0: Peripheral increment mode disabled + +1: Peripheral increment mode enabled + 6 + 1 + read-write + + + MINC + MINC: Memory increment mode + +This bit is set and cleared by software. + +0: Memory increment mode disabled + +1: Memory increment mode enabled + 7 + 1 + read-write + + + PSIZE + PSIZE[1:0]: Peripheral size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 8 + 2 + read-write + + + MSIZE + MSIZE[1:0]: Memory size + +These bits are set and cleared by software. + +00: 8-bits + +01: 16-bits + +10: 32-bits + 10 + 2 + read-write + + + PL + PL[1:0]: Channel priority level + +These bits are set and cleared by software. + +00: Low + +01: Medium + +10: High + +11: Very high + 12 + 2 + read-write + + + MEM2MEM + MEM2MEM: Memory to memory mode + +This bit is set and cleared by software. + +0: Memory to memory mode disabled + +1: Memory to memory mode enabled + 14 + 1 + read-write + + + + + DMA_CNDTR8 + DMA_CNDTR8 + DMA_CNDTRx register + 0x98 + 0x20 + read-write + 0x0 + 0xF + + + NDT + NDT[15:0]: Number of data to transfer + +Number of data to be transferred (0 up to 65535). This register can only be written when the + +channel is disabled. Once the channel is enabled, this register is read-only, indicating the + +remaining bytes to be transmitted. This register decrements after each DMA transfer. + +Once the transfer is completed, this register can either stay at zero or be reloaded + +automatically by the value previously programmed if the channel is configured in auto-reload + +mode. + +If this register is zero, no transaction can be served whether the channel is enabled or not. + 0 + 16 + read-write + + + + + DMA_CPAR8 + DMA_CPAR8 + DMA_CPARx register + 0x9C + 0x20 + read-write + 0x0 + 0xF + + + PA + PA[31:0]: Peripheral address + +Base address of the peripheral data register from/to which the data will be read/written. + +When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + DMA_CMAR8 + DMA_CMAR8 + DMA_CMARx register + 0xA0 + 0x20 + read-write + 0x0 + 0xF + + + MA + MA[31:0]: Memory address + +Base address of the memory area from/to which the data will be read/written. + +When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword + +address. + +When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word + +address. + 0 + 32 + read-write + + + + + + + DYNAMIC_REG + DYNAMIC_REG + 0x49000500 + + 0x0 + 0x40 + registers + + + + PCKTLEN_CONFIG + PCKTLEN_CONFIG + PCKTLEN_CONFIG register + 0x0 + 0x20 + read-write + 0x00000014 + + + PCKTLEN + This bit field has different meanings/usages: + + 0 + 16 + read-write + + + + + MOD0_CONFIG + MOD0_CONFIG + MOD0_CONFIG register + 0x4 + 0x20 + read-write + 0x00083A93 + + + DATARATE_M + The mantissa of the specified data rate (default: 38. + 0 + 16 + read-write + + + DATARATE_E + The exponent of the specified data rate (default: 38. + 16 + 4 + read-write + + + MOD_TYPE + Select the modulation type + + 20 + 3 + read-write + + + CONST_MAP + Also known as FOUR_GFSK_CONST_MAP + + 24 + 2 + read-write + + + BT_SEL + Select BT value for GFSK + + 26 + 1 + read-write + + + PA_CLKON_LOCKONTX + Enable the clock on analog PA in LOCKONTX state + + 31 + 1 + read-write + + + + + MOD1_CONFIG + MOD1_CONFIG + MOD1_CONFIG register + 0x8 + 0x20 + read-write + 0x00400435 + + + FDEV_M + Mantissa of the frequency deviation (default: 28. + 0 + 8 + read-write + + + FDEV_E + Exponent of the frequency deviation (default: 28. + 8 + 4 + read-write + + + CHFLT_M + Mantissa of the channel filter BW (default: 100 kHz) + 16 + 4 + read-write + + + CHFLT_E + Exponent of the channel filter BW (default: 100 kHz) + 20 + 4 + read-write + + + + + SNYTH_FREQ + SNYTH_FREQ + SNYTH_FREQ register + 0xc + 0x20 + read-write + 0x04851615 + + + SYNTH_FRAC + Fractional part of the PLL fractional divide factor (default: 868 MHz, XTAL: 48 MHz) + 0 + 20 + read-write + + + SYNTH_INT + PLL integer divide factor (default: 868 MHz, XTAL: 48 MHz) + 20 + 8 + read-write + + + BS + Synthesizer band selector, i. + 30 + 1 + read-write + + + + + VCO_CAL_CONFIG + VCO_CAL_CONFIG + VCO_CAL_CONFIG register + 0x10 + 0x20 + read-write + 0x00400088 + + + VCO_CALAMP_EXT + VCO magnitude calibration word in thermometric code + + 0 + 14 + read-write + + + VCO_CALAMP_EXT_SEL + Select the mode to provide an external VCO amplitude calibration value through VCO_CALAMP_EXT bit field + + 15 + 1 + read-write + + + VCO_CALFREQ_EXT + VCO Cbank frequency calibration word. + 16 + 7 + read-write + + + VCO_CALFREQ_EXT_SEL + Select the mode to provide an external VCO frequency calibration value through VCO_CALFREQ_EXT bit field + + 23 + 1 + read-write + + + VCO_CALIB_REQ + Define if the Radio FSM must launch a VCO calibration request after VCO start-up + + 31 + 1 + read-write + + + + + RX_TIMER + RX_TIMER + RX_TIMER register + 0x14 + 0x20 + read-write + 0x00000000 + + + RX_TIMEOUT + RX timer timeout (relative duration in interpolated absolute time unit) + 0 + 23 + read-write + + + RX_CS_TIMEOUT_MASK + - 0: CS flag does not contribute to timeout disabling + + 28 + 1 + read-write + + + RX_PQI_TIMEOUT_MASK + - 0: PREAMBLE valid flag does not contribute to timeout disabling + + 29 + 1 + read-write + + + RX_SQI_TIMEOUT_MASK + - 0: SYNC valid flag does not contribute to timeout disabling + + 30 + 1 + read-write + + + RX_OR_nAND_SELECT + Select logical OR or logcial AND to apply on CS/PQI/SQI timeout mask + + 31 + 1 + read-write + + + + + DATABUFFER_THR + DATABUFFER_THR + DATABUFFER_THR register + 0x18 + 0x20 + read-write + 0x00000000 + + + RX_ALMOST_FULL_THR + Almost Full threshold for RX Data Buffers + + 0 + 16 + read-write + + + TX_ALMOST_EMPTY_THR + Almost Empty threshold for TX Data Buffers. + 16 + 16 + read-write + + + + + RFSEQ_IRQ_ENABLE + RFSEQ_IRQ_ENABLE + RFSEQ_IRQ_ENABLE register + 0x1c + 0x20 + read-write + 0x00000000 + + + TX_DONE_E + Enable interrupt on TX_DONE_F flag + 0 + 1 + read-write + + + RX_OK_E + Enable interrupt on RX_OK_F flag + 1 + 1 + read-write + + + RX_TIMEOUT_E + Enable interrupt on RX_TIMEOUT_F flag + 2 + 1 + read-write + + + RX_CRC_ERROR_E + Enable interrupt on RX_CRC_ERROR_F flag + 3 + 1 + read-write + + + FAST_RX_TERM_E + Enable interrupt on FAST_RX_TERM_F flag + 4 + 1 + read-write + + + RXTIMER_STOP_CDT_E + Enable interrupt on RXTIMER_STOP_CDT_F flag + 7 + 1 + read-write + + + SABORT_DONE_E + Enable interrupt on SABORT command treated and done flag + 8 + 1 + read-write + + + COMMAND_REJECTED_E + Enable interrupt on COMMAND_REJECTED flag + 9 + 1 + read-write + + + CS_E + Enable interrupt on CS_F flag + 12 + 1 + read-write + + + PREAMBLE_VALID_E + Enable interrupt on PREAMBLE_VALID_F flag + 13 + 1 + read-write + + + SYNC_VALID_E + Enable interrupt on SYNC_VALID_F flag + 14 + 1 + read-write + + + DATABUFFER0_USED_E + Enable interrupt on DATABUFFER0_USED_F flag + 16 + 1 + read-write + + + DATABUFFER1_USED_E + Enable interrupt on DATABUFFER1_USED_F flag + 17 + 1 + read-write + + + RX_ALMOST_FULL_0_E + Enable interrupt on RX_ALMOST_FULL_0_F flag + 18 + 1 + read-write + + + RX_ALMOST_FULL_1_E + Enable interrupt on RX_ALMOST_FULL_1_F flag + 19 + 1 + read-write + + + TX_ALMOST_EMPTY_0_E + Enable interrupt on TX_ALMOST_EMPTY_0_F flag + 20 + 1 + read-write + + + TX_ALMOST_EMPTY_1_E + Enable interrupt on TX_ALMOST_EMPTY_1_F flag + 21 + 1 + read-write + + + AHB_ACCESS_ERROR_E + Enable interrupt on AHB_ACCESS_ERROR_F flag + 22 + 1 + read-write + + + HW_ANA_FAILURE_E + Enable interrupt on HW_ANA_FAILURE_F flag + 24 + 1 + read-write + + + SEQ_E + Enable interrupt on SEQ_F flag + 26 + 1 + read-write + + + RRM_CMD_START_E + Enable interrupt on RRM_CMD_END_F flag + 27 + 1 + read-write + + + RRM_CMD_END_E + Enable interrupt on RRM_CMD_END_F flag + 28 + 1 + read-write + + + SAFEASK_CALIB_DONE_E + Enable interrupt on SAFEASK_CALIB_DONE_F flag + 30 + 1 + read-write + + + AGC_CALIB_DONE_E + Enable interrupt on AGC_CALIB_DONE_F flag + 31 + 1 + read-write + + + + + ADDITIONAL_CTRL + ADDITIONAL_CTRL + ADDITIONAL_CTRL register + 0x20 + 0x20 + read-write + 0x00038800 + + + CH_NUM + Channel number. + 0 + 8 + read-write + + + CH_SPACING + Channel spacing. + 8 + 8 + read-only + + + PA_FC + Power control bandwidth selection according data rate + + 16 + 2 + read-write + + + TIME_CAPTURESEL + Select the trigger event to capture the interpolated absolute time in the TIME_CAPTURE[31:0] register + + 20 + 3 + read-write + + + AS_ENABLE + Enable the antenna switching feature. + 31 + 1 + read-write + + + + + FAST_RX_TIMER + FAST_RX_TIMER + FAST_RX_TIMER register + 0x24 + 0x20 + read-write + 0x00000000 + + + FAST_RX_TIMEOUT + Fast RX termination timer value (corresponding to the delay to measure the RSSI and to let the HW check CS flag information) + + 0 + 8 + read-write + + + FAST_CS_TERM_EN + Enable the Fast RX Termination feature + + 8 + 1 + read-write + + + + + COMMAND + COMMAND + COMMAND register + 0x28 + 0x20 + read-write + 0x00000000 + + + COMMAND_ID + Opcode coresponding to a command: + + 0 + 4 + read-write + + + BACK2ACTIVE + Select the default/return state for the Radio FSM to be ACTIVE2 + + 25 + 1 + read-write + + + BACK2LOCKON + Request to the Radio FSM to stay in LOCKON state when exiting a RX or a TX + + 26 + 1 + read-write + + + + + + + FLASH_CTRL + 4kb addressable space + FLASH_CTRL + 0x40001000 + + 0x0 + 0x200 + registers + + + Flash + Non-volatile memory (flash) +controller + 0 + + + + COMMAND + COMMAND + COMMAND register + 0x00 + 0x20 + read-write + 0x00000000 + + + COMMAND + Macro commands for flash operations (may require DATA0...DATA3 to be set): +- 0x11 : ERASE +- 0x22 : MASSERASE +- 0x33 : WRITE +- 0x55 : MASSREAD +- 0xAA : SLEEP +- 0xBB : WAKEUP +- 0xCC : BURSTWRITE +- 0xEE : OTPWRITE +- 0xFF : KEYWRITE + 0 + 8 + read-write + + + + + CONFIG + CONFIG + CONFIG register + 0x04 + 0x20 + read-write + 0x00000010 + + + REMAP + CPU access routing (it supersedes PREMAP configuration): +- 0 : FLASH memory addressed +- 1 : SRAM0 memory addressed + 1 + 1 + read-write + + + DIS_GROUP_WRITE + Burst write Control: +- 0 : burst write allowed +- 1 : burst write forbidden + 2 + 1 + read-write + + + WAIT_STATE + Add latency to flash read opeations: +- 00 : no latency +- 01 : 1 clock cycle latency +- 10 : 2 clock cycles latency +- 11 : 3 clock cycles latency + 4 + 2 + read-write + + + SLEEP_SM + Flash memory power-down mode enable in SLEEP mode +This bit allows to have the Flash memory in power-down mode or in idle mode when the +device is in Sleep mode. +- 0: When the device is in Sleep mode, the NVM is in Idle mode. +- 1: When the device is in Sleep mode, the NVM is in power-down mode. + 6 + 1 + read-write + + + + + IRQSTAT + IRQSTAT + IRQSTAT register + 0x08 + 0x20 + read-write + 0x00000000 + + + CMDDONE_MIS + (1: clear, 0: inactive) CMDDONE_MIS flag + 0 + 1 + read-write + + + CMDSTART_MIS + (1: clear, 0: inactive) CMDSTART_MIS flag + 1 + 1 + read-write + + + CMDBUSYERR_MIS + (1: clear, 0: inactive) CMDBUSYERR_MIS flag + 2 + 1 + read-write + + + ILLCMD_MIS + (1: clear, 0: inactive) ILLCMD_MIS flag + 3 + 1 + read-write + + + READOK_MIS + (1: clear, 0: inactive) READOK_MIS flag + 4 + 1 + read-write + + + FNREADY_MIS + (1: clear, 0: inactive) FNREADY_MIS flag + 5 + 1 + read-write + + + + + IRQMASK + IRQMASK + IRQMASK register + 0x0C + 0x20 + read-write + 0x0000003F + + + CMDDONEM + (1: mask, 0: inactive) CMDDONE_MIS mask + 0 + 1 + read-write + + + CMDSTARTM + (1: mask, 0: inactive) CMDSTART_MIS mask + 1 + 1 + read-write + + + CMDBUSYERRM + (1: mask, 0: inactive) CMDBUSYERR_MIS mask + 2 + 1 + read-write + + + ILLCMDM + (1: mask, 0: inactive) ILLCMD_MIS mask + 3 + 1 + read-write + + + READOKM + (1: mask, 0: inactive) READOK_MIS mask + 4 + 1 + read-write + + + FNREADYM + (1: mask, 0: inactive) FNREADY_MIS mask + 5 + 1 + read-write + + + + + IRQRAW + IRQRAW + IRQRAW register + 0x10 + 0x20 + read-write + 0x00000001 + + + CMDDONE_RIS + (1: active, 0: inactive) COMMAND sequence ended + 0 + 1 + read-write + + + CMDSTART_RIS + (1: active, 0: inactive) COMMAND sequence started + 1 + 1 + read-write + + + CMDBUSYERR_RIS + (1: active, 0: inactive) COMMAND issued while flash busy + 2 + 1 + read-write + + + ILLCMD_RIS + (1: active, 0: inactive) Illegal command issued + 3 + 1 + read-write + + + READOK_RIS + (1: active, 0: inactive) READ COMMAND completed successfully + 4 + 1 + read-write + + + CMDSLEEPERR_RIS + (1: active, 0: inactive) COMMAND issued while flash in sleep-mode (SLM=1) + 5 + 1 + read-write + + + + + SIZE + SIZE + SIZE register + 0x14 + 0x20 + read-only + 0x0000FFFF + + + FLASH_SIZE + Maximum valid address for flash memory: +- 00 : 0x03FFF (64kb) +- 01 : 0x07FFF (128kb) +- 10 : 0x0BFFF (192kb) +- 11 : 0x0FFFF (256kb) + 0 + 17 + read-only + + + RAM_SIZE + RAM memory size selection: +- 0 : 16kb +- 1 : 32kb + 17 + 1 + read-only + + + FLASH_SECURE + Flash memory protection (0: no key present, 1: key present) + 19 + 1 + read-only + + + JTAG_DISABLE + Flash+JTAG protection (0: no JTAG protection - see FLASH_SECURE, 1: Flash and JTAG protected) + 20 + 1 + read-only + + + PACKAGE_SIZE + Package selection: +- 0- : CSP +- 10 : 32pins +- 11 : 48pins + 21 + 2 + read-only + + + + + ADDRESS + ADDRESS + ADDRESS register + 0x18 + 0x20 + read-write + 0x00000000 + + + YADDR + Flash column address offset to be used with some COMMAND + 0 + 6 + read-write + + + XADDR + Flash row address offset to be used with some COMMAND + 6 + 10 + read-write + + + + + LFSRVAL + LFSRVAL + LFSRVAL register + 0x24 + 0x20 + read-only + 0xFFFFFFFF + + + LFSRVAL + Flash read data CRC signature + 0 + 32 + read-only + + + + + PAGEPROT0 + PAGEPROT0 + PAGEPROT0 register + 0x34 + 0x20 + read-write + 0x00000000 + + + SEGSIZE0 + First segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 0 + 7 + read-write + + + SEGOFFSET0 + First segment, 7-bit page protection offset (first page number in protected segment) + 8 + 7 + read-write + + + SEGSIZE1 + Second segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 16 + 7 + read-write + + + SEGOFFSET1 + Second segment, 7-bit page protection offset (first page number in protected segment) + 24 + 7 + read-write + + + + + PAGEPROT1 + PAGEPROT1 + PAGEPROT1 register + 0x38 + 0x20 + read-write + 0x00000000 + + + SEGSIZE2 + Third segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 0 + 7 + read-write + + + SEGOFFSET2 + Third segment, 7-bit page protection offset (first page number in protected segment) + 8 + 7 + read-write + + + SEGSIZE3 + Fourth segment, 7-bit page protection size (number of pages to protect in segment, first page included) + 16 + 7 + read-write + + + SEGOFFSET3 + Fourth segment, 7-bit page protection offset (first page number in protected segment) + 24 + 7 + read-write + + + + + DATA0 + DATA0 + DATA0 register + 0x40 + 0x20 + read-write + 0xFFFFFFFF + + + DATA0 + Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD + 0 + 32 + read-write + + + + + DATA1 + DATA1 + DATA1 register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + DATA1 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA2 + DATA2 + DATA2 register + 0x48 + 0x20 + read-write + 0xFFFFFFFF + + + DATA2 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + DATA3 + DATA3 + DATA3 register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + DATA3 + Value to be used as DATA for any COMMAND of type WRITE + 0 + 32 + read-write + + + + + UNLOCK012 + UNLOCK012 + UNLOCK012 register + 0x50 + 0x20 + read-write + 0xFFFFFFFF + + + UNLOCK012 + (NOT TO BE DOCUMENTED) Remove read-write protection from IFR0, IFR1, IFR2 sectors + 0 + 32 + read-write + + + + + UNLOCK3 + UNLOCK3 + UNLOCK3 register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + UNLOCK3 + (NOT TO BE DOCUMENTED) Remove read-write protection from IFR3 sector + 0 + 32 + read-write + + + + + + + GPIOA + GPIOA + 0x48000000 + + 0x0 + 0x2C + registers + + + GPIOA + GPIOA interrupt + 15 + + + + MODER + MODER + MODER register + 0x00 + 0x20 + read-write + 0x000000A0 + + + MODE0 + MODE0[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 0 + 2 + read-write + + + MODE1 + MODE1[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 2 + 2 + read-write + + + MODE2 + MODE2[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 4 + 2 + read-write + + + MODE3 + MODE3[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 6 + 2 + read-write + + + MODE4 + MODE4[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 8 + 2 + read-write + + + MODE5 + MODE5[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 10 + 2 + read-write + + + MODE6 + MODE6[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 12 + 2 + read-write + + + MODE7 + MODE7[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 14 + 2 + read-write + + + MODE8 + MODE8[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 16 + 2 + read-write + + + MODE9 + MODE9[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 18 + 2 + read-write + + + MODE10 + MODE10[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 20 + 2 + read-write + + + MODE11 + MODE11[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 22 + 2 + read-write + + + MODE12 + MODE12[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 24 + 2 + read-write + + + MODE13 + MODE13[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 26 + 2 + read-write + + + MODE14 + MODE14[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 28 + 2 + read-write + + + MODE15 + MODE15[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 30 + 2 + read-write + + + + + OTYPER + OTYPER + OTYPER register + 0x04 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 0 + 1 + read-write + + + OT1 + OT1: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 1 + 1 + read-write + + + OT2 + OT2: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 2 + 1 + read-write + + + OT3 + OT3: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 3 + 1 + read-write + + + OT4 + OT4: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 4 + 1 + read-write + + + OT5 + OT5: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 5 + 1 + read-write + + + OT6 + OT6: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 6 + 1 + read-write + + + OT7 + OT7: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 7 + 1 + read-write + + + OT8 + OT8: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 8 + 1 + read-write + + + OT9 + OT9: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 9 + 1 + read-write + + + OT10 + OT10: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 10 + 1 + read-write + + + OT11 + OT11: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 11 + 1 + read-write + + + OT12 + OT12: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 12 + 1 + read-write + + + OT13 + OT13: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 13 + 1 + read-write + + + OT14 + OT14: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 14 + 1 + read-write + + + OT15 + OT15: Port A configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 15 + 1 + read-write + + + + + OSPEEDR + OSPEEDR + OSPEEDR register + 0x08 + 0x20 + read-write + 0x00000030 + + + OSPEED0 + OSPEED0[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 0 + 2 + read-write + + + OSPEED1 + OSPEED1[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 2 + 2 + read-write + + + OSPEED2 + OSPEED2[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 4 + 2 + read-write + + + OSPEED3 + OSPEED3[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 6 + 2 + read-write + + + OSPEED4 + OSPEED4[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 8 + 2 + read-write + + + OSPEED5 + OSPEED5[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 10 + 2 + read-write + + + OSPEED6 + OSPEED6[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 12 + 2 + read-write + + + OSPEED7 + OSPEED7[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 14 + 2 + read-write + + + OSPEED8 + OSPEED8[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 16 + 2 + read-write + + + OSPEED9 + OSPEED9[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 18 + 2 + read-write + + + OSPEED10 + OSPEED10[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 20 + 2 + read-write + + + OSPEED11 + OSPEED11[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 22 + 2 + read-write + + + OSPEED12 + OSPEED12[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 24 + 2 + read-write + + + OSPEED13 + OSPEED13[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 26 + 2 + read-write + + + OSPEED14 + OSPEED14[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 28 + 2 + read-write + + + OSPEED15 + OSPEED15[1:0]: Port A configuration bits +These bits are written by software to configure the I/O output speed. + 30 + 2 + read-write + + + + + PUPDR + PUPDR + PUPDR register + 0x0C + 0x20 + read-write + 0x55555595 + + + PUPD0 + PUPD0: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 0 + 2 + read-write + + + PUPD1 + PUPD1: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 2 + 2 + read-write + + + PUPD2 + PUPD2: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 4 + 2 + read-write + + + PUPD3 + PUPD3: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 6 + 2 + read-write + + + PUPD4 + PUPD4: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 8 + 2 + read-write + + + PUPD5 + PUPD5: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 10 + 2 + read-write + + + PUPD6 + PUPD6: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 12 + 2 + read-write + + + PUPD7 + PUPD7: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 14 + 2 + read-write + + + PUPD8 + PUPD8: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 16 + 2 + read-write + + + PUPD9 + PUPD9: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 18 + 2 + read-write + + + PUPD10 + PUPD10: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 20 + 2 + read-write + + + PUPD11 + PUPD11: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 22 + 2 + read-write + + + PUPD12 + PUPD12: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 24 + 2 + read-write + + + PUPD13 + PUPD13: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 26 + 2 + read-write + + + PUPD14 + PUPD14: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 28 + 2 + read-write + + + PUPD15 + PUPD15: Port A configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 30 + 2 + read-write + + + + + IDR + IDR + IDR register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + ID0: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 0 + 1 + read-only + + + ID1 + ID1: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 1 + 1 + read-only + + + ID2 + ID2: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 2 + 1 + read-only + + + ID3 + ID3: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 3 + 1 + read-only + + + ID4 + ID4: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 4 + 1 + read-only + + + ID5 + ID5: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 5 + 1 + read-only + + + ID6 + ID6: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 6 + 1 + read-only + + + ID7 + ID7: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 7 + 1 + read-only + + + ID8 + ID8: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 8 + 1 + read-only + + + ID9 + ID9: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 9 + 1 + read-only + + + ID10 + ID10: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 10 + 1 + read-only + + + ID11 + ID11: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 11 + 1 + read-only + + + ID12 + ID12: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 12 + 1 + read-only + + + ID13 + ID13: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 13 + 1 + read-only + + + ID14 + ID14: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 14 + 1 + read-only + + + ID15 + ID15: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 15 + 1 + read-only + + + + + ODR + ODR + ODR register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + OD0: Port A output data bit +These bits can be read and written by software + 0 + 1 + read-write + + + OD1 + OD1: Port A output data bit +These bits can be read and written by software + 1 + 1 + read-write + + + OD2 + OD2: Port A output data bit +These bits can be read and written by software + 2 + 1 + read-write + + + OD3 + OD3: Port A output data bit +These bits can be read and written by software + 3 + 1 + read-write + + + OD4 + OD4: Port A output data bit +These bits can be read and written by software + 4 + 1 + read-write + + + OD5 + OD5: Port A output data bit +These bits can be read and written by software + 5 + 1 + read-write + + + OD6 + OD6: Port A output data bit +These bits can be read and written by software + 6 + 1 + read-write + + + OD7 + OD7: Port A output data bit +These bits can be read and written by software + 7 + 1 + read-write + + + OD8 + OD8: Port A output data bit +These bits can be read and written by software + 8 + 1 + read-write + + + OD9 + OD9: Port A output data bit +These bits can be read and written by software + 9 + 1 + read-write + + + OD10 + OD10: Port A output data bit +These bits can be read and written by software + 10 + 1 + read-write + + + OD11 + OD11: Port A output data bit +These bits can be read and written by software + 11 + 1 + read-write + + + OD12 + OD12: Port A output data bit +These bits can be read and written by software + 12 + 1 + read-write + + + OD13 + OD13: Port A output data bit +These bits can be read and written by software + 13 + 1 + read-write + + + OD14 + OD14: Port A output data bit +These bits can be read and written by software + 14 + 1 + read-write + + + OD15 + OD15: Port A output data bit +These bits can be read and written by software + 15 + 1 + read-write + + + + + BSRR + BSRR + BSRR register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +0: No action on the corresponding ODx bit +1: Sets the corresponding ODx bit + 0 + 1 + write-only + + + BS1 + BS1: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +0: No action on the corresponding ODx bit +1: Sets the corresponding ODx bit + 1 + 1 + write-only + + + BS2 + BS2: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. +0: No action on the corresponding ODx bit +1: Sets the corresponding ODx bit + 2 + 1 + write-only + + + BS3 + BS3: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + BS4 + BS4: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + BS5 + BS5: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000 + 5 + 1 + write-only + + + BS6 + BS6: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + BS7 + BS7: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000 + 7 + 1 + write-only + + + BS8 + BS8: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + BS9 + BS9: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + BS10 + BS10: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + BS11 + BS11: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + BS12 + BS12: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + BS13 + BS13: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + BS14 + BS14: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + BS15 + BS15: Port A set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + BR0 + BR0: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + BR1 + BR1: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + BR2 + BR2: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + BR3 + BR3: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + BR4 + BR4: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + BR5 + BR5: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + BR6 + BR6: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + BR7 + BR7: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + BR8 + BR8: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + BR9 + BR9: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + BR10 + BR10: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + BR11 + BR11: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + BR12 + BR12: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + BR13 + BR13: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + BR14 + BR14: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + BR15 + BR15: Port A reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + + + LCKR + LCKR + LCKR register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0: Port A lock bit 0 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 0 + 1 + read-write + + + LCK1 + LCK1: Port A lock bit 1 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 1 + 1 + read-write + + + LCK2 + LCK2: Port A lock bit 2 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 2 + 1 + read-write + + + LCK3 + LCK3: Port A lock bit 3 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 3 + 1 + read-write + + + LCK4 + LCK4: Port A lock bit 4 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 4 + 1 + read-write + + + LCK5 + LCK5: Port A lock bit 5 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 5 + 1 + read-write + + + LCK6 + LCK6: Port A lock bit 6 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 6 + 1 + read-write + + + LCK7 + LCK7: Port A lock bit 7 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 7 + 1 + read-write + + + LCK8 + LCK8: Port A lock bit 8 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 8 + 1 + read-write + + + LCK9 + LCK9: Port A lock bit 9 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 9 + 1 + read-write + + + LCK10 + LCK10: Port A lock bit 10 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 10 + 1 + read-write + + + LCK11 + LCK11: Port A lock bit 11 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 11 + 1 + read-write + + + LCK12 + LCK12: Port A lock bit 12 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 12 + 1 + read-write + + + LCK13 + LCK13: Port A lock bit 13 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 13 + 1 + read-write + + + LCK14 + LCK14: Port A lock bit 14 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 14 + 1 + read-write + + + LCK15 + LCK15: Port A lock bit 15 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 15 + 1 + read-write + + + LCKK + LCKK: Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +-0: Port configuration lock key not active +-1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU +reset or peripheral reset. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Any error in the lock sequence aborts the lock. +After the first lock sequence on any bit of the port, any read access on the LCKK bit will +return 1 until the next MCU reset or peripheral reset + 16 + 1 + read-write + + + + + AFRL + AFRL + AFRL register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL1 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL2 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL3 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL4 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL5 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL6 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL7 + y[3:0]: Alternate function selection for port A pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + AFRH + AFRH + AFRH register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL9 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL10 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL11 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL12 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL13 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL14 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL15 + y[3:0]: Alternate function selection for port A pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + BRR + BRR + BRR register + 0x28 + 0x20 + read-write + 0x00000000 + + + BR0 + BR0: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 0 + 1 + write-only + + + BR1 + BR1: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 1 + 1 + write-only + + + BR2 + BR2: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 2 + 1 + write-only + + + BR3 + BR3: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 3 + 1 + write-only + + + BR4 + BR4: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 4 + 1 + write-only + + + BR5 + BR5: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 5 + 1 + write-only + + + BR6 + BR6: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 6 + 1 + write-only + + + BR7 + BR7: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 7 + 1 + write-only + + + BR8 + BR8: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 8 + 1 + write-only + + + BR9 + BR9: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 9 + 1 + write-only + + + BR10 + BR10: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 10 + 1 + write-only + + + BR11 + BR11: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 11 + 1 + write-only + + + BR12 + BR12: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 12 + 1 + write-only + + + BR13 + BR13: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 13 + 1 + write-only + + + BR14 + BR14: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 14 + 1 + write-only + + + BR15 + BR15: Port A reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 15 + 1 + write-only + + + + + + + GPIOB + GPIOB + 0x48100000 + + 0x0 + 0x2C + registers + + + GPIOB + GPIOB interrupt + 16 + + + + MODER + MODER + MODER register + 0x00 + 0x20 + read-write + 0x00000000 + + + MODE0 + MODE0[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 0 + 2 + read-write + + + MODE1 + MODE1[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 2 + 2 + read-write + + + MODE2 + MODE2[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 4 + 2 + read-write + + + MODE3 + MODE3[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 6 + 2 + read-write + + + MODE4 + MODE4[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 8 + 2 + read-write + + + MODE5 + MODE5[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 10 + 2 + read-write + + + MODE6 + MODE6[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 12 + 2 + read-write + + + MODE7 + MODE7[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 14 + 2 + read-write + + + MODE8 + MODE8[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 16 + 2 + read-write + + + MODE9 + MODE9[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 18 + 2 + read-write + + + MODE10 + MODE10[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 20 + 2 + read-write + + + MODE11 + MODE11[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 22 + 2 + read-write + + + MODE12 + MODE12[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 24 + 2 + read-write + + + MODE13 + MODE13[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 26 + 2 + read-write + + + MODE14 + MODE14[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 28 + 2 + read-write + + + MODE15 + MODE15[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode. +-00: Input mode +-01: output mode +-10: Alternate function mode +-11: Analog mode + 30 + 2 + read-write + + + + + OTYPER + OTYPER + OTYPER register + 0x04 + 0x20 + read-write + 0x00000000 + + + OT0 + OT0: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 0 + 1 + read-write + + + OT1 + OT1: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 1 + 1 + read-write + + + OT2 + OT2: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 2 + 1 + read-write + + + OT3 + OT3: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 3 + 1 + read-write + + + OT4 + OT4: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 4 + 1 + read-write + + + OT5 + OT5: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 5 + 1 + read-write + + + OT6 + OT6: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 6 + 1 + read-write + + + OT7 + OT7: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 7 + 1 + read-write + + + OT8 + OT8: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 8 + 1 + read-write + + + OT9 + OT9: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 9 + 1 + read-write + + + OT10 + OT10: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 10 + 1 + read-write + + + OT11 + OT11: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 11 + 1 + read-write + + + OT12 + OT12: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 12 + 1 + read-write + + + OT13 + OT13: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 13 + 1 + read-write + + + OT14 + OT14: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 14 + 1 + read-write + + + OT15 + OT15: Port B configuration bits +These bits are written by software to configure the I/O output type. +-0: Output push-pull (reset state) +-1: Output open-drain + 15 + 1 + read-write + + + + + OSPEEDR + OSPEEDR + OSPEEDR register + 0x08 + 0x20 + read-write + 0x00000000 + + + OSPEED0 + OSPEED0[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 0 + 2 + read-write + + + OSPEED1 + OSPEED1[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 2 + 2 + read-write + + + OSPEED2 + OSPEED2[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 4 + 2 + read-write + + + OSPEED3 + OSPEED3[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 6 + 2 + read-write + + + OSPEED4 + OSPEED4[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 8 + 2 + read-write + + + OSPEED5 + OSPEED5[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 10 + 2 + read-write + + + OSPEED6 + OSPEED6[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 12 + 2 + read-write + + + OSPEED7 + OSPEED7[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 14 + 2 + read-write + + + OSPEED8 + OSPEED8[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 16 + 2 + read-write + + + OSPEED9 + OSPEED9[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 18 + 2 + read-write + + + OSPEED10 + OSPEED10[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 20 + 2 + read-write + + + OSPEED11 + OSPEED11[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 22 + 2 + read-write + + + OSPEED12 + OSPEED12[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 24 + 2 + read-write + + + OSPEED13 + OSPEED13[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 26 + 2 + read-write + + + OSPEED14 + OSPEED14[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 28 + 2 + read-write + + + OSPEED15 + OSPEED15[1:0]: Port B configuration bits +These bits are written by software to configure the I/O output speed. + 30 + 2 + read-write + + + + + PUPDR + PUPDR + PUPDR register + 0x0C + 0x20 + read-write + 0x55555555 + + + PUPD0 + PUPD0: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 0 + 2 + read-write + + + PUPD1 + PUPD1: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 2 + 2 + read-write + + + PUPD2 + PUPD2: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 4 + 2 + read-write + + + PUPD3 + PUPD3: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 6 + 2 + read-write + + + PUPD4 + PUPD4: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 8 + 2 + read-write + + + PUPD5 + PUPD5: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 10 + 2 + read-write + + + PUPD6 + PUPD6: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 12 + 2 + read-write + + + PUPD7 + PUPD7: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 14 + 2 + read-write + + + PUPD8 + PUPD8: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 16 + 2 + read-write + + + PUPD9 + PUPD9: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 18 + 2 + read-write + + + PUPD10 + PUPD10: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 20 + 2 + read-write + + + PUPD11 + PUPD11: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 22 + 2 + read-write + + + PUPD12 + PUPD12: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 24 + 2 + read-write + + + PUPD13 + PUPD13: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 26 + 2 + read-write + + + PUPD14 + PUPD14: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 28 + 2 + read-write + + + PUPD15 + PUPD15: Port B configuration bits +These bits are written by software to configure the I/O pull-up or pull-down +-00: No pull-up, pull-down +-01: Pull-up +-10: Pull-down +-11: Reserved + 30 + 2 + read-write + + + + + IDR + IDR + IDR register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID0 + ID0: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 0 + 1 + read-only + + + ID1 + ID1: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 1 + 1 + read-only + + + ID2 + ID2: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 2 + 1 + read-only + + + ID3 + ID3: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 3 + 1 + read-only + + + ID4 + ID4: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 4 + 1 + read-only + + + ID5 + ID5: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 5 + 1 + read-only + + + ID6 + ID6: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 6 + 1 + read-only + + + ID7 + ID7: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 7 + 1 + read-only + + + ID8 + ID8: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 8 + 1 + read-only + + + ID9 + ID9: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 9 + 1 + read-only + + + ID10 + ID10: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 10 + 1 + read-only + + + ID11 + ID11: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 11 + 1 + read-only + + + ID12 + ID12: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 12 + 1 + read-only + + + ID13 + ID13: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 13 + 1 + read-only + + + ID14 + ID14: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 14 + 1 + read-only + + + ID15 + ID15: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port + 15 + 1 + read-only + + + + + ODR + ODR + ODR register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD0 + OD0: Port B output data bit +These bits can be read and written by software + 0 + 1 + read-write + + + OD1 + OD1: Port B output data bit +These bits can be read and written by software + 1 + 1 + read-write + + + OD2 + OD2: Port B output data bit +These bits can be read and written by software + 2 + 1 + read-write + + + OD3 + OD3: Port B output data bit +These bits can be read and written by software + 3 + 1 + read-write + + + OD4 + OD4: Port B output data bit +These bits can be read and written by software + 4 + 1 + read-write + + + OD5 + OD5: Port B output data bit +These bits can be read and written by software + 5 + 1 + read-write + + + OD6 + OD6: Port B output data bit +These bits can be read and written by software + 6 + 1 + read-write + + + OD7 + OD7: Port B output data bit +These bits can be read and written by software + 7 + 1 + read-write + + + OD8 + OD8: Port B output data bit +These bits can be read and written by software + 8 + 1 + read-write + + + OD9 + OD9: Port B output data bit +These bits can be read and written by software + 9 + 1 + read-write + + + OD10 + OD10: Port B output data bit +These bits can be read and written by software + 10 + 1 + read-write + + + OD11 + OD11: Port B output data bit +These bits can be read and written by software + 11 + 1 + read-write + + + OD12 + OD12: Port B output data bit +These bits can be read and written by software + 12 + 1 + read-write + + + OD13 + OD13: Port B output data bit +These bits can be read and written by software + 13 + 1 + read-write + + + OD14 + OD14: Port B output data bit +These bits can be read and written by software + 14 + 1 + read-write + + + OD15 + OD15: Port B output data bit +These bits can be read and written by software + 15 + 1 + read-write + + + + + BSRR + BSRR + BSRR register + 0x18 + 0x20 + write-only + 0x00000000 + + + BS0 + BS0: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 0 + 1 + write-only + + + BS1 + BS1: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 1 + 1 + write-only + + + BS2 + BS2: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 2 + 1 + write-only + + + BS3 + BS3: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 3 + 1 + write-only + + + BS4 + BS4: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 4 + 1 + write-only + + + BS5 + BS5: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 5 + 1 + write-only + + + BS6 + BS6: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 6 + 1 + write-only + + + BS7 + BS7: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 7 + 1 + write-only + + + BS8 + BS8: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 8 + 1 + write-only + + + BS9 + BS9: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 9 + 1 + write-only + + + BS10 + BS10: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 10 + 1 + write-only + + + BS11 + BS11: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 11 + 1 + write-only + + + BS12 + BS12: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 12 + 1 + write-only + + + BS13 + BS13: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 13 + 1 + write-only + + + BS14 + BS14: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 14 + 1 + write-only + + + BS15 + BS15: Port B set bit y +These bits are write-only. A read to these bits returns the value 0x0000. + 15 + 1 + write-only + + + BR0 + BR0: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 16 + 1 + write-only + + + BR1 + BR1: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 17 + 1 + write-only + + + BR2 + BR2: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 18 + 1 + write-only + + + BR3 + BR3: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 19 + 1 + write-only + + + BR4 + BR4: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 20 + 1 + write-only + + + BR5 + BR5: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 21 + 1 + write-only + + + BR6 + BR6: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 22 + 1 + write-only + + + BR7 + BR7: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 23 + 1 + write-only + + + BR8 + BR8: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 24 + 1 + write-only + + + BR9 + BR9: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 25 + 1 + write-only + + + BR10 + BR10: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 26 + 1 + write-only + + + BR11 + BR11: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 27 + 1 + write-only + + + BR12 + BR12: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 28 + 1 + write-only + + + BR13 + BR13: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 29 + 1 + write-only + + + BR14 + BR14: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 30 + 1 + write-only + + + BR15 + BR15: Port B reset bit y +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit +Note: If both BSx and BRx are set, BSx has priority. + 31 + 1 + write-only + + + + + LCKR + LCKR + LCKR register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCK0 + LCK0: Port B lock bit 0 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 0 + 1 + read-write + + + LCK1 + LCK1: Port B lock bit 1 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 1 + 1 + read-write + + + LCK2 + LCK2: Port B lock bit 2 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 2 + 1 + read-write + + + LCK3 + LCK3: Port B lock bit 3 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 3 + 1 + read-write + + + LCK4 + LCK4: Port B lock bit 4 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 4 + 1 + read-write + + + LCK5 + LCK5: Port B lock bit 5 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 5 + 1 + read-write + + + LCK6 + LCK6: Port B lock bit 6 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 6 + 1 + read-write + + + LCK7 + LCK7: Port B lock bit 7 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 7 + 1 + read-write + + + LCK8 + LCK8: Port B lock bit 8 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 8 + 1 + read-write + + + LCK9 + LCK9: Port B lock bit 9 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 9 + 1 + read-write + + + LCK10 + LCK10: Port B lock bit 10 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 10 + 1 + read-write + + + LCK11 + LCK11: Port B lock bit 11 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 11 + 1 + read-write + + + LCK12 + LCK12: Port B lock bit 12 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 12 + 1 + read-write + + + LCK13 + LCK13: Port B lock bit 13 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 13 + 1 + read-write + + + LCK14 + LCK14: Port B lock bit 14 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 14 + 1 + read-write + + + LCK15 + LCK15: Port B lock bit 15 +These bits are read/write but can only be written when the LCKK bit is 0, using the specific +sequence described in LCKK bit description. +-0: Port configuration not locked +-1: Port configuration locked + 15 + 1 + read-write + + + LCKK + LCKK: Lock key +This bit can be read any time. It can only be modified using the lock key write sequence. +-0: Port configuration lock key not active +-1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU +reset or peripheral reset. +LOCK key write sequence: +WR LCKR[16] = 1 + LCKR[15:0] +WR LCKR[16] = 0 + LCKR[15:0] +WR LCKR[16] = 1 + LCKR[15:0] +RD LCKR +RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) +Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. +Any error in the lock sequence aborts the lock. +After the first lock sequence on any bit of the port, any read access on the LCKK bit will +return 1 until the next MCU reset or peripheral reset + 16 + 1 + read-write + + + + + AFRL + AFRL + AFRL register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL0 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL1 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL2 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL3 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL4 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL5 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL6 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL7 + y[3:0]: Alternate function selection for Port B pin y (y = 0..7) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + AFRH + AFRH + AFRH register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL8 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 0 + 4 + read-write + + + AFSEL9 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 4 + 4 + read-write + + + AFSEL10 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 8 + 4 + read-write + + + AFSEL11 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 12 + 4 + read-write + + + AFSEL12 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 16 + 4 + read-write + + + AFSEL13 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 20 + 4 + read-write + + + AFSEL14 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 24 + 4 + read-write + + + AFSEL15 + y[3:0]: Alternate function selection for Port B pin y (y = 8..15) +These bits are written by software to configure alternate function I/Os +AFSELy selection: +-0000: AF0 +-0001: AF1 +-0010: AF2 +-0011: AF3 +-0100: AF4 +-0101: AF5 +-0110: AF6 +-0111: AF7 +1xxx: Reserved + 28 + 4 + read-write + + + + + BRR + BRR + BRR register + 0x28 + 0x20 + read-write + + + BR0 + BR0: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 0 + 1 + write-only + + + BR1 + BR1: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 1 + 1 + write-only + + + BR2 + BR2: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 2 + 1 + write-only + + + BR3 + BR3: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 3 + 1 + write-only + + + BR4 + BR4: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 4 + 1 + write-only + + + BR5 + BR5: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 5 + 1 + write-only + + + BR6 + BR6: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 6 + 1 + write-only + + + BR7 + BR7: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 7 + 1 + write-only + + + BR8 + BR8: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 8 + 1 + write-only + + + BR9 + BR9: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 9 + 1 + write-only + + + BR10 + BR10: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 10 + 1 + write-only + + + BR11 + BR11: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 11 + 1 + write-only + + + BR12 + BR12: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 12 + 1 + write-only + + + BR13 + BR13: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 13 + 1 + write-only + + + BR14 + BR14: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 14 + 1 + write-only + + + BR15 + BR15: Port B reset bit y (y = 0..15) +These bits are write-only. A read to these bits returns the value 0x0000. +-0: No action on the corresponding ODx bit +-1: Resets the corresponding ODx bit + 15 + 1 + write-only + + + + + + + I2C1 + I2C1 + 0x41000000 + + 0x0 + 0x2C + registers + + + I2C1 + I2C1 interrupt + 3 + + + + I2C_CR1 + I2C_CR1 + I2C_CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable +- 0: Peripheral disable +- 1: Peripheral enable + 0 + 1 + read-write + + + TXIE + TX Interrupt enable +- 0: Transmit (TXIS) interrupt disabled +- 1: Transmit (TXIS) interrupt enabled + 1 + 1 + read-write + + + RXIE + RX Interrupt enable +- 0: Receive (RXNE) interrupt disabled +- 1: Receive (RXNE) interrupt enabled + 2 + 1 + read-write + + + ADDRIE + Address match Interrupt enable (slave only) +- 0: Address match (ADDR) interrupts disabled +- 1: Address match (ADDR) interrupts enabled + 3 + 1 + read-write + + + NACKIE + Not acknowledge received Interrupt enable +- 0: Not acknowledge (NACKF) received interrupts disabled +- 1: Not acknowledge (NACKF) received interrupts enabled + 4 + 1 + read-write + + + STOPIE + STOP detection Interrupt enable +- 0: Stop detection (STOPF) interrupt disabled +- 1: Stop detection (STOPF) interrupt enabled + 5 + 1 + read-write + + + TCIE + Transfer Complete interrupt enable +- 0: Transfer Complete interrupt disabled +- 1: Transfer Complete interrupt enabled + 6 + 1 + read-write + + + ERRIE + Error interrupts enable +- 0: Error detection interrupts disabled +- 1: Error detection interrupts enabled +Note: Any of these errors generate an interrupt: +Arbitration Loss (ARLO) +Bus Error detection (BERR) +Overrun/Underrun (OVR) +Timeout detection (TIMEOUT) +PEC error detection (PECERR) +Alert pin event detection (ALERT) + 7 + 1 + read-write + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter +will filter spikes with a length of up to DNF[3:0] * tI2CCLK +- 0000: Digital filter disabled +- 0001: Digital filter enabled and filtering capability up to 1 tI2CCLK +- 1111: digital filter enabled and filtering capability up to15 tI2CCLK + 8 + 4 + read-write + + + ANFOFF + Analog noise filter OFF +- 0: Analog noise filter enabled +- 1: Analog noise filter disabled + 12 + 1 + read-write + + + TXDMAEN + DMA transmission requests enable +- 0: DMA mode disabled for transmission +- 1: DMA mode enabled for transmission + 14 + 1 + read-write + + + RXDMAEN + DMA reception requests enable +- 0: DMA mode disabled for reception +- 1: DMA mode enabled for reception + 15 + 1 + read-only + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. +- 0: Slave byte control disabled +- 1: Slave byte control enabled + 16 + 1 + read-write + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +- 0: Clock stretching enabled +- 1: Clock stretching disabled +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + GCEN + General call enable + + 19 + 1 + read-write + + + B_0x0 + General call disabled. Address 0b00000000 is NACKed. + + 0x0 + + + B_0x1 + General call enabled. Address 0b00000000 is ACKed. + 0x1 + + + + + SMBHEN + SMBus Host address enable +- 0: Host address disabled. Address 0b0001000x is NACKed. +- 1: Host address enabled. Address 0b0001000x is ACKed. + 20 + 1 + read-write + + + SMBDEN + SMBus Device Default address enable +- 0: Device default address disabled. Address 0b1100001x is NACKed. +- 1: Device default address enabled. Address 0b1100001x is ACKed. + 21 + 1 + read-write + + + ALERTEN + SMBus alert enable +Device mode (SMBHEN=0): +- 0: Releases SMBA pin high and Alert Response Address Header disabled: 0001100x followed by NACK. +- 1: Drives SMBA pin low and Alert Response Address Header enables: 0001100x followed by ACK. +Host mode (SMBHEN=1): +- 0: SMBus Alert pin (SMBA) not supported. +- 1: SMBus Alert pin (SMBA) supported. + 22 + 1 + read-write + + + PECEN + PEC enable +- 0: PEC calculation disabled +- 1: PEC calculation enabled + 23 + 1 + read-write + + + + + I2C_CR2 + I2C_CR2 + I2C_CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + SADD + Slave address + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +- 0: Master requests a write transfer. +- 1: Master requests a read transfer. + 10 + 1 + read-write + + + ADD10 + Ten-bit addressing mode (master mode) +- 0: The master operates in 7-bit addressing mode, +- 1: The master operates in 10-bit addressing mode + 11 + 1 + read-write + + + HEAD10R + Ten bit (10-bit) address header only read direction (master receiver mode) +- 0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. +- 1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction. + 12 + 1 + read-write + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. +- 0: No Start generation. +- 1: Restart/Start generation: +If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. +Otherwise setting this bit will generate a START condition once the bus is free. + 13 + 1 + read-write + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. +In Master Mode: +- 0: No Stop generation. +- 1: Stop generation after current byte transfer. + 14 + 1 + read-write + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP +condition or an Address matched is received, or when PE=0. +- 0: an ACK is sent after current received byte. +- 1: a NACK is sent after current received byte. + 15 + 1 + read-write + + + NBYTES + Number of bytes +The number of bytes to be transmitted/received is programmed there. This field is dont care in +slave mode with SBC=0. + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. +- 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). +- 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). +TCR flag is set when NBYTES data are transferred, stretching SCL low. + 24 + 1 + read-write + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +- 0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. +- 1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are +transferred. + 25 + 1 + read-write + + + PECBYTE + Packet error checking byte +This bit is set by software, and cleared by hardware when the PEC is transferred, or when a +STOP condition or an Address matched is received, also when PE=0. +- 0: No PEC transfer. +- 1: PEC transmission/reception is requested + 26 + 1 + read-write + + + + + I2C_OAR1 + I2C_OAR1 + I2C_OAR1 register + 0x08 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + read-write + + + OA1MODE + Own Address 1 10-bit mode +- 0: Own address 1 is a 7-bit address. +- 1: Own address 1 is a 10-bit address. + 10 + 1 + read-write + + + OA1EN + Own Address 1 enable +- 0: Own address 1 disabled. The received slave address OA1 is NACKed. +- 1: Own address 1 enabled. The received slave address OA1 is ACKed. + 15 + 1 + read-write + + + + + I2C_OAR2 + I2C_OAR2 + I2C_OAR2 register + 0x0C + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address +bits 7:1 of address +Note: These bits can be written only when OA2EN=0. + 1 + 7 + read-write + + + OA2MSK + Own Address 2 masks +- 000: No mask +- 001: OA2[1] is masked and dont care. Only OA2[7:2] are compared. +- 010: OA2[2:1] are masked and dont care. Only OA2[7:3] are compared. +- 011: OA2[3:1] are masked and dont care. Only OA2[7:4] are compared. +- 100: OA2[4:1] are masked and dont care. Only OA2[7:5] are compared. +- 101: OA2[5:1] are masked and dont care. Only OA2[7:6] are compared. +- 110: OA2[6:1] are masked and dont care. Only OA2[7] is compared. +- 111: OA2[7:1] are masked and dont care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 8 + 3 + read-write + + + OA2EN + Own Address 2 enable + + 15 + 1 + read-write + + + B_0x0 + Own address 2 disabled. The received slave address OA2 is NACKed. + + 0x0 + + + B_0x1 + Own address 2 enabled. The received slave address OA2 is ACKed. + 0x1 + + + + + + + I2C_TIMING + I2C_TIMING + I2C_TIMING register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +tSCLL = (SCLL+1) x tPRESC +Note: SCLL is also used to generate tBUF and tSU:STA timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +tSCLH = (SCLH+1) x tPRESC +Note: SCLH is also used to generate tSU:STO and tHD:STA timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay tSDADEL between SCL falling edge SDA edge in +transmission mode. +tSDADEL= SDADEL x tPRESC +Note: SDADEL is used to generate tHD:DAT timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge in +transmission mode. +tSCLDEL = (SCLDEL+1) x tPRESC +Note: tSCLDEL is used to generate tSU:DAT timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler +This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data +setup and hold counters and for SCL high and low level +counters +tPRESC = (PRESC+1) x tI2CCLK + 28 + 4 + read-write + + + + + I2C_TIMEOUT + I2C_TIMEOUT + I2C_TIMEOUT register + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus Timeout A +This field is used to configure: +The SCL low timeout condition tTIMEOUT when TIDLE=0 +tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK +The bus idle condition (both SCL and SDA high) when TIDLE=1 +tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK +Note: These bits can be written only when TIMOUTEN=0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +- 0: TIMEOUTA is used to detect SCL low timeout +- 1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) +Note: This bit can be written only when TIMOUTEN=0. + 12 + 1 + read-write + + + TIMEOUTEN + Clock timeout enable +- 0: SCL timeout detection is disabled +- 1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or +high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1). + 15 + 1 + read-write + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected +In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected +tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK +Note: These bits can be written only when TEXTEN=0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable +- 0: Extended clock timeout detection is disabled +- 1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more +than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1). + 31 + 1 + read-write + + + + + I2C_ISR + I2C_ISR + I2C_ISR register + 0x18 + 0x20 + read-write + 0x00000000 + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE=0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). +Note: This bit is cleared by hardware when PE=0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE=0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE=0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE=0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: +either as a master, provided that the STOP condition is generated by the peripheral. +or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE=0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE=0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE=0. +This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE=0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE=0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE=0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception +This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 11 + 1 + read-only + + + TIMEOUT + Timeout or tLOW detection flag +This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 12 + 1 + read-only + + + ALERT + SMBus alert +This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 13 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) +This flag is updated when an address match event occurs (ADDR=1). +- 0: Write transfer, slave enters receiver mode. +- 1: Read transfer, slave enters transmitter mode. + 16 + 1 + read-only + + + ADDCODE + Address match code (Slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C_ICR register + 0x1C + 0x20 + read-write + 0x00000000 + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears +the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the ACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + Stop detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration Lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + PECCF + PEC Error flag clear +Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear +Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 12 + 1 + write-only + + + ALERTCF + Alert flag clear +Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 13 + 1 + write-only + + + + + I2C_PEC + I2C_PEC + I2C_PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE=0. + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C_RXDR register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + Eight bit (8-bit) receive data +Data byte received from the I2C bus. + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C_TXDR register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + Eight bits (8-bit) transmit data +Data byte to be transmitted to the I2C bus. +Note: These bits can be written only when TXE=1. + 0 + 8 + read-write + + + + + + + I2C2 + I2C2 + 0x41001000 + + 0x0 + 0x2C + registers + + + I2C2 + I2C2 interrupt + 4 + + + + I2C_CR1 + I2C_CR1 + I2C_CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable +- 0: Peripheral disable +- 1: Peripheral enable + 0 + 1 + read-write + + + TXIE + TX Interrupt enable +- 0: Transmit (TXIS) interrupt disabled +- 1: Transmit (TXIS) interrupt enabled + 1 + 1 + read-write + + + RXIE + RX Interrupt enable +- 0: Receive (RXNE) interrupt disabled +- 1: Receive (RXNE) interrupt enabled + 2 + 1 + read-write + + + ADDRIE + Address match Interrupt enable (slave only) +- 0: Address match (ADDR) interrupts disabled +- 1: Address match (ADDR) interrupts enabled + 3 + 1 + read-write + + + NACKIE + Not acknowledge received Interrupt enable +- 0: Not acknowledge (NACKF) received interrupts disabled +- 1: Not acknowledge (NACKF) received interrupts enabled + 4 + 1 + read-write + + + STOPIE + STOP detection Interrupt enable +- 0: Stop detection (STOPF) interrupt disabled +- 1: Stop detection (STOPF) interrupt enabled + 5 + 1 + read-write + + + TCIE + Transfer Complete interrupt enable +- 0: Transfer Complete interrupt disabled +- 1: Transfer Complete interrupt enabled + 6 + 1 + read-write + + + ERRIE + Error interrupts enable +- 0: Error detection interrupts disabled +- 1: Error detection interrupts enabled +Note: Any of these errors generate an interrupt: +Arbitration Loss (ARLO) +Bus Error detection (BERR) +Overrun/Underrun (OVR) +Timeout detection (TIMEOUT) +PEC error detection (PECERR) +Alert pin event detection (ALERT) + 7 + 1 + read-write + + + DNF + Digital noise filter +These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter +will filter spikes with a length of up to DNF[3:0] * tI2CCLK +- 0000: Digital filter disabled +- 0001: Digital filter enabled and filtering capability up to 1 tI2CCLK +- 1111: digital filter enabled and filtering capability up to15 tI2CCLK + 8 + 4 + read-write + + + ANFOFF + Analog noise filter OFF +- 0: Analog noise filter enabled +- 1: Analog noise filter disabled + 12 + 1 + read-write + + + TXDMAEN + DMA transmission requests enable +- 0: DMA mode disabled for transmission +- 1: DMA mode enabled for transmission + 14 + 1 + read-write + + + RXDMAEN + DMA reception requests enable +- 0: DMA mode disabled for reception +- 1: DMA mode enabled for reception + 15 + 1 + read-only + + + SBC + Slave byte control +This bit is used to enable hardware byte control in slave mode. +- 0: Slave byte control disabled +- 1: Slave byte control enabled + 16 + 1 + read-write + + + NOSTRETCH + Clock stretching disable +This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. +- 0: Clock stretching enabled +- 1: Clock stretching disabled +Note: This bit can only be programmed when the I2C is disabled (PE = 0). + 17 + 1 + read-write + + + GCEN + General call enable +- 0: General call disabled. Address 0b00000000 is NACKed. +- 1: General call enabled. Address 0b00000000 is ACKed. + 19 + 1 + read-write + + + SMBHEN + SMBus Host address enable +- 0: Host address disabled. Address 0b0001000x is NACKed. +- 1: Host address enabled. Address 0b0001000x is ACKed. + 20 + 1 + read-write + + + SMBDEN + SMBus Device Default address enable +- 0: Device default address disabled. Address 0b1100001x is NACKed. +- 1: Device default address enabled. Address 0b1100001x is ACKed. + 21 + 1 + read-write + + + ALERTEN + SMBus alert enable +Device mode (SMBHEN=0): +- 0: Releases SMBA pin high and Alert Response Address Header disabled: 0001100x followed by NACK. +- 1: Drives SMBA pin low and Alert Response Address Header enables: 0001100x followed by ACK. +Host mode (SMBHEN=1): +- 0: SMBus Alert pin (SMBA) not supported. +- 1: SMBus Alert pin (SMBA) supported. + 22 + 1 + read-write + + + PECEN + PEC enable +- 0: PEC calculation disabled +- 1: PEC calculation enabled + 23 + 1 + read-write + + + + + I2C_CR2 + I2C_CR2 + I2C_CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + SADD + Slave address + 0 + 10 + read-write + + + RD_WRN + Transfer direction (master mode) +- 0: Master requests a write transfer. +- 1: Master requests a read transfer. + 10 + 1 + read-write + + + ADD10 + Ten-bit addressing mode (master mode) +- 0: The master operates in 7-bit addressing mode, +- 1: The master operates in 10-bit addressing mode + 11 + 1 + read-write + + + HEAD10R + Ten bit (10-bit) address header only read direction (master receiver mode) +- 0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction. +- 1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction. + 12 + 1 + read-write + + + START + Start generation +This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. +- 0: No Start generation. +- 1: Restart/Start generation: +If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. +Otherwise setting this bit will generate a START condition once the bus is free. + 13 + 1 + read-write + + + STOP + Stop generation (master mode) +The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. +In Master Mode: +- 0: No Stop generation. +- 1: Stop generation after current byte transfer. + 14 + 1 + read-write + + + NACK + NACK generation (slave mode) +The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP +condition or an Address matched is received, or when PE=0. +- 0: an ACK is sent after current received byte. +- 1: a NACK is sent after current received byte. + 15 + 1 + read-write + + + NBYTES + Number of bytes +The number of bytes to be transmitted/received is programmed there. This field is dont care in +slave mode with SBC=0. + 16 + 8 + read-write + + + RELOAD + NBYTES reload mode +This bit is set and cleared by software. +- 0: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow). +- 1: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded). +TCR flag is set when NBYTES data are transferred, stretching SCL low. + 24 + 1 + read-write + + + AUTOEND + Automatic end mode (master mode) +This bit is set and cleared by software. +- 0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. +- 1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are +transferred. + 25 + 1 + read-write + + + PECBYTE + Packet error checking byte +This bit is set by software, and cleared by hardware when the PEC is transferred, or when a +STOP condition or an Address matched is received, also when PE=0. +- 0: No PEC transfer. +- 1: PEC transmission/reception is requested + 26 + 1 + read-write + + + + + I2C_OAR1 + I2C_OAR1 + I2C_OAR1 register + 0x08 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + read-write + + + OA1MODE + Own Address 1 10-bit mode +- 0: Own address 1 is a 7-bit address. +- 1: Own address 1 is a 10-bit address. + 10 + 1 + read-write + + + OA1EN + Own Address 1 enable +- 0: Own address 1 disabled. The received slave address OA1 is NACKed. +- 1: Own address 1 enabled. The received slave address OA1 is ACKed. + 15 + 1 + read-write + + + + + I2C_OAR2 + I2C_OAR2 + I2C_OAR2 register + 0x0C + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address +bits 7:1 of address +Note: These bits can be written only when OA2EN=0. + 1 + 7 + read-write + + + OA2MSK + Own Address 2 masks +- 000: No mask +- 001: OA2[1] is masked and dont care. Only OA2[7:2] are compared. +- 010: OA2[2:1] are masked and dont care. Only OA2[7:3] are compared. +- 011: OA2[3:1] are masked and dont care. Only OA2[7:4] are compared. +- 100: OA2[4:1] are masked and dont care. Only OA2[7:5] are compared. +- 101: OA2[5:1] are masked and dont care. Only OA2[7:6] are compared. +- 110: OA2[6:1] are masked and dont care. Only OA2[7] is compared. +- 111: OA2[7:1] are masked and dont care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged. + 8 + 3 + read-write + + + OA2EN + Own Address 2 enable +- 0: Own address 2 disabled. The received slave address OA2 is NACKed. +- 1: Own address 2 enabled. The received slave address OA2 is ACKed. + 15 + 1 + read-write + + + + + I2C_TIMING + I2C_TIMING + I2C_TIMING register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) +This field is used to generate the SCL low period in master mode. +tSCLL = (SCLL+1) x tPRESC +Note: SCLL is also used to generate tBUF and tSU:STA timings. + 0 + 8 + read-write + + + SCLH + SCL high period (master mode) +This field is used to generate the SCL high period in master mode. +tSCLH = (SCLH+1) x tPRESC +Note: SCLH is also used to generate tSU:STO and tHD:STA timing. + 8 + 8 + read-write + + + SDADEL + Data hold time +This field is used to generate the delay tSDADEL between SCL falling edge SDA edge in +transmission mode. +tSDADEL= SDADEL x tPRESC +Note: SDADEL is used to generate tHD:DAT timing. + 16 + 4 + read-write + + + SCLDEL + Data setup time +This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge in +transmission mode. +tSCLDEL = (SCLDEL+1) x tPRESC +Note: tSCLDEL is used to generate tSU:DAT timing. + 20 + 4 + read-write + + + PRESC + Timing prescaler +This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data +setup and hold counters and for SCL high and low level +counters +tPRESC = (PRESC+1) x tI2CCLK + 28 + 4 + read-write + + + + + I2C_TIMEOUT + I2C_TIMEOUT + I2C_TIMEOUT register + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus Timeout A +This field is used to configure: +The SCL low timeout condition tTIMEOUT when TIDLE=0 +tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK +The bus idle condition (both SCL and SDA high) when TIDLE=1 +tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK +Note: These bits can be written only when TIMOUTEN=0. + 0 + 12 + read-write + + + TIDLE + Idle clock timeout detection +- 0: TIMEOUTA is used to detect SCL low timeout +- 1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition) +Note: This bit can be written only when TIMOUTEN=0. + 12 + 1 + read-write + + + TIMEOUTEN + Clock timeout enable +- 0: SCL timeout detection is disabled +- 1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or +high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1). + 15 + 1 + read-write + + + TIMEOUTB + Bus timeout B +This field is used to configure the cumulative clock extension timeout: +In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected +In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected +tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK +Note: These bits can be written only when TEXTEN=0. + 16 + 12 + read-write + + + TEXTEN + Extended clock timeout enable +- 0: Extended clock timeout detection is disabled +- 1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more +than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1). + 31 + 1 + read-write + + + + + I2C_ISR + I2C_ISR + I2C_ISR register + 0x18 + 0x20 + read-write + 0x00000000 + + + TXE + Transmit data register empty (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. +Note: This bit is set by hardware when PE=0. + 0 + 1 + read-write + + + TXIS + Transmit interrupt status (transmitters) +This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. +This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). +Note: This bit is cleared by hardware when PE=0. + 1 + 1 + read-write + + + RXNE + Receive data register not empty (receivers) +This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. +Note: This bit is cleared by hardware when PE=0. + 2 + 1 + read-only + + + ADDR + Address matched (slave mode) +This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. +Note: This bit is cleared by hardware when PE=0. + 3 + 1 + read-only + + + NACKF + Not Acknowledge received flag +This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. +Note: This bit is cleared by hardware when PE=0. + 4 + 1 + read-only + + + STOPF + Stop detection flag +This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: +either as a master, provided that the STOP condition is generated by the peripheral. +or as a slave, provided that the peripheral has been addressed previously during this transfer. +It is cleared by software by setting the STOPCF bit. +Note: This bit is cleared by hardware when PE=0. + 5 + 1 + read-only + + + TC + Transfer Complete (master mode) +This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. +Note: This bit is cleared by hardware when PE=0. + 6 + 1 + read-only + + + TCR + Transfer Complete Reload +This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. +Note: This bit is cleared by hardware when PE=0. +This flag is only for master mode, or for slave mode when the SBC bit is set. + 7 + 1 + read-only + + + BERR + Bus error +This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. +Note: This bit is cleared by hardware when PE=0. + 8 + 1 + read-only + + + ARLO + Arbitration lost +This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. +Note: This bit is cleared by hardware when PE=0. + 9 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) +This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. +Note: This bit is cleared by hardware when PE=0. + 10 + 1 + read-only + + + PECERR + PEC Error in reception +This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 11 + 1 + read-only + + + TIMEOUT + Timeout or tLOW detection flag +This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 12 + 1 + read-only + + + ALERT + SMBus alert +This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. +Note: This bit is cleared by hardware when PE=0. +If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 13 + 1 + read-only + + + BUSY + Bus busy +This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0. + 15 + 1 + read-only + + + DIR + Transfer direction (Slave mode) +This flag is updated when an address match event occurs (ADDR=1). +- 0: Write transfer, slave enters receiver mode. +- 1: Read transfer, slave enters transmitter mode. + 16 + 1 + read-only + + + ADDCODE + Address match code (Slave mode) +These bits are updated with the received address when an address match event occurs (ADDR = 1). +In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address. + 17 + 7 + read-only + + + + + I2C_ICR + I2C_ICR + I2C_ICR register + 0x1C + 0x20 + read-write + 0x00000000 + + + ADDRCF + Address matched flag clear +Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears +the START bit in the I2C_CR2 register. + 3 + 1 + write-only + + + NACKCF + Not Acknowledge flag clear +Writing 1 to this bit clears the ACKF flag in I2C_ISR register. + 4 + 1 + write-only + + + STOPCF + Stop detection flag clear +Writing 1 to this bit clears the STOPF flag in the I2C_ISR register. + 5 + 1 + write-only + + + BERRCF + Bus error flag clear +Writing 1 to this bit clears the BERRF flag in the I2C_ISR register. + 8 + 1 + write-only + + + ARLOCF + Arbitration Lost flag clear +Writing 1 to this bit clears the ARLO flag in the I2C_ISR register. + 9 + 1 + write-only + + + OVRCF + Overrun/Underrun flag clear +Writing 1 to this bit clears the OVR flag in the I2C_ISR register. + 10 + 1 + write-only + + + PECCF + PEC Error flag clear +Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 11 + 1 + write-only + + + TIMOUTCF + Timeout detection flag clear +Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 12 + 1 + write-only + + + ALERTCF + Alert flag clear +Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. +Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. +Please refer to Section 22.3: I2C implementation. + 13 + 1 + write-only + + + + + I2C_PEC + I2C_PEC + I2C_PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register +This field contains the internal PEC when PECEN=1. +The PEC is cleared by hardware when PE=0. + 0 + 8 + read-only + + + + + I2C_RXDR + I2C_RXDR + I2C_RXDR register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + Eight bit (8-bit) receive data +Data byte received from the I2C bus. + 0 + 8 + read-only + + + + + I2C_TXDR + I2C_TXDR + I2C_TXDR register + 0x28 + 0x20 + read-write + + + TXDATA + Eight bits (8-bit) transmit data +Data byte to be transmitted to the I2C bus. +Note: These bits can be written only when TXE=1. + 0 + 8 + read-write + + + + + + + IWDG + IWDG + 0x40003000 + + 0x0 + 0x14 + registers + + + + IWDG_KR + IWDG_KR + IWDG_KR register + 0x00 + 0x20 + read-write + 0x00000000 + + + KEY + Key value. +Software can only write these bits. Reading returns the reset value. +These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. +Writing the key value 0x5555 to enables access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers. +Writing the key value CCCCh starts the watchdog + 0 + 16 + write-only + + + + + IWDG_PR + IWDG_PR + IWDG_PR register + 0x04 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider. +Set and reset by software. +These bits are write access protected. They are written by software to select the prescaler divider feeding the counter clock. +PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. +000: divider/4 +001: divider/8 +010: divider/16 +011: divider/32 +100: divider/64 +101: divider/128 +110: divider/256 +111: divider/256 + 0 + 3 + read-write + + + + + IWDG_RLR + IWDG_RLR + IWDG_RLR register + 0x08 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value. +Set and reset by software. +These bits are write access protected. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. +The timeout period is a function of this value and the clock prescaler. +The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + IWDG_SR + IWDG_SR + IWDG_SR register + 0x0C + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value update. +Read only bit. +This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is +reset by hardware when the prescaler update operation is completed in the VDD voltage +domain (takes up to 5 RC 40 kHz cycles). +Prescaler value can be updated only when PVU bit is reset + 0 + 1 + read-only + + + RVU + Watchdog counter reload value update. +Read only bit. +This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Reload value can be updated only when RVU bit is reset + 1 + 1 + read-only + + + WVU + Watchdog counter window value update. +Read only bit. +This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). +Window value can be updated only when WVU bit is reset. +This bit is generated only if generic 'window' = 1 + 2 + 1 + read-only + + + + + IWDG_WINR + IWDG_WINR + IWDG_WINR register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value. +Set and reset by software. +These bits are write access protected. These bits contain the high limit of the window value to be compared to the downcounter. +To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 +The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. + 0 + 12 + read-write + + + + + + + LCD + LCD + 0x40007000 + + 0x0 + 0x54 + registers + + + LCD + LCD interrupt + 27 + + + + LCD_CR + LCD_CR + LCD_CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + LCDEN + LCD controller enable + + 0 + 1 + read-write + + + VSEL + Voltage source selection + + 1 + 1 + read-write + + + DUTY + Duty selection + + 2 + 3 + read-write + + + BIAS + Bias selector + + 5 + 2 + read-write + + + BUFEN + Voltage output buffer enable + + 8 + 1 + read-write + + + + + LCD_FCR + LCD_FCR + LCD_FCR register + 0x04 + 0x20 + read-write + 0x00000000 + + + HD + High drive enable + + 0 + 1 + read-write + + + SOFIE + Start of frame interrupt enable + + 1 + 1 + read-write + + + UDDIE + Update display done interrupt enable + + 3 + 1 + read-write + + + PON + Pulse ON duration + + 4 + 3 + read-write + + + DEAD + Dead time duration + + 7 + 3 + read-write + + + CC + Contrast control + + 10 + 3 + read-write + + + BLINKF + Blink frequency selection + + 13 + 3 + read-write + + + B_0x0 + fLCD/8 + 0x0 + + + + + BLINK + Blink mode selection + + 16 + 2 + read-write + + + DIV + DIV clock divider + + 18 + 4 + read-write + + + PS + PS 16-bit prescaler + + 22 + 4 + read-write + + + + + LCD_SR + LCD_SR + LCD_SR register + 0x08 + 0x20 + read-only + 0x00000020 + + + ENS + LCD enabled status + + 0 + 1 + read-only + + + SOF + Start of frame flag + + 1 + 1 + read-only + + + UDR + Update display request + + 2 + 1 + read-only + + + UDD + Update Display Done + + 3 + 1 + read-only + + + RDY + Ready flag + + 4 + 1 + read-only + + + FCRSF + LCD Frame Control Register Synchronization flag + + 5 + 1 + read-only + + + + + LCD_CLR + LCD_CLR + LCD_CLR register + 0x0C + 0x20 + read-write + 0x00000000 + + + SOFC + Start of frame flag clear + + 1 + 1 + write-only + + + UDDC + Update display done clear + + 3 + 1 + write-only + + + + + LCD_RAM_COM0 + LCD_RAM_COM0 + LCD_RAM_COMx register + 0x14 + 0x20 + read-write + 0x00000000 + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + + + LCD_RAM_COM1 + LCD_RAM_COM1 + LCD_RAM_COMx register + 0x1C + 0x20 + read-write + 0x00000000 + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + + + LCD_RAM_COM2 + LCD_RAM_COM2 + LCD_RAM_COMx register + 0x24 + 0x20 + read-write + 0x00000000 + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + + + LCD_RAM_COM3 + LCD_RAM_COM3 + LCD_RAM_COMx register + 0x2C + 0x20 + read-write + 0x00000000 + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + + + LCD_RAM_COM4 + LCD_RAM_COM4 + LCD_RAM_COMx register + 0x34 + 0x20 + read-write + 0x00000000 + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + + + LCD_RAM_COM5 + LCD_RAM_COM5 + LCD_RAM_COMx register + 0x3C + 0x20 + read-write + 0x00000000 + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + + + LCD_RAM_COM6 + LCD_RAM_COM6 + LCD_RAM_COMx register + 0x44 + 0x20 + read-write + 0x00000000 + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + + + LCD_RAM_COM7 + LCD_RAM_COM7 + LCD_RAM_COMx register + 0x4C + 0x20 + read-write + 0x00000000 + + + SEGMENT_DATA + Each bit corresponds to one pixel of the LCD display. + 0 + 16 + read-write + + + + + + + LPUART + LPUART + 0x41005000 + + 0x0 + 0x30 + registers + + + LPUART + LPUART interrupt + 9 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + UE + UE: USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and +current operations are discarded. The configuration of the USART is kept, but all the status +flags, in the USART_ISR are reset. This bit is set and cleared by software. +-0: USART prescaler and outputs disabled, low power mode +-1: USART enabled + 0 + 1 + read-write + + + UESM + UESM: LPUART enable in Stop mode +When this bit is cleared, the LPUART is not able to wake up the MCU from Stop mode. +When this bit is set, the LPUART is able to wake up the MCU from Stop mode, provided that +the LPUART clock selection is LSE in the RCC. +This bit is set and cleared by software. +-0: LPUART not able to wake up the MCU from Stop mode. +-1: LPUART able to wake up the MCU from Stop mode. When this function is active, the +clock source for the LPUART must be LSE (see RCC chapter) + 1 + 1 + read-write + + + RE + RE: Receiver enable +This bit enables the receiver. It is set and cleared by software. +-0: Receiver is disabled +-1: Receiver is enabled and begins searching for a start bit + 2 + 1 + read-write + + + TE + TE: Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +-0: Transmitter is disabled +-1: Transmitter is enabled + 3 + 1 + read-write + + + IDLEIE + IDLEIE: IDLE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register + 4 + 1 + read-write + + + RXNEIE_RXFNEIE + RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the +USART_ISR register + 5 + 1 + read-write + + + TCIE + TCIE: Transmission complete interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TC=1 in the USART_ISR register + 6 + 1 + read-write + + + TXEIE_TXFNFIE + TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register + 7 + 1 + read-write + + + PEIE + PEIE: PE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever PE=1 in the USART_ISR register + 8 + 1 + read-write + + + PS + PS: Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE +bit set). It is set and cleared by software. The parity will be selected after the current byte. +-0: Even parity +-1: Odd parity +This bit field can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + PCE + PCE: Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity +control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit +if M=0) and parity is checked on the received data. This bit is set and cleared by software. +Once it is set, PCE is active after the current byte (in reception and in transmission). +-0: Parity control disabled +-1: Parity control enabled +This bit field can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + WAKE + WAKE: Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by +software. +-0: Idle line +-1: Address mark +This bit field can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + M_0 + M0: Word length +This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit +-28 (M1)description. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + MME: Mute mode enable +This bit activates the mute mode function of the USART. When set, the USART can switch +between the active and mute modes, as defined by the WAKE bit. It is set and cleared by +software. +-0: Receiver in active mode permanently +-1: Receiver can switch between mute mode and active mode + 13 + 1 + read-write + + + CMIE + CMIE: Character match interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 14 + 1 + read-write + + + DEDT + DEDT[4:0]: Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted +message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample +time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only +when the DEDT and DEAT times have both elapsed. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + DEAT[4:0]: Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and +the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, +depending on the oversampling rate). +This bit field can only be written when the USART is disabled (UE=0). + 21 + 5 + read-write + + + M_1 + Word length +This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0).s + 28 + 1 + read-write + + + FIFOEN + FIFOEN :FIFO mode enable +This bit is set and cleared by software. +-0: FIFO mode is disabled. +-1: FIFO mode is enabled. + 29 + 1 + read-write + + + TXFEIE + TXFEIE :TXFIFO empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFE=1 in the USART_ISR register + 30 + 1 + read-write + + + RXFFIE + RXFFIE :RXFIFO Full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when RXFF=1 in the USART_ISR register + 31 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + ADDM7 + ADDM7:7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +-0: 4-bit address detection +-1: 7-bit address detection (in 8-bit data mode) +This bit can only be written when the USART is disabled (UE=0) + 4 + 1 + read-write + + + STOP + STOP[1:0]: STOP bits +These bits are used for programming the stop bits. +-00: 1 stop bit +-01: 0.5 stop bit. +-10: 2 stop bits +-11: 1.5 stop bits +This bit field can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + SWAP + SWAP: Swap TX/RX pins +This bit is set and cleared by software. +-0: TX/RX pins are used as defined in standard pinout +-1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired +connection to another UART. +This bit field can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + RXINV + RXINV: RX pin active level inversion +This bit is set and cleared by software. +-0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the RX line. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + TXINV + TXINV: TX pin active level inversion +This bit is set and cleared by software. +-0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the TX line. +This bit field can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + DATAINV + DATAINV: Binary data inversion +This bit is set and cleared by software. +-0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) +-1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The +parity bit is also inverted. +This bit field can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + MSBFIRST + MSBFIRST: Most significant bit first +This bit is set and cleared by software. +-0: data is transmitted/received with data bit 0 first, following the start bit. +-1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. +This bit field can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + ADD + ADD[7:0]: Address of the USART node +This bit-field gives the address of the USART node or a character code to be recognized. +This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- +bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. +It may also be used for character detection during normal reception, Mute mode inactive (for +example, end of block detection in ModBus protocol). In this case, the whole received character (8- +bit) is compared to the ADD[7:0] value and CMF flag is set on match. +This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled +(UE=0) + 24 + 8 + read-write + + + + + CR3 + CR3 + CR3 register + 0x08 + 0x20 + read-write + 0x00000000 + + + EIE + EIE: Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing +error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR += 1 in the USART_ISR register). +-0: Interrupt is inhibited +-1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) +in the USART_ISR register. + 0 + 1 + read-write + + + HDSEL + HDSEL: Half-duplex selection +Selection of Single-wire Half-duplex mode +-0: Half duplex mode is not selected +-1: Half duplex mode is selected +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + DMAR + DMAR: DMA enable receiver +This bit is set/reset by software +-1: DMA mode is enabled for reception +-0: DMA mode is disabled for reception + 6 + 1 + read-write + + + DMAT + DMAT: DMA enable transmitter +This bit is set/reset by software +-1: DMA mode is enabled for transmission +-0: DMA mode is disabled for transmission + 7 + 1 + read-write + + + RTSE + RTSE: RTS enable +-0: RTS hardware flow control disabled +-1: RTS output enabled, data is only requested when there is space in the receive buffer. The +transmission of data is expected to cease after the current character has been transmitted. +The nRTS output is asserted (pulled to 0) when data can be received. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CTSE + CTSE: CTS enable +-0: CTS hardware flow control disabled +-1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). +If the nCTS input is deasserted while data is being transmitted, then the transmission is +completed before stopping. If data is written into the data register while nCTS is asserted, +the transmission is postponed until nCTS is asserted. +This bit can only be written when the USART is disabled (UE=0) + 9 + 1 + read-write + + + CTSIE + CTSIE: CTS interrupt enable +-0: Interrupt is inhibited +-1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 10 + 1 + read-write + + + OVRDIS + OVRDIS: Overrun Disable +This bit is used to disable the receive overrun detection. +-0: Overrun Error Flag, ORE, is set when received data is not read before receiving new +data. +-1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set +the ORE flag is not set and the new received data overwrites the previous content of the +USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data +will be written directly in USARTx_RDR register. Even when FIFO management is enabled, +the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + DDRE + DDRE: DMA Disable on Reception Error +-0: DMA is not disabled in case of reception error. The corresponding error flag is set but +RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not +asserted, so the erroneous data is not transferred (no DMA request), but next correct +received data will be transferred. (used for Smartcard mode) +-1: DMA is disabled following a reception error. The corresponding error flag is set, as well +as RXNE. The DMA request is masked until the error flag is cleared. This means that the +software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case +FIFO mode is enabled) before clearing the error flag. +This bit can only be written when the USART is disabled (UE=0). + 13 + 1 + read-write + + + DEM + DEM: Driver enable mode +This bit allows the user to activate the external transceiver control, through the DE signal. +-0: DE function is disabled. +-1: DE function is enabled. The DE signal is output on the RTS pin. +This bit can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + DEP + DEP: Driver enable polarity selection +-0: DE signal is active high. +-1: DE signal is active low. +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + WUS + WUS[1:0]: Wakeup from Stop mode interrupt flag selection +This bit-field specify the event which activates the WUF (Wakeup from Stop mode flag). +-00: WUF active on address match (as defined by ADD[7:0] and ADDM7) +-01:Reserved. +-10: WUF active on Start bit detection +-11: WUF active on RXNE. +This bit field can only be written when the LPUART is disabled (UE=0). + 20 + 2 + read-write + + + WUFIE + WUFIE: Wakeup from Stop mode interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An LPUART interrupt is generated whenever WUF=1 in the LPUART_ISR register + 22 + 1 + read-write + + + TXFTIE + TXFTIE: TXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in +TXFTCFG. + 23 + 1 + read-write + + + RXFTCFG + RXFTCFG: Receive FIFO threshold configuration +-000:Receive FIFO reaches 1/8 of its depth. +-001:Receive FIFO reaches 1/4 of its depth. +-010:Receive FIFO reaches 1/2 of its depth. +-011:Receive FIFO reaches 3/4 of its depth. +-100:Receive FIFO reaches 7/8 of its depth. +-101:Receive FIFO becomes full. +Remaining combinations: Reserved. + 25 + 3 + read-write + + + RXFTIE + RXFTIE: RXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when Receive FIFO reaches the threshold +programmed in RXFTCFG. + 28 + 1 + read-write + + + TXFTCFG + TXFTCFG: TXFIFO threshold configuration +-000:TXFIFO reaches 1/8 of its depth. +-001:TXFIFO reaches 1/4 of its depth. +-010:TXFIFO reaches 1/2 of its depth. +-011:TXFIFO reaches 3/4 of its depth. +-100:TXFIFO reaches 7/8 of its depth. +-101:TXFIFO becomes empty. +Remaining combinations: Reserved. + 29 + 3 + read-write + + + + + BRR + BRR + BRR register + 0x0C + 0x20 + read-write + 0x00000000 + + + BRR + BRR[19:0] + 0 + 20 + read-write + + + + + RQR + RQR + RQR register + 0x18 + 0x20 + read-write + 0x00000000 + + + SBKRQ + SBKRQ: Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as +the transmit machine is available. + 1 + 1 + write-only + + + MMRQ + MMRQ: Mute mode request +Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + RXFRQ: Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This allows to discard the received data without reading them, and avoid an overrun +condition. + 3 + 1 + write-only + + + TXFRQ + TXFRQ: Transmit data flush request +When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. +This allows to discard the transmit data. This bit must be used only in Smartcard mode, +when data has not been sent due to errors (NACK) and the FE flag is active in the +USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved +and forced by hardware to 0 +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE +(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is +supported in both UART and Smartcard modes. + 4 + 1 + write-only + + + + + ISR + ISR + ISR register + 0x1C + 0x20 + read-only + 0x000000C0 + + + PE + PE: Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by +software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +-0: No parity error +-1: Parity error + 0 + 1 + read-only + + + FE + FE: Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character +is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +In Smartcard mode, in transmission, this bit is set when the maximum number of transmit +attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR1 register. +-0: No Framing error is detected +-1: Framing error or break character is detected + 1 + 1 + read-only + + + NF + NF: START bit Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by +software, writing 1 to the NFCF bit in the USART_ICR register. +-0: No noise is detected +-1: Noise is detected + 2 + 1 + read-only + + + ORE + ORE: Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case +FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the +USARTx_ICR register. +An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. +-0: No overrun error +-1: Overrun error is detected + 3 + 1 + read-only + + + IDLE + IDLE: Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if +IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in +the USART_ICR register. +-0: No Idle line is detected +-1: Idle line is detected + 4 + 1 + read-only + + + RXNE_RXFNE + RXNE/RXFNE:Read data register not empty/RXFIFO not empty +RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been +transferred +to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from +the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It +is cleared when the RXFIFO is empty. +The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR +register. +An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. +-0: Data is not received +-1: Received data is ready to be read. + 5 + 1 + read-only + + + TC + TC: Transmission complete +This bit indicates when the last data written in the USART_TDR has been transmitted out of +the shift register. +It is set by hardware if the transmission of a frame containing data is complete and if +TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is +cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the +USART_TDR register. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +-0: Transmission is not complete +-1: Transmission is complete + 6 + 1 + read-only + + + TXE_TXFNF + TXE/TXFNF: Transmit data register empty/TXFIFO not full +When FIFO mode is disabled, TXE is set by hardware when the content of the +USARTx_TDR register has been transferred into the shift register. It is cleared by a write to +the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the +USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of +transmission failure). +When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so +data can be written in the USART_TDR. Every write in the USART_TDR places the data in +the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag +is cleared indicating that data can not be written into the USART_TDR. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After +sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to +writing in TXFIFO. (TXFNF and TXFE will be set at the same time). +An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. +-0: Data register is full/Transmit FIFO is full. +-1: Data register/Transmit FIFO is not full + 7 + 1 + read-only + + + CTSIF + CTSIF: CTS interrupt flag +This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared +by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +-0: No change occurred on the nCTS status line +-1: A change occurred on the nCTS status line + 9 + 1 + read-only + + + CTS + CTS: CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. +-0: nCTS line set +-1: nCTS line reset + 10 + 1 + read-only + + + BUSY + BUSY: Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the +RX line (successful start bit detected). It is reset at the end of the reception (successful or +not). +-0: USART is idle (no reception) +-1: Reception on going + 16 + 1 + read-only + + + CMF + CMF: Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is +cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. +-0: No Character match detected +-1: Character Match detected + 17 + 1 + read-only + + + SBKF + SBKF: Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing +1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during +the stop bit of break transmission. +-0: No break character is transmitted +-1: Break character will be transmitted + 18 + 1 + read-only + + + RWU + RWU: Receiver wakeup from Mute mode +This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a +wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) +is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the +MMRQ bit in the USART_RQR register. +-0: Receiver in active mode +-1: Receiver in mute mode + 19 + 1 + read-only + + + WUF + WUF: Wakeup from Stop mode flag +This bit is set by hardware, when a wakeup event is detected. The event is defined by the +WUS bit field. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. +An interrupt is generated if WUFIE=1 in the LPUART_CR3 register + 20 + 1 + read-only + + + TEACK + TEACK: Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by +the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 +in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + REACK: Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by +the USART. +It can be used to verify that the USART is ready for reception before entering Stop mode. + 22 + 1 + read-only + + + TXFE + TXFE: TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one +data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in +the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. +-0: TXFIFO is not empty. +-1: TXFIFO is empty. + 23 + 1 + read-only + + + RXFF + RXFF: RXFIFO Full +This bit is set by hardware when RXFIFO is Full. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. +-0: RXFIFO is not Full. +-1: RXFIFO is Full. + 24 + 1 + read-only + + + RXFT + RXFT: RXFIFO threshold flag +This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 +register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and +one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in +the USART_CR3 register. +-0: Receive FIFO doesnt reach the programmed threshold. +-1: Receive FIFO reached the programmed threshold + 26 + 1 + read-only + + + TXFT + TXFT: TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG +in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is +generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. +-0: TXFIFO doesnt reach the programmed threshold. +-1: TXFIFO reached the programmed threshold + 27 + 1 + read-only + + + + + ICR + ICR + ICR register + 0x20 + 0x20 + read-write + 0x00000000 + + + PECF + PECF: Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + FECF: Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register + 1 + 1 + write-only + + + NECF + NECF: Noise detected clear flag +Writing 1 to this bit clears the NF flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + ORECF: Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + IDLECF: Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TCCF + TCCF: Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register + 6 + 1 + write-only + + + CTSCF + CTSCF: CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register + 9 + 1 + write-only + + + CMCF + CMCF: Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register + 17 + 1 + write-only + + + WUCF + WUCF: Wakeup from Stop mode clear flag +Writing 1 to this bit clears the WUF flag in the LPUART_ISR register. + 20 + 1 + write-only + + + + + RDR + RDR + RDR register + 0x24 + 0x20 + read-only + 0x0 + + + RDR + RDR[8:0]: Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the +internal bus (see Figure 124). +When receiving with the parity enabled, the value read in the MSB bit is the received parity +bit. + 0 + 9 + read-only + + + + + TDR + TDR + TDR register + 0x28 + 0x20 + read-write + 0x0 + + + TDR + TDR[8:0]: Transmit data value +Contains the data character to be transmitted. +The USARTx_TDR register provides the parallel interface between the internal bus and the +output shift register (see Figure 124). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), +the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect +because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + PRESC + PRESC + PRESC register + 0x2C + 0x20 + read-write + 0x0 + + + PRESCALER + PRESCALER[3:0]: Clock prescaler +The USART input clock can be divided by a prescaler: +-0000: input clock not divided +-0001: input clock divided by 2 +-0010: input clock divided by 4 +-0011: input clock divided by 6 +-0100: input clock divided by 8 +-0101: input clock divided by 10 +-0110: input clock divided by 12 +-0111: input clock divided by 16 +-1000: input clock divided by 32 +-1001: input clock divided by 64 +-1010: input clock divided by 128 +-1011: input clock divided by 256 +Remaing combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, +programmed prescaler value will be '1011' i.e. input clock divided by 256 + 0 + 4 + read-write + + + + + + + LCSC + LCSC + 0x4000A000 + + 0x0 + 0x48 + registers + + + LCSC + LCSC interrupt + 28 + + + LC_ACTIVITY + LCSC LC_ACTIVITY interrupt + 29 + + + + LCSC_CR0 + LCSC_CR0 + LCSC_CR0 register + 0x0 + 0x20 + read-write + 0x000B005C + + + TMEAS + Measurement Time + + 0 + 14 + read-write + + + TCAP + Capture Time + + 16 + 6 + read-write + + + TICAP + Inter Capture Time + + 24 + 3 + read-write + + + + + LCSC_CR1 + LCSC_CR1 + LCSC_CR1 register + 0x4 + 0x20 + read-write + 0x3C010C80 + + + LCAB_DAMP_THRES + LCAB_DAMP_THRES[7:0]: Damping threshold for LCA and LCB + + 0 + 8 + read-write + + + TREC_VCM + VCMBUFF Recovery Time + + 10 + 9 + read-write + + + TSTART_VCM + VCMBUFF Starting Time + + 20 + 11 + read-write + + + + + LCSC_CR2 + LCSC_CR2 + LCSC_CR2 register + 0x8 + 0x20 + read-write + 0x00008000 + + + TAMP_PSC + Tamper measurement interval. + 0 + 8 + read-write + + + LCT_DAMP_THRES + Damping threshold for LCT + + 8 + 8 + read-write + + + + + LCSC_PULSE_CR + LCSC_PULSE_CR + LCSC_PULSE_CR register + 0xc + 0x20 + read-write + 0x00000070 + + + LCAB_PULSE_WIDTH + Low Pulse Width for LCA and LCB + + 0 + 4 + read-write + + + LCT_PULSE_WIDTH + Low Pulse Width for LCT + + 8 + 4 + read-write + + + + + LCSC_ENR + LCSC_ENR + LCSC_ENR register + 0x10 + 0x20 + read-write + 0x00000000 + + + CLKWISE_IE + Clock Wise Interrupt and Wakeup Enable + + 0 + 1 + read-write + + + ACLKWISE_IE + Anti Clock Wise Interrupt and Wakeup Enable + + 1 + 1 + read-write + + + TAMP_IE + Tamper Interrupt and Wakeup Enable + + 2 + 1 + read-write + + + CNT_OFB_WKP_IE + LCAB Counter Out Of Bound wakeup enable + + 3 + 1 + read-write + + + LCSC_EN + LCSC Enable + + 31 + 1 + read-write + + + + + LCSC_WHEEL_SR + LCSC_WHEEL_SR + LCSC_WHEEL_SR register + 0x14 + 0x20 + read-only + 0x00000000 + + + CLKWISE + Number of Clock Wise revolutions + 0 + 16 + read-only + + + ACLKWISE + Number of Anti Clock Wise revolutions + 16 + 16 + read-only + + + + + LCSC_CONFR + LCSC_CONFR + LCSC_CONFR register + 0x18 + 0x20 + read-write + 0x00000000 + + + CLKWISE_THRES + Number of Clock Wise revolutions target + 0 + 16 + read-write + + + ACLKWISE_THRES + Number of Anti Clock Wise revolutions target + 16 + 16 + read-write + + + + + LCSC_COMP_CTN + LCSC_COMP_CTN + LCSC_COMP_CTN register + 0x1c + 0x20 + read-only + 0x00000000 + + + CMP_LCA_CNT + LCA Comparator last damping count + 0 + 8 + read-only + + + CMP_LCB_CNT + LCB Comparator last damping count + 10 + 8 + read-only + + + CMP_LCT_CNT + LCT Comparator last damping count + 20 + 8 + read-only + + + + + LCSC_SR + LCSC_SR + LCSC_SR register + 0x20 + 0x20 + read-only + 0x00000000 + + + CLKWISE_STATE + The current state of the LCSC clockwise FSM: + + 0 + 2 + read-only + + + ACLKWISE_STATE + The current state of the LCSC anti clockwise FSM: + + 2 + 2 + read-only + + + LAST_DIR + The last direction detected: + + 4 + 2 + read-only + + + + + LCSC_STAT + LCSC_STAT + LCSC_STAT register + 0x24 + 0x20 + read-write + 0xFF0000FF + + + MIN_LCAB_CNT + The Minimum of CMP_LCA_CNT, CMP_LCB_CNT reached during the + + 0 + 8 + read-only + + + MAX_LCAB_CNT + The Maximum of CMP_LCA_CNT, CMP_LCB_CNT reached during + + 8 + 8 + read-only + + + MIN_LCAB_CNT_BOUND + The Minimum bound of CMP_LCA_COUNT, + + 16 + 8 + read-write + + + MAX_LCAB_CNT_BOUND + The Maximum bound of CMP_LCA_COUNT, + + 24 + 8 + read-write + + + + + LCSC_TST_CFG + LCSC_TST_CFG + LCSC Test Configuration Register + 0x28 + 0x20 + read-write + 0x00000000 + + + TST_EN + Test Enable + 0 + 1 + read-write + + + TST_CFG + DTB output selection + 1 + 3 + read-write + + + + + LCSC_ANATST_CFG + LCSC_ANATST_CFG + LCSC ANA Test Configuration Register + 0x2C + 0x20 + read-write + 0x00000000 + + + VCMBUFF_ENOUT_SEL + Selection of the signal to be used to supply the DAC in the LCSC + 0 + 1 + read-write + + + VCMBUFF_ENOUT + VCMBUFFER output buffer enable pin + 1 + 1 + read-write + + + VCMBUFF_PWDN_SEL + Selection of the signal to be used to supply the DAC in the LCSC + 2 + 1 + read-write + + + VCMBUFF_PWDN + VCMBUFF power-down pin + 3 + 1 + read-write + + + COMP_PWDN_SEL + Selection of the signal to be used to supply the COMP in the LCSC +Analog part + 4 + 1 + read-write + + + COMP_PWDN + COMP power-down pin + 5 + 1 + read-write + + + DAC_PWDN_SEL + Selection of the signal to be used to supply the DAC in the LCSC Analog +part + 6 + 1 + read-write + + + DAC_PWDN + DAC power-down pin + 7 + 1 + read-write + + + + + LCSC_VER + LCSC_VER + LCSC_VER register + 0x40 + 0x20 + read-only + 0x00001000 + + + REV + Revision of the RFIP to be used for metal fixes) + 4 + 4 + read-only + + + VER + Version of the RFIP (to be used for cut upgrades) + 8 + 4 + read-only + + + PROD + Used for major upgrades (new protocols support / new features) + 12 + 4 + read-only + + + + + LCSC_ISR + LCSC_ISR + LCSC_ISR register + 0x44 + 0x20 + read-write + 0x00000000 + + + CLKWISE_F + Clock Wise Flag: + + 0 + 1 + read-write + + + ACLKWISE_F + Anti Clock Wise Flag: + + 1 + 1 + read-write + + + TAMP_F + Tamper Flag + + 2 + 1 + read-write + + + CNT_OFB_F + Out of Bound Counter Flag + + 3 + 1 + read-write + + + + + + + LPAWUR + LPAWUR + 0x49001000 + + 0x0 + 0x40 + registers + + + LPAWUR + LPAWUR interrupt + 18 + + + CPU_WKUP + CPU Wakeup interrupt + 23 + + + SUBG_WKUP + SUBG Wakeup interrupt + 24 + + + + FRAME_CONFIG0 + FRAME_CONFIG0 + FRAME_CONFIG0 register + 0x0 + 0x20 + read-write + 0x02074012 + + + PREAMBLE_THRESHOLD_COUNT + The number of transitions for preamble detection when receiving the manchester encoded preamble. + 0 + 8 + read-write + + + SYNC_LENGTH + Frame sync pattern length ( Manchester encoded ). + 8 + 1 + read-write + + + SYNC_THRESHOLD_COUNT + detection threshold when receivng the Frame sync ( Manchester encoded). + 10 + 6 + read-write + + + PAYLOAD_LENGTH + The number of data Bytes in the payload ( decoded ). + 16 + 4 + read-write + + + SLOW_CLK_CYCLE_PER_BIT_CNT + The number of expected slow clock cycle per each manchester coded bit. + 21 + 5 + read-write + + + + + FRAME_CONFIG1 + FRAME_CONFIG1 + FRAME_CONFIG1 register + 0x4 + 0x20 + read-write + 0x00024669 + + + KI + ki gain value for the timing recovery loop. + 0 + 4 + read-write + + + KP + kp gain value for the timing recovery loop. + 4 + 4 + read-write + + + FRAME_SYNC_COUNTER_TIMEOUT + The timeout in manchester encoded bits for the Frame Sync,it represents the number of samples after which in case the frame sync is not detected a sync_error is raised. + 8 + 8 + read-write + + + PREAMBLE_ENABLE + Preamble detection enable + + 17 + 1 + read-write + + + TREC_LOOP_ALGO_SEL + Timing recovery loop algorithm selection: + + 18 + 1 + read-write + + + + + FRAME_SYNC_CONFIG + FRAME_SYNC_CONFIG + FRAME_SYNC_CONFIG register + 0x8 + 0x20 + read-write + 0x00009696 + + + FRAME_SYNC_PATTERN_L + The value of the frame sync pattern, Low word, manchester encoded, used when the frame sync length is 16 bit (default 0x9696 which represent a frame sync value of 0x99) + 0 + 16 + read-write + + + FRAME_SYNC_PATTERN_H + The value of the frame sync pattern, High word, manchester encoded, used only when the frame sync length is 32 bits (default 0x0000 ) + 16 + 16 + read-write + + + + + RFIP_CONFIG + RFIP_CONFIG + RFIP_CONFIG register + 0xc + 0x20 + read-write + 0x00000006 + + + LPAWUR_ENABLE + Enable (start) or Disable (stop) the LPAWUR feature (0: disabled by default) + 0 + 1 + read-write + + + WAKEUP_LEVEL + - 00: the bit Sync has been detected + + 1 + 2 + read-write + + + + + RF_CONFIG + RF_CONFIG + RF_CONFIG register + 0x10 + 0x20 + read-write + 0x000133EE + + + ED_SWITCH + - 0 : Normal operation (default) + + 0 + 1 + read-write + + + CLKDIV + Calibrate 4kHz clock (programmable divider) + + 1 + 4 + read-write + + + AGC_LOW_LVL + AGC level (Low) (default value: 0x2) + 11 + 2 + read-write + + + ED_DC_CTRL + DC current subtraction enabling signal (default value: 0x1) + 13 + 1 + read-write + + + AGC_HIGH_LVL + AGC level (High) (default value: 0x4) + 14 + 4 + read-write + + + ED_ICAL + Current versus VBAT calibration for ED + + 18 + 3 + read-write + + + LPF3_CAL + + 21 + 1 + read-write + + + + + AGC_CONFIG + AGC_CONFIG + AGC_CONFIG register + 0x14 + 0x20 + read-write + 0x00000000 + + + AGC_MODE + Define the working mode of the AGC: + + 0 + 2 + read-write + + + AGC_HOLD_MODE + The behavior when the AGC is ON and is working in HOLD mode + + 2 + 1 + read-write + + + AGC_RESET_MODE + The AGC reset behavior when the AGC is working in ON or HOLD mode + + 3 + 1 + read-write + + + + + PAYLOAD_0 + PAYLOAD_0 + PAYLOAD_0 register + 0x1c + 0x20 + read-only + 0x00000000 + + + PAYLOAD_0 + First part of the payload (Least significant Byte First) + 0 + 32 + read-only + + + + + PAYLOAD_1 + PAYLOAD_1 + PAYLOAD_1 register + 0x20 + 0x20 + read-only + 0x00000000 + + + PAYLOAD_1 + Second part of the payload (Least significant Byte First) + 0 + 32 + read-only + + + + + + + MISC + MISC + 0x49000700 + + 0x0 + 0x80 + registers + + + + RFIP_VERSION + RFIP_VERSION + RFIP_VERSION register + 0x0 + 0x20 + read-only + 0x00001200 + + + REVISION + Revision of the MR_SubG (to be used for metal fixes) + 4 + 4 + read-only + + + VERSION + Version of the MR_SubG (to be used for cut upgrades) + 8 + 4 + read-only + + + PRODUCT + Used for major upgrades (new protocols support / new features) + 12 + 4 + read-only + + + + + RRM_UDRA_CTRL + RRM_UDRA_CTRL + RRM_UDRA_CTRL register + 0x4 + 0x20 + write-only + 0x00000000 + + + RRM_CMD_REQ + Action bit: write 1 to request a RRM-UDRA command. + 0 + 1 + write-only + + + + + SEQUENCER_CTRL + SEQUENCER_CTRL + SEQUENCER_CTRL register + 0x8 + 0x20 + read-write + 0x00000000 + + + GEN_SEQ_TRIGGER + Action bit: write 1 to generate a trigger event on Sequencer. + 0 + 1 + write-only + + + DISABLE_SEQ + Enable/disable the Sequencer + + 1 + 1 + read-write + + + + + ABSOLUTE_TIME + ABSOLUTE_TIME + ABSOLUTE_TIME register + 0xc + 0x20 + read-only + 0x00000000 + + + ABSOLUTE_TIME + Indicate the interpolated absolute. + 0 + 32 + read-only + + + + + SCM_COUNTER_VAL + SCM_COUNTER_VAL + SCM_COUNTER_VAL register + 0x10 + 0x20 + read-only + 0x00000000 + + + SCM_COUNTER_CURRVAL + Slow Clock Measurement: number of 16 MHz clock cycles contained in 32 slow clock periods. + 0 + 15 + read-only + + + + + SCM_MIN_MAX + SCM_MIN_MAX + SCM_MIN_MAX register + 0x14 + 0x20 + read-write + 0x00007FFF + + + SCM_COUNTER_MINVAL + Slow Clock Measurement: minimum SCM_COUNTER value seen since the counter is ON and since last clear request. + 0 + 15 + read-only + + + SCM_COUNTER_MAXVAL + Slow Clock Measurement: maximum SCM_COUNTER value seen since the counter is ON and since last clear request. + 16 + 15 + read-only + + + CLEAR_MIN_MAX + Write 1' to clear the SCM_COUNTER_MINVAL and SCM_COUNTER_MAXVAL bit fields. + 31 + 1 + write-only + + + + + WAKEUP_IRQ_STATUS + WAKEUP_IRQ_STATUS + WAKEUP_IRQ_STATUS register + 0x18 + 0x20 + read-write + 0x00000000 + + + CPU_WAKEUP_F + Set when the interpolated absolute time matches the CPU_WAKEUPTIME while WAKEUP_CTRL. + 0 + 1 + + + RFIP_WAKEUP_F + Set when the interpolated absolute time matches the RFIP_WAKEUPTIME while WAKEUP_CTRL. + 1 + 1 + + + + + + + MR_SUBG + MR_SUBG + 0x49000000 + + 0x0 + 0x400 + registers + + + MR_SUBG_BUSY + MR_SUBG Busy interrupt + 20 + + + MR_SUBG + MR_SUBG interrupt + 21 + + + TX_RX_SEQUENCE + MR_SUBG TX/RX Sequence +interrupt + 22 + + + + RF_FSM0_TIMEOUT + RF_FSM0_TIMEOUT + RF_FSM0_TIMEOUT register + 0x00 + 0x20 + read-write + 0x00000000 + + + ENA_RFREG_TIMER + Timeout for the RF regulator startup (duration in ENA_RF_REG state) + + 0 + 8 + read-write + + + + + RF_FSM1_TIMEOUT + RF_FSM1_TIMEOUT + RF_FSM1_TIMEOUT register + 0x04 + 0x20 + read-write + 0x00000006 + + + SYNTH_SETUP_TIMER + Timeout management for the RF regulator to stabilize after RF PLL power on + + 0 + 8 + read-write + + + + + RF_FSM2_TIMEOUT + RF_FSM2_TIMEOUT + RF_FSM2_TIMEOUT register + 0x08 + 0x20 + read-write + 0x00000050 + + + VCO_CALIB_LOCK_TIMER + Timeout for the RF PLL calibration + RF PLL lock (duration in CALIB_VCO+LOCKRXTX state) + + 0 + 8 + read-write + + + + + RF_FSM3_TIMEOUT + RF_FSM3_TIMEOUT + RF_FSM3_TIMEOUT register + 0x0C + 0x20 + read-write + 0x00000028 + + + VCO_LOCK_TIMER + Timeout for the RF PLL lock event when no calibration is requested (duration in LOCKRXTX state) + + 0 + 8 + read-write + + + + + RF_FSM4_TIMEOUT + RF_FSM4_TIMEOUT + RF_FSM4_TIMEOUT register + 0x10 + 0x20 + read-write + 0x0000000F + + + EN_RX_TIMER + Timeout for the analog RX chain setup (duration in EN_RX state) + + 0 + 8 + read-write + + + + + RF_FSM5_TIMEOUT + RF_FSM5_TIMEOUT + RF_FSM5_TIMEOUT register + 0x14 + 0x20 + read-write + 0x00000019 + + + EN_PA_TIMER + Timeout for the analog PA (DAC) setup (duration in EN_PA state) + + 0 + 8 + read-write + + + + + RF_FSM6_TIMEOUT + RF_FSM6_TIMEOUT + RF_FSM6_TIMEOUT register + 0x18 + 0x20 + read-write + 0x00000019 + + + PA_DWN_ANA_TIMER + Timeout for the analog PA (DAC) ramp down (duration in PA_DWN_ANA state) + + 0 + 8 + read-write + + + + + RF_FSM7_TIMEOUT + RF_FSM7_TIMEOUT + RF_FSM7_TIMEOUT register + 0x1C + 0x20 + read-write + 0x00000005 + + + EN_LNA_TIMER + Timeout for the analog RX chain signals settlement once PGA precharge is shut down (duration in EN_LNA state) + + 0 + 8 + read-write + + + + + AFC0_CONFIG + AFC0_CONFIG + AFC0_CONFIG register + 0x20 + 0x20 + read-write + 0x00000025 + + + AFC_SLOW_GAIN_LOG2 + AFC loop gain in slow mode (2's log) + 0 + 4 + read-write + + + AFC_FAST_GAIN_LOG2 + AFC loop gain in fast mode (2's log) + 4 + 4 + read-write + + + + + AFC1_CONFIG + AFC1_CONFIG + AFC1_CONFIG register + 0x24 + 0x20 + read-write + 0x00000018 + + + AFC_FAST_PERIOD + Length of the AFC fast period (in number of samples unit) + + 0 + 8 + read-write + + + + + AFC2_CONFIG + AFC2_CONFIG + AFC2_CONFIG register + 0x28 + 0x20 + read-write + 0x000000C8 + + + AFC_PD_LEAKAGE + AFC Peak Detection leakage. + 0 + 5 + read-write + + + AFC_MODE + Select AFC mode: + + 5 + 1 + read-write + + + AFC_EN + Enable AFC. + 6 + 1 + read-write + + + AFC_FREEZE_ON_SYNC + Freeze AFC correction upon SYNC word detection + 7 + 1 + read-write + + + + + AFC3_CONFIG + AFC3_CONFIG + AFC3_CONFIG register + 0x2C + 0x20 + read-write + 0x000000E8 + + + AFC_INIT_MODE + Control the initialization phase of the AFC and clock recovery algorithms: + + 0 + 1 + read-write + + + AFC_SIGN_PERM_CHECK + Enable the check of sign permanence of AFC corrected signal. + 1 + 1 + read-write + + + AFC_TH_SIGN_PERM + Threshold of chech sign permanence mechanism. + 2 + 4 + read-write + + + AFC_REINIT_OPTION + Select the AFC reinitialization option: + + 6 + 2 + read-write + + + + + CLKREC_CTRL0 + CLKREC_CTRL0 + CLKREC_CTRL0 register + 0x30 + 0x20 + read-write + 0x000000B8 + + + CLKREC_I_GAIN_FAST + Integral fast gain for the clock recovery loop (PLL mode only) + + 0 + 4 + read-write + + + CLKREC_P_GAIN_FAST + Clock recovery fast loop gain (log2) + + 4 + 3 + read-write + + + PSTFLT_LEN + Control the length of the demodulator post-filter + + 7 + 1 + read-write + + + + + CLKREC_CTRL1 + CLKREC_CTRL1 + CLKREC_CTRL1 register + 0x34 + 0x20 + read-write + 0x0000005C + + + CLKREC_I_GAIN_SLOW + Integral slow gain for the clock recovery loop (PLL mode only) + + 0 + 4 + read-write + + + CLKREC_P_GAIN_SLOW + Clock recovery slow loop gain (log2) + + 4 + 3 + read-write + + + CLKREC_ALGO_SEL + Symbol timing recovery algorithm selection + + 7 + 1 + read-write + + + + + DCREM_CTRL0 + DCREM_CTRL0 + DCREM_CTRL0 register + 0x38 + 0x20 + read-write + 0x000000E8 + + + START_GAIN + Filter gain in start mode for the DC removal block. + 0 + 5 + read-write + + + TRACK_GAIN + Filter gain in track mode for the DC removal block. + 7 + 1 + read-write + + + + + IQC_CTRL0 + IQC_CTRL0 + IQC_CTRL0 register + 0x40 + 0x20 + read-write + 0x000000E3 + + + FAST_GAIN + Gain of the correction loop in fast mode. + 0 + 4 + read-write + + + SLOW_GAIN + Gain of the correction loop in slow mode. + 4 + 4 + read-write + + + + + IQC_CTRL1 + IQC_CTRL1 + IQC_CTRL1 register + 0x44 + 0x20 + read-write + 0x00000008 + + + QPD_ATTACK + Attack coefficient for QPD: + + 0 + 8 + read-write + + + + + IQC_CTRL2 + IQC_CTRL2 + IQC_CTRL2 register + 0x48 + 0x20 + read-write + 0x00000008 + + + QPD_DECAY + Decay coefficient for QPD: + + 0 + 8 + read-write + + + + + IQC_CTRL3 + IQC_CTRL3 + IQC_CTRL3 register + 0x4C + 0x20 + read-write + 0x00000007 + + + FAST_TIME + Duration of the fast mode. + 0 + 4 + read-write + + + + + AGC_ANA_ENG + AGC_ANA_ENG + AGC_ANA_ENG register + 0x50 + 0x20 + read-write + 0x00000000 + + + FORCE_AGC_GAINS + Select the mode for AGC analog part: + + 0 + 1 + read-write + + + RFD_RX_ATTEN_AGCGAIN + Attenuation at LNA level by step of 6dB with thermometric code: + + 1 + 4 + read-write + + + RFD_RX_PGA_AGCGAIN + Attenuation at PGA level by step of 6dB with binary code: + + 5 + 3 + read-write + + + + + AGC0_CTRL + AGC0_CTRL + AGC0_CTRL register + 0x54 + 0x20 + read-write + 0x00000099 + + + AGC_HOLD_TIME + AGC hold time. + 0 + 6 + read-write + + + AGC_START_ONHOLD + Start the AGC with a hold phase. + 6 + 1 + read-write + + + AGC_EN + Enable the AGC + + 7 + 1 + read-write + + + + + AGC1_CTRL + AGC1_CTRL + AGC1_CTRL register + 0x58 + 0x20 + read-write + 0x00000062 + + + AGC_MIN_THR + Minimum signal threshold. + 0 + 4 + read-write + + + AGC_MAX_THR + Maximum signal threshold. + 4 + 4 + read-write + + + + + AGC2_CTRL + AGC2_CTRL + AGC2_CTRL register + 0x5C + 0x20 + read-write + 0x000000AF + + + AGC_MEAS_TIME + Measure time. + 0 + 4 + read-write + + + AGC_START_MAX_ATTEN + Start the AGC with maximum attenuation. + 4 + 1 + read-write + + + AGC_FREEZE_ON_SYNC + Enable the freeze on SYNC detection feature + 5 + 1 + read-write + + + AGC_FREEZE_ON_STEADY + Enable the autofreeze feature + 6 + 1 + read-write + + + AGC_HIGH_ATTEN_MODE + Enable the high attenuation mode. + 7 + 1 + read-write + + + + + AGC3_CTRL + AGC3_CTRL + AGC3_CTRL register + 0x60 + 0x20 + read-write + 0x00000090 + + + AGC_MIN_ATTEN + Minimum AGC attenuation. + 0 + 4 + read-write + + + AGC_MAX_ATTEN + Maximum AGC attenuation. + 4 + 4 + read-write + + + + + AGC4_CTRL + AGC4_CTRL + AGC4_CTRL register + 0x64 + 0x20 + read-write + 0x00000002 + + + AGC_FREEZE_THR + Signal threshold for the autofreeze feature. + 0 + 4 + read-write + + + + + AGC_PGA_HWTRIM_OUT + AGC_PGA_HWTRIM_OUT + AGC_PGA_HWTRIM_OUT register + 0xA0 + 0x20 + read-only + 0x00000008 + + + AGC_HW_PGA_TRIM + AGC PGA calibration information loaded by HW from the SoC flash. + 0 + 4 + read-only + + + + + PA_REG + PA_REG + PA_REG register + 0xA8 + 0x20 + read-write + 0x00000000 + + + CFG_FILT + FIR configuration: + + 0 + 2 + read-write + + + PA_DEGEN_ON + Enable a 'degeneration' mode, which introduces a pre-distortion to linearize the power control curve. + 3 + 1 + read-write + + + + + PA_HWTRIM_OUT + PA_HWTRIM_OUT + PA_HWTRIM_OUT register + 0xAC + 0x20 + read-only + 0x00000088 + + + PA_HW_DEGEN_TRIM + MSB part meaning: + + 4 + 4 + read-only + + + + + RSSI_FLT + RSSI_FLT + RSSI_FLT register + 0xBC + 0x20 + read-write + 0x000000E0 + + + OOK_PEAK_DECAY + Peak decay control for OOK: 3 slow decay; 0 fast decay + 0 + 4 + read-write + + + RSSI_FLT + Gain of the RSSI filter + 4 + 4 + read-write + + + + + SYNTH2_ANA_ENG + SYNTH2_ANA_ENG + SYNTH2_ANA_ENG register + 0xC8 + 0x20 + read-write + 0x0000004C + + + RFD_PLL_VCO_ALC_AMP + Select the level of max VCO amplitude in amplitude level control loop. + 0 + 3 + read-write + + + RFD_PLL_LD_WIN_ACC + Select the PLL lock detector window selection: + + 3 + 1 + read-write + + + + + RXADC_HWDELAYTRIM_OUT + RXADC_HWDELAYTRIM_OUT + RXADC_HWDELAYTRIM_OUT register + 0xE8 + 0x20 + read-only + 0x0000001B + + + RXADC_HW_DELAYTRIM_I + Control bits of the RX ADC loop delay for I channel (from SoC Flash). + 0 + 3 + read-only + + + RXADC_HW_DELAYTRIM_Q + Control bits of the RX ADC loop delay for Q channel (from SoC Flash). + 3 + 3 + read-only + + + + + RX_AAF_HWTRIM_OUT + RX_AAF_HWTRIM_OUT + RX_AAF_HWTRIM_OUT register + 0xF4 + 0x20 + read-only + 0x00000006 + + + AAF_HW_FCTRIM + AAF calibration information loaded by HW. + 0 + 4 + read-only + + + + + SINGEN_ANA_ENG + SINGEN_ANA_ENG + SINGEN_ANA_ENG register + 0x100 + 0x20 + read-write + 0x00000000 + + + RFD_SINGEN_ENA + Enable SINGEN signal for the RFSUBGanalog IP. + 0 + 1 + read-write + + + RFD_SINGEN_DIV2_PUP + This bit value is directly connected to the RFSUBG analog IP pin. + 1 + 1 + read-write + + + RFD_SINGEN_LBE + This bit value is directly connected to the RFSUBG analog IP pin. + 2 + 1 + read-write + + + + + RF_INFO_OUT + RF_INFO_OUT + RF_INFO_OUT register + 0x108 + 0x20 + read-only + 0x00000040 + + + FQCY_BAND_ID + FQCY_BAND_ID[3:0]: Indicates the version of the RFSUBG IP embedded in the device + + 0 + 4 + read-only + + + RFSUBG_ID + Indicate the version of the analog RFSUBG IP embedded in the device + + 4 + 4 + read-only + + + + + RF_FSM8_TIMEOUT + RF_FSM8_TIMEOUT + RF_FSM8_TIMEOUT register + 0x124 + 0x20 + read-write + 0x0000000A + + + SYNTH_PDWN_TIMER + Timeout management for the RF regulator to stabilize after PLL shut down + + 0 + 8 + read-write + + + + + RF_FSM9_TIMEOUT + RF_FSM9_TIMEOUT + RF_FSM9_TIMEOUT register + 0x128 + 0x20 + read-write + 0x00000006 + + + END_RX_TIMER + Timeout management for the RF regulator to stabilize after analog RX chain shut down + + 0 + 8 + read-write + + + + + RF_FSM10_TIMEOUT + RF_FSM10_TIMEOUT + RF_FSM10_TIMEOUT register + 0x12C + 0x20 + read-write + 0x00000006 + + + END_TX_TIMER + Timeout management for the RF regulator to stabilize after clock stops on the analog PA block + + 0 + 8 + read-write + + + + + SUBG_DIG_CTRL0 + SUBG_DIG_CTRL0 + SUBG_DIG_CTRL0 register + 0x144 + 0x20 + read-write + 0x00000000 + + + FORCE_GPIO_OUTPUT + Option for the direct GPIO signal output + + 0 + 1 + read-write + + + + + RX_CHAIN_ENG + RX_CHAIN_ENG + RX_CHAIN_ENG register + 0x148 + 0x20 + read-write + 0x00000003 + + + LNA_ISOL_ENA + Option for LNA during the EN_RX state of the Radio FSM: + + 0 + 1 + read-write + + + PGA_PRECH_ENA + Option for PGA precharge during the EN_RX state of the Radio FSM: + + 1 + 1 + read-write + + + + + DEMOD_DIG_ENG + DEMOD_DIG_ENG + DEMOD_DIG_ENG register + 0x14C + 0x20 + read-write + 0x00000003 + + + RX_BLANKING_LENGTH + Number of data samples at RX start for which the signal at the output of the channel filter is kept forced to zero: + + 0 + 3 + read-write + + + + + + + PWRC + PWRC + 0x48500000 + + 0x0 + 0xA8 + registers + + + PVD + PVD / BORH + 2 + + + + CR1 + CR1 + CR1 register + 0x0 + 0x20 + read-write + 0x114 + + + LPMS + LPMS Low Power Mode Selection +Selection of the low power mode entered when CPU enters DEEP SLEEP mode and BLE is rdy2sleep. +- 0: Deep Stop mode (default) +- 1: Shutdown mode + 0 + 1 + read-write + + + ENSDNBOR + ENSDNBOR: Enable BOR supply monitoring during shutdown mode. +- 1: the PD_ALL_SHUTDOWN signal is not set during SHUTDOWN mode +- 0: the PD_ALL_SHUTDOWN signal is set during SHUTDOWN mode. + 1 + 1 + read-write + + + IBIAS_RUN_AUTO + IBIAS_RUN_AUTO: Enable automatic IBIAS control during RUN/DEEPSTOP mode. +- 0: IBIAS control is manual (and controlled by IBIAS_RUN_STATE register) +- 1: IBIAS control is automatic (default). + 2 + 1 + read-write + + + IBIAS_RUN_STATE + IBIAS_RUN_STATE: Enable/Disable IBIAS during RUN mode when automatic mode is +disabled. +- 0: IBIAS control is disabled (default). +- 1: IBIAS control is enabled. + 3 + 1 + read-write + + + APC + APC Apply Pull-up and pull-down configuration from CPU +- 1: the I/O pull-up and pull-down configurations defined in the PUCRx and PDCRx registers is applied. +- 0: the PUCRx and PDCRx are not used to control the I/O pull-up and pull-down configuration of the product I/Os. + 4 + 1 + read-write + + + ENBORH + ENBORH: enable BORH configuration +- 1: BORH is enabled, threshold level depends on SELBOR[1:0] +- 0: BORH off (VBOR0): threshold level for above 1.60V voltage operation. + 5 + 1 + read-write + + + SELBORH + SELBORH[1:0]: BORH selection of Vbor threshold +- 11: BORH Level 4(VBOR4): threshold level for above 2.81 V voltage operation. +- 10: BORH Level 3 (VBOR3): threshold level for above 2.52 V voltage operation +- 01: BORH Level 2 (VBOR2): threshold level for above 2.21 V voltage operation +- 00: BORH Level 1 (VBOR1): threshold level for above 2.0V voltage operation. + 6 + 2 + read-write + + + ENBORL + ENBORL: Enable BORL reset supervising during RUN mode. +- 0: No BORL is monitored during RUN mode. +- 1: BORL is monitored during RUN mode (a POR reset will happen if VDDIO goes below 1.6V during RUN mode) (default). +Note: Enabling this feature prevents blocking the device if VDDIO goes below supported voltages during RUN. + 8 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x4 + 0x20 + read-write + 0x0000 + + + PVDE + PVDE Programmable Voltage Detector Enable +When this bit is set the Power Voltage Detector is enabled + 0 + 1 + read-write + + + PVDLS + PVDLS[2:0] Programmable Voltage Detector Level selection +- 000: 2.05 V - Lowest level +- 001: 2.20 V +- 010: 2.36 V +- 011: 2.52 V +- 100: 2.64 V +- 101: 2.81 V +- 110: 2.91 V - Highest level +- 111: External input analog voltage (compare internally to VBGP; When external input VBGP +then PVDO=1) + 1 + 3 + read-write + + + DBGRET + DBGRET: PA2 and PA3 retention enable after DEEPSTOP +- 0: PA2, PA3 don't retain their status exiting from DEEPSTOP (default). +- 1: PA2, PA3 retain their status exiting from DEEPSTOP. + 4 + 1 + read-write + + + RAMRET1 + RAMRET1: RAM1 retention during low power mode +- 1: RAM1 bank is powered during low power mode +- 0: RAM1 bank is disabled during low power mode (by default) + 5 + 1 + read-write + + + LPREG_FORCE_VH + force LPREG=1.2V during DEEPSTOP +- 1: Force LPREG=1.2V during DEEPSTOP +- 0: No Force (Default) +Note LPREG= 1.2v can still apply when LCDEN or COMP.SCALEREN request it + 6 + 1 + read-write + + + LPREG_VH_STATUS + status LPREG VH (1.2v) during DEEPSTOP +- 1: LPREG=1.2V during DEEPSTOP +- 0: LPREG=1V during DEEPSTOP + 7 + 1 + read-only + + + GPIORET + GPIORET: GPIO retention enable. +- 0: Release GPIO retention after deepstop (Should be reset after restore Context) +- 1: Enable GPIO Retention during deepstop (Must be set before deepstop) + 8 + 1 + read-write + + + ENTS + ENTS: Enable Temperature Sensor +- 1: Temperature sensor is enabled +- 0: Temperature sensor is disabled + 9 + 1 + read-write + + + RFREGEN + RFREGEN: RF Regulator Enable +- 1: Enable RF Regulator +- 0: Disable RF Regulator (Note: RF Regulator can still be enabled by the RFSUGB or RCC_CR.HSEON) + 10 + 1 + read-write + + + RFREGCEXT + RFREGCEXT: RF Regulator External Supply Bypass +- 1: External supply bypass capability +- 0: Internal supply only + 11 + 1 + read-write + + + RFREGBYP + RFREGBYP: RF Regulator Bypass Enable +- 1: LDO output connected to VSMPS. +- 0: internally generated 1.2V + 12 + 1 + read-write + + + RFREGRDY + RFDREGRDY: RF Regulator Ready flag +- 1: RF Regulator is ready +- 0: RF Regulator is not ready + 13 + 1 + read-only + + + RFREGON_STATUS + RFREGON_STATUS: RF Regulator On Status +- 1: RF Regulator is enabled +- 0: RF Regulator is disabled + 14 + 1 + read-only + + + + + IEWU + IEWU + IEWU register + 0x8 + 0x20 + read-write + 0x0000 + + + EIWL0 + EWL0 Enable Internal WakeUp line LPUART +When this bit is set the internal wakeup line is enabled and a rising edge will trigger a CPU wakeup event. +- 0: wakeup disabled. +- 1: wakeup enabled. + 0 + 1 + read-write + + + EIWL1 + EIWL1 Enable Internal WakeUp line RTC +When this bit is set the internal wakeup line is enabled and a rising edge will trigger a CPU wakeup event. +- 0: wakeup disabled. +- 1: wakeup enabled. + 1 + 1 + read-write + + + EIWL2 + EIWL2 Enable Internal WakeUp line LCD +When this bit is set the internal wakeup line is enabled and a rising edge will trigger a CPU wakeup event. +- 0: wakeup disabled. +- 1: wakeup enabled. + 2 + 1 + read-write + + + EIWL3 + EIWL3 Enable Internal Wakeup line COMP +When this bit is set the COMP wakeup is enabled and an edge will trigger a COMP wakeup event +- 0: wakeup disabled. +- 1: wakeup enabled. + 3 + 1 + read-write + + + EIWL4 + EIWL4 Enable Internal Wakeup line LCSC +When this bit is set the LCSC wakeup is enabled and an edge will trigger a LCSC wakeup event +- 0: wakeup disabled. +- 1: wakeup enabled. + 4 + 1 + read-write + + + EWMRSUBG + EWMRSUB Wakeup MRSUBG Enable +When this bit is set the MRSUBG wakeup is enabled and a rising edge will trigger a MRSUBG wakeup event +- 0: MRSUBG wakeup disabled. +- 1: MRSUBG wakeup enabled. + 8 + 1 + read-write + + + EWMRSUBGHCPU + EWMRSUBGHCPU Wakeup MRSUBG Host CPU Enable +When this bit is set the MRSUBG HOST CPU wakeup is enabled and a rising edge will trigger a MRSUBG Host CPU wakeup event +- 0: MRSUBG Host CPU wakeup disabled. +- 1: MRSUBG Host CPU wakeup enabled. + 9 + 1 + read-write + + + EWLPAWUR + EWLPAWUR: Wakeup Bubble Enable +When this bit is set the Bubble wakeup is enabled and a rising edge will trigger a LPAWUR wakeup event +- 0: LPAWUR wakeup disabled. +- 1: LPAWUR wakeup enabled. + 10 + 1 + read-write + + + + + IWUP + IWUP + IWUP register + 0xc + 0x20 + read-write + 0x0 + + + IWUP0 + IWUP0: Wakeup polarity for internal wakeup line 0 event (LPUART). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 0 + 1 + read-write + + + IWUP1 + IWUP1: Wakeup polarity for internal wakeup line 1 event (RTC). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 1 + 1 + read-write + + + IWUP2 + IWUP2: Wakeup polarity for internal wakeup line 2 event (LCD). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 2 + 1 + read-write + + + IWUP3 + IWUP3: Wakeup polarity for internal wakeup line 3 event (COMP). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 3 + 1 + read-write + + + IWUP4 + IWUP4: Wakeup polarity for internal wakeup line 4 event (LCSC). +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 4 + 1 + read-write + + + WMRSUBGHP + WMRSUBGHP: Wakeup polarity for internal wakeup MRSUBG event +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 8 + 1 + read-write + + + WMRSUBGHCPUP + WMRSUBGHCPUP: Wakeup polarity for internal wakeup MRSUBG Host CPU event +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 9 + 1 + read-write + + + WLPAWURP + WLPAWURP: Wakeup polarity for wakeup LPAWUR event. +- 0: Detection of wakeup event on rising edge (default). +- 1: Detection of wakeup event on falling edge. + 10 + 1 + read-write + + + + + IWUF + IWUF + IWUF register + 0x10 + 0x20 + read-write + 0x0 + + + IWUF0 + IWUF0: Internal wakeup flag (LPUART). +- 0: no wakeup from LPUART occurred since last clear. +- 1: a wakeup from LPUART occurred since last clear. +Cleared by writing 1 in this bit. + 0 + 1 + read-write + + + IWUF1 + IWUF1: Internal wakeup flag (RTC). +- 0: no wakeup from RTC occurred since last clear. +- 1: a wakeup from RTC occurred + 1 + 1 + read-write + + + IWUF2 + IWUF2: Internal wakeup flag (LCD). +- 0: no wakeup from LCD occurred since last clear. +- 1: a wakeup from LCD occurred since last clear. +Cleared by writing 1 in this bit. + 2 + 1 + read-write + + + IWUF3 + IWUF3: Internal wakeup flag (COMP). +- 0: no wakeup from COMP occurred since last clear. +- 1: a wakeup from COMP occurred since last clear. +Cleared by writing 1 in this bit. + 3 + 1 + read-write + + + IWUF4 + IWUF4: Internal wakeup flag (LCSC). +- 0: no wakeup from LCSC occurred since last clear. +- 1: a wakeup from LCSC occurred since last clear. +Cleared by writing 1 in this bit. + 4 + 1 + read-write + + + WMRSUBGF + WMRSUBGF Wakeup MRSUBG Flag +This bit is set by hardware when a MRSUBG wakeup is detected +It is cleared by a reset pad or by software writing 1 in this bit field. +- 0: No MRSUBG Wakeup detected +- 1: MRSUBG Wakeup detected +writting 1 in this bit, clears the interrupt + 8 + 1 + read-write + + + WMRSUBGHCPUF + WMRSUBGHCPUF Wakeup MRSUBG HOST CPU Flag (cf. user manual) +This bit is set by hardware when a MRSUBG HOST CPU wakeup is detected +It is cleared by a reset pad or by software writing 1 in this bit field. +- 0: No MRSUBG Host CPU wakeup detected +- 1: MRSUBG Host CPU wakeup detected +writting 1 in this bit, clears the interrupt + 9 + 1 + read-write + + + WLPAWURF + WLPAWURF Wakeup LPAWUR Flag (cf. user manual) +This bit is set by hardware when a LPAWUR wakeup is detected +It is cleared by a reset pad or by software writing 1 in this bit field. +- 0: No LPAWUR wakeup detected +- 1: LPAWUR wakeup detected +writting 1 in this bit, clears the interrupt + 10 + 1 + read-write + + + + + SR2 + SR2 + SR2 register + 0x14 + 0x20 + read-only + 0xF3F6 + + + SMPSBYPR + SMPSBYPR: SMPS Force Bypass Control Replica +This bit mirrors the actual BYPASS_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 0 + 1 + read-only + + + SMPSENR + SMPSENR: SMPS Enable Control Replica +This bit mirrors the actual ENABLE_3V3 control signal driven to the SMPS regulator, dependant on the real working state. + 1 + 1 + read-only + + + SMPSRDY + SMPSRDY: SMPS Ready Status +This bit provides the information whether SMPS is ready. +- 0: SMPS regulator is not ready +- 1: SMPS regulator is ready. + 2 + 1 + read-only + + + IOBOOTVAL2 + Bit3: PB15 input value on VDD33 latched at POR +Bit2: PB14 input value on VDD33 latched at POR +Bit1: PB13 input value on VDD33 latched at POR +Bit0: PB12 input value on VDD33 latched at POR + 4 + 4 + read-only + + + REGLPS + REGLPS: Regulator Low Power Started +This bit provides the information whether low power regulator is ready. +- 0: LP regulator is not ready. +- 1: LP regulator is ready. + 8 + 1 + read-only + + + REGMS + REGMS: Main regulator ready status. +- 0: The Main regulator is not ready. +- 1: The Main regulator is ready. + 9 + 1 + read-only + + + PVDO + PVDO: Power Voltage Detector Output +When the Power Voltage Detector is enabled (CR2.PVDE) this bit is set when the system supply (VDDIO) is +lower than the selected PVD threshold (CR2.PVDLS) + 11 + 1 + read-only + + + IOBOOTVAL + Bit3: PA11 input value on VDD33 latched at POR +Bit2: PA10 input value on VDD33 latched at POR +Bit1: PA9 input value on VDD33 latched at POR +Bit0: PA8 input value on VDD33 latched at POR + 12 + 4 + read-only + + + + + CR5 + CR5 + CR5 register + 0x1c + 0x20 + read-write + 0x6014 + + + SMPSLVL + SMPSLVL[3:0] SMPS Output Level Voltage Selection +Select the SMPS output voltage with a granularity of 50mV. Default = '0100' (1.4V) +Vout = 1.2 + 0.05*SMPSOUT (V) + 0 + 4 + read-write + + + SMPSBOMSEL + SMPSBOMSEL: SMPS BOM Selection: +- 00: BOM1 +- 01: BOM2 (default) +- 10: BOM3 +- 11: n/a + 4 + 2 + read-write + + + SMPS_BOF_STATIC + SMPS_BOF_STATIC: SMPS Bypass on the Fly static +- 0 : disabled (by default) +- 1 : SMPS Bypass on the fly static is enabled (EN_SW=1) + 6 + 1 + read-write + + + NOSMPS_BOF + NOSMPS_BOF: No SMPS Mode to be used in accordance to SMPS_BOF_STATIC =1 +When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only SMPS_BOF_STATIC=1. +- 0 : No effect, SMPS is enabled. (default) +- 1 : SMPS is disabled; + 7 + 1 + read-write + + + SMPSLPOPEN + SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode). +When this bit is set, when the chip is in Low power mode the SMPS regulator will be disabled (HZ) Documentation needed. +- 0 : in Low Power mode, SMPS is in PRECHARGE, output is connected to VDDIO. (default) +- 1 : in Low Power mode, SMPS is disabled, output is floating + 8 + 1 + read-write + + + SMPSFBYP + SMPSFB Force SMPS Regulator in bypass mode +When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. +- 0 : no effect (by default) +- 1 : SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1) + 9 + 1 + read-write + + + NOSMPS + NOSMPS: No SMPS Mode +When this bit is set, the SMPS regulator will be disabled. Note that this configuration should be used only when SMPS_FB pad is directly connected to VBATT or Vext, without L/C BOM. +- 0 : No effect, SMPS is enabled. (Default) +- 1 : SMPS is disabled; + 10 + 1 + read-write + + + SMPS_ENA_DCM + SMPS_ENA_DCM: enable discontinuous conduction mode +- 0 : disable (Default) +- 1 : enable + 11 + 1 + read-write + + + CLKDETR_DISABLE + CLKDETR_DISABLE: disable SMPS clock detection +The SMPS clock detection enables an automatic SMPS bypass switching in case of unwanted loss of SMPS clock. +- 0 : SMPS clock detection enabled (default) +- 1 : SMPS clock detection disabled + 12 + 1 + read-write + + + SMPS_PRECH_CUR_SEL + SMPS_PRECH_CUR_SEL[1:0] Selection for SMPS PRECHARGE limit current +- 00: 2.5mA +- 01: 5mA +- 10: 10mA +- 11: 20mA (default) + 13 + 2 + read-write + + + SMPS_BOF_DYN + SMPS_BOF_DYN: SMPS Bypass on the Fly dynamic +- 0 : disabled (by default) +- 1 : SMPS Bypass on the fly dynamic is enabled (EN_LDO=1) + 15 + 1 + read-write + + + + + PUCRA + PUCRA + PUCRA register + 0x20 + 0x20 + read-write + 0xFFF7 + + + PUA + PUA[x] : Pull Up Port A +Pull up activation on port A[i] pad when APC bit of PWRC CR1 is set +- 1: Pull-Up activated on port A[i] when APC bit of PWRC CR1 bit is set and PWR_PDCRA[x] is reset +- 0: Pull-Up not activated on port A[i] + 0 + 16 + read-write + + + + + PDCRA + PDCRA + PDCRA register + 0x24 + 0x20 + read-write + 0x8 + + + PDA + PDA[x]: Pull Down Port A +Pull Down activation on port A[i] pad when APC bit of PWRC CR1 is set +- 1: Pull-Down activated on Port A[i] when APC bit of PWRC CR1 bit is set +- 0: Pull-Down not activated on Port A[i] + 0 + 16 + read-write + + + + + PUCRB + PUCRB + PUCRB register + 0x28 + 0x20 + read-write + 0xFFFF + + + PUB + PUB[x] : Pull Up Port B +Pull up activation on port B[i] pad when APC bit of PWRC CR1 is set +- 1: Pull-Up activated on port B[i] when APC bit of PWRC CR1 bit is set and PWR_PDCRB[x] is reset +- 0: Pull-Up not activated on port B[i] + 0 + 16 + read-write + + + + + PDCRB + PDCRB + PDCRB register + 0x2c + 0x20 + read-write + 0x0 + + + PDB + PDB[x]: Pull Down Port B +Pull Down activation on port B[i] pad when APC bit of PWRC CR1 is set +- 1: Pull-Down activated on Port B[i] when APC bit of PWRC CR1 bit is set +- 0: Pull-Down not activated on Port B[i] + 0 + 16 + read-write + + + + + EWUA + EWUA + EWUA register + 0x30 + 0x20 + read-write + 0x0 + + + EWUA + EWUA[x] Enable WakeUp line PA[x] +When this bit is set the PA[x] wakeup line is enabled and a rising or falling edge on wakeup line PA[x] will trigger a CPU wakeup event depending on CR7.WUPA[x] bit. + 0 + 16 + read-write + + + + + WUPA + WUPA + WUPA register + 0x34 + 0x20 + read-write + 0x0 + + + WUPA + WUPA[x] Wake-up Line PA[x] Polarity +This bit defines the polarity used for event detection on external wake-up line PA[x] +- 0: Detection on high level (rising edge) +- 1: Detection on low level (falling edge) + 0 + 16 + read-write + + + + + WUFA + WUFA + WUFA register + 0x38 + 0x20 + read-write + 0x0 + + + WUFA + WUFA[x] WakeUp Flag PA[x] +This bit is set when a wakeup is detected on wakeup line PA[x]. It is cleared by a reset pad or by writing 1 in this bit field. +Writing 1 this bit, clears the interrupt: + 0 + 16 + read-write + + + + + EWUB + EWUB + EWUB register + 0x40 + 0x20 + read-write + 0x0 + + + EWUB + EWUB[x] Enable WakeUp line PB[x] +When this bit is set the PB[x] wakeup line is enabled and a rising or falling edge on wakeup line PB[x] will trigger a CPU wakeup event depending on CR9.WUPB[x] bit. + 0 + 16 + read-write + + + + + WUPB + WUPB + WUPB register + 0x44 + 0x20 + read-write + 0x0 + + + WUPB + WUPB[x] Wake-up Line PB[x] Polarity +This bit defines the polarity used for event detection on external wake-up line PB[x] +- 0: Detection on high level (rising edge) +- 1: Detection on low level (falling edge) + 0 + 16 + read-write + + + + + WUFB + WUFB + WUFB register + 0x48 + 0x20 + read-write + 0x0 + + + WUFB + WUFB[x] WakeUp Flag PB[x] +This bit is set when a wakeup is detected on wakeup line PB[x]. It is cleared by a reset pad or by writing 1 in this bit field. +Writing 1 this bit, clears the interrupt: + 0 + 16 + read-write + + + + + SDWN_WUEN + SDWN_WUEN + SDWN_WUEN register + 0x4c + 0x20 + read-write + 0x0 + + + WUEN + WUEN PB0 I/O WakeUp from shutdown Enable +When this bit is set the PB0 wakeup from shutdown is enabled so that a rising or falling edge on PB0 (depending on SDWN_WUPOL..WUPOL bit) will trigger a CPU wakeup. It is cleared by a PORESETn. +- 0: PB0 wakeup from shutdown disabled +- 1: PB0 wakeup from shutdown enabled + 0 + 1 + read-write + + + + + SDWN_WUPOL + SDWN_WUPOL + SDWN_WUPOL register + 0x50 + 0x20 + read-write + 0x0 + + + WUPOL + WUPOL PB0 I/O WakeUp from shutdown Polarity +This bit defines the polarity used for wakeup from shutdown detection on PB0 pin. It is cleared by a PORESETn. +- 0: Detection on high level (rising edge) +- 1: Detection on low level (falling edge) + 0 + 1 + read-write + + + + + SDWN_WUF + SDWN_WUF + SDWN_WUF register + 0x54 + 0x20 + read-write + 0x0 + + + WUF + WUF PB0 I/O WakeUp from shutdown Flag +This bit is set when a wakeup from shutdown is detected on PB0 pin. It is cleared by a PORESETn or by writing 0 in this bit field. +- 0: Shutdown wakeup from PB0 not occurred +- 1: Shutdown wakeup from PB0 occurred + 0 + 1 + read-write + + + + + BOF_TUNE + BOF_TUNE + BOF_TUNE register + 0x58 + 0x20 + read-write + 0x4 + + + BOF_TUNE + BOF_TUNE: selection of the Bypass on the Fly LDO output voltage. +- 0: 1.2V +- 1: 1.2V +- 2: 1.2V +- 3: 1.3V +- 4: 1.4V (Default) +- 5: 1.5V +- 6: 1.6V +- 7: 1.7V +- 8: 1.8V +- 9: 1.9V +- 10: 2V +- 11: 2.1V +- 12: 2.2V +- 13: 2.3V +- 14: 2.4V +- 15: 2.4V + 0 + 4 + read-write + + + + + DBGR + DBGR + DBGR register + 0x84 + 0x20 + read-write + 0x0 + + + DEEPSTOP2 + DEEPSTOP2 low power saving mode emulation enable +this bit enable an emulated debug DEEPSTOP low power mode. +If emulation is enabled, entering in DEEPSTOP mode, the v12i power domain still enters power saving mode, but its clock and power are maintained. + 0 + 1 + read-write + + + SMPSFRDY + SMPSFB Force ready check +When this bit is set, the SMPS regulator will be forced to operate in precharge mode. the actual state of SMPS can be observed thanks to the replica SR2.SMPSBYPR. +- 0 : no effect (by default) +- 1 : SMPS is disabled and bypassed (ENABLE_3V3=0 and PRECHARGE_3V3=1) + 7 + 1 + read-write + + + KELVIN_TEST + KELVIN_TEST[2:0]: Enable TEST mode Kelvin for LDO_RF (Write protected by IFR3 key) +- 000: 0mA (open) (default 0x0) +- 001 for 1mA +- 010 for 3mA +- 011 for 5mA +- 100 for 8mA +- 101 for 10mA +else: 0mA (open) for other combinations. + 8 + 3 + read-write + + + DIS_PRECH + DIS_PRECH[2:0]: disable precharge during deepstop (debug) +allowed combination are: +- 111: precharge and SMPS monitoring are disabled (whatever CR5.SMPSLPOPEN) +- 101: precharge are activated only at deepstop exit (to be used only with CR5.SMPSLPOPEN=1) +else: No effect (default 0x0) + 13 + 3 + read-write + + + + + EXTSRR + EXTSRR + EXTSRR register + 0x88 + 0x20 + read-write + 0x0 + + + DEEPSTOPF + DEEPSTOPF System DeepStop Flag +This bit is set by hardware and cleared only by a POR reset or by writing '1' in this bit field +- 0: System has not been in DEEPSTOP mode +- 1: System has been in DEEPSTOP mode + 9 + 1 + read-write + + + RFPHASEF + RFPHASEF RFPHASE Flag +This bit is set by hardware after a S3LP wake-up event (S3LP activation); it +is cleared either by software, writing '1' in this bit field, or by hardware when Ready2Sleep signal is asserted by the Radio IP. +- 0: RF IP does not require attention +- 1: RF IP awake and requesting system attention + 10 + 1 + read-write + + + + + DBGSMPS + DBGSMPS + DBGSMPS register + 0x8c + 0x20 + read-write + 0x8000 + + + TESTDIG + TESTDIG: SMPS TEST_DIG_3V3[3:0] SMPS control signal + 0 + 4 + read-write + + + TESTKEL + TESTKEL: SMPS TEST_KEL_3V3[1:0] SMPS control signal + 4 + 2 + read-write + + + HOT_STUP + HOT_STUP_3V3 SMPS control signal + 6 + 1 + read-write + + + NO_STUP + NO_STUP_3V3 SMPS control signal + 7 + 1 + read-write + + + TESTILIM + TESTILIM: SMPS TEST_ILIM_3V3 SMPS control signal + 8 + 1 + read-write + + + CTLRES_RAMP + CTLRES_RAM_3V3 SMPS control signal + 9 + 1 + read-write + + + DIS_BIG_MOS + DIS_BIG_MOS_3V3 SMPS control signal + 10 + 1 + read-write + + + TEST_OL + TEST_OL_3V3 SMPS control signal + 11 + 1 + read-write + + + DIS_ILIM + DIS_ILIM_3V3 SMPS control signal + 12 + 1 + read-write + + + ILIM_BOOST + ILIM_BOOST_3V3 SMPS current limitation Boost +- 0: Max current = 110mA (Default) +- 1: Max current = 130mA + 13 + 1 + read-write + + + BOF_CUR_SEL + BOF_CUR_SEL Bypass On the Fly current limitation +- 00 : 20mA +- 01 : 40mA +- 10 : 60mA (default) +- 11 : no limit + 14 + 2 + read-write + + + + + TRIMR + TRIMR + TRIMR register + 0x90 + 0x20 + read-only + 0x2304 + + + RFD_REG_TRIM + RFD_REG_TRIM[2:0]: RF LDO Trimming +By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. +if associated ENGTRIM is enabled the RF LDO trimming can be controlled by the dedicated ENGTRIM register. Default= '100'. + 0 + 3 + read-only + + + SPARE + 3 + 1 + read-only + + + TRIM_MR + TRIM_MR[3:0]: Main Regulator Voltage Trimming +By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. +if associated ENGTRIM.TRIMMREN is enabled the Main Regulator Voltage can be controlled by the dedicated ENGTRIM.TRIM_MR register. Default= '0000'. + 4 + 4 + read-only + + + SMPS_TRIM + SMPS_TRIM[2:0]: SMPS Output Voltage Trimming +By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. +if associated ENGTRIM is enabled the SMPS output voltage can be controlled by the dedicated ENGTRIM register. Default= '011'. + 8 + 3 + read-only + + + BOF_TRIM + BOF_TRIM[2:0]: Bypass On the Fly Output Voltage Trimming +By default, this value is taken from the engi bytes; and saved on V12o domain when OBL done. +if associated ENGTRIM is enabled the SMPS output voltage can be controlled by the dedicated ENGTRIM register. Default= '100'. + 11 + 3 + read-only + + + + + ENGTRIM + ENGTRIM + ENGTRIM register + 0x94 + 0x20 + read-write + 0x0 + + + TRIMRFDREGEN + TRIMRFDREGEN: trimming RFREG enabled +- 1: trimming bit applied from ENGTRIM register +- 0: trimming bit applied from OBL (can be read on TRIMR register) + 0 + 1 + read-write + + + TRIM_RFDREG + TRIM_RFDREG: RF Regulator Trimming +By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.TRIMRFDREGEN=1, the startup current can be controlled by this register. + 1 + 3 + read-write + + + SPARE + 4 + 1 + read-write + + + TRIMMREN + TRIMMREN: trimming MR enabled +- 1: trimming bit applied from ENGTRIM register +- 0: trimming bit applied from OBL (can be read on TRIMR register) + 5 + 1 + read-write + + + TRIM_MR + TRIM_MR: Main Regulator Output Voltage Trimming +By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.TRIMMREN=1, the startup current can be controlled by this register. + 6 + 4 + read-write + + + SMPSTRIMEN + SMPSTRIMEN: trimming SMPS enabled +- 1: trimming bit applied from ENGTRIM register +- 0: trimming bit applied from OBL (can be read on TRIMR register) + 10 + 1 + read-write + + + SMPS_TRIM + SMPS_TRIM: SMPS Output Voltage Trimming +By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.SMPSTRIMEN=1, the SMPS output voltage can be controlled by this register. + 11 + 3 + read-write + + + + + DBG_STATUS_REG1 + DBG_STATUS_REG1 + DBG_STATUS_REG1 register + 0x98 + 0x20 + read-only + 0x202 + + + SMPS_FSM_STATE + SMPS_FSM_STATE[2:0]: Indicates the current state of the SMPS FSM inside the PWRC.: +- 000: STARTUP +- 001: SMPS_REQ +- 010: SMPS_RUN +- 011: STOP +- 100: NOSMPS +- 101: PRECHARGE +- 110: NOSMPS_BOF + 0 + 3 + read-only + + + FLASH_FSM_STATE + FLASH_FSM_STATE[2:0]: Indicates the current state of the FLASH FSM inside the PWRC: +- 000: STATE1: FLASH POR +- 001: STATE2: FLASH PWRUP +- 010: STATE3: FLASH READY +- 101: STATE4: FLASH SWITCH OFF +- 110: STATE5: FLASH PWR DOWN + 8 + 3 + read-only + + + + + DBG_STATUS_REG2 + DBG_STATUS_REG2 + DBG_STATUS_REG2 register + 0x9c + 0x20 + read-only + 0x201 + + + PMU_FSM_STATE + PMU_FSM_STATE[3:0]: Indicates the current state of the PMU FSM inside the PWRC. +- 0000: POR +- 0001: RUN +- 0010: DS ENTRY +- 0011: WAIT1 +- 0100: WAIT2 +- 0101: WAIT +- 0110: WAIT3 +- 0111: WAIT4 +- 1000: ISOLATION +- 1001: DEEPSTOP +- 1010: SHUTDOWN +- 1011: DEEPSTOP EXIT + 0 + 4 + read-only + + + RAM_FSM_STATE + RAM_FSM_STATE[1:0]: Indicates the current state of the RAM FSM inside the PWRC: +- 00: POR +- 01: POWER UP +- 10: READY +- 11: OFF + 8 + 2 + read-only + + + + + ENGTRIM2 + ENGTRIM2 + ENGTRIM2 register + 0xa0 + 0x20 + read-write + 0x0 + + + BOFTRIMEN + BOFTRIMEN: trimming BOF enabled +- 1: trimming bit applied from ENGTRIM2 register +- 0: trimming bit applied from OBL (can be read on TRIMR register) + 0 + 1 + read-write + + + BOF_TRIM + SMPS_TRIM: SMPS Output Voltage Trimming +By default, this value is not applied, but taken from the engi bytes; if ENGTRIM.BOFTRIMEN=1, the SMPS output voltage can be controlled by this register. + 1 + 3 + read-write + + + + + + + RCC + RCC + 0x48400000 + + 0x0 + 0xB0 + registers + + + RCC + Reset and Clock Controller + 1 + + + + CR + CR + CR register + 0x0 + 0x20 + read-write + 0x00001400 + + + LSION + Internal Low Speed oscillator enable +Set and reset by software. +Reset source only for this field: PORESETn +0: LSI RC oscillator OFF +1: LSI RC oscillator ON + 2 + 1 + read-write + + + LSIRDY + Internal Low Speed oscillator Ready +Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. +Reset source only for this field: PORESETn +0: LSI RC oscillator not ready +1: LSI RC oscillator ready + 3 + 1 + read-only + + + LSEON + External Low Speed Clock enable. +Set and reset by software. +Reset source only for this field: PORESETn +0: LSE oscillator OFF +1: LSE oscillator ON +Note that enablng this bit, the configuration of PB12 and PB13 will be bypassed (whatever DFTMUX or AF selection) + 4 + 1 + read-write + + + LSERDY + External Low Speed Clock ready flag. +Set by hardware to indicate that LSE oscillator is stable. +0: LSE oscillator not ready +1: LSE oscillator ready + 5 + 1 + read-only + + + LSEBYP + External Low Speed Clock bypass. +Set and reset by software. +Reset source only for this field: PORESETn +0: LSE oscillator bypass OFF +1: LSE oscillator bypass ON +Note that enablng this bit, the configuration of PB13 will be bypassed (whatever DFTMUX or AF selection) + 6 + 1 + read-write + + + LOCKDET_NSTOP + Lock detector Nstop value +When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0. + 7 + 3 + read-write + + + HSIRDY + Internal High Speed clock ready flag. +Set by hardware to indicate that internal RC 64MHz oscillator is stable. +This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request). +0: internal RC 64 MHz oscillator not ready +1: internal RC 64 MHz oscillator ready + 10 + 1 + read-only + + + HSEPLLBUFON + External High Speed Clock Buffer for PLL RF enable. +Set and reset by software. +0: HSE PLL Buffer OFF +1: HSE PLL Buffer ON (default) + 12 + 1 + read-write + + + HSIPLLON + Internal High Speed Clock PLL enable +0: PLL is OFF +1: PLL is ON + 13 + 1 + read-write + + + HSIPLLRDY + Internal High Speed Clock PLL ready flag. +0: PLL is unlocked +1: PLL is locked + 14 + 1 + read-only + + + FMRAT + Force MRSUBG accurate clock ready status (for debug purpose) +0: no effect +1: active_transmission is force to '1' whatever the HSIPLLRDY/HSE status + 15 + 1 + read-write + + + HSEON + External High Speed Clock enable. +Set and reset by software. +in low power mode, HSE is turned off. +HSE is turned ON only when RFSUBG LDO is Ready +0: HSE oscillator OFF +1: HSE oscillator ON + 16 + 1 + read-write + + + HSERDY + External High Speed Clock ready flag. +Set by hardware to indicate that HSE oscillator is stable. +0: HSE oscillator not ready +1: HSE oscillator ready + 17 + 1 + read-only + + + + + ICSCR + ICSCR + ICSCR register + 0x4 + 0x20 + read-write + 0x3f000000 + + + LSITRIMEN + Low Speed oscillator trimming enable +Set and reset by software. +Reset source only for this field: PORESETn +0: LSI oscillator Bias trimming disabled +1: LSI oscillator Bias trimming enabled + 0 + 1 + read-write + + + LSITRIMOK + LSITRIMOK: Low Speed oscillator trimming OK +Set and reset by hardware to indicate when the Low Speed Internal RC oscillator has reached an optimal trimming of its bias current; this bit is only valid when LSITRIMEN is active. +0: LSI Bias trimming (LSIBW) is not good +1: LSI Bias trimming (LSIBW) value is OK + 1 + 1 + read-only + + + LSIBW + Trimming in test mode +The value stored is the correspondent Engi Byte and represents the actual value driving the input of the hardware macro. +This value is loaded soon after the completion of the Option Byte Loading procedure. +This field is directly writeable only in Test Mode. + 2 + 4 + read-only + + + HSITRIMOFFSET + ICSCR[18:16] = HSITRIMOFFSET[2:0]: High Speed oscillator signed trimming offset + 000: 0 (+ 0 MHz / default) + 001: 1 (-0.5 MHz) + 010: 2 (-1MHz) + 011: 3 (-1.5 MHz) + 100: -1 (+2 MHz) + 101: -2 (+1.5MHz) + 110: -3 (+1 MHz) + 111: -4 (+0.5 MHz) + 16 + 3 + read-write + + + HSITRIM + High Speed Internal clock trimming. +This value is loaded soon after the completion of the Option Byte Loading procedure. +When max value 0x3f is set, HSI is less than 64MHz + 24 + 6 + read-only + + + + + CFGR + CFGR + CFGR register + 0x8 + 0x20 + read-write + 0x00000240 + + + HSESEL + Clock source selection request: +0: HSI clock source is requested (default) +1: HSE clock source is requested + 1 + 1 + read-write + + + STOPHSI + Stop HSI clock source request +0: HSI is enabled (default) +1: disable HSI is requested + 2 + 1 + read-write + + + HSESEL_STATUS + Clock source selection Status +0: HSI clock source is selected +1: HSE clock source is selected +Mirror the actual system clock source, depending on clock switching mechanism and limitations + 3 + 1 + read-only + + + CLKSYSDIV + system clock frequency selection request +000: div1 (HSI 64M / HSE 48M) +001: div2 (HSI 32M / HSE 24M) +010: div4/div3 (HSI/HSE) (16M) +011: div8/div6 (HSI/HSE) (8M) * +100: div16/div12 (HSI/HSE) (4M) * +101: div32/div24 (HSI/HSE) (2M) * +110: div64/div48 (HSI/HSE) (1M) * +Note: behavior depends on depending on CFGR.HSESEL and (*) APB2ENR.MRSUBGEN or LPAWUREN register + 5 + 3 + read-write + + + CLKSYSDIV_STATUS + system clock frequency selection status +000: div1 (HSI 64M / HSE 48M) +001: div2 (HSI 32M / HSE 24M) +010: div4/div3 (HSI/HSE) (16M) +011: div8/div6 (HSI/HSE) (8M) +100: div16/div12 (HSI/HSE) (4M) +101: div32/div24 (HSI/HSE) (2M) +110: div64/div48 (HSI/HSE) (1M) +Note: behavior depends on depending on CFGR.HSESEL and APB2ENR.MRSUBGEN register + 8 + 3 + read-only + + + SMPSDIV + SMPS clock prescaling factor to generate 4MHz or 8MHz +0: SMPS clock 8MHz (default ) +1: SMPS clock 4MHz + 12 + 1 + read-write + + + LPUCLKSEL + LPUCLKSEL: Selection of LPUART clock +0: 16 MHz peripheral clock (default) +1: LSE clock (Mandatory in LPUART deepstop mode) + 13 + 1 + read-write + + + CLKSLOWSEL + slow clock source selection +Set by software to select the clock source. This is no glitch free mechanism +Reset source only for this field: PORESETn +00: '0' (default) +01: LSE oscillator clock used as slow clock +10: LSI oscillator clock used as slow clock +11:HSI_64M divided by 2048 used as slow clock + 15 + 2 + read-write + + + IOBOOSTEN + IOBOOSTEN: IO BOOSTER enable +0: IO BOOSTER block is disabled +1: IO BOOSTER block is enabled. + 17 + 1 + read-write + + + LCOEN + LCOEN: LCO enable on PA10 also in deepstop. +0: LCO output on PA10 is disabled +1: LCO output on PA10 is enabled. + 19 + 1 + read-write + + + SPI3I2SCLKSEL + SPI3I2SCLKSEL: Selection of I2S clock for SPI3 IP. +00: 32 MHz peripheral clock (default) +01: 16 MHz peripheral clock +10: CLK_SYS +11: CLK_SYS +Note: the I2S clock frequency must be higher or equal to the system clock (configured +through RCC_CFGR.CLKSYSDIV[2:0] bit field). + 22 + 2 + read-write + + + LCOSEL + Low speed Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. +Reset source only for this field: PORESETn +00: LCO output disabled, no clock on LCO +01: not used +10: internal 32 KHz (LSI) oscillator clock selected +11: external 32 KHz (LSE) oscillator clock selected + 24 + 2 + read-write + + + MCOSEL + Main Configurable Clock Output Selection. +Set and reset by software. Glitches propagation possible. +000: MCO output disabled, no clock on MCO +001: system clock selected +010: na +011: internal RC 64 MHz (HSI) oscillator clock selected +100: external oscillator (HSE) clock selected +101: internal RC 64 MHz (HSI) oscillator divided by 2048 and used as slow clock selected +110: SMPS clock selected +111: AUX ADC ANA clock selected + 26 + 3 + read-write + + + CCOPRE + Configurable Clock Output Prescaler. +Set and reset by software. +Glitches propagation if CCOPRE is modified after CCO output is enabled. +000: CCO clock is divided by 1 +001: CCO clock is divided by 2 +010: CCO clock is divided by 4 +011: CCO clock is divided by 8 +100: CCO clock is divided by 16 +101: CCO clock is divided by 32 +Others: not used + 29 + 3 + read-write + + + + + CSSWCR + CSSWCR + CSSWCR register + 0xc + 0x20 + read-write + 0x00000000 + + + LSISWTRIMEN + Low Speed oscillator trimming by SW enable +Set and reset by software. +Reset source only for this field: PORESETn +0: LSI oscillator Bias trimming by SW disabled +1: LSI oscillator Bias trimming by SW enabled + 0 + 1 + read-write + + + LSISWBW + Low Speed Internal clock trimming value to set by SW +Reset source only for this field: PORESETn + 1 + 4 + read-write + + + LSEDRV + Maximum Crystal gm for Low Speed External XO +(to connect to XTDRV of 32kHz LSE XO => into IO V33?) to amplify drinving capacity modulation +Set by software. +Reset source only for this field: PORESETn +00: 0.0, low drive capability +01: 0.1, medium low drive capability +10: 1.0, medium high drive capability +11: 1.1, highdrive capability + 5 + 2 + read-write + + + HSISWTRIMEN + High Speed oscillator trimming by SW enable +Set and reset by software. +0: HSI oscillator Bias trimming by SW disabled +1: HSI oscillator Bias trimming by SW enabled + 23 + 1 + read-write + + + HSITRIMSW + High Speed Internal clock trimming value to set by SW. + 24 + 6 + read-write + + + + + KRMR + KRMR + KRMR register + 0x10 + 0x20 + read-write + 0x000000000 + + + KRM_EN + KRM_EN: Variable rate multiplier Enable +Reset source only for this field: PORESETn +0: KRM is disabled (default) +1: KRM is enabled. + 0 + 1 + read-write + + + KRM + KRM[4:0] :SMPS clock dividing Ratio (CLK_SPMS_KRM frequency= CLK_ROOT frequency +(depending on RCC_CFGR.HSESEL) divided by KRM when KRMEN=1) +Reset source only for this field: PORESETn +- 0x00 to 0x08: SMPS clock frequency equals CLK_ROOT/8 (8.00 MHz / 6.00 MHz) +- 0x09: SMPS clock frequency equals CLK_ROOT/9 (7.11 MHz / 5.33 MHz) +- 0x0A: SMPS clock frequency equals CLK_ROOT/10 (6.40 MHz / 4.80 MHz) +- 0x0B: SMPS clock frequency equals CLK_ROOT/11 (5.82 MHz / 4.36 MHz) +- 0x0C: SMPS clock frequency equals CLK_ROOT/12 (5.33 MHz / 4.00 MHz) +- 0x0D: SMPS clock frequency equals CLK_ROOT/13 (4.92 MHz / 3.69 MHz) +- 0x0E: SMPS clock frequency equals CLK_ROOT/14 (4.57 MHz / 3.43 MHz) +- 0x0F: SMPS clock frequency equals CLK_ROOT/15 (4.27 MHz / 3.20 MHz) +- 0x10: SMPS clock frequency equals CLK_ROOT/16 (4.00 MHz / 3.00 MHz) +- 0x1x: Reserved +Note: SMPS clock frequency must be selected in a range [4-8] MHz (depending on +RCC_KRMR.KRM and RCC_CFGR.HSESEL). + 1 + 5 + read-write + + + + + CIER + CIER + CIER register + 0x18 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by internal RC 32 kHz oscillator stabilization. +0: LSI ready interrupt disabled +1: LSI ready interrupt enabled + 0 + 1 + read-write + + + LSERDYIE + LSE Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. +0: LSE ready interrupt disabled +1: LSE ready interrupt enabled + 1 + 1 + read-write + + + HSIRDYIE + HSI Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the internal RC 64MHz oscillator stabilization. +0: HSI ready interrupt disabled +1: HSI ready interrupt enabled + 3 + 1 + read-write + + + HSERDYIE + HSE Ready Interrupt Enable +Set and reset by software to enable/disable interrupt caused by the external HSE oscillator stabilization. +0: HSE ready interrupt disabled +1: HSE ready interrupt enabled + 4 + 1 + read-write + + + HSIPLLRDYIE + HSI PLL Ready Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL locked on HSE. +0: HSI PLL ready interrupt disabled +1: HSI PLL ready interrupt enabled + 5 + 1 + read-write + + + HSIPLLUNLOCKDETIE + HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the HSI 64MHz PLL unlock. +0: HSI PLL unlock detection interrupt disabled +1: HSI PLL unlock detection interrupt enabled + 6 + 1 + read-write + + + RTCRSTIE + RTCRSTIE: RTC reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the RTC reset end. +0: HSI PLL unlock detection interrupt disabled +1: HSI PLL unlock detection interrupt enabled + 7 + 1 + read-write + + + WDGRSTIE + WDGRSTIE: Watchdog reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the watchdog reset end. +0: interrupt disabled +1: interrupt enabled + 8 + 1 + read-write + + + LPURSTIE + LPURSTIE: LPUART reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the LPUART reset end. +0: interrupt disabled +1: interrupt enabled + 9 + 1 + read-write + + + LCDRSTIE + LCDRSTIE: LCD reset end Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the LCD reset end. +0: interrupt disabled +1: interrupt enabled + 10 + 1 + read-write + + + LCSCRSTIE + LCSCRSTIE: LCSC reset release interrupt enable. +0: LCSC reset release interrupt is disabled. +1: LCSC reset release interrupt is enabled. + 13 + 1 + read-write + + + + + CIFR + CIFR + CIFR register + 0x1c + 0x20 + read-write + 0x00000008 + + + LSIRDYIF + LSI Ready Interrupt flag +Set by hardware when LSI clock becomes stable. +0: No clock ready interrupt caused by the internal RC 32 KHz oscillator +1: Clock ready interrupt caused by the internal RC 32 kHz oscillator + 0 + 1 + read-write + + + LSERDYIF + LSE Ready Interrupt Flag. +Set by hardware when LSE clock becomes stable. +0: No clock ready interrupt caused by the LSE oscillator +1: Clock ready interrupt caused by the LSE oscillator + 1 + 1 + read-write + + + HSIRDYIF + HSI Ready Interrupt Flag. +Set by hardware when HSI becomes stable. +0: No clock ready interrupt caused by the HSI oscillator +1: Clock ready interrupt caused by the HSI oscillator + 3 + 1 + read-write + + + HSERDYIF + HSE Ready Interrupt Flag. +Set by hardware when HSE becomes stable. +0: No clock ready interrupt caused by the HSE oscillator +1: Clock ready interrupt caused by the HSE oscillator + 4 + 1 + read-write + + + HSIPLLRDYIF + HSI PLL Ready Interrupt Flag. +Set by hardware when HSI PLL 64MHz becomes stable. +0: No clock ready interrupt caused by the HSI PLL64 MHz oscillator +1: Clock ready interrupt caused by the HSI PLL64 MHz oscillator + 5 + 1 + read-write + + + HSIPLLUNLOCKDETIF + HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag. + 6 + 1 + read-write + + + RTCRSTIF + RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 7 + 1 + read-write + + + WDGRSTIF + WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 8 + 1 + read-write + + + LPURSTIF + LPUART reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 9 + 1 + read-write + + + LCDRSTIF + LCD reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 10 + 1 + read-write + + + LCSCRSTIF + LCSC reset end Interrupt Flag. Raised when reset is released on 32kHz clock + 13 + 1 + read-write + + + + + CSCMDR + CSCMDR + CSCMDR register + 0x20 + 0x20 + read-write + 0x00000080 + + + REQUEST + Request for system clock switching +Cleared by hardware when system clock frequency switch is done +0: To cancel an ongiong request - still possible until IRQ assertion +1: To update the system clock frequency + 0 + 1 + read-write + + + CLKSYSDIV_REQ + system clock frequency selection request +000: div1 (HSI 64M / HSE) (48M) +001: div2 (HSI 32M / HSE (24M*) +010: div4/div3 (HSI/HSE) (16M) +011: div8/div6 (HSI/HSE) (8M) * +100: div16/div12 (HSI/HSE) (4M) * +101: div32/div24 (HSI/HSE) (2M) * +110: div64/div48 (HSI/HSE) (1M) * +Note: behavior depends on depending on CFGR.HSESEL and (*) APB2ENR.MRSUBGEN or LPAWUREN + 1 + 3 + read-write + + + STATUS + Status of clock switch sequence +00: IDLE no switch requested +01: ONGOING clock frequency switch is ongoing +10: DONE clock frequency switch done +11: Reserved + 4 + 2 + read-only + + + EOFSEQ_IE + End of sequence Interrupt Enable. +Set and reset by software to enable/disable interrupt caused by the clock system switch. +0: End of sequence interrupt disabled +1: End of sequence interrupt enabled + 6 + 1 + read-write + + + EOFSEQ_IRQ + End of Sequence flag +Set by hardware when clock system swtich is ended +0: No end of sequence event occured +1: End of sequece event occured + 7 + 1 + read-write + + + + + AHBRSTR + AHBRSTR + AHBRSTR register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMARST + DMA and DMAMUX reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 0 + 1 + read-write + + + GPIOARST + GPIOA reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 2 + 1 + read-write + + + GPIOBRST + GPIOB reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 3 + 1 + read-write + + + CRCRST + CRC reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 12 + 1 + read-write + + + RNGRST + RNG reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 18 + 1 + read-write + + + AESRST + AES reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 20 + 1 + read-write + + + + + APB0RSTR + APB0RSTR + APB0RSTR register + 0x34 + 0x20 + read-write + 0x00000000 + + + TIM2RST + TIM2RST: TIM2 reset. +0: TIM2 IP is not under reset. +1: TIM2 IP is under reset. + 0 + 1 + read-write + + + TIM16RST + TIM16RST: TIM16 reset. +0: TIM16 IP is not under reset. +1: TIM16 IP is under reset. + 1 + 1 + read-write + + + SYSCFGRST + SYSCFGRST: system controller reset. +0: system controller IP is not under reset. +1: system controller IP is under reset. + 8 + 1 + read-write + + + LCDCRST + LCDCRST: LCD controller reset. +0: LCD controller IP is not under reset. +1: LCD controller IP is under reset. + 9 + 1 + read-write + + + COMPRST + COMPRST: COMP reset. +0: COMP IP is not under reset. +1: COMP IP is under reset. + 10 + 1 + read-write + + + DACRST + DACRST: DAC reset. +0: DAC IP is not under reset. +1: DAC IP is under reset. + 11 + 1 + read-write + + + RTCRST + RTCRST: RTC reset. +0: RTC IP is not under reset. +1: RTC IP is under reset. + 12 + 1 + read-write + + + LCSCRST + LCSCRST: LCSC reset. +0: LCSC IP is not under reset. +1: LCSC IP is under reset. + 13 + 1 + read-write + + + WDGRST + WDGRST: Watchdog reset. +0: Watchdog IP is not under reset. +1: Watchdog IP is under reset. + 14 + 1 + read-write + + + DBGMCURST + DBGMCURST: DBGMCU reset. +0: DBGMCU IP is not under reset. +1: DBGMCU IP is under reset. + 15 + 1 + read-write + + + + + APB1RSTR + APB1RSTR + APB1RSTR register + 0x38 + 0x20 + read-write + 0x00000000 + + + SPI1RST + SPI1 reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 0 + 1 + read-write + + + ADCRST + ADC reset for Aux-ADC IP +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 4 + 1 + read-write + + + LPUARTRST + LPUART reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 8 + 1 + read-write + + + USARTRST + USART reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 10 + 1 + read-write + + + SPI3RST + SPI3 reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 14 + 1 + read-write + + + I2C1RST + I2C1 reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 21 + 1 + read-write + + + I2C2RST + I2C2 reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 23 + 1 + read-write + + + + + APB2RSTR + APB2RSTR + APB2RSTR register + 0x40 + 0x20 + read-write + 0x00000000 + + + MRSUBGRST + Radio MRSUBG reset. +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 0 + 1 + read-write + + + LPAWURRST + Bubble reset +Set and reset by software. +0: IP is not under reset. +1: IP is under reset. + 3 + 1 + read-write + + + + + AHBENR + AHBENR + AHBENR register + 0x50 + 0x20 + read-write + 0x0000000C + + + DMAEN + DMA and DMAMUX enable +Set and enable by software. +0: does not enable +1: enable + 0 + 1 + read-write + + + GPIOAEN + GPIOA enable. It must be enabled by default + 2 + 1 + read-write + + + GPIOBEN + GPIOB enable. It must be enabled by default + 3 + 1 + read-write + + + CRCEN + CRC enable +Set and enable by software. +0: does not enable +1: enable + 12 + 1 + read-write + + + RNGEN + RNG clock enable +Set and enable by software. +0: does not enable +1: enable + 18 + 1 + read-write + + + AESEN + AESEN: AES clock enable. +0: AES IP is clock gated. +1: AES IP is clocked. + 20 + 1 + read-write + + + + + APB0ENR + APB0ENR + APB0ENR register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM2: Advanced Timer clock enable +Set and enable by software. +0: clock disable +1: clock enable + 0 + 1 + read-write + + + TIM16EN + TIM16: Advanced Timer clock enable +Set and enable by software. +0: clock disable +1: clock enable + 1 + 1 + read-write + + + SYSCFGEN + SYSTEM CONFIG clock enable +Set and enable by software. +0: clock disable +1: clock enable + 8 + 1 + read-write + + + LCDEN + LCD clock enable +Set and enable by software. +0: clock disable +1: clock enable + 9 + 1 + read-write + + + COMPEN + COMP clock enable +Set and enable by software. +0: clock disable +1: clock enable + 10 + 1 + read-write + + + DACEN + DAC clock enable +Set and enable by software. +0: clock disable +1: clock enable + 11 + 1 + read-write + + + RTCEN + RTC clock enable +Set and enable by software. +Reset source only for this field: PORESETn +0: clock disable +1: clock enable + 12 + 1 + read-write + + + LCSCEN + LCSC clock enable. +Set and enable by software. +0: clock disable +1: clock enable + 13 + 1 + read-write + + + WDGEN + Watchdog clock enable. +Set and enable by software. +0: clock disable +1: clock enable + 14 + 1 + read-write + + + DBGMCUEN + DBG MCU clock enable. +Set and enable by software. +0: clock disable +1: clock enable + 15 + 1 + read-write + + + + + APB1ENR + APB1ENR + APB1ENR register + 0x58 + 0x20 + read-write + 0x00000000 + + + SPI1EN + SPI1 clock enable +Set and enable by software. +0: clock disable +1: clock enable + 0 + 1 + read-write + + + ADCDIGEN + AUXADC clock enable for Aux-ADC digital clock +Set and enable by software. +0: clock disable +1: clock enable + 4 + 1 + read-write + + + ADCANAEN + ADC clock enable for Aux-ADC analog clock +Set and enable by software. +0: clock disable +1: clock enable + 5 + 1 + read-write + + + LPUARTEN + LPUART clock enable +Set and enable by software. +0: clock disable +1: clock enable + 8 + 1 + read-write + + + USARTEN + USART clock enable +Set and enable by software. +0: clock disable +1: clock enable + 10 + 1 + read-write + + + SPI3EN + SPI3 clock enable +Set and enable by software. +0: clock disable +1: clock enable + 14 + 1 + read-write + + + I2C1EN + I2C1 clock enable +Set and enable by software. +0: clock disable +1: clock enable + 21 + 1 + read-write + + + I2C2EN + I2C2 clock enable +Set and enable by software. +0: clock disable +1: clock enable + 23 + 1 + read-write + + + + + APB2ENR + APB2ENR + APB2ENR register + 0x60 + 0x20 + read-write + 0x00000000 + + + MRSUBGEN + MRSUBG clock enable. +Note: when this bit is '1', it must prevent clk_sys different from 16, 32, 64. If the configured clock is lower than 16MHz (1, 2, 4 or 8 MHz) or equal to 24MHz, clk_sys must be 16MHz +0: clock disable +1: clock enable + 0 + 1 + read-write + + + LPAWUREN + Bubble clock enable +Set and enable by software. +0: clock disable +1: clock enable + 3 + 1 + read-write + + + + + DBGR + DBGR + DBGR register + 0x80 + 0x20 + read-write + 0x00000000 + + + DBGHSIOFF + used for debug or test +0: No effect (default) +1: HSI forced off. + 19 + 1 + read-write + + + DBGBYPHSI + used for debug mode with HSI bypassed by HSE +0: No effect (default) +1: HSI bypassed HSE. + 20 + 1 + read-write + + + DBGXOEXT + used for debug mode with HSE bypassed by FXTAL_IN clock and ZIV12 output used. +0: No effect (default) +1: HSE bypassed by FXTAL_IN clock and ZIV12 output used. + 21 + 1 + read-write + + + FORCEXO48MREADY + FORCEXO48MREADY Force XO48M Ready input signal +This bit is for debug and force the XO48M ready input, in order to bypass XO48M comparators. +0: No effect (default) +1: Force XOREADY=1 + 22 + 1 + read-write + + + + + CSR + CSR + CSR register + 0x94 + 0x20 + read-write + 0x0C000000 + + + RMVF + Remove reset flag +Set by software to clear the value of the reset flags. +It auto clears by HW after clearing reason flags +0: Nothing done +1: Reset the value of the reset flags + 23 + 1 + write-only + + + PADRSTF + SYSTEM reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a reset from pad occurs. +0: No reset from pad occurred +1: Reset from pad occurred + 26 + 1 + read-only + + + PORRSTF + POWER reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a power reset occurs from LPMURESET block. +0: No POWER reset occurred +1: POWER reset occurred + 27 + 1 + read-only + + + SFTRSTF + Software reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a software reset occurs. +0: No software reset occurred +1: Software reset occurred + 28 + 1 + read-only + + + WDGRSTF + Watchdog reset flag +Reset by software by writing the RMVF bit. +Set by hardware when a watchdog reset from V33 domain occurs. +0: No watchdog reset occurred +1: Watchdog reset occurred + 29 + 1 + read-only + + + LOCKUPRSTF + LOCK UP reset flag from CM0 +Reset by software by writing the RMVF bit. +Set by hardware from unrecoverable exception CPU. It reset V12i domain, FLASH controller and peripherals. +0: No lockup reset occurred +1: lockup reset occurred + 30 + 1 + read-only + + + + + RFSWHSECR + RFSWHSECR + RFSWHSECR register + 0x98 + 0x20 + read-write + 0x00000803F + + + GMC + GMC[6:5]: High speed external XO current control reference +00: 10 uA +01: 20 uA +1x: 40 uA +GMC[4:0]: High speed external XO current control multiplying factor +IcoreHSE= GMC[4:0] * GMC[6:5] +Example: GMC[6:0]=0x1111001 -> IcoreHSE=25*40uA / Default 3F: IcoreHSE= 10uA x 31 = 310uA +Note: this value is set only by software. + 0 + 7 + read-write + + + SWXOTUNEEN + RF-HSE capacitor bank tuning by SW enable +Set by software + 7 + 1 + read-write + + + SWXOTUNE + RF-HSE capacitor bank tuning value by SW +Set by software + 8 + 6 + read-write + + + ISTARTUP + RF-HSE Startup current +Set by software +Default value 2 + 14 + 2 + read-write + + + AMPLTHRESH + RF-HSE Amplitude Control threshold +Set by software +Default value 0 + 16 + 3 + read-write + + + + + RFHSECR + RFHSECR + RFHSECR register + 0x9c + 0x20 + read-only + 0x000000000 + + + XOTUNE + RF-HSE capacitor bank tuning +Set by option byte loading soon after Power On Reset. + 0 + 6 + read-only + + + AMPLREADY + RF-HSE Amplitude Control Ready output + 6 + 1 + read-only + + + + + AHBSMENR + AHBSMENR + AHBSMENR register + 0xa0 + 0x20 + read-write + 0x0014160F + + + DMASMEN + DMA clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: DMA clock disabled in Sleep mode +- 1: DMA clock enabled in Sleep mode (if enabled in DMAEN) + 0 + 1 + read-write + + + FLASHSMEN + Flash clocks enable during Flash Sleep PD and CPU Sleep mode bit +This bit is set and reset by software. +- 0: Flash clocks are disabled in Flash Sleep PD* and CPU Sleep mode +- 1: Flash clocks are enabled in Sleep mode +Note: Flash Sleep PD is enabled through nvm_control register CONFIG.SLEEP_PD + 1 + 1 + read-write + + + GPIOASMEN + GPIOA clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: GPIOA clock disabled in Sleep mode +- 1: GPIOA clock enabled in Sleep mode (if enabled by GPIOAEN) + 2 + 1 + read-write + + + GPIOBSMEN + GPIOB clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: GPIOB clock disabled in Sleep mode +- 1: GPIOB clock enabled in Sleep mode (if enabled in GPIOBEN) + 3 + 1 + read-write + + + SRAM0SMEN + SRAM0 clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SRAM0 clock disabled in Sleep mode +- 1: SRAM0 clock enabled in Sleep mode + 9 + 1 + read-write + + + SRAM1SMEN + SRAM1 clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SRAM1 clock disabled in Sleep mode +- 1: SRAM1 clock enabled in Sleep mode + 10 + 1 + read-write + + + CRCSMEN + CRC clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: CRC clock disabled in Sleep mode +- 1: CRC clock enabled in Sleep mode (if enabled in CRCEN) + 12 + 1 + read-write + + + RNGSMEN + RNG bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: RNG bus clock disabled in Sleep mode +- 1: RNG bus clock enabled in Sleep mode (if enabled in RNGEN) + 18 + 1 + read-write + + + AESSMEN + AES bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: AES bus clock disabled in Sleep mode +- 1: AES bus clock enabled in Sleep mode (if enabled in AESEN) + 20 + 1 + read-write + + + + + APB0SMENR + APB0SMENR + APB0SMENR register + 0xa4 + 0x20 + read-write + 0x0000FF03 + + + TIM2SMEN + TIM2 bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: TIM2 bus clock disabled in Sleep mode +- 1: TIM2 bus clock enabled in Sleep mode (if enabled in TIM2EN) + 0 + 1 + read-write + + + TIM16SMEN + TIM16 bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: TIM16 bus clock disabled in Sleep mode +- 1: TIM16 bus clock enabled in Sleep mode (if enabled in TIM16EN) + 1 + 1 + read-write + + + SYSCFGSMEN + SYSCFG bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SYSCFG bus clock disabled in Sleep mode +- 1: SYSCFG bus clock enabled in Sleep mode (if enabled in SYSCFGEN) + 8 + 1 + read-write + + + LCDCSMEN + LCDC bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: LCDC bus clock disabled in Sleep mode +- 1: LCDC bus clock enabled in Sleep mode (if enabled in LCDCEN) + 9 + 1 + read-write + + + COMPSMEN + COMP bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: COMP bus clock disabled in Sleep mode +- 1: COMP bus clock enabled in Sleep mode (if enabled in COMPEN) + 10 + 1 + read-write + + + DACSMEN + DAC bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: DAC bus clock disabled in Sleep mode +- 1: DAC bus clock enabled in Sleep mode (if enabled in DACEN) + 11 + 1 + read-write + + + RTCSMEN + RTC bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: RTC bus clock disabled in Sleep mode +- 1: RTC bus clock enabled in Sleep mode (if enabled in RTCEN) + 12 + 1 + read-write + + + LCSCSMEN + LCSC bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: LCSC bus clock disabled in Sleep mode +- 1: LCSC bus clock enabled in Sleep mode (if enabled in LCSCEN) + 13 + 1 + read-write + + + WDGSMEN + WDG clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: WDG clock disabled in Sleep mode +- 1: WDG clock enabled in Sleep mode (if enabled in WDGEN) + 14 + 1 + read-write + + + DBGMCUSMEN + DBGMCU clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: DBGMCU clock disabled in Sleep mode +- 1: DBGMCU clock enabled in Sleep mode (if enabled in DBGMCUEN) + 15 + 1 + read-write + + + + + APB1SMENR + APB1SMENR + APB1SMENR register + 0xa8 + 0x20 + read-write + 0x00A04511 + + + SPI1SMEN + SPI1 bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SPI1 bus clock disabled in Sleep mode +- 1: SPI1 bus clock enabled in Sleep mode (if enabled in SPI1EN) + 0 + 1 + read-write + + + ADCDIGSMEN + ADCDIG bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: ADCDIG bus clock disabled in Sleep mode +- 1: ADCDIG bus clock enabled in Sleep mode (if enabled by ADCDIGEN) + 4 + 1 + read-write + + + LPUARTSMEN + LPUART bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: LPUART bus clock disabled in Sleep mode +- 1: LPUART bus clock enabled in Sleep mode (if enabled in LPUARTEN) + 8 + 1 + read-write + + + USARTSMEN + USART bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: USART bus clock disabled in Sleep mode +- 1: USART bus clock enabled in Sleep mode (if enabled in USARTEN) + 10 + 1 + read-write + + + SPI3SMEN + SPI3 bus clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: SPI3 bus clock disabled in Sleep mode +- 1: SPI3 bus clock enabled in Sleep mode (if enabled in SPI3EN) + 14 + 1 + read-write + + + I2C1SMEN + I2C1 clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: I2C1 clock disabled in Sleep mode +- 1: I2C1 clock enabled in Sleep mode (if enabled in I2C1EN) + 21 + 1 + read-write + + + I2C2SMEN + I2C2 clock enable during Sleep mode bit +This bit is set and reset by software. +- 0: I2C2 clock disabled in Sleep mode +- 1: I2C2 clock enabled in Sleep mode (if enabled in I2C2EN) + 23 + 1 + read-write + + + + + + + RETAINED + RETAINED + 0x49000780 + + 0x0 + 0x80 + registers + + + + RFIP_WAKEUPTIME + RFIP_WAKEUPTIME + RFIP_WAKEUPTIME register + 0x0 + 0x20 + read-only + 0x00000000 + + + RFIP_WAKEUPTIME + (Absolute) Target time to wakeup the RFIP. + 0 + 32 + read-only + + + + + CPU_WAKEUPTIME + CPU_WAKEUPTIME + CPU_WAKEUPTIME register + 0x4 + 0x20 + read-write + 0x00000000 + + + CPU_WAKEUPTIME + (Absolute) Target time to wakeup the CPU. + 1 + 31 + read-write + + + + + WAKEUP_CTRL + WAKEUP_CTRL + WAKEUP_CTRL register + 0x8 + 0x20 + read-write + 0x00000000 + + + SOC_WAKEUP_OFFSET + Delay to be considered by the Wakeup block to anticipate the wakeup request to the PWRC of the SoC versus the target to wakeup the RFIP (or the CPU). + 0 + 8 + read-write + + + CPU_WAKEUP_EN + Indicates if the wakeup timer has to wakeup the SoC (match on CPU_WAKEUPTIME[31:4] bit field only) + set the CPU_WAKEUP_F in the WAKEUP_IRQ_STATUS Misc register when match on CPU_WAKEUPTIME[31:0] occurs. + 30 + 1 + read-write + + + RFIP_WAKEUP_EN + Indicates if the wakeup timer has to wakeup the SoC (match on RFIP_WAKEUPTIME[31:4] bit field only) + trigger an event on the Sequencer and set the RFIP_WAKEUP_F in the WAKEUP_IRQ_STATUS Misc register when match on RFIP_WAKEUPTIME[31:0] occurs. + 31 + 1 + read-only + + + + + RRM_CMDLIST_PTR + RRM_CMDLIST_PTR + RRM_CMDLIST_PTR register + 0xc + 0x20 + read-write + 0x00000000 + + + CMDLIST_PTR_OFFSET + Contain the offset versus the SoC RAM base address where to find the RRM-UDRA command list entry point. + 0 + 16 + read-write + + + CMDLIST_PTR_VALID + Indicate if a command list has to be executed or not + + 31 + 1 + read-write + + + + + SEQ_GLOBALTABLE_PTR + SEQ_GLOBALTABLE_PTR + SEQ_GLOBALTABLE_PTR register + 0x10 + 0x20 + read-write + 0x00000000 + + + SEQ_GLOBALTABLE_PTR + Contain the offset versus the SoC RAM base address of the GlobalConfiguration RAM table entry point. + 0 + 16 + read-write + + + + + + + RNG + RNG + 0x48600000 + + 0x0 + 0x1000 + registers + + + + RNG_CR + RNG_CR + RNG_CR register + 0x00 + 0x20 + read-write + 0x00000000 + + + RNG_DIS + RNG Disable bit. + 2 + 1 + read-write + + + TST_CLK + RNG Test Clock bit. + 3 + 1 + read-write + + + + + RNG_SR + RNG_SR + RNG_SR register + 0x04 + 0x20 + read-write + 0x00000000 + + + RNGRDY + New Random Value Ready. + 0 + 1 + read-only + + + REVCLK + RNGCLK Clock Reveal bit. + 1 + 1 + read-only + + + FAULT + Fault Reveal bit. + 2 + 1 + read-write + + + + + RNG_VAL + RNG_VAL + RNG_VAL register + 0x08 + 0x20 + read-only + 0x00000000 + + + RANDOM_VALUE + Random Value + 0 + 16 + read-only + + + + + RNG_TCR + RNG_TCR + RNG_TCR register + 0x80 + 0x20 + read-write + 0x00000000 + + + TCR + Test-control register + 0 + 1 + read-write + + + + + RNG_ITIP + RNG_ITIP + RNG_ITIP register + 0x84 + 0x20 + read-write + 0x00000000 + + + ITIP + Integration-test input register + 0 + 1 + read-write + + + + + RNGPeriphID0 + RNGPeriphID0 + RNGPeriphID0 register + 0xFE0 + 0x20 + read-only + 0x000000E1 + + + PartNumber0 + These bits are read back as 0xE1 + 0 + 8 + read-only + + + + + RNGPeriphID1 + RNGPeriphID1 + RNGPeriphID1 register + 0xFE4 + 0x20 + read-only + 0x0000005 + + + PartNumber1 + These bits are read back as 0x05 + 0 + 4 + read-only + + + Designer0 + These bits are read back as 0x00 + 4 + 4 + read-only + + + + + RNGPeriphID2 + RNGPeriphID2 + RNGPeriphID2 register + 0xFE8 + 0x20 + read-only + 0x00000028 + + + Designer1 + These bits are read back as 0x08 + 0 + 4 + read-only + + + Revision + These bits are read back as 0x02 + 4 + 4 + read-only + + + + + RNGPeriphID3 + RNGPeriphID3 + RNGPeriphID3 register + 0xFEC + 0x20 + read-only + 0x00000000 + + + Configuration + These bits are read back as 0x00 + 0 + 8 + read-only + + + + + RNGPCellID0 + RNGPCellID0 + RNGPCellID0 register + 0xFF0 + 0x20 + read-only + 0x0000000D + + + RNGPCellID0 + These bits are read back as 0x0D + 0 + 8 + read-only + + + + + RNGPCellID1 + RNGPCellID1 + RNGPCellID1 register + 0xFF4 + 0x20 + read-only + 0x000000F0 + + + RNGPCellID1 + These bits are read back as 0xF0 + 0 + 8 + read-only + + + + + RNGPCellID2 + RNGPCellID2 + RNGPCellID2 register + 0xFF8 + 0x20 + read-only + 0x00000005 + + + RNGPCellID2 + These bits are read back as 0x05 + 0 + 8 + read-only + + + + + RNGPCellID3 + RNGPCellID3 + RNGPCellID3 register + 0xFFC + 0x20 + read-only + 0x000000B1 + + + RNGPCellID3 + These bits are read back as 0xB1 + 0 + 8 + read-only + + + + + + + RTC + RTC + 0x40004000 + + 0x0 + 0x58 + registers + + + RTC + RTC interrupt + 11 + + + + RTC_TR + RTC_TR + RTC_TR register + 0x00 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation. +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + + + RTC_DR + RTC_DR + RTC_DR register + 0x04 + 0x20 + read-write + 0x00002101 + + + DU + Date units in BCD format. + 0 + 4 + read-write + + + DT + Date tens in BCD format. + 4 + 2 + read-write + + + MU + Month units in BCD format. + 8 + 4 + read-write + + + MT + Month tens in BCD format. + 12 + 1 + read-write + + + WDU + Week day units +000: forbidden +001: Monday +010: Tuesday +011: Wednesday +100: Thursday +101: Friday +110: Saturday +111: Sunday + 13 + 3 + read-write + + + YU + Year units in BCD format. + 16 + 4 + read-write + + + YT + Year tens in BCD format. + 20 + 4 + read-write + + + + + RTC_CR + RTC_CR + RTC_CR register + 0x08 + 0x20 + read-write + 0x00000000 + + + WUCKSEL + Wakeup clock selection +000: RTC/16 clock is selected +001: RTC/8 clock is selected +010: RTC/4 clock is selected +011: RTC/2 clock is selected +10x: ck_spre (usually 1 Hz) clock is selected +11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value + 0 + 3 + read-write + + + TSEDGE + Time-stamp event active edge +0: RTC_TS input rising edge generates a time-stamp event +1: RTC_TS input falling edge generates a time-stamp event +TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting. + 3 + 1 + read-write + + + BYPSHAD + Bypass the shadow registers +0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles. +1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters. + 5 + 1 + read-write + + + FMT + Hour format + + 6 + 1 + read-write + + + B_0x0 + 24 hour/day format + + 0x0 + + + B_0x1 + AM/PM hour format + 0x1 + + + + + ALRAE + Alarm A enable +0: Alarm A disabled +1: Alarm A enabled + 8 + 1 + read-write + + + WUTE + Wakeup timer enable +0: Wakeup timer disabled +1: Wakeup timer enabled + 10 + 1 + read-write + + + TSE + Timestamp enable +0: Timestamp disable +1: Timestamp enable + 11 + 1 + read-write + + + ALRAIE + Alarm A interrupt enable +0: Alarm A interrupt disabled +1: Alarm A interrupt enabled + 12 + 1 + read-write + + + WUTIE + Wakeup timer interrupt enable +0: Wakeup timer interrupt disabled +1: Wakeup timer interrupt enabled + 14 + 1 + read-write + + + TSIE + Time-stamp interrupt enable + + 15 + 1 + read-write + + + B_0x0 + Time-stamp Interrupt disable + + 0x0 + + + B_0x1 + Time-stamp Interrupt enable + 0x1 + + + + + ADD1H + Add 1 hour (summer time change) +When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. +0: No effect +1: Adds 1 hour to the current time. This can be used for summer time change + 16 + 1 + write-only + + + SUB1H + Subtract 1 hour (winter time change) +When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. +Setting this bit has no effect when current hour is 0. +0: No effect +1: Subtracts 1 hour to the current time. This can be used for winter time change. + 17 + 1 + write-only + + + BKP + Backup +This bit can be written by the user to memorize whether the daylight saving time change has been performed or not. + 18 + 1 + read-write + + + COSEL + Calibration output selection +When COE=1, this bit selects which signal is output on RTC_CALIB. +0: Calibration output is 512 Hz +1: Calibration output is 1 Hz +These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). + 19 + 1 + read-write + + + POL + Output polarity +This bit is used to configure the polarity of RTC_ALARM output +0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0]) +1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0]). + 20 + 1 + read-write + + + OSEL + Output selection +These bits are used to select the flag to be routed to RTC_ALARM output +00: Output disabled +01: Alarm A output enabled +10: Reserved +11: Wakeup output enabled + 21 + 2 + read-write + + + COE + Calibration output enable +This bit enables the RTC_CALIB output +0: Calibration output disabled +1: Calibration output enabled + 23 + 1 + read-write + + + ITSE + Timestamp on internal event enable +0: Internal event timestamp disable +1: Internal event timestamp enable + 24 + 1 + read-write + + + + + RTC_ISR + RTC_ISR + RTC_ISR register + 0x0C + 0x20 + read-write + 0x00000007 + + + ALRAWF + Alarm A write flag +This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. +It is cleared by hardware in initialization mode. +0: Alarm A update not allowed +1: Alarm A update allowed. + 0 + 1 + read-write + + + WUTWF + Wakeup timer write flag +This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. +0: Wakeup timer configuration update not allowed +1: Wakeup timer configuration update allowed. + 2 + 1 + read-write + + + SHPF + Shift operation pending +0: No shift operation is pending +1: A shift operation is pending +This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect. + 3 + 1 + read-write + + + INITS + Initialization status flag +This bit is set by hardware when the calendar year field is different from 0 (power-on reset state). +0: Calendar has not been initialized +1: Calendar has been initialized + 4 + 1 + read-write + + + RSF + Registers synchronization flag +This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow regsiter mode (BYPSHAD=1). This bit can also be cleared by software. +It is cleared either by software or by hardware in initialization mode. +0: Calendar shadow registers not yet synchronized +1: Calendar shadow registers synchronized. + 5 + 1 + read-write + + + INITF + Initialization flag +When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. +0: Calendar registers update is not allowed +1: Calendar registers update is allowed. + 6 + 1 + read-write + + + INIT + Initialization mode +0: Free running mode +1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + 7 + 1 + read-write + + + ALRAF + Alarm A flag +This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). +This flag is cleared by software by writing 0. + 8 + 1 + read-write + + + WUTF + Wakeup timer flag +This flag is set by hardware when the wakeup auto-reload counter reaches 0. +This flag is cleared by software by writing 0. +This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again. + 10 + 1 + read-write + + + TSF + This flag is set by hardware when a time-stamp event occurs. +This flag is cleared by software by writing 0. If ITSF flag is set, TSF must be cleared together with ITSF by writing 0 in both bits. + 11 + 1 + read-write + + + TSOVF + This flag is set by hardware when a time-stamp event occurs while TSF is already set. +This flag is cleared by software by writing 0. +It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp +event occurs immediately before the TSF bit is cleared. + 12 + 1 + read-write + + + TAMP1F + RTC_TAMP1 detection flag +This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. +It is cleared by software writing 0 + 13 + 1 + read-write + + + RECALPF + Recalibration pending Flag +The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. + 16 + 1 + read-write + + + ITSF + Internal time-stamp flag +This flag is set by hardware when a time-stamp on the internal event occurs. +This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits. + 17 + 1 + read-write + + + + + RTC_PRER + RTC_PRER + RTC_PRER register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_S + Synchronous prescaler factor +This is the synchronous division factor: +ck_spre frequency = ck_apre frequency/(PREDIV_S+1) + 0 + 15 + read-write + + + PREDIV_A + Asynchronous prescaler factor +This is the asynchronous division factor: +ck_apre frequency = RTCCLK frequency/(PREDIV_A+1) + 16 + 7 + read-write + + + + + RTC_WUTR + RTC_WUTR + RTC_WUTR register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits +When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register +When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. +The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden. + 0 + 16 + read-write + + + + + RTC_ALRMAR + RTC_ALRMAR + RTC_ALRMAR register + 0x1C + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MSK1 + Alarm A seconds mask +0: Alarm A set if the seconds match +1: Seconds dont care in Alarm A comparison + 7 + 1 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + MSK2 + Alarm A minutes mask +0: Alarm A set if the minutes match +1: Minutes dont care in Alarm A comparison + 15 + 1 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + MSK3 + Alarm A hours mask +0: Alarm A set if the hours match +1: Hours dont care in Alarm A comparison + 23 + 1 + read-write + + + DU + Date units or day in BCD format. + 24 + 4 + read-write + + + DT + Date tens in BCD format. + 28 + 2 + read-write + + + WDSEL + Week day selection +0: DU[3:0] represents the date units +1: DU[3:0] represents the week day. DT[1:0] is dont care. + 30 + 1 + read-write + + + MSK4 + Alarm A date mask +0: Alarm A set if the date/day match +1: Date/day dont care in Alarm A comparison + 31 + 1 + read-write + + + + + RTC_WPR + RTC_WPR + RTC_WPR register + 0x24 + 0x20 + read-write + 0x00000000 + + + KEY + Write protection key +This byte is written by software. +Reading this byte always returns 0x00 + 0 + 8 + write-only + + + + + RTC_SSR + RTC_SSR + RTC_SSR register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value +SS[15:0] is the value in the synchronous prescalers counter. The fraction of a second is given by the formula below: +Second fraction = ( PREDIV_S - SS ) / ( PREDIV_S + 1 ) + 0 + 16 + read-only + + + + + RTC_SHIFTR + RTC_SHIFTR + RTC_SHIFTR register + 0x2C + 0x20 + read-write + 0x00000000 + + + SUBFS + Subtract a fraction of a second +These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +The value which is written to SUBFS is added to the synchronous prescalers counter. +Since this counter counts down, this operation effectively subtracts from (delays) the clock by: +Delay (seconds) = SUBFS / ( PREDIV_S + 1 ) +A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by : +Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) . + 0 + 15 + write-only + + + ADD1S + Add one second +0: No effect +1: Add one second to the clock/calendar +This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). +This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation. + 31 + 1 + write-only + + + + + RTC_TSTR + RTC_TSTR + RTC_TSTR register + 0x30 + 0x20 + read-write + 0x00000000 + + + SU + Second units in BCD format. + 0 + 4 + read-write + + + ST + Second tens in BCD format. + 4 + 3 + read-write + + + MNU + Minute units in BCD format. + 8 + 4 + read-write + + + MNT + Minute tens in BCD format. + 12 + 3 + read-write + + + HU + Hour units in BCD format. + 16 + 4 + read-write + + + HT + Hour tens in BCD format. + 20 + 2 + read-write + + + PM + AM/PM notation +0: AM or 24-hour format +1: PM + 22 + 1 + read-write + + + + + RTC_TSDR + RTC_TSDR + RTC_TSDR register + 0x34 + 0x20 + read-write + 0x00000000 + + + DU + Date units in BCD format. + 0 + 4 + read-write + + + DT + Date tens in BCD format. + 4 + 2 + read-write + + + MU + Month units in BCD format. + 8 + 4 + read-write + + + MT + Month tens in BCD format. + 12 + 1 + read-write + + + WDU + Week day units + 13 + 3 + read-write + + + + + RTC_TSSSR + RTC_TSSSR + RTC_TSSSR register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value +SS[15:0] is the value of the synchronous prescalers counter when the timestamp event occurred. + 0 + 16 + read-only + + + + + RTC_CALR + RTC_CALR + RTC_CALR register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALM + Calibration minus +The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. +To increase the frequency of the calendar, this feature should be used in conjunction with CALP. + 0 + 9 + read-write + + + CALW16 + Use a 16-second calibration cycle period +When CALW16 is set to 1 , the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. +Note: CALM[0] is stucked at 0 when CALW16=1. + 13 + 1 + read-write + + + CALW8 + Use an 8-second calibration cycle period +When CALW8 is set to 1 , the 8-second calibration cycle period is selected. +Note: CALM[1:0] are stucked at '00' when CALW8=1. + 14 + 1 + read-write + + + CALP + Increase frequency of RTC by 488.5 ppm +0: No RTCCLK pulses are added. +1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency incresed by 488.5 ppm). +This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. + 15 + 1 + read-write + + + + + RTC_TAMPCR + RTC_TAMPCR + RTC_TAMPCR register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP1E + RTC_TAMP1 input detection enable +0: RTC_TAMP1 detection disabled +1: RTC_TAMP1 detection enabled. + 0 + 1 + read-write + + + TAMP1TRG + Active level for RTC_TAMP1 input +If TAMPFLT != 00 +0: RTC_TAMP1 input staying low triggers a tamper detection event. +1: RTC_TAMP1 input staying high triggers a tamper detection event. +if TAMPFLT = 00: +0: RTC_TAMP1 input rising edge triggers a tamper detection event. +1: RTC_TAMP1 input falling edge triggers a tamper detection event. + 1 + 1 + read-write + + + TAMPIE + Tamper interrupt enable +0: Tamper interrupt disabled +1: Tamper interrupt enabled. + 2 + 1 + read-write + + + TAMPTS + Activate timestamp on tamper detection event +0: Tamper detection event does not cause a timestamp to be saved +1: Save timestamp on tamper detection event +TAMPTS is valid even if TSE=0 in the RTC_CR register. + 7 + 1 + read-write + + + TAMPFREQ + Tamper sampling frequency +Determines the frequency at which each of the RTC_TAMPx inputs are sampled. +0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) +0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) +0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) +0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) +0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) +0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) +0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) +0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + 8 + 3 + read-write + + + TAMPFLT + RTC_TAMPx filter count +These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. +TAMPFLT is valid for each of the RTC_TAMPx inputs. +0x0: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input). +0x1: Tamper event is activated after 2 consecutive samples at the active level. +0x2: Tamper event is activated after 4 consecutive samples at the active level. +0x3: Tamper event is activated after 8 consecutive samples at the active level. + 11 + 2 + read-write + + + TAMPPRCH + RTC_TAMPx precharge duration +These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs. +0x0: 1 RTCCLK cycle +0x1: 2 RTCCLK cycles +0x2: 4 RTCCLK cycles +0x3: 8 RTCCLK cycles + 13 + 2 + read-write + + + TAMPPUDIS + RTC_TAMPx pull-up disable +This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample. +0: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) +1: Disable precharge of RTC_TAMPx pins. + 15 + 1 + read-write + + + TAMP1IE + Tamper 1 interrupt enable +0: Tamper 1 interrupt is disabled if TAMPIE = 0. +1: Tamper 1 interrupt enabled. + 16 + 1 + read-write + + + TAMP1NOERASE + Tamper 1 no erase +0: Tamper 1 event erases the backup registers. +1: Tamper 1 event does not erase the backup registers. + 17 + 1 + read-write + + + TAMP1MF + Tamper 1 mask flag +0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection. +1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased. + 18 + 1 + read-write + + + + + RTC_ALRMASSR + RTC_ALRMASSR + RTC_ALRMASSR register + 0x44 + 0x20 + read-write + 0x00000000 + + + SS + Sub seconds value +This value is compared with the contents of the synchronous prescalers counter to +determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared. + 0 + 15 + read-write + + + MASKSS + Mask the most-significant bits starting at this bit +0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). +1: SS[14:1] are dont care in Alarm A comparison. Only SS[0] is compared. +2: SS[14:2] are dont care in Alarm A comparison. Only SS[1:0] are compared. +3: SS[14:3] are dont care in Alarm A comparison. Only SS[2:0] are compared. +... +12: SS[14:12] are dont care in Alarm A comparison. SS[11:0] are compared. +13: SS[14:13] are dont care in Alarm A comparison. SS[12:0] are compared. +14: SS[14] is dont care in Alarm A comparison. SS[13:0] are compared. +15: All 15 SS bits are compared and must match to activate alarm. +The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. + 24 + 4 + read-write + + + + + RTC_OR + RTC_OR + RTC_OR register + 0x4C + 0x20 + read-write + 0x00000000 + + + ALARMOUTTYPE + RTC_ALARM on PA8 output type + + 0 + 1 + read-write + + + B_0x0 + RTC_ALARM, when mapped on PA8, is open-drain output + + 0x0 + + + B_0x1 + RTC_ALARM, when mapped on PA8, is push-pull output + 0x1 + + + + + RTC_OUT_RMP + RTC_OUT remap +Setting this bit allows to remap the RTC outputs on PA9 as follows: +0 : +If OSEL/= '00' : RTC_ALARM is ouput on PA8 +If OSEL= '00' and COE = 1 : RTC_CALIB is output on PA8 +1 : +If OSEL /= '00' and COE = 0 : RTC_ALARM is output on PA9 +If OSEL = '00' and COE = 1: RTC_CALIB is output on PA9 +If OSEL /= '00' and COE = 1: RTC_CALIB is output on PA9 and RTC_ALARM is output on PA8. +Note: the RTC outputs are functional in DEEPSTOP mode only on PA8. + 1 + 1 + read-write + + + + + RTC_BKP0R + RTC_BKP0R + RTC_BKPxR register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + RTC_BKP1R + RTC_BKP1R + RTC_BKPxR register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + The application can write or read data to and from these registers. +They are powered-on by VDD12o so they are retained during DEEPSTOP mode. +The application can write or read data to and from these registers. +This register is reset on PORESETn only. + 0 + 32 + read-write + + + + + + + SPI + SPI + 0x41002000 + + 0x0 + 0x1C + registers + + + SPI1 + SPI1 interrupt + 5 + + + + SPI_SSPCR1 + SPI_SSPCR1 + SPI_SSPCR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + CPHA + Clock phase +- 0: The first clock transition is the first data capture edge +- 1: The second clock transition is the first data capture edge + 0 + 1 + read-write + + + CPOL + Clock polarity +- 0: CK to 0 when idle +- 1: CK to 1 when idle + 1 + 1 + read-write + + + MSTR + Master selection +- 0: Slave configuration +- 1: Master configuration + 2 + 1 + read-write + + + BR + Baud rate control +- 000: fPCLK/2 +- 001: fPCLK/4 +- 010: fPCLK/8 +- 011: fPCLK/16 +- 100: fPCLK/32 +- 101: fPCLK/64 +- 110: fPCLK/128 +- 111: fPCLK/256 + 3 + 3 + read-write + + + SPE + SPI enable +- 0: Peripheral disabled +- 1: Peripheral enabled + 6 + 1 + read-write + + + LSBFIRST + Frame format +- 0: data is transmitted / received with the MSB first +- 1: data is transmitted / received with the LSB first + 7 + 1 + read-write + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +- 0: Software slave management disabled +- 1: Software slave management enabled + 9 + 1 + read-write + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +- 0: Full duplex (Transmit and receive) +- 1: Output disabled (Receive-only mode) + 10 + 1 + read-write + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +- 0: 8-bit CRC length +- 1: 16-bit CRC length + 11 + 1 + read-write + + + CRCNEXT + Transmit CRC next +- 0: Next transmit value is from Tx buffer +- 1: Next transmit value is from Tx CRC register + 12 + 1 + read-write + + + CRCEN + Hardware CRC calculation enable +- 0: CRC calculation disabled +- 1: CRC calculation Enabled + 13 + 1 + read-write + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode +- 0: Output disabled (receive-only mode) +- 1: Output enabled (transmit-only mode) + 14 + 1 + read-write + + + BIDIMODE + Bidirectional data mode enable. This bit enables half-duplex communication using +common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is +active. +- 0: 2-line unidirectional data mode selected +- 1: 1-line bidirectional data mode selected + 15 + 1 + read-write + + + + + SPI_SSPCR2 + SPI_SSPCR2 + SPI_SSPCR2 register + 0x04 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. +- 0: Rx buffer DMA disabled +- 1: Rx buffer DMA enabled + 0 + 1 + read-write + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. +- 0: Tx buffer DMA disabled +- 1: Tx buffer DMA enabled + 1 + 1 + read-write + + + SSOE + SS output enable +- 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration +- 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 2 + 1 + read-write + + + NSSP + NSS pulse management +This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1, or FRF = 1. +- 0: No NSS pulse +- 1: NSS pulse generated + 3 + 1 + read-write + + + FRF + Frame format +- 0: SPI Motorola mode +- 1 SPI TI mode + 4 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). +- 0: Error interrupt is masked +- 1: Error interrupt is enabled + 5 + 1 + read-write + + + RXNEIE + RX buffer not empty interrupt enable +- 0: RXNE interrupt masked +- 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 6 + 1 + read-write + + + TXEIE + Tx buffer empty interrupt enable +- 0: TXE interrupt masked +- 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 7 + 1 + read-write + + + DS + Data size +These bits configure the data length for SPI transfers: +- 0000: Not used +- 0001: Not used +- 0010: Not used +- 0011: 4-bit +- 0100: 5-bit +- 0101: 6-bit +- 0110: 7-bit +- 0111: 8-bit +- 1000: 9-bit +- 1001: 10-bit +- 1010: 11-bit +- 1011: 12-bit +- 1100: 13-bit +- 1101: 14-bit +- 1110: 15-bit +- 1111: 16-bit +If software attempts to write one of the 'Not used' values, they are forced to the value '0111'(8-bit). + 8 + 4 + read-write + + + FRXTH + FIFO reception threshold +FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +- 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) +- 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 12 + 1 + read-write + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 13 + 1 + read-write + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 14 + 1 + read-write + + + + + SPI_SSPSR + SPI_SSPSR + SPI_SSPSR register + 0x08 + 0x20 + read-write + 0x00000002 + + + RXNE + Receive buffer not empty +- 0: Rx buffer empty +- 1: Rx buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty +- 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). +- 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer). + 1 + 1 + read-only + + + CHSIDE + Channel side +- 0: Channel Left has to be transmitted or has been received +- 1: Channel Right has to be transmitted or has been received + 2 + 1 + read-only + + + UDR + Underrun flag +- 0: No underrun occurred +- 1: Underrun occurred + 3 + 1 + read-only + + + CRCERR + CRC error flag +- 0: CRC value received matches the SPIx_RXCRCR value +- 1: CRC value received does not match the SPIx_RXCRCR value +This flag is set by hardware and cleared by software writing 0. + 4 + 1 + read-write + + + MODF + Mode fault +- 0: No mode fault occurred +- 1: Mode fault occurred + 5 + 1 + read-only + + + OVR + Overrun flag +- 0: No overrun occurred +- 1: Overrun occurred + 6 + 1 + read-only + + + BSY + Busy flag +- 0: SPI (or I2S) not busy +- 1: SPI (or I2S) is busy in communication or Tx buffer is not empty +This flag is set and cleared by hardware. + 7 + 1 + read-only + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. +- 0: No frame format error +- 1: A frame format error occurred + 8 + 1 + read-only + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full + 9 + 2 + read-only + + + FTLVL + FIFO Transmission Level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 11 + 2 + read-only + + + + + SPI_SSPDR + SPI_SSPDR + SPI_SSPDR register + 0x0C + 0x20 + read-write + 0x00000000 + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO +(See Section 18.5.8: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI_SSPCRCPR + SPI_SSPCRCPR + SPI_SSPCRCPR register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI_SSPRXCRCR + SPI_SSPRXCRCR + SPI_SSPRXCRCR register + 0x14 + 0x20 + read-only + 0x00000000 + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +A read to this register when the BSY Flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + SPI_SSPTXCRCR + SPI_SSPTXCRCR + SPI_SSPTXCRCR register + 0x18 + 0x20 + read-only + 0x00000000 + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode. + 0 + 1 + read-only + + + + + + + SPI3 + SPI3 + 0x41007000 + + 0x0 + 0x24 + registers + + + SPI3 + SPI3 interrupt + 7 + + + + SPI_SSPCR1 + SPI_SSPCR1 + SPI_SSPCR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + CPHA + Clock phase +- 0: The first clock transition is the first data capture edge +- 1: The second clock transition is the first data capture edge + 0 + 1 + read-write + + + CPOL + Clock polarity +- 0: CK to 0 when idle +- 1: CK to 1 when idle + 1 + 1 + read-write + + + MSTR + Master selection +- 0: Slave configuration +- 1: Master configuration + 2 + 1 + read-write + + + BR + Baud rate control +- 000: fPCLK/2 +- 001: fPCLK/4 +- 010: fPCLK/8 +- 011: fPCLK/16 +- 100: fPCLK/32 +- 101: fPCLK/64 +- 110: fPCLK/128 +- 111: fPCLK/256 + 3 + 3 + read-write + + + SPE + SPI enable +- 0: Peripheral disabled +- 1: Peripheral enabled + 6 + 1 + read-write + + + LSBFIRST + Frame format +- 0: data is transmitted / received with the MSB first +- 1: data is transmitted / received with the LSB first + 7 + 1 + read-write + + + SSI + Internal slave select +This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. + 8 + 1 + read-write + + + SSM + Software slave management +When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. +- 0: Software slave management disabled +- 1: Software slave management enabled + 9 + 1 + read-write + + + RXONLY + Receive only mode enabled. +This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. +- 0: Full duplex (Transmit and receive) +- 1: Output disabled (Receive-only mode) + 10 + 1 + read-write + + + CRCL + CRC length +This bit is set and cleared by software to select the CRC length. +- 0: 8-bit CRC length +- 1: 16-bit CRC length + 11 + 1 + read-write + + + CRCNEXT + Transmit CRC next +- 0: Next transmit value is from Tx buffer +- 1: Next transmit value is from Tx CRC register + 12 + 1 + read-write + + + CRCEN + Hardware CRC calculation enable +- 0: CRC calculation disabled +- 1: CRC calculation Enabled + 13 + 1 + read-write + + + BIDIOE + Output enable in bidirectional mode +This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode +- 0: Output disabled (receive-only mode) +- 1: Output enabled (transmit-only mode) + 14 + 1 + read-write + + + BIDIMODE + Bidirectional data mode enable. This bit enables half-duplex communication using +common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is +active. +- 0: 2-line unidirectional data mode selected +- 1: 1-line bidirectional data mode selected + 15 + 1 + read-write + + + + + SPI_SSPCR2 + SPI_SSPCR2 + SPI_SSPCR2 register + 0x04 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable +When this bit is set, a DMA request is generated whenever the RXNE flag is set. +- 0: Rx buffer DMA disabled +- 1: Rx buffer DMA enabled + 0 + 1 + read-write + + + TXDMAEN + Tx buffer DMA enable +When this bit is set, a DMA request is generated whenever the TXE flag is set. +- 0: Tx buffer DMA disabled +- 1: Tx buffer DMA enabled + 1 + 1 + read-write + + + SSOE + SS output enable +- 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration +- 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment. + 2 + 1 + read-write + + + NSSP + NSS pulse management +This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. +It has no meaning if CPHA = 1, or FRF = 1. +- 0: No NSS pulse +- 1: NSS pulse generated + 3 + 1 + read-write + + + FRF + Frame format +- 0: SPI Motorola mode +- 1 SPI TI mode + 4 + 1 + read-write + + + ERRIE + Error interrupt enable +This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I2S mode). +- 0: Error interrupt is masked +- 1: Error interrupt is enabled + 5 + 1 + read-write + + + RXNEIE + RX buffer not empty interrupt enable +- 0: RXNE interrupt masked +- 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. + 6 + 1 + read-write + + + TXEIE + Tx buffer empty interrupt enable +- 0: TXE interrupt masked +- 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. + 7 + 1 + read-write + + + DS + Data size +These bits configure the data length for SPI transfers: +- 0000: Not used +- 0001: Not used +- 0010: Not used +- 0011: 4-bit +- 0100: 5-bit +- 0101: 6-bit +- 0110: 7-bit +- 0111: 8-bit +- 1000: 9-bit +- 1001: 10-bit +- 1010: 11-bit +- 1011: 12-bit +- 1100: 13-bit +- 1101: 14-bit +- 1110: 15-bit +- 1111: 16-bit +If software attempts to write one of the 'Not used' values, they are forced to the value '0111'(8-bit). + 8 + 4 + read-write + + + FRXTH + FIFO reception threshold +FRXTH shall be set according the read access (16-bit or 8-bit) to the FIFO. +This bit is used to set the threshold of the RXFIFO that triggers an RXNE event +- 0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) +- 1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + 12 + 1 + read-write + + + LDMA_RX + Last DMA transfer for reception +This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 13 + 1 + read-write + + + LDMA_TX + Last DMA transfer for transmission +This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPIx_CR2 register is set and if packing mode is used (data length = 8-bit and write access to SPIx_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPIx_CR1 register). +- 0: Number of data to transfer is even +- 1: Number of data to transfer is odd + 14 + 1 + read-write + + + + + SPI_SSPSR + SPI_SSPSR + SPI_SSPSR register + 0x08 + 0x20 + read-write + 0x00000002 + + + RXNE + Receive buffer not empty +- 0: Rx buffer empty +- 1: Rx buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty +- 0: No more empty space in Tx buffer. (software shall not write data to the Tx buffer). +- 1: At least one empty space in Tx buffer. (software may write data to the Tx buffer). + 1 + 1 + read-only + + + CHSIDE + Channel side +- 0: Channel Left has to be transmitted or has been received +- 1: Channel Right has to be transmitted or has been received + 2 + 1 + read-only + + + UDR + Underrun flag +- 0: No underrun occurred +- 1: Underrun occurred + 3 + 1 + read-only + + + CRCERR + CRC error flag +- 0: CRC value received matches the SPIx_RXCRCR value +- 1: CRC value received does not match the SPIx_RXCRCR value +This flag is set by hardware and cleared by software writing 0. + 4 + 1 + read-write + + + MODF + Mode fault +- 0: No mode fault occurred +- 1: Mode fault occurred + 5 + 1 + read-only + + + OVR + Overrun flag +- 0: No overrun occurred +- 1: Overrun occurred + 6 + 1 + read-only + + + BSY + Busy flag +- 0: SPI (or I2S) not busy +- 1: SPI (or I2S) is busy in communication or Tx buffer is not empty +This flag is set and cleared by hardware. + 7 + 1 + read-only + + + FRE + Frame format error +This flag is used for SPI in TI slave mode and I2S slave mode. Refer to Section 18.5.10: SPI error flags and Section 18.7.6: I2S error flags. +This flag is set by hardware and reset when SPIx_SR is read by software. +- 0: No frame format error +- 1: A frame format error occurred + 8 + 1 + read-only + + + FRLVL + FIFO reception level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full + 9 + 2 + read-only + + + FTLVL + FIFO Transmission Level +These bits are set and cleared by hardware. +- 00: FIFO empty +- 01: 1/4 FIFO +- 10: 1/2 FIFO +- 11: FIFO full (considered as FULL when the FIFO threshold is greater than 1/2) + 11 + 2 + read-only + + + + + SPI_SSPDR + SPI_SSPDR + SPI_SSPDR register + 0x0C + 0x20 + read-write + 0x00000000 + + + DR + Data register +Data received or to be transmitted +The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO +(See Section 18.5.8: Data transmission and reception procedures). +Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used. + 0 + 16 + read-write + + + + + SPI_SSPCRCPR + SPI_SSPCRCPR + SPI_SSPCRCPR register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register +This register contains the polynomial for the CRC calculation. +The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. + 0 + 16 + read-write + + + + + SPI_SSPRXCRCR + SPI_SSPRXCRCR + SPI_SSPRXCRCR register + 0x14 + 0x20 + read-only + 0x00000000 + + + RXCRC + Rx CRC register +When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +A read to this register when the BSY Flag is set could return an incorrect value. + 0 + 16 + read-only + + + + + SPI_SSPTXCRCR + SPI_SSPTXCRCR + SPI_SSPTXCRCR register + 0x18 + 0x20 + read-only + 0x00000000 + + + TXCRC + Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the Tx CRC register +When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPIx_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPIx_CRCPR register. +Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (CRCL bit in the SPIx_CR1 is cleared). CRC calculation is done based on any CRC8 standard. +The entire 16-bits of this register are considered when a 16-bit data frame format is selected (CRCL bit in the SPIx_CR1 register is set). CRC calculation is done based on any CRC16 standard. +Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode. + 0 + 1 + read-only + + + + + SPI2S_I2SCFGR + SPI2S_I2SCFGR + SPI2S_I2SCFGR register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHLEN + Channel length (number of bits per audio channel) +- 0: 16-bit wide +- 1: 32-bit wide +The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. + 0 + 1 + read-write + + + DATLEN + Data length to be transferred +- 00: 16-bit data length +- 01: 24-bit data length +- 10: 32-bit data length +- 11: Not allowed + 1 + 2 + read-write + + + CKPOL + Steady state clock polarity +- 0: I2S clock steady state is low level +- 1: I2S clock steady state is high level + 3 + 1 + read-write + + + I2SSTD + I2S standard selection +- 00: I2S Philips standard. +- 01: MSB justified standard (left justified) +- 10: LSB justified standard (right justified) +- 11: PCM standard + 4 + 2 + read-write + + + PCMSYNC + PCM frame synchronization +- 0: Short frame synchronization +- 1: Long frame synchronization +Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). It is not used in SPI mode. + 7 + 1 + read-write + + + I2SCFG + I2S configuration mode +- 00: Slave - transmit +- 01: Slave - receive +- 10: Master - transmit +- 11: Master - receive + 8 + 2 + read-write + + + I2SE + I2S enable +- 0: I2S peripheral is disabled +- 1: I2S peripheral is enabled +Note: This bit is not used in SPI mode. + 10 + 1 + read-write + + + I2SMOD + I2S mode selection +- 0: SPI mode is selected +- 1: I2S mode is selected +Note: This bit should be configured when the SPI is disabled. + 11 + 1 + read-write + + + ASTREN + Asynchronous start enable. +Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. + 12 + 1 + read-write + + + B_0x0 + The Asynchronous start is disabled. When the I2S is enabled in slave mode, the I2S slave starts the transfer when the I2S clock is received and an appropriate transition (depending on the protocol selected) is detected on the WS signal. + + 0x0 + + + B_0x1 + The Asynchronous start is enabled. When the I2S is enabled in slave mode, the I2S slave starts immediately the transfer when the I2S clock is received from the master without checking the expected transition of WS signal. + + 0x1 + + + + + + + SPI2S_I2SPR + SPI2S_I2SPR + SPI2S_I2SPR register + 0x20 + 0x20 + read-write + 0x00000002 + + + I2SDIV + I2S linear prescaler +I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. + 0 + 8 + read-write + + + ODD + Odd factor for the prescaler +- 0: Real divider value is = I2SDIV *2 +- 1: Real divider value is = (I2SDIV * 2)+1 + 8 + 1 + read-write + + + MCKOE + Master clock output enable +- 0: Master clock output is disabled +- 1: Master clock output is enabled + 9 + 1 + read-write + + + + + + + SYSTEM_CTRL + SYSTEM_CTRL + 0x40000000 + + 0x0 + 0x48 + registers + + + + DIE_ID + DIE_ID + DIE_ID register + 0x00 + 0x20 + read-only + 0x00000120 + + + REVISION + Cut revision (metal fix) + 0 + 4 + read-only + + + VERSION + Cut version + 4 + 4 + read-only + + + PRODUCT + Product version. +May be used to discriminate several version of a same digital BLE LPH device embedding +different analog versions + 8 + 4 + read-only + + + + + JTAG_ID + JTAG_ID + JTAG_ID register + 0x04 + 0x20 + read-only + 0x02027041 + + + MANUF_ID + Manufacturer ID + 1 + 11 + read-only + + + PART_NUMBER + Part number + 12 + 16 + read-only + + + VERSION_NUMBER + Version + 28 + 4 + read-only + + + + + I2C_FMP_CTRL + I2C_FMP_CTRL + I2C_FMP_CTRL register + 0x08 + 0x20 + read-write + 0x00000000 + + + I2C1_PA0_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. +0: PA0 pin operated in standard mode. +1: FM+ mode is enabled on PA0 pin, and speed control is bypassed + 0 + 1 + read-write + + + I2C1_PA1_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. +0: PA1 pin operated in standard mode. +1: FM+ mode is enabled on PA1 pin, and speed control is bypassed + 1 + 1 + read-write + + + I2C1_PB6_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O. +0: PB6 pin operated in standard mode. +1: FM+ mode is enabled on PB6 pin, and speed control is bypassed. + 2 + 1 + read-write + + + I2C1_PB7_FMP + I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O. +0: PB7 pin operated in standard mode. +1: FM+ mode is enabled on PB7 pin, and speed control is bypassed + 3 + 1 + read-write + + + I2C1_PB10_FMP + I2C1_PB10_FMP: I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB10 I/O. +0: PB10 pin operated in standard mode. +1: FM+ mode is enabled on PB10 pin, and speed control is bypassed. + 4 + 1 + read-write + + + I2C1_PB11_FMP + I2C1_PB11_FMP: I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB11 I/O. +0: PB11 pin operated in standard mode. +1: FM+ mode is enabled on PB11 pin, and speed control is bypassed + 5 + 1 + read-write + + + I2C2_PA6_FMP + I2C2_PA6_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SCL on PA6 I/O. +0: PA6 pin operated in standard mode. +1: FM+ mode is enabled on PA6 pin, and speed control is bypassed. + 6 + 1 + read-write + + + I2C2_PA7_FMP + I2C2_PA7_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SDA on PA7 I/O. +0: PA7 pin operated in standard mode. +1: FM+ mode is enabled on PA7 pin, and speed control is bypassed + 7 + 1 + read-write + + + I2C2_PA13_FMP + I2C2_PA13_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SCL on PA13 I/O. +0: PA13 pin operated in standard mode. +1: FM+ mode is enabled on PA13 pin, and speed control is bypassed. + 8 + 1 + read-write + + + I2C2_PA14_FMP + I2C2_PA14_FMP: I2C2 Fast-Mode Plus driving capability for I2C2_SDA on PA14 I/O. +0: PA14 pin operated in standard mode. +1: FM+ mode is enabled on PA14 pin, and speed control is bypassed. + 9 + 1 + read-write + + + + + IO_DTR + IO_DTR + IO_DTR register + 0x0C + 0x20 + read-write + 0x00000000 + + + PA0_DT + PA0_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 0 + 1 + read-write + + + PA1_DT + PA1_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 1 + 1 + read-write + + + PA2_DT + PA2_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 2 + 1 + read-write + + + PA3_DT + PA3_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 3 + 1 + read-write + + + PA4_DT + PA4_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 4 + 1 + read-write + + + PA5_DT + PA5_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 5 + 1 + read-write + + + PA6_DT + PA6_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 6 + 1 + read-write + + + PA7_DT + PA7_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 7 + 1 + read-write + + + PA8_DT + PA8_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 8 + 1 + read-write + + + PA9_DT + PA9_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 9 + 1 + read-write + + + PA10_DT + PA10_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 10 + 1 + read-write + + + PA11_DT + PA11_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 11 + 1 + read-write + + + PA12_DT + PA12_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 12 + 1 + read-write + + + PA13_DT + PA13_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 13 + 1 + read-write + + + PA14_DT + PA14_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 14 + 1 + read-write + + + PA15_DT + PA15_DT: Interrupt Detection Type for port A I/Os. +0: edge detection. +1: level detection. + 15 + 1 + read-write + + + PB0_DT + PB0_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 16 + 1 + read-write + + + PB1_DT + PB1_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 17 + 1 + read-write + + + PB2_DT + PB2_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 18 + 1 + read-write + + + PB3_DT + PB3_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 19 + 1 + read-write + + + PB4_DT + PB4_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 20 + 1 + read-write + + + PB5_DT + PB5_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 21 + 1 + read-write + + + PB6_DT + PB6_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 22 + 1 + read-write + + + PB7_DT + PB7_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 23 + 1 + read-write + + + PB8_DT + PB8_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 24 + 1 + read-write + + + PB9_DT + PB9_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 25 + 1 + read-write + + + PB10_DT + PB10_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 26 + 1 + read-write + + + PB11_DT + PB11_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 27 + 1 + read-write + + + PB12_DT + PB12_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 28 + 1 + read-write + + + PB13_DT + PB13_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 29 + 1 + read-write + + + PB14_DT + PB14_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 30 + 1 + read-write + + + PB15_DT + PB15_DT: Interrupt Detection Type for port B I/Os. +0: edge detection. +1: level detection. + 31 + 1 + read-write + + + + + IO_IBER + IO_IBER + IO_IBER register + 0x10 + 0x20 + read-write + 0x000000000 + + + PA0_IBE + PA0_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 0 + 1 + read-write + + + PA1_IBE + PA1_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 1 + 1 + read-write + + + PA2_IBE + PA2_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 2 + 1 + read-write + + + PA3_IBE + PA3_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 3 + 1 + read-write + + + PA4_IBE + PA4_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 4 + 1 + read-write + + + PA5_IBE + PA5_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 5 + 1 + read-write + + + PA6_IBE + PA6_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 6 + 1 + read-write + + + PA7_IBE + PA7_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 7 + 1 + read-write + + + PA8_IBE + PA8_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 8 + 1 + read-write + + + PA9_IBE + PA9_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 9 + 1 + read-write + + + PA10_IBE + PA10_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 10 + 1 + read-write + + + PA11_IBE + PA11_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 11 + 1 + read-write + + + PA12_IBE + PA12_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 12 + 1 + read-write + + + PA13_IBE + PA13_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 13 + 1 + read-write + + + PA14_IBE + PA14_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 14 + 1 + read-write + + + PA15_IBE + PA15_IBE: Interrupt edge selection for Port A I/Os. +0: single edge detection. +1: both edges detection + 15 + 1 + read-write + + + PB0_IBE + PB0_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 16 + 1 + read-write + + + PB1_IBE + PB1_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 17 + 1 + read-write + + + PB2_IBE + PB2_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 18 + 1 + read-write + + + PB3_IBE + PB3_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 19 + 1 + read-write + + + PB4_IBE + PB4_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 20 + 1 + read-write + + + PB5_IBE + PB5_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 21 + 1 + read-write + + + PB6_IBE + PB6_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 22 + 1 + read-write + + + PB7_IBE + PB7_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 23 + 1 + read-write + + + PB8_IBE + PB8_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 24 + 1 + read-write + + + PB9_IBE + PB9_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 25 + 1 + read-write + + + PB10_IBE + PB10_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 26 + 1 + read-write + + + PB11_IBE + PB11_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 27 + 1 + read-write + + + PB12_IBE + PB12_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 28 + 1 + read-write + + + PB13_IBE + PB13_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 29 + 1 + read-write + + + PB14_IBE + PB14_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 30 + 1 + read-write + + + PB15_IBE + PB15_IBE: Interrupt edge selection for port B I/Os. 0: single edge detection. +1: both edges detection. + 31 + 1 + read-write + + + + + IO_IEVR + IO_IEVR + IO_IEVR register + 0x14 + 0x20 + read-write + 0x00000000 + + + PA0_IEV + PA0_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 0 + 1 + read-write + + + PA1_IEV + PA1_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 1 + 1 + read-write + + + PA2_IEV + PA2_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 2 + 1 + read-write + + + PA3_IEV + PA3_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 3 + 1 + read-write + + + PA4_IEV + PA4_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 4 + 1 + read-write + + + PA5_IEV + PA5_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 5 + 1 + read-write + + + PA6_IEV + PA6_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 6 + 1 + read-write + + + PA7_IEV + PA7_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 7 + 1 + read-write + + + PA8_IEV + PA8_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 8 + 1 + read-write + + + PA9_IEV + PA9_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 9 + 1 + read-write + + + PA10_IEV + PA10_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 10 + 1 + read-write + + + PA11_IEV + PA11_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 11 + 1 + read-write + + + PA12_IEV + PA12_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 12 + 1 + read-write + + + PA13_IEV + PA13_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 13 + 1 + read-write + + + PA14_IEV + PA14_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 14 + 1 + read-write + + + PA15_IEV + PA15_IEV : Interrupt polarity event for Port A I/Os. +0: falling edge / low level. +1: rising edge / high level. + 15 + 1 + read-write + + + PB0_IEV + PB0_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 16 + 1 + read-write + + + PB1_IEV + PB1_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 17 + 1 + read-write + + + PB2_IEV + PB2_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 18 + 1 + read-write + + + PB3_IEV + PB3_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 19 + 1 + read-write + + + PB4_IEV + PB4_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 20 + 1 + read-write + + + PB5_IEV + PB5_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 21 + 1 + read-write + + + PB6_IEV + PB6_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 22 + 1 + read-write + + + PB7_IEV + PB7_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 23 + 1 + read-write + + + PB8_IEV + PB8_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 24 + 1 + read-write + + + PB9_IEV + PB9_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 25 + 1 + read-write + + + PB10_IEV + PB10_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 26 + 1 + read-write + + + PB11_IEV + PB11_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 27 + 1 + read-write + + + PB12_IEV + PB12_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 28 + 1 + read-write + + + PB13_IEV + PB13_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 29 + 1 + read-write + + + PB14_IEV + PB14_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 30 + 1 + read-write + + + PB15_IEV + PB15_IEV : Interrupt polarity event for Port B I/Os. +0: falling edge / low level. +1: rising edge / high level. + 31 + 1 + read-write + + + + + IO_IER + IO_IER + IO_IER register + 0x18 + 0x20 + read-write + 0x000000000 + + + PA0_IE + PA0_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 0 + 1 + read-write + + + PA1_IE + PA1_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 1 + 1 + read-write + + + PA2_IE + PA2_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 2 + 1 + read-write + + + PA3_IE + PA3_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 3 + 1 + read-write + + + PA4_IE + PA4_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 4 + 1 + read-write + + + PA5_IE + PA5_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 5 + 1 + read-write + + + PA6_IE + PA6_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 6 + 1 + read-write + + + PA7_IE + PA7_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 7 + 1 + read-write + + + PA8_IE + PA8_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 8 + 1 + read-write + + + PA9_IE + PA9_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 9 + 1 + read-write + + + PA10_IE + PA10_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 10 + 1 + read-write + + + PA11_IE + PA11_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 11 + 1 + read-write + + + PA12_IE + PA12_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 12 + 1 + read-write + + + PA13_IE + PA13_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 13 + 1 + read-write + + + PA14_IE + PA14_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 14 + 1 + read-write + + + PA15_IE + PA15_IE: Interrupt enable for port A I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 15 + 1 + read-write + + + PB0_IE + PB0_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 16 + 1 + read-write + + + PB1_IE + PB1_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 17 + 1 + read-write + + + PB2_IE + PB2_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 18 + 1 + read-write + + + PB3_IE + PB3_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 19 + 1 + read-write + + + PB4_IE + PB4_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 20 + 1 + read-write + + + PB5_IE + PB5_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 21 + 1 + read-write + + + PB6_IE + PB6_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 22 + 1 + read-write + + + PB7_IE + PB7_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 23 + 1 + read-write + + + PB8_IE + PB8_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 24 + 1 + read-write + + + PB9_IE + PB9_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 25 + 1 + read-write + + + PB10_IE + PB10_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 26 + 1 + read-write + + + PB11_IE + PB11_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 27 + 1 + read-write + + + PB12_IE + PB12_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 28 + 1 + read-write + + + PB13_IE + PB13_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 29 + 1 + read-write + + + PB14_IE + PB14_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 30 + 1 + read-write + + + PB15_IE + PB15_IE: Interrupt enable for port B I/Os. 0: interrupt is disabled. +1: interrupt is enabled. + 31 + 1 + read-write + + + + + IO_ISCR + IO_ISCR + IO_ISCR register + 0x1C + 0x20 + read-write + 0x00000000 + + + PA0_ISC + PA0_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 0 + 1 + read-write + + + PA1_ISC + PA1_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + PA2_ISC + PA2_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 2 + 1 + read-write + + + PA3_ISC + PA3_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 3 + 1 + read-write + + + PA4_ISC + PA4_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 4 + 1 + read-write + + + PA5_ISC + PA5_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 5 + 1 + read-write + + + PA6_ISC + PA6_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 6 + 1 + read-write + + + PA7_ISC + PA7_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 7 + 1 + read-write + + + PA8_ISC + PA8_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 8 + 1 + read-write + + + PA9_ISC + PA9_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 9 + 1 + read-write + + + PA10_ISC + PA10_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 10 + 1 + read-write + + + PA11_ISC + PA11_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 11 + 1 + read-write + + + PA12_ISC + PA12_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 12 + 1 + read-write + + + PA13_ISC + PA13_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 13 + 1 + read-write + + + PA14_ISC + PA14_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 14 + 1 + read-write + + + PA15_ISC + PA15_ISC: Interrupt status (before mask) for port a I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 15 + 1 + read-write + + + PB0_ISC + PB0_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 16 + 1 + read-write + + + PB1_ISC + PB1_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 17 + 1 + read-write + + + PB2_ISC + PB2_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 18 + 1 + read-write + + + PB3_ISC + PB3_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 19 + 1 + read-write + + + PB4_ISC + PB4_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 20 + 1 + read-write + + + PB5_ISC + PB5_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 21 + 1 + read-write + + + PB6_ISC + PB6_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 22 + 1 + read-write + + + PB7_ISC + PB7_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 23 + 1 + read-write + + + PB8_ISC + PB8_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 24 + 1 + read-write + + + PB9_ISC + PB9_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 25 + 1 + read-write + + + PB10_ISC + PB10_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 26 + 1 + read-write + + + PB11_ISC + PB11_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 27 + 1 + read-write + + + PB12_ISC + PB12_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 28 + 1 + read-write + + + PB13_ISC + PB13_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 29 + 1 + read-write + + + PB14_ISC + PB14_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 30 + 1 + read-write + + + PB15_ISC + PB15_ISC: Interrupt status (before mask) for port B I/Os. +0: no pending interrupt. +1: event occurred on corresponding I/O / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 31 + 1 + read-write + + + + + PWRC_IER + PWRC_IER + PWRC_IER register + 0x20 + 0x20 + read-write + 0x000000000 + + + BORH_IE + BORH_IE: BORH interrupt enable. +0: BORH interrupt is disabled. +1: BORH interrupt is enabled. + 0 + 1 + read-write + + + PVD_IE + PVD_IE: Programmable Voltage Detector interrupt enable. +0: PVD interrupt is disabled. +1: PVD interrupt is enabled. + 1 + 1 + read-write + + + WKUP_IE + WKUP_IE: Power Controller Wakeup event interrupt enable. +0: Interrupt on wakeup event seen by the PWRC is disabled. +1: Interrupt on wakeup event seen by the PWRC is enabled. + 2 + 1 + read-write + + + + + PWRC_ISCR + PWRC_ISCR + PWRC_ISCR register + 0x24 + 0x20 + read-write + 0x000000000 + + + BORH_ISC + BORH_ISC: BORH interrupt status. +0: no pending interrupt. +1: voltage went under BORH threshold / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 0 + 1 + read-write + + + PVD_ISC + PVD_ISC: Programmable Voltage Detector status. +0: no pending interrupt. +1: voltage went under programmed threshold / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. + 1 + 1 + read-write + + + WKUP_ISC + WKUP_ISC: Indicates the Power Controller receives a Wakeup event. +0: no pending interrupt. +1: Wakeup event on PWRC occurred / interrupt occurred (if enabled). +Cleared by writing 1 in the bit. +This flag will be read at 1 if a wakeup event arrives so close to the low power mode entry +requests that the PWRC aborts before shutting down the system. + 2 + 1 + read-write + + + + + GPIO_SWA_CTRL + GPIO_SWA_CTRL + GPIO_SWA_CTRL register + 0x28 + 0x20 + read-write + 0x000000000 + + + ATB1_nPVD + ATB1_nPVD: select the analog feature on PB14 between ATB1 and PVD when the PB14 I/O +is programmed in analog mode (in the associated GPIO_MODER register): +0: PVD external voltage feature is selected (default). +1: ATB1 feature is selected + 0 + 1 + read-write + + + + + INTAI_DTR + INTAI_DTR + INTAI_DTR register + 0x2C + 0x20 + read-write + 0x000000000 + + + TX_DT + TX_DT: detection type on TX_SEQUENCE signal: +0: detection on edge (default). +1: detection on level + 0 + 1 + read-write + + + RX_DT + RX_DT: detection type on RX_SEQUENCE signal: +0: detection on edge (default). +1: detection on level + 1 + 1 + read-write + + + COMP_DT + COMP_DT: detection type on COMP_OUT (after COMP_POL selection) signal: +0: detection on edge (default). +1: detection on level + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_DT + RFIP_BUSY_STATUS_DT: detection type on RFIP_BUSY_STATUS signal: +0: detection on edge (default). +1: detection on level + 5 + 1 + read-write + + + + + INTAI_IBER + INTAI_IBER + INTAI_IBER register + 0x30 + 0x20 + read-write + 0x000000000 + + + TX_IBE + TX_IBE: interrupt edge register on TX_SEQUENCE signal: +0: detection on single edge (default). +1: detection on both edges + 0 + 1 + read-write + + + RX_IBE + RX_IBE: interrupt edge register on RX_SEQUENCE signal: +0: detection on single edge (default). +1: detection on both edges + 1 + 1 + read-write + + + COMP_IBE + COMP_IBE: interrupt edge register on COMP_OUT signal: +0: detection on single edge (default). +1: detection on both edges + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_IBE + RFIP_BUSY_STATUS_IBE: interrupt edge register on RFIP_BUSY_STATUS signal: +0: detection on single edge (default). +1: detection on both edges + 5 + 1 + read-write + + + + + INTAI_IEVR + INTAI_IEVR + INTAI_IEVR register + 0x34 + 0x20 + read-write + 0x000000000 + + + TX_IEV + TX_IEV: interrupt polarity event on TX_SEQUENCE signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 0 + 1 + read-write + + + RX_IEV + RX_IEV: interrupt polarity event on RX_SEQUENCE signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 1 + 1 + read-write + + + COMP_IEV + COMP_IEV: interrupt polarity event on COMP_OUT signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_IEV + RFIP_BUSY_STATUS_IEV: interrupt polarity event on RFIP_BUSY_STATUS signal: +0: detection on falling edge / low level (default). +1: detection on rising edge / high level + 5 + 1 + read-write + + + + + INTAI_IER + INTAI_IER + INTAI_IER register + 0x38 + 0x20 + read-write + 0x000000000 + + + TX_IE + TX_IE: interrupt enable on TX_SEQUENCE signal: +0: TX_SEQUENCE interrupt is disabled (default). +1: TX_SEQUENCE interrupt is enabled + 0 + 1 + read-write + + + RX_IE + RX_IE: interrupt enable on RX_SEQUENCE signal: +0: RX_SEQUENCE interrupt is disabled (default). +1: RX_SEQUENCE interrupt is enabled + 1 + 1 + read-write + + + COMP_IE + COMP_IE: interrupt enable on COMP_OUT signal: +0: COMP_OUT interrupt is disabled (default). +1: COMP_OUT interrupt is enabled + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_IE + RFIP_BUSY_STATUS_IE: interrupt enable on RFIP_BUSY_STATUS signal: +0: RFIP_BUSY_STATUS interrupt is disabled (default). +1: RFIP_BUSY_STATUS interrupt is enabled + 5 + 1 + read-write + + + + + INTAI_ISCR + INTAI_ISCR + INTAI_ISCR register + 0x3C + 0x20 + read-write + 0x000000000 + + + TX_ISC + TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): +0: no activity on TX_SEQUENCE detected. +1: activity on TX_SEQUENCE occurred + 0 + 1 + read-write + + + RX_ISC + RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge +depending on BLERXTX_IEVR and BLERXTX_IBER): +0: no activity on RX_SEQUENCE detected. +1: activity on RX_SEQUENCE occurred + 1 + 1 + read-write + + + TX_ISEDGE + TX_ISEDGE: interrupt edge status on TX_SEQUENCE signal: +0: falling edge on TX_SEQUENCE detected. +1: rising edge on TX_SEQUENCE detected. + 2 + 1 + read-only + + + RX_ISEDGE + RX_ISEDGE: interrupt edge status on RX_SEQUENCE signal: +0: falling edge on RX_SEQUENCE detected. +1: rising edge on RX_SEQUENCE detected. + 3 + 1 + read-only + + + COMP_ISC + COMP_ISC: interrupt status on COMP_OUT (can be a rising or a falling edge depending on +INTAI_IEVR and INTAI_IBER): +0: no activity on COMP_OUT detected. +1: activity on COMP_OUT occurred + 4 + 1 + read-write + + + RFIP_BUSY_STATUS_ISC + RFIP_BUSY_STATUS_ISC: interrupt status on RFIP_BUSY_STATUS (can be a rising or a +falling edge depending on INTAI_IEVR and INTAI_IBER): +0: no activity on RFIP_BUSY_STATUS detected. +1: activity on RFIP_BUSY_STATUS occurred + 5 + 1 + read-write + + + + + SYSCFG_SR1 + SYSCFG_SR1 + SYSCFG_SR1 register + 0x40 + 0x20 + read-only + 0x000000000 + + + RFIP_BUSY_STATUS + RFIP_BUSY_STATUS: MR_SUBG BUSY status: +Software should check that MR_SUBG IP is not busy (or relay on the related interrupt) before +to initiate any system clock frequency switch to operate the switching in a safe way. +0: MR_SUBG is not busy. +1: MR_SUBG is busy + 5 + 1 + read-only + + + + + RF_DTB_CONFIG + RF_DTB_CONFIG + RF_DTB_CONFIG register + 0x44 + 0x20 + read-write + 0x000000000 + + + RF_DTB_CONFIG + Controlling AF7 extended mode: +- 00 : MR_SUBG DTB default configuration +- 01 : MR_SUBG DTB shuffled configuration +- 10 : BUBBLE_DTB configuration +- 11 : MR_SUBG DTB default configuration (as per 00) + 0 + 2 + read-write + + + + + + + SWITCHABLE + SWITCHABLE + 0x49001040 + + 0x0 + 0x40 + registers + + + + RFIP_VERSION + RFIP_VERSION + RFIP_VERSION register + 0x0 + 0x20 + read-only + 0x00001100 + + + REVISION + Revision of the RFIP to be used for metal fixes) + 4 + 4 + read-only + + + VERSION + Version of the RFIP (to be used for cut upgrades) + 8 + 4 + read-only + + + PRODUCT + Used for major upgrades (new protocols support / new features) + 12 + 4 + read-only + + + + + IRQ_ENABLE + IRQ_ENABLE + IRQ_ENABLE register + 0x4 + 0x20 + read-write + 0x00000000 + + + BIT_SYNC_DETECTED_E + Preamble has been detected, the content of the PAYLOAD_X registers is not yet valid. + 0 + 1 + read-write + + + FRAME_SYNC_COMPLETE_E + Frame Sync has been detected, the content of the PAYLOAD_X registers is not yet valid. + 1 + 1 + read-write + + + FRAME_COMPLETE_E + Frame ( payload + CRC) received, the content of the PAYLOAD_X registers is valid. + 2 + 1 + read-write + + + FRAME_VALID_E + Frame ( payload + CRC) received wthout error (the CRC has been checked and is matching with the received CRC). + 3 + 1 + read-write + + + + + STATUS + STATUS + STATUS register + 0x8 + 0x20 + read-write + 0x00000000 + + + BIT_SYNC_DETECTED_F + Preamble has been detected, the content of the PAYLOAD_X registers is not yet valid. + 0 + 1 + read-write + + + FRAME_SYNC_COMPLETE_F + Frame Sync has been detected, the content of the PAYLOAD_X registers is not yet valid. + 1 + 1 + read-write + + + FRAME_COMPLETE_F + Frame ( payload + CRC) received, the content of the PAYLOAD_X registers is valid. + 2 + 1 + read-write + + + FRAME_VALID_F + Frame ( payload + CRC) received wthout error (the CRC has been checked and is matching with the received CRC). + 3 + 1 + read-write + + + ERROR_F + - 11 : CRC error + + 30 + 2 + read-write + + + + + + + STATUS + STATUS + 0x49000600 + + 0x0 + 0x40 + registers + + + + RFSEQ_IRQ_STATUS + RFSEQ_IRQ_STATUS + RFSEQ_IRQ_STATUS register + 0x0 + 0x20 + read-write + 0x00000000 + + + TX_DONE_F + Transmission done flag + 0 + 1 + + + RX_OK_F + Reception ended and OK flag + 1 + 1 + + + RX_TIMEOUT_F + Reception timeout flag + 2 + 1 + + + RX_CRC_FRROR_F + Reception with CRC error flag + 3 + 1 + + + FAST_RX_TERM_F + Fast RX Termination flag + 4 + 1 + + + RXTIMER_STOP_CDT_F + Enable interrupt on RXTIMER_STOP_CDT_F flag + 7 + 1 + + + SABORT_DONE_F + SABORT command treated and done flag + 8 + 1 + + + COMMAND_REJECTED_F + Command rejection flag. + 9 + 1 + + + CS_F + Carrier Sense (RSSI over threshold) flag + 12 + 1 + + + PREAMBLE_VALID_F + Valid PREAMBLE detection flag. + 13 + 1 + + + SYNC_VALID_F + Valid SYNC word detection flag. + 14 + 1 + + + DATABUFFER0_USED_F + Data Buffer 0 fully read in TX or fully written in RX flag + 16 + 1 + + + DATABUFFER1_USED_F + Data Buffer 1 fully read in TX or fully written in RX flag + 17 + 1 + + + RX_ALMOST_FULL_0_F + Data Buffer0 used (written during a RX) up to programmed thresold flag + 18 + 1 + + + RX_ALMOST_FULL_1_F + Data Buffer1 used (written during a RX) up to programmed thresold flag + 19 + 1 + + + TX_ALMOST_EMPTY_0_F + Data Buffer0 used (read during a TX) up to programmed thresold flag + 20 + 1 + + + TX_ALMOST_EMPTY_1_F + Data Buffer1 used (read during a TX) up to programmed thresold flag + 21 + 1 + + + AHB_ACCESS_ERROR_F + An AHB transfer issue occurred for one of the AHB masters (RRM, Data Buffer Manager, Sequencer). + 22 + 1 + + + HW_ANA_FAILURE_F + Analog HW failure flag (PLL lock / unlock error, calibration error) + + 24 + 1 + + + SEQ_F + Sequencer completion flag. + 26 + 1 + + + RRM_CMD_START_F + RRM-UDRA command list execution started flag. + 27 + 1 + + + RRM_CMD_END_F + RRM-UDRA command list execution ended flag. + 28 + 1 + + + SAFEASK_CALIB_DONE_F + End of Safe-ASK PA calibration flag. + 30 + 1 + + + AGC_CALIB_DONE_F + Valid RSSI value available in the RSSI_RUNNING bit field flag. + 31 + 1 + + + + + RFSEQ_STATUS_DETAIL + RFSEQ_STATUS_DETAIL + RFSEQ_STATUS_DETAIL register + 0x4 + 0x20 + read-write + 0x00000000 + + + DBM_FIFO_ERROR_F + Data Buffer Manager internal FIFO overflow/underflow flag. + 5 + 1 + + + PLL_LOCK_FAIL_F + PLL lock fail status flag + 8 + 1 + + + PLL_UNLOCK_F + PLL unlock event flag + 9 + 1 + + + PLL_CALFREQ_ERROR_F + VCO frequency calibration error flag + 10 + 1 + + + PLL_CALAMP_ERROR_F + VCO amplitude calibration error flag + 11 + 1 + + + SEQ_ACTIONTIMEOUT_F + The Sequencer has ended because the current SeqAction reached its ActionTimeout. + 14 + 1 + + + SEQ_COMPLETE_F + The Sequencer has ended the last defined SeqAction properly( NextAction math or null pointer) + 15 + 1 + + + + + RADIO_FSM_INFO + RADIO_FSM_INFO + RADIO_FSM_INFO register + 0x8 + 0x20 + read-only + 0x00000000 + + + RADIO_FSM_STATE + State of the Radio FSM + + 0 + 5 + read-only + + + + + RX_INDICATOR + RX_INDICATOR + RX_INDICATOR register + 0xc + 0x20 + read-only + 0x00000000 + + + RSSI_LEVEL_ON_SYNC + RSSI level captured at the end of the SYNC word detection of the received packet. + 0 + 9 + read-only + + + RSSI_LEVEL_RUN + Continuous level of the output of the measured RSSI value + 12 + 9 + read-only + + + AGC_WORD + AGC word of the received packet. + 24 + 4 + read-only + + + ANT_SELECT + Currently selected antenna + 31 + 1 + read-only + + + + + RX_INFO_REG + RX_INFO_REG + RX_INFO_REG register + 0x10 + 0x20 + read-only + 0x00000000 + + + RX_PCKTLEN_OUT + Indicates received packet length in bytes: + + 0 + 16 + read-only + + + + + RX_CRC_REG + RX_CRC_REG + RX_CRC_REG register + 0x14 + 0x20 + read-only + 0x00000000 + + + RX_CRC_OUT + CRC field of the received packet (read-only info) + 0 + 32 + read-only + + + + + QI_INFO + QI_INFO + QI_INFO register + 0x18 + 0x20 + read-only + 0x00000000 + + + PQI_INFO + Preamble Quality Indicator (PQI) value of the received packet. + 0 + 8 + read-only + + + SQI_INFO + SYNC Quality Indicator (SQI) value of the received packet. + 8 + 6 + read-only + + + SQI_SEC + Indicate if measured SQI refers to SYNC word or secondary SYNC word + + 14 + 1 + read-only + + + AFC_CORRECTION + AFC value frozen at sync reception. + 16 + 8 + read-only + + + + + DATABUFFER_INFO + DATABUFFER_INFO + DATABUFFER_INFO register + 0x1c + 0x20 + read-only + 0x00000000 + + + CURRENT_DATABUFFER_COUNT + Indicates the number of bytes used in the last used DATA BUFFER. + 0 + 16 + read-only + + + NB_DATABUFFER_USED + Provides the number of data buffers which have been fully used + + 16 + 15 + read-only + + + CURRENT_DATABUFFER + Indicates which Data Buffer is currently used by the HW + + 31 + 1 + read-only + + + + + TIME_CAPTURE + TIME_CAPTURE + TIME_CAPTURE register + 0x20 + 0x20 + read-only + 0x00000000 + + + TIME_CAPTURE + Interpolated absolute time value captured on specific programmable event through TIME_CAPTURESEL[2:0] bit field. + 0 + 32 + read-only + + + + + IQC_CORRECTION_OUT + IQC_CORRECTION_OUT + IQC_CORRECTION_OUT register + 0x24 + 0x20 + read-only + 0x00000000 + + + IQC_CORRECT_OUT + Final correction value output from IQC (compensation engine). + 0 + 24 + read-only + + + + + PA_SAFEASK_OUT + PA_SAFEASK_OUT + PA_SAFEASK_OUT register + 0x28 + 0x20 + read-only + 0x00000000 + + + PA_CODEMAX + Safe ASK level (provided after a CALIB_SAFEASK command), indicating the maximum PA Power to program before reaching ohmic saturation. + 0 + 8 + read-only + + + + + VCO_CALIB_OUT + VCO_CALIB_OUT + VCO_CALIB_OUT register + 0x2c + 0x20 + read-only + 0x0000FF40 + + + VCO_CALFREQ_OUT + VCO frequency calibration value currently output by the VCO calibration block (and applied on the VCO when ON) + + 0 + 7 + read-only + + + VCO_CALAMP_OUT + VCO amplitude calibration value currently output by the VCO calibration block (and applied on the VCO when ON) + + 8 + 14 + read-only + + + + + SEQ_INFO + SEQ_INFO + SEQ_INFO register + 0x30 + 0x20 + read-only + 0x00000000 + + + SEQ_FSM_STATE + Current state of the Sequencer + + 0 + 5 + read-only + + + + + SEQ_EVENT_STATUS + SEQ_EVENT_STATUS + SEQ_EVENT_STATUS register + 0x34 + 0x20 + read-only + 0x00000000 + + + SEQ_EVENT_STATUS + Current value of the seq_event_status used by the Sequencer for next action mask comparison. + 0 + 32 + read-only + + + + + + + STATIC + STATIC + 0x49000400 + + 0x0 + 0x40 + registers + + + + PCKT_CONFIG + PCKT_CONFIG + PCKT_CONFIG register + 0x0 + 0x20 + read-write + 0x000103F1 + + + CRC_MODE + CRC type (0, 8, 16, 16 802. + 0 + 3 + read-write + + + SECONDARY_SYNC_SEL + In TX mode: this bit selects which synchro word is sent on the frame between SYNC and SEC_SYNC + + 3 + 1 + read-write + + + SYNC_LEN + Length of the SYNC (and secondary) SYNC word in 1-bit granularity + + 4 + 5 + read-write + + + SYNC_PRESENT + Indicate if a SYNC word is present on the frame or not (null length) + + 9 + 1 + read-write + + + LEN_WIDTH + Indicates if the LENGTH field is defined on 1 byte or 2 bytes + + 10 + 1 + read-write + + + FIX_VAR_LEN + Select the length mode + + 11 + 1 + read-write + + + PREAMBLE_LENGTH + Length of the PREAMBLE in pairs of bits (0 to 2046) + 12 + 10 + read-write + + + PREAMBLE_SEQ + Select the PREAMBLE pattern to be applied + + 22 + 2 + read-write + + + POSTAMBLE_LENGTH + Length of the POSTAMBLE in pair of bits (0 to 126 bits) + 24 + 6 + read-write + + + POSTAMBLE_SEQ + Packet postamble control: postamble bit sequence selection + + 30 + 2 + read-write + + + + + SYNC + SYNC + SYNC register + 0x4 + 0x20 + read-write + 0x23232323 + + + SYNC + Synchro word. + 0 + 32 + read-write + + + + + SEC_SYNC + SEC_SYNC + SEC_SYNC register + 0x8 + 0x20 + read-write + 0x00000000 + + + SEC_SYNC + Secondary Synchro word. + 0 + 32 + read-write + + + + + CRC_INIT + CRC_INIT + CRC_INIT register + 0xc + 0x20 + read-write + 0x00000000 + + + CRC_INIT_VAL + CRC intialization value + 0 + 32 + read-write + + + + + PCKT_CTRL + PCKT_CTRL + PCKT_CTRL register + 0x10 + 0x20 + read-write + 0x00000000 + + + PCKT_FORMAT + Packet format + + 0 + 1 + read-write + + + BYTE_SWAP + Invert MSB-LSB transmission order (bitendianess) + + 2 + 1 + read-write + + + FOUR_FSK_SYM_SWAP + Invert bit to symbol mapping for 4-(G)FSK + + 3 + 1 + read-write + + + RX_MODE + RX mode + + 4 + 3 + read-write + + + TX_MODE + TX mode + + 7 + 2 + read-write + + + WHIT_BF_FEC + Whitening before FEC feature + + 10 + 1 + read-write + + + WHIT_EN + Whitening enable + + 11 + 1 + read-write + + + WHIT_INIT + Whitening initialization value. + 12 + 9 + read-write + + + CODING_SEL + Coding / decoding selection + + 21 + 2 + read-write + + + MANCHESTER_TYPE + Select the Manchester encoding polarity + + 24 + 1 + read-write + + + INT_EN_4G + This field is used as Interleaving enable for 802. + 25 + 1 + read-write + + + FEC_TYPE_4G + FEC type for 802. + 26 + 1 + read-write + + + FCS_TYPE_4G + FCS type value in header field for 802. + 27 + 1 + read-write + + + MOD_INTERP_EN + Enable frequency interpolator (for 2-GFSK and 4-GFSK) + + 28 + 1 + read-write + + + PN_SEL + Select the Pseudo Random Binary Sequence (PRBS) polynomial to apply when the selected transmission mode is PN mode (TX_MODE = '11') + + 29 + 1 + read-write + + + FORCE_2FSK_SYNC_MODE + Force SYNC word to be formatted as a 2-(G)FSK bit steam instead of 4-(G)FSK + + 31 + 1 + read-write + + + + + DATABUFFER0_PTR + DATABUFFER0_PTR + DATABUFFER0_PTR register + 0x14 + 0x20 + read-write + 0x00000000 + + + DATABUFFER0_PTR + Start address to be used by the Data Buffer0 + + 2 + 30 + read-write + + + + + DATABUFFER1_PTR + DATABUFFER1_PTR + DATABUFFER1_PTR register + 0x18 + 0x20 + read-write + 0x00000000 + + + DATABUFFER1_PTR + Start address to be used by the Data Buffer1 + + 2 + 30 + read-write + + + + + DATABUFFER_SIZE + DATABUFFER_SIZE + DATABUFFER_SIZE register + 0x1c + 0x20 + read-write + 0x00000000 + + + DATABUFFER_SIZE + Size of the Data Buffers (Data Buffer0 and Data Buffer1) expressed in byte unit. + 0 + 16 + read-write + + + + + PA_LEVEL_3_0 + PA_LEVEL_3_0 + PA_LEVEL_3_0 register + 0x20 + 0x20 + read-write + 0x230B0100 + + + PA_LEVEL0 + Output power level for first step + + 0 + 8 + read-write + + + PA_LEVEL1 + Output power level for second step + + 8 + 8 + read-write + + + PA_LEVEL2 + Output power level for third step + + 16 + 8 + read-write + + + PA_LEVEL3 + Output power level for fourth step + + 24 + 8 + read-write + + + + + PA_LEVEL_7_4 + PA_LEVEL_7_4 + PA_LEVEL_7_4 register + 0x24 + 0x20 + read-write + 0x51473B2F + + + PA_LEVEL4 + Output power level for fifth step + + 0 + 8 + read-write + + + PA_LEVEL5 + Output power level for sixth step + + 8 + 8 + read-write + + + PA_LEVEL6 + Output power level for seventh step + + 16 + 8 + read-write + + + PA_LEVEL7 + Output power level for eighth step + + 24 + 8 + read-write + + + + + PA_CONFIG + PA_CONFIG + PA_CONFIG register + 0x28 + 0x20 + read-write + 0x0000015C + + + PA_RAMP_STEP_WIDTH + Step width (unit: 1/8 of bit period). + 0 + 2 + read-write + + + PA_LEVEL_MAX_INDEX + Final level for power ramping (i. + 2 + 3 + read-write + + + PA_INTERP_EN + Enable power level interpolator. + 6 + 1 + read-write + + + ASK_OOK_EN + Enable the generation of the internal TXDATA signal provided to the FIR. + 7 + 1 + read-write + + + PA_DRV_MODE + Select the PA topology + + 8 + 2 + read-write + + + PA_MODE + Configure the Power Amplifier (PA) mode + + 10 + 2 + read-write + + + LIN_NLOG + Enable/disable the linear-to- log conversion of the PA code output from Safe-ASK calibrator + + 13 + 1 + read-write + + + PA_RAMP_ENABLE + Enable the power ramping + + 14 + 1 + read-write + + + + + IF_CTRL + IF_CTRL + IF_CTRL register + 0x2c + 0x20 + read-write + 0x04CD04CD + + + IF_OFFSET_DIG + Intermediate frequency setting for the digital shift-to-baseband circuits (default: 300 kHz) + + 0 + 13 + read-write + + + IF_OFFSET_ANA + Intermediate frequency setting for the synthesizer configuration (default: 300 kHz). + 16 + 13 + read-write + + + IF_MODE + Select the cutoff frequency of the AAF for the analog RFSUBG IP + + 31 + 1 + read-write + + + + + AS_QI_CTRL + AS_QI_CTRL + AS_QI_CTRL register + 0x30 + 0x20 + read-write + 0x58008028 + + + RSSI_THR + Signal detect threshold in 1 dB resolution. + 0 + 9 + read-write + + + PQI_THR + PQI threshold (if 0 then ). + 9 + 4 + read-write + + + CS_MODE + Carrier Sense mode selection + + 13 + 2 + read-write + + + SQI_EN + SQI enable + + 15 + 1 + read-write + + + SQI_THR + SQI threshold defining the precision requested to detect the SYNC word. + 16 + 3 + read-write + + + AS_EQU_CTRL + ISI cancellation equalizer + + 26 + 2 + read-write + + + AS_MEAS_TIME + Select the RSSI measurement duration during Antenna switching procedure + 28 + 3 + read-write + + + AS_CS_BLANKING + Blank received data if signal is below the CS threshold + + 31 + 1 + read-write + + + + + IQC_CONFIG + IQC_CONFIG + IQC_CONFIG register + 0x34 + 0x20 + read-write + 0xC0000000 + + + IQC_CORRECT_IN + Correction value Input for the IQ compensation engine (to be used as starting point or when the engine is disabled). + 0 + 24 + read-write + + + LOAD_IQC_INIT + Action bit to load the IQC_CORRECT_IN[23:0] bit field in the recirculation register when this bit is written to 1. + 29 + 1 + write-only + + + REUSE_CORRECTION + Reuse last correction value + 30 + 1 + read-write + + + IQC_ENABLE + Enable IQC + 31 + 1 + read-write + + + + + DSSS_CTRL + DSSS_CTRL + DSSS_CTRL register + 0x38 + 0x20 + read-write + 0x00000000 + + + ACQ_WINDOW + DSSS acquisition window + 0 + 4 + read-write + + + SPREADING_EXP + DSSS spreading exponent + 4 + 3 + read-write + + + DSSS_EN + DSSS mode enable + 7 + 1 + read-write + + + ACQ_HITS + DSSS acquisition hits + 8 + 2 + read-write + + + ACQ_THR + DSSS acquisition threshold + 10 + 6 + read-write + + + + + + + TIM16 + TIM16 address block description + TIM16 + 0x40005000 + + 0x0 + 0x6C + registers + + + TIM16 + TIM16 interrupt + 26 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIF_REMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + CCPC + CCPC: Capture/compare preloaded control + +0: CCxE, CCxNE and OCxM bits are not preloaded + +1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated + +only when COM bit is set. + +Note: This bit acts only on channels that have a complementary output. + 0 + 1 + read-write + + + CCUS + CCUS: Capture/compare control update selection + +0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit only. + +1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting + +the COMG bit or when an rising edge occurs on TRGI. + +Note: This bit acts only on channels that have a complementary output. + 2 + 1 + read-write + + + CCDS + CCDS: Capture/compare DMA selection + +0: CCx DMA request sent when CCx event occurs + +1: CCx DMA requests sent when update event occurs + 3 + 1 + read-write + + + MMS + MMS[2:0]: Master mode selection + +These bits allow to select the information to be sent in master mode to slave timers for + +synchronization (TRGO). The combination is as follows: + +000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the + +reset is generated by the trigger input (slave mode controller configured in reset mode) then + +the signal on TRGO is delayed compared to the actual reset. + +001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is + +useful to start several timers at the same time or to control a window in which a slave timer is + +enable. The Counter Enable signal is generated by a logic OR between CEN control bit and + +the trigger input when configured in gated mode. When the Counter Enable signal is + +controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is + +selected (see the MSM bit description in TIMx_SMCR register). + +010: Update - The update event is selected as trigger output (TRGO). For instance a master + +timer can then be used as a prescaler for a slave timer. + +011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be + +set (even if it was already high), as soon as a capture or a compare match occurred. + +(TRGO). + +100: Compare - OC1REF signal is used as trigger output (TRGO). + 4 + 3 + read-write + + + TI1S + TI1S: TI1 selection + +0: The TIMx_CH1 pin is connected to TI1 input + +1: Reserved + 7 + 1 + read-write + + + OIS1 + OIS1: Output Idle state 1 (OC1 output) + +0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 + +1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 8 + 1 + read-write + + + OIS1N + OIS1N: Output Idle state 1 (OC1N output) + +0: OC1N=0 after a dead-time when MOE=0 + +1: OC1N=1 after a dead-time when MOE=0 + +Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BKR register). + 9 + 1 + read-write + + + + + SMCR + SMCR + SMCR register + 0x08 + 0x20 + read-write + 0x0 + 0xF + + + SMS_2_0 + SMS[3:0]: Slave mode selection +When external signals are selected the active edge of the trigger signal (TRGI) is linked to +the polarity selected on the external input (see Input Control register and Control Register +description. + 0 + 3 + read-write + + + TS_2_0 + TS[4:0]: Trigger selection + +This bitfield selects the trigger input to be used to synchronize the counter. + +00000: Internal Trigger 0 (ITR0) + +00001: Internal Trigger 1 (ITR1) + +00010: Internal Trigger 2 (ITR2) + +00011: Internal Trigger 3 (ITR3) + +00100: TI1 Edge Detector (TI1F_ED) + +00101: Filtered Timer Input 1 (TI1FP1) + +Other codes: Reserved + +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to + +avoid wrong edge detections at the transition. + +See Table 79 in IUM: TIM16 register map and reset values on page 469 for more details on ITRx + +meaning for each Timer. + 4 + 3 + read-write + + + MSM + MSM: Master/slave mode + +0: No action + +1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect + +synchronization between the current timer and its slaves (through TRGO). It is useful if we + +want to synchronize several timers on a single external event. + 7 + 1 + read-write + + + SMS_3 + SMS[3:0]: Slave mode selection. See SMS_LSB description + 16 + 1 + read-write + + + TS_4_3 + TS[4:0]: Trigger selection. See TS_LSB description + 20 + 2 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + COMIE + COMIE: COM interrupt enable + +0: COM interrupt disabled + +1: COM interrupt enabled + 5 + 1 + read-write + + + TIE + TIE: Trigger interrupt enable + +0: Trigger interrupt disabled + +1: Trigger interrupt enabled + 6 + 1 + read-write + + + BIE + BIE: Break interrupt enable + +0: Break interrupt disabled + +1: Break interrupt enabled + 7 + 1 + read-write + + + UDE + UDE: Update DMA request enable + +0: Update DMA request disabled + +1: Update DMA request enabled + 8 + 1 + read-write + + + CC1DE + CC1DE: Capture/Compare 1 DMA request enable + +0: CC1 DMA request disabled + +1: CC1 DMA request enabled + 9 + 1 + read-write + + + CCUDE + CCUDE: CC-Update DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: CC-Update DMA request disabled. + +1: CC-Update DMA request enabled. + 13 + 1 + read-write + + + TDE + TDE: Trigger DMA request enable + +0: Trigger DMA request disabled + +1: Trigger DMA request enabled + 14 + 1 + read-write + + + BDE + BDE: Break DMA request Enable. + +Not used in Blue51. Not available in IUM + +0: Break DMA request disabled. + +1: Break DMA request enabled. + 15 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value. It is cleared by + +software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + COMIF + COMIF: COM interrupt flag + +This flag is set by hardware on a COM event (once the capture compare control bits CCxE, + +CCxNE, OCxMhave been updated). It is cleared by software. + +0: No COM event occurred + +1: COM interrupt pending + 5 + 1 + read-write + + + TIF + TIF: Trigger interrupt flag + +This flag is set by hardware on trigger event (active edge detected on TRGI input when the + +slave mode controller is enabled in all modes but gated mode, both edges in case gated + +mode is selected). It is cleared by software. + +0: No trigger event occurred + +1: Trigger interrupt pending + 6 + 1 + read-write + + + BIF + BIF: Break interrupt flag + +This flag is set by hardware as soon as the break input goes active. It can be cleared by + +software if the break input is not active. + +0: No break event occurred + +1: An active level has been detected on the break input + 7 + 1 + read-write + + + CC1OF + CC1OF: Capture_Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + COMG + COMG: Capture/Compare control update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action + +1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits + +Note: This bit acts only on channels that have a complementary output. + 5 + 1 + write-only + + + TG + TG: Trigger generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action + +1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if + +enabled + 6 + 1 + write-only + + + BG + BG: Break generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or + +DMA transfer can occur if enabled. + 7 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately.. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M[2:0]: Output Compare 1 mode (bits 2 to 0) +These bits define the behavior of the output reference signal OC1REF from which OC1 and +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends +on CC1P and CC1NP bits. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable. + +Not used in Blue51. Not available in IUM + +0: OC1REF is not affected by the ocref_clr_int signal. + +1: OC1REF is cleared as soon as a high level is detected on the ocref_clr_int signal. + 7 + 1 + read-write + + + OC1M_3 + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1_in register + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations.. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + B_0x1 + Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + 0x1 + + + + + CC1NE + CC1NE: Capture/Compare 1 complementary output enable + +0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1E bits. + +1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1E bits. + 2 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 complementary output polarity + +CC1 channel configured as output: + +0: OC1N active high + +1: OC1N active low + +CC1 channel configured as input: + +This bit is used in conjunction with CC1P to define the polarity of TI1FP1. Refer + +to the description of CC1P. + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the + +preloaded bit only when a commutation event is generated. + 3 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIF_CPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0xFFFF + 0xFFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x0 + 0xF + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 8 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + CCR + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + BDTR + BDTR + BDTR register + 0x44 + 0x20 + read-write + 0x0 + 0xF + + + DTG + DTG[7:0]: Dead-time generator setup + +This bit-field defines the duration of the dead-time inserted between the complementary + +outputs. DT correspond to this duration. + +DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS + +DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS + +DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS + +DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS + +Example if TDTS=125ns (8MHz), dead-time possible values are: + +0 to 15875 ns by 125 ns steps, + +16 us to 31750 ns by 250 ns steps, + +32 us to 63 us by 1 us steps, + +64 us to 126 us by 2 us steps + +Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + +(LOCK bits in TIMx_BDTR register). + 0 + 8 + read-write + + + LOCK + LOCK[1:0]: Lock configuration + +These bits offer a write protection against software errors. + +00: LOCK OFF - No bit is write protected + +01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 + +register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in + +TIMx_AF1 register can no longer be written. + +10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER + +register, as long as the related channel is configured in output through the CCxS bits) as well + +as OSSR and OSSI bits can no longer be written. + +11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in + +TIMx_CCMRx registers, as long as the related channel is configured in output through the + +CCxS bits) can no longer be written. + +Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + +has been written, their content is frozen until the next reset. + 8 + 2 + read-write + + + OSSI + OSSI: Off-state selection for Idle mode + +This bit is used when MOE=0 on channels configured as outputs. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) + +1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or + +CCxNE=1. OC/OCN enable output signal=1) + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 10 + 1 + read-write + + + OSSR + OSSR: Off-state selection for Run mode + +This bit is used when MOE=1 on channels that have a complementary output which are + +configured as outputs. OSSR is not implemented if no complementary output is implemented + +in the timer. + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + +0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which + +is taken over by the AFIO logic, which forces a Hi-Z state) + +1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 + +or CCxNE=1 (the output is still controlled by the timer). + +Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK + +bits in TIMx_BDTR register). + 11 + 1 + read-write + + + BKE + BKE: Break enable + +1; Break inputs (BRK) enabled + +Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in + +TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 12 + 1 + read-write + + + B_0x0 + Break inputs (BRK) disabled + 0x0 + + + + + BKP + BKP: Break polarity + +0: Break input BRK is active low. + +1: Break input BRK is active high + +Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register). + +Note: 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 13 + 1 + read-write + + + AOE + AOE: Automatic output enable + +not be active) + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + 14 + 1 + read-write + + + B_0x0 + MOE can be set only by software + 0x0 + + + B_0x1 + MOE can be set by software or automatically at the next update event (if the break input is + 0x1 + + + + + MOE + MOE: Main output enable + +This bit is cleared asynchronously by hardware as soon as the break input is active. It is set + +by software or automatically depending on the AOE bit. It is acting only on the channels + +which are configured in output. + +0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. + +1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in + +TIMx_CCER register) + +See OC/OCN enable description for more details (Section 22.4.8: TIM16 capture/compare + +enable register (TIMx_CCER)). + 15 + 1 + read-write + + + BKDSRM + BKDSRM: Break Disarm + +0: Break input BRK is armed + +1: Break input BRK is disarmed + +This bit is cleared by hardware when no break source is active. + +The BKDSRM bit must be set by software to release the bidirectional output control (opendrain + +output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the + +fault condition has disappeared. + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 26 + 1 + read-write + + + BKBID + BKBID: Break Bidirectional + +0: Break input BRK in input mode + +1: Break input BRK in bidirectional mode + +In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input + +mode and in open drain output mode. Any active break event asserts a low logic level on the + +Break input to indicate an internal break event to external devices. + +Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits + +in TIMx_BDTR register). + +Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. + 28 + 1 + read-write + + + + + DCR + DCR + DCR register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + DBA + DBA[4:0]: DMA base address + +This 5-bit field defines the base-address for DMA transfers (when read/write access are + +done through the TIMx_DMAR address). DBA is defined as an offset starting from the + +address of the TIMx_CR1 register. + +Example: + +00000: TIMx_CR1, + +00001: TIMx_CR2, + +00010: Reserved, + +... + +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In + +this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + DBL + DBL[4:0]: DMA burst length + +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when + +a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. + +Transfers can be in half-words or in bytes (see example below). + +00000: 1 transfer, + +00001: 2 transfers, + +00010: 3 transfers, + +... + +10001: 18 transfers. + 8 + 5 + read-write + + + + + DMAR + DMAR + DMAR register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + DMAB + DMAB[15:0]: DMA register for burst accesses + +A read or write operation to the DMAR register accesses the register located at the address + +(TIMx_CR1 address) + (DBA + DMA index) x 4 + +where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base + +address configured in TIMx_DCR register, DMA index is automatically controlled by the + +DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). + 0 + 16 + read-write + + + + + OR1 + OR1 + OR1 register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + OR1_0 + Not used in Blue51. Not available in IUM + 0 + 1 + read-write + + + TI1_RMP + TI1_RMP[1:0]: Timer 16 input 1 connection + +This bit is set and cleared by software. + +00: TIM16 TI1 is connected to GPIO + +01: TIM16 TI1 is connected to LCO + +10: TIM16 TI1 is connected to COMP_OUT + +11: TIM16 TI1 is connected to MCO + 1 + 2 + read-write + + + + + AF1 + AF1 + AF1 register + 0x60 + 0x20 + read-write + 0x1 + 0xF + + + BKINE + BKINE: BRK BKIN enable. + +This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is + +ORed with the other enabled BRK sources. + +0: BKIN input disabled. + +1: BKIN input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 0 + 1 + read-write + + + BKCMP1E + BKCMP1E: BRK COMP1 enable. + +This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other + +enabled BRK sources. + +0: COMP1 input disabled. + +1: COMP1 input enabled. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 1 + 1 + read-write + + + BKINP + BKINP: BRK BKIN input polarity. + +This bit selects the BKIN alternate function input sensitivity. It must be programmed together + +with the BKP polarity bit. + +0: BKIN input is active low. + +1: BKIN input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 9 + 1 + read-write + + + BKCMP1P + BKCMP1P: BRK COMP1 input polarity. + +This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP + +polarity bit. + +0: COMP1 input is active low. + +1: COMP1 input is active high. + +Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 10 + 1 + read-write + + + + + TISEL + TISEL + TISEL register + 0x68 + 0x20 + read-write + + + TI1SEL + TI1SEL[3:0]: selects TI1[0] to TI1[15] input + +0000: TIMx_CH1 input + +Others: Reserved + 0 + 4 + read-write + + + + + + + TIM2 + TIM2 address block description + TIM2 + 0x40002000 + + 0x0 + 0x6C + registers + + + TIM2 + TIM2 interrupt + 10 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x0 + 0xF + + + CEN + CEN: Counter enable + +0: Counter disabled + +1: Counter enabled + +Note: External clock and gated mode can work only if the CEN bit has been previously set by + +software. However trigger mode can set the CEN bit automatically by hardware. + 0 + 1 + read-write + + + UDIS + UDIS: Update disable + +This bit is set and cleared by software to enable/disable UEV event generation. + +0: UEV enabled. The Update (UEV) event is generated by one of the following events: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +Buffered registers are then loaded with their preload values. + +1: UEV disabled. The Update event is not generated, shadow registers keep their value + +(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is + +set or if a hardware reset is received from the slave mode controller. + 1 + 1 + read-write + + + URS + URS: Update request source + +This bit is set and cleared by software to select the UEV event sources. + +0: Any of the following events generate an update interrupt or DMA request if enabled. + +These events can be: + +- Counter overflow/underflow + +- Setting the UG bit + +- Update generation through the slave mode controller + +1: Only counter overflow/underflow generates an update interrupt or DMA request if + +enabled. + 2 + 1 + read-write + + + OPM + OPM: One pulse mode + +0: Counter is not stopped at update event. + +1: Counter stops counting at the next update event (clearing the bit CEN) + 3 + 1 + read-write + + + DIR + DIR: Direction + +0: Counter used as upcounter + +1: Counter used as downcounter + +Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder + +mode. + 4 + 1 + read-write + + + CMS + CMS[1:0]: Center-aligned mode selection + +00: Edge-aligned mode. The counter counts up or down depending on the direction bit + +(DIR). + +01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting down. + +10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +only when the counter is counting up. + +11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare + +interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set + +both when the counter is counting up or down. + +Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as + +the counter is enabled (CEN=1) + 5 + 2 + read-write + + + ARPE + ARPE: Auto-reload preload enable + +0: TIMx_ARR register is not buffered + +1: TIMx_ARR register is buffered + 7 + 1 + read-write + + + CKD + CKD[1:0]: Clock division + +This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the + +dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters + +(TIx), + +00: tDTS=tCK_INT + +01: tDTS=2*tCK_INT + +10: tDTS=4*tCK_INT + +11: Reserved, do not program this value + 8 + 2 + read-write + + + UIF_REMAP + UIFREMAP: UIF status bit remapping + +0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31. + +1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31. + 11 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x0 + 0xF + + + CCDS + CCDS: Capture/compare DMA selection + +0: CCx DMA request sent when CCx event occurs + +1: CCx DMA requests sent when update event occurs + 3 + 1 + read-write + + + MMS + MMS[2:0]: Master mode selection + +These bits allow to select the information to be sent in master mode to slave timers for + +synchronization (TRGO). The combination is as follows: + +000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the + +reset is generated by the trigger input (slave mode controller configured in reset mode) then + +the signal on TRGO is delayed compared to the actual reset. + +001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is + +useful to start several timers at the same time or to control a window in which a slave timer is + +enabled. The Counter Enable signal is generated by a logic OR between CEN control bit + +and the trigger input when configured in gated mode. + +When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, + +except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR + +register). + +010: Update - The update event is selected as trigger output (TRGO). For instance a master + +timer can then be used as a prescaler for a slave timer. + +011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be + +set (even if it was already high), as soon as a capture or a compare match occurred. + +(TRGO) + +100: Compare - OC1REF signal is used as trigger output (TRGO) + +101: Compare - OC2REF signal is used as trigger output (TRGO) + +110: Compare - OC3REF signal is used as trigger output (TRGO) + +111: Compare - OC4REF signal is used as trigger output (TRGO) + +Note: The clock of the slave timer must be enabled prior to receive events from the master + +timer, and must not be changed on-the-fly while triggers are received from the master + +timer. + 4 + 3 + read-write + + + TI1S + TI1S: TI1 selection + +0: The TIMx_CH1 pin is connected to TI1 input. + +1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) + 7 + 1 + read-write + + + + + SMCR + SMCR + SMCR register + 0x08 + 0x20 + read-write + 0x0 + 0x0 + + + SMS_2_0 + SMS: Slave mode selection + +When external signals are selected the active edge of the trigger signal (TRGI) is linked to + +the polarity selected on the external input (see Input Control register and Control Register + +description. + +0000: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal + +clock. + +0001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 + +level. + +0010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 + +level. + +0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges + +depending on the level of the other input. + +0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter + +and generates an update of the registers. + +0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The + +counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of + +the counter are controlled. + +0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not + +reset). Only the start of the counter is controlled. + +0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + +1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) + +reinitializes the counter, generates an update of the registers and starts the counter. + +Codes above 1000: Reserved. + +Note: The gated mode must not be used if TI1F_ED is selected as the trigger input + +(TS='100'). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the + +gated mode checks the level of the trigger signal. + 0 + 3 + read-write + + + OCCS + OCCS: OCREF clear selection + +This bit is used to select the OCREF clear source. + +0: OCREF_CLR_INT is connected to the OCREF_CLR input (stuck at 0 so no effect) + +1: OCREF_CLR_INT is connected to ETRF + 3 + 1 + read-write + + + TS_2_0 + TS[4:0]: Trigger selection + +This bit-field selects the trigger input to be used to synchronize the counter. + +00000: Internal Trigger 0 (ITR0) + +00001: Internal Trigger 1 (ITR1) + +00010: Internal Trigger 2 (ITR2) + +00011: Internal Trigger 3 (ITR3) + +00100: TI1 Edge Detector (TI1F_ED) + +00101: Filtered Timer Input 1 (TI1FP1) + +00110: Filtered Timer Input 2 (TI2FP2) + +00111: External Trigger input (ETRF) + +Others: Reserved + +See Table Note:: TIM2 internal trigger connection on page 395 for more details on ITRx + +meaning for each Timer. + +Note: These bits must be changed only when they are not used (e.g. when SMS=000) to + +avoid wrong edge detections at the transition. + 4 + 3 + read-write + + + MSM + MSM: Master/Slave mode + +0: No action + +1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect + +synchronization between the current timer and its slaves (through TRGO). It is useful if we + +want to synchronize several timers on a single external event. + 7 + 1 + read-write + + + ETF + ETF[3:0]: External trigger filter + +This bit-field then defines the frequency used to sample ETRP signal and the length of the + +digital filter applied to ETRP. The digital filter is made of an event counter in which N events + +are needed to validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N=6 + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 8 + 4 + read-write + + + ETPS + ETPS[1:0]: External trigger prescaler + +External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A + +prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external + +clocks. + +00: Prescaler OFF + +01: ETRP frequency divided by 2 + +10: ETRP frequency divided by 4 + +11: ETRP frequency divided by 8 + 12 + 2 + read-write + + + ECE + ECE: External clock enable + +This bit enables External clock mode 2. + +0: External clock mode 2 disabled + +1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF + +signal. + +Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with + +TRGI connected to ETRF (SMS=111 and TS=111). + +Note: 2: It is possible to simultaneously use external clock mode 2 with the following slave + +modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be + +connected to ETRF in this case (TS bits must not be 111). + +Note: 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, + +the external clock input is ETRF. + 14 + 1 + read-write + + + ETP + ETP: External trigger polarity + +This bit selects whether ETR or ETR is used for trigger operations + +0: ETR is non-inverted, active at high level or rising edge. + +1: ETR is inverted, active at low level or falling edge. + 15 + 1 + read-write + + + SMS_3 + SMS[3]: Slave mode selection - bit 3 + +Refer to SMS description - bits2:0 + 16 + 1 + read-write + + + TS_4_3 + Trigger selection. See TS_2_0_ description + 20 + 2 + read-write + + + + + DIER + DIER + DIER register + 0x0C + 0x20 + read-write + 0x0 + 0xF + + + UIE + UIE: Update interrupt enable + +0: Update interrupt disabled + +1: Update interrupt enabled + 0 + 1 + read-write + + + CC1IE + CC1IE: Capture/Compare 1 interrupt enable + +0: CC1 interrupt disabled. + +1: CC1 interrupt enabled + 1 + 1 + read-write + + + CC2IE + CC2IE: Capture/Compare 2 interrupt enable + +0: CC2 interrupt disabled + +1: CC2 interrupt enabled + 2 + 1 + read-write + + + CC3IE + CC3IE: Capture/Compare 3 interrupt enable + +0: CC3 interrupt disabled + +1: CC3 interrupt enabled + 3 + 1 + read-write + + + CC4IE + CC4IE: Capture/Compare 4 interrupt enable + +0: CC4 interrupt disabled + +1: CC4 interrupt enabled + 4 + 1 + read-write + + + TIE + TIE: Trigger interrupt enable + +0: Trigger interrupt disabled + +1: Trigger interrupt enabled + 6 + 1 + read-write + + + UDE + UDE: Update DMA request enable + +0: Update DMA request disabled + +1: Update DMA request enabled + 8 + 1 + read-write + + + CC1DE + CC1DE: Capture/Compare 1 DMA request enable + +0: CC1 DMA request disabled + +1: CC1 DMA request enabled + 9 + 1 + read-write + + + CC2DE + CC2DE: Capture/Compare 2 DMA request enable + +0: CC2 DMA request disabled + +1: CC2 DMA request enabled + 10 + 1 + read-write + + + CC3DE + CC3DE: Capture/Compare 3 DMA request enable + +0: CC3 DMA request disabled + +1: CC3 DMA request enabled + 11 + 1 + read-write + + + CC4DE + CC4DE: Capture/Compare 4 DMA request enable + +0: CC4 DMA request disabled + +1: CC4 DMA request enabled + 12 + 1 + read-write + + + TDE + TDE: Trigger DMA request enable + +0: Trigger DMA request disabled + +1: Trigger DMA request enabled + 14 + 1 + read-write + + + + + SR + SR + SR register + 0x10 + 0x20 + read-write + 0x0 + 0xF + + + UIF + UIF: Update interrupt flag + +This bit is set by hardware on an update event. It is cleared by software. + +0: No update occurred. + +1: Update interrupt pending. This bit is set by hardware when the registers are updated: + +At overflow regarding the repetition counter value (update if repetition counter = 0) + +and if the UDIS=0 in the TIMx_CR1 register. + +When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if + +URS=0 and UDIS=0 in the TIMx_CR1 register. + 0 + 1 + read-write + + + CC1IF + CC1IF: Capture/Compare 1 interrupt flag + +If channel CC1 is configured as output: + +This flag is set by hardware when the counter matches the compare value, with some + +exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register + +description). It is cleared by software. + +0: No match. + +1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. + +When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF + +bit goes high on the counter overflow (in upcounting and up/down-counting modes) or + +underflow (in downcounting mode) + +If channel CC1 is configured as input: + +This bit is set by hardware on a capture. It is cleared by software or by reading the + +TIMx_CCR1 register. + +0: No input capture occurred + +1: The counter value has been captured in TIMx_CCR1 register (An edge has been + +detected on IC1 which matches the selected polarity) + 1 + 1 + read-write + + + CC2IF + CC2IF: Capture/Compare 2 interrupt flag + +refer to CC1IF description + 2 + 1 + read-write + + + CC3IF + CC3IF: Capture/Compare 3 interrupt flag + +refer to CC1IF description + 3 + 1 + read-write + + + CC4IF + CC4IF: Capture/Compare 4 interrupt flag + +refer to CC1IF description + 4 + 1 + read-write + + + TIF + TIF: Trigger interrupt flag + +This flag is set by hardware on trigger event (active edge detected on TRGI input when the + +slave mode controller is enabled in all modes but gated mode. It is set when the counter + +starts or stops when gated mode is selected. It is cleared by software.. + +0: No trigger event occurred. + +1: Trigger interrupt pending. + 6 + 1 + read-write + + + CC1OF + CC1OF: Capture/Compare 1 overcapture flag + +This flag is set by hardware only when the corresponding channel is configured in input + +capture mode. It is cleared by software by writing it to '0'. + +0: No overcapture has been detected + +1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was + +already set + 9 + 1 + read-write + + + CC2OF + CC2OF: Capture/Compare 2 overcapture flag + +refer to CC1OF description + 10 + 1 + read-write + + + CC3OF + CC3OF: Capture/Compare 3 overcapture flag + +refer to CC1OF description + 11 + 1 + read-write + + + CC4OF + CC4OF: Capture/Compare 4 overcapture flag + +refer to CC1OF description + 12 + 1 + read-write + + + + + EGR + EGR + EGR register + 0x14 + 0x20 + read-write + 0x0 + 0xF + + + UG + UG: Update generation + +This bit can be set by software, it is automatically cleared by hardware. + +0: No action. + +1: Reinitialize the counter and generates an update of the registers. Note that the prescaler + +counter is cleared too (anyway the prescaler ratio is not affected). + 0 + 1 + write-only + + + CC1G + CC1G: Capture/Compare 1 generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action. + +1: A capture/compare event is generated on channel 1: + +If channel CC1 is configured as output: + +CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. + +If channel CC1 is configured as input: + +The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, + +the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the + +CC1IF flag was already high. + 1 + 1 + write-only + + + CC2G + CC2G: Capture/Compare 2 generation + +refer to CC1G description + 2 + 1 + write-only + + + CC3G + CC3G: Capture/Compare 3 generation + +refer to CC1G description + 3 + 1 + write-only + + + CC4G + CC4G: Capture/Compare 4 generation + +refer to CC1G description + 4 + 1 + write-only + + + TG + TG: Trigger generation + +This bit is set by software in order to generate an event, it is automatically cleared by + +hardware. + +0: No action + +1: The TIF flag is set in TIMx_SR register. Related interrupt can occur if enabled. + 6 + 1 + write-only + + + + + CCMR1 + CCMR1 + CCMR1 register + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC1FE + OC1FE: Output Compare 1 fast enable + +This bit is used to accelerate the effect of an event on the trigger in input on the CC output. + +0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is + +ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is + +5 clock cycles. + +1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC + +is set to the compare level independently of the result of the comparison. Delay to sample + +the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if + +the channel is configured in PWM1 or PWM2 mode. + 2 + 1 + read-write + + + OC1PE + OC1PE: Output Compare 1 preload enable + +0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the + +new value is taken in account immediately. + +1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload + +register. TIMx_CCR1 preload value is loaded in the active register at each update event. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: The PWM mode can be used without validating the preload register only in one + +pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. + 3 + 1 + read-write + + + OC1M_2_0 + OC1M: Output Compare 1 mode + +These bits define the behavior of the output reference signal OC1REF from which OC1 and + +OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends + +on CC1P and CC1NP bits. + +0000: Frozen - The comparison between the output compare register TIMx_CCR1 and the + +counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing + +base). + +0001: Set channel 1 to active level on match. OC1REF signal is forced high when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the + +counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). + +0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. + +0100: Force inactive level - OC1REF is forced low. + +0101: Force active level - OC1REF is forced high. + +0110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT TIMx_CCR1 + +else inactive. In downcounting, channel 1 is inactive (OC1REF='0') as long as + +TIMx_CNT>TIMx_CCR1 else active (OC1REF='1'). + +0111: PWM mode 2 - In upcounting, channel 1 is inactive as long as + +TIMx_CNT TIMx_CCR1 else active. In downcounting, channel 1 is active as long as + +TIMx_CNT>TIMx_CCR1 else inactive. + +1000: Retrigerrable OPM mode 1 - In up-counting mode, the channel is active until a trigger + +event is detected (on TRGI signal). Then, a comparison is performed as in PWM mode 1 + +and the channels becomes active again at the next update. In down-counting mode, the + +channel is inactive until a trigger event is detected (on TRGI signal). Then, a comparison is + +performed as in PWM mode 1 and the channels becomes inactive again at the next update. + +1001: Retrigerrable OPM mode 2 - In up-counting mode, the channel is inactive until a + +trigger event is detected (on TRGI signal). Then, a comparison is performed as in PWM + +mode 2 and the channels becomes inactive again at the next update. In down-counting + +mode, the channel is active until a trigger event is detected (on TRGI signal). Then, a + +comparison is performed as in PWM mode 1 and the channels becomes active again at the + +next update. + +1010: Reserved + +1011: Reserved + +1100: Combined PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. + +OC1REFC is the logical OR between OC1REF and OC2REF. + +1101: Combined PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. + +OC1REFC is the logical AND between OC1REF and OC2REF + +1110: Asymmetric PWM mode 1 - OC1REF has the same behavior as in PWM mode 1. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +1111: Asymmetric PWM mode 2 - OC1REF has the same behavior as in PWM mode 2. + +OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting + +down. + +Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed + +(LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in + +output). + +Note: 2: In PWM mode, the OCREF level changes only when the result of the comparison + +changes or when the output compare mode switches from 'frozen' mode to 'PWM' + +mode. + 4 + 3 + read-write + + + OC1CE + OC1CE: Output Compare 1 Clear Enable + +0: OC1Ref is not affected by the ETRF Input + +1: OC1Ref is cleared as soon as a High level is detected on ETRF input + 7 + 1 + read-write + + + CC2S + CC2S[1:0]: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through the TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC2FE + OC2FE: Output Compare 2 fast enable + 10 + 1 + read-write + + + OC2PE + OC2PE: Output Compare 2 preload enable + 11 + 1 + read-write + + + OC2M_2_0 + OC2M[2:0]: Output Compare 2 mode + 12 + 3 + read-write + + + OC2CE + OC2CE: Output Compare 2 clear enable + 15 + 1 + read-write + + + OC1M_3 + OC1M[3]: Output Compare 1 mode (bit 3) + 16 + 1 + read-write + + + OC2M_3 + OC2M[3]: Output Compare 2 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR1_in + CCMR1_in + CCMR1_in register + CCMR1 + 0x18 + 0x20 + read-write + 0x0 + 0xF + + + CC1S + CC1S: Capture/Compare 1 Selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC1 channel is configured as output + +01: CC1 channel is configured as input, IC1 is mapped on TI1 + +1x: Reserved + +Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC1PSC + IC1PSC: Input capture 1 prescaler + +This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). + +The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). + +00: no prescaler, capture is done each time an edge is detected on the capture input. + +01: capture is done once every 2 events + +10: capture is done once every 4 events + +11: capture is done once every 8 events + 2 + 2 + read-write + + + IC1F + Bits 7:4 IC1F[3:0]: Input capture 1 filter + +This bit-field defines the frequency used to sample TI1 input and the length of the digital filter + +applied to TI1. The digital filter is made of an event counter in which N events are needed to + +validate a transition on the output: + +0000: No filter, sampling is done at fDTS + +0001: fSAMPLING=fCK_INT, N=2 + +0010: fSAMPLING=fCK_INT, N=4 + +0011: fSAMPLING=fCK_INT, N=8 + +0100: fSAMPLING=fDTS/2, N= + +0101: fSAMPLING=fDTS/2, N=8 + +0110: fSAMPLING=fDTS/4, N=6 + +0111: fSAMPLING=fDTS/4, N=8 + +1000: fSAMPLING=fDTS/8, N=6 + +1001: fSAMPLING=fDTS/8, N=8 + +1010: fSAMPLING=fDTS/16, N=5 + +1011: fSAMPLING=fDTS/16, N=6 + +1100: fSAMPLING=fDTS/16, N=8 + +1101: fSAMPLING=fDTS/32, N=5 + +1110: fSAMPLING=fDTS/32, N=6 + +1111: fSAMPLING=fDTS/32, N=8 + 4 + 4 + read-write + + + CC2S + CC2S: Capture/Compare 2 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC2 channel is configured as output + +01: CC2 channel is configured as input, IC2 is mapped on TI2 + +10: CC2 channel is configured as input, IC2 is mapped on TI1 + +11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an + +internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC2PSC + IC2PSC[1:0]: Input capture 2 prescaler + 10 + 2 + read-write + + + IC2F + IC2F: Input capture 2 filter + 12 + 4 + read-write + + + + + CCMR2 + CCMR2 + CCMR2 register + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/Compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + OC3FE + OC3FE: Output compare 3 fast enable + 2 + 1 + read-write + + + OC3PE + OC3PE: Output compare 3 preload enable + 3 + 1 + read-write + + + OC3M_2_0 + OC3M: Output compare 3 mode + 4 + 3 + read-write + + + OC3CE + OC3CE: Output compare 3 clear enable + 7 + 1 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + OC4FE + OC4FE: Output Compare 4 fast enable + 10 + 1 + read-write + + + OC4PE + OC4PE: Output Compare 4 preload enable + 11 + 1 + read-write + + + OC4M_2_0 + OC4M[2:0]: Output Compare 4 mode + 12 + 3 + read-write + + + OC4CE + OC4CE: Output Compare 4 clear enable + 15 + 1 + read-write + + + OC3M_3 + OC3M[3]: Output Compare 3 mode (bit 3) + 16 + 1 + read-write + + + OC4M_3 + OC4M[3]: Output Compare 4 mode (bit 3) + 24 + 1 + read-write + + + + + CCMR2_in + CCMR2_in + CCMR2_in register + CCMR2 + 0x1C + 0x20 + read-write + 0x0 + 0xF + + + CC3S + CC3S: Capture/compare 3 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC3 channel is configured as output + +01: CC3 channel is configured as input, IC3 is mapped on TI3 + +10: CC3 channel is configured as input, IC3 is mapped on TI4 + +11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER). + 0 + 2 + read-write + + + IC3PSC + IC3PSC: Input capture 3 prescaler + 2 + 2 + read-write + + + IC3F + IC3F: Input capture 3 filter + 4 + 4 + read-write + + + CC4S + CC4S: Capture/Compare 4 selection + +This bit-field defines the direction of the channel (input/output) as well as the used input. + +00: CC4 channel is configured as output + +01: CC4 channel is configured as input, IC4 is mapped on TI4 + +10: CC4 channel is configured as input, IC4 is mapped on TI3 + +11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if + +an internal trigger input is selected through TS bit (TIMx_SMCR register) + +Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER). + 8 + 2 + read-write + + + IC4PSC + IC4PSC: Input capture 4 prescaler + 10 + 2 + read-write + + + IC4F + IC4F: Input capture 4 filter + 12 + 4 + read-write + + + + + CCER + CCER + CCER register + 0x20 + 0x20 + read-write + 0x0 + 0xF + + + CC1E + CC1E: Capture/Compare 1 output enable + +CC1 channel configured as output: + +0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N + +and CC1NE bits. + +1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, + +OSSR, OIS1, OIS1N and CC1NE bits. + +CC1 channel configured as input: + +This bit determines if a capture of the counter value can actually be done into the input + +capture/compare register 1 (TIMx_CCR1) or not. + +0: Capture disabled + +1: Capture enabled + 0 + 1 + read-write + + + CC1P + CC1P: Capture/Compare 1 output polarity + +CC1 channel configured as output: + +0: OC1 active high + +1: OC1 active low + +CC1 channel configured as input: + +The CC1NP/CC1P bits select the polarity of TI1FP1 for trigger or capture operations. + +00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or + +trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger + +operation in gated mode). + +01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger + +operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in + +gated mode. + +10: Reserved, do not use this configuration. + +11: Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges + +(capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted + +(trigger operation in gated mode). + +Note: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in TIMx_BDTR register). + +2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit + +is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the + +preloaded bit only when a Commutation event is generated. + 1 + 1 + read-write + + + CC1NP + CC1NP: Capture/Compare 1 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +Note: This bit is no longer writeable as soon as LOCK level 2 or 3 has been programmed (LOCK + +bits in GPT_BDTR register) and CC1S='00' (the channel is configured in output). + 3 + 1 + read-write + + + B_0x0 + OC1N active high. + 0x0 + + + B_0x1 + OC1N active low. + 0x1 + + + + + CC2E + CC2E: Capture/Compare 2 output enable + +refer to CC1E description + 4 + 1 + read-write + + + CC2P + CC2P: Capture/Compare 2 output polarity + +refer to CC1P description + 5 + 1 + read-write + + + CC2NP + CC2NP: Capture/Compare 2 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 7 + 1 + read-write + + + CC3E + CC3E: Capture/Compare 3 output enable + +refer to CC1E description + 8 + 1 + read-write + + + CC3P + CC3P: Capture/Compare 3 output polarity + +refer to CC1P description + 9 + 1 + read-write + + + CC3NP + CC3NP: Capture/Compare 3 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 11 + 1 + read-write + + + CC4E + CC4E: Capture/Compare 4 output enable + +refer to CC1E description + 12 + 1 + read-write + + + CC4P + CC4P: Capture/Compare 4 output polarity + +refer to CC1P description + 13 + 1 + read-write + + + CC4NP + CC4NP: Capture/Compare 4 Complementary output Polarity. + +This field is not used in Blue51. Not available in IUM + +refer to CC1NP description + 15 + 1 + read-write + + + + + CNT + CNT + CNT register + 0x24 + 0x20 + read-write + 0x0 + 0xF + + + CNT + CNT[15:0]: Counter value + 0 + 16 + read-write + + + UIF_CPY + UIFCPY: UIF Copy + +This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in + +TIMx_CR1 is reset, bit 31 is reserved and read as 0. + 31 + 1 + read-only + + + + + PSC + PSC + PSC register + 0x28 + 0x20 + read-write + 0x0 + 0xF + + + PSC + PSC[15:0]: Prescaler value + +The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). + +PSC contains the value to be loaded in the active prescaler register at each update event + +(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger + +controller when configured in 'reset mode'). + 0 + 16 + read-write + + + + + ARR + ARR + ARR register + 0x2C + 0x20 + read-write + 0xFFFF + 0xFFFF + + + ARR + ARR[15:0]: Prescaler value + +ARR is the value to be loaded in the actual auto-reload register. + +Refer to the Section 22.3.1: Time-base unit on page 418 for more details about ARR update + +and behavior. + +The counter is blocked while the auto-reload value is null. + 0 + 16 + read-write + + + + + RCR + RCR + RCR register + 0x30 + 0x20 + read-write + 0x0 + 0xF + + + REP + REP[7:0]: Repetition counter value + +These bits allow the user to set-up the update rate of the compare registers (i.e. periodic + +transfers from preload to active registers) when preload registers are enable, as well as the + +update interrupt generation rate, if this interrupt is enable. + +Each time the REP_CNT related downcounter reaches zero, an update event is generated + +and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the + +repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until + +the next repetition update event. + +It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned + +mode. + 0 + 8 + read-write + + + + + CCR1 + CCR1 + CCR1 register + 0x34 + 0x20 + read-write + 0x0 + 0xF + + + CCR1 + CCR1[15:0]: Capture/Compare 1 value + +If channel CC1 is configured as output: + +CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit + +OC1PE). Else the preload value is copied in the active capture/compare 1 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC1 output. + +If channel CC1 is configured as input: + +CCR1 is the counter value transferred by the last input capture 1 event (IC1). + 0 + 16 + read-write + + + + + CCR2 + CCR2 + CCR2 register + 0x38 + 0x20 + read-write + 0x0 + 0xF + + + CCR2 + CCR2[15:0]: Capture/Compare 2 value + +If channel CC2 is configured as output: + +CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit + +OC2PE). Else the preload value is copied in the active capture/compare 2 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC2 output. + +If channel CC2 is configured as input: + +CCR2 is the counter value transferred by the last input capture 2 event (IC2). + 0 + 16 + read-write + + + + + CCR3 + CCR3 + CCR3 register + 0x3C + 0x20 + read-write + 0x0 + 0xF + + + CCR3 + CCR3[15:0]: Capture/Compare 3 value + +If channel CC3 is configured as output: + +CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit + +OC3PE). Else the preload value is copied in the active capture/compare 3 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC3 output. + +If channel CC3 is configured as input: + +CCR3 is the counter value transferred by the last input capture 3 event (IC3). + 0 + 16 + read-write + + + + + CCR4 + CCR4 + CCR4 register + 0x40 + 0x20 + read-write + 0x0 + 0xF + + + CCR4 + CCR4[15:0]: Capture/Compare 4 value + +If channel CC4 is configured as output: + +CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). + +It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit + +OC4PE). Else the preload value is copied in the active capture/compare 4 register when an + +update event occurs. + +The active capture/compare register contains the value to be compared to the counter + +TIMx_CNT and signaled on OC4 output. + +If channel CC4 is configured as input: + +CCR4 is the counter value transferred by the last input capture 4 event (IC4). + 0 + 16 + read-write + + + + + DCR + DCR + DCR register + 0x48 + 0x20 + read-write + 0x0 + 0xF + + + DBA + DBA[4:0]: DMA base address + +This 5-bit field defines the base-address for DMA transfers (when read/write access are + +done through the TIMx_DMAR address). DBA is defined as an offset starting from the + +address of the TIMx_CR1 register. + +Example: + +00000: TIMx_CR1, + +00001: TIMx_CR2, + +00010: Reserved, + +... + +Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In + +this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. + 0 + 5 + read-write + + + DBL + DBL[4:0]: DMA burst length + +This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when + +a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. + +Transfers can be in half-words or in bytes (see example below). + +00000: 1 transfer, + +00001: 2 transfers, + +00010: 3 transfers, + +... + +10001: 18 transfers. + 8 + 5 + read-write + + + + + DMAR + DMAR + DMAR register + 0x4C + 0x20 + read-write + 0x0 + 0xF + + + DMAB + DMAB[15:0]: DMA register for burst accesses + +A read or write operation to the DMAR register accesses the register located at the address + +(TIM2_CR1 address) + (DBA + DMA index) x 4 + +where TIM2_CR1 address is the address of the control register 1, DBA is the DMA base + +address configured in TIM2_DCR register, DMA index is automatically controlled by the + +DMA transfer, and ranges from 0 to DBL (DBL configured in TIM2_DCR). + 0 + 16 + read-write + + + + + OR1 + OR1 + OR1 register + 0x50 + 0x20 + read-write + 0x0 + 0xF + + + ETR_RMP + ETR_RMP: ETR remapping capability + +0: TIMx_ETR is not connected to ADC AWD (must be selected when the ETR comes from + +the ETR input pin) + +1: TIMx_ETR is connected to ADC AWD + +Note: ADC AWD source is 'ORed' with the TIMx_ETR input signals. When ADC AWD is used, + +it is necessary to make sure that the corresponding TIMx_ETR input pin is not enabled + +in the alternate function controller. + 0 + 1 + read-write + + + OR1_1 + This field is not used in Blue51. Not available in IUM + 1 + 1 + read-write + + + TI4_RMP + TI4_RMP: Input capture 4 remap + +0: TIM2 input capture 4 is connected to I/O + +1: TIM2 input capture 4 is connected to COMP1-OUT + 2 + 1 + read-write + + + + + AF1 + AF1 + AF1 register + 0x60 + 0x20 + read-write + 0x0 + 0xF + + + ETR_SEL + ETRSEL[2:0]: External trigger source selection + +000: TIMx External trigger legacy mode + +001: TIMx External trigger source select COMP1_OUT + +Other: Reserved + +Note: These bits can't be modified as long as LOCK level 1 has been programmed (LOCK + +bits in TIMx_BDTR register) + 14 + 3 + read-write + + + ETR_SEL_3 + ETRSEL[2:0]: External trigger source selection + +This field is not used in Blue51. Not available in IUM + 17 + 1 + read-write + + + + + TISEL + TISEL + TISEL register + 0x68 + 0x20 + read-write + + + TI1SEL + TI1SEL[3:0]: selects TI1[0] to TI1[15] input + +0000: TIMx_CH1 input + +Others: Reserved + 0 + 4 + read-write + + + TI2SEL + TI2SEL[3:0]: selects TI2[0] to TI2[15] input + +0000: TIMx_CH2 input + +Others: Reserved + 8 + 4 + read-write + + + TI3SEL + TI3SEL[3:0]: selects TI3[0] to TI3[15] input + +0000: TIMx_CH3 input + +Others: Reserved + 16 + 4 + read-write + + + TI4SEL + TI4SEL[3:0]: selects TI4[0] to TI4[15] input + +0000: TIMx_CH4 input + +Others: Reserved + 24 + 4 + read-write + + + + + + + USART + USART + 0x41004000 + + 0x0 + 0x30 + registers + + + USART + USART interrupt + 8 + + + + CR1 + CR1 + CR1 register + 0x00 + 0x20 + read-write + 0x00000000 + + + UE + UE: USART enable +When this bit is cleared, the USART prescalers and outputs are stopped immediately, and +current operations are discarded. The configuration of the USART is kept, but all the status +flags, in the USART_ISR are reset. This bit is set and cleared by software. +-0: USART prescaler and outputs disabled, low power mode +-1: USART enabled + 0 + 1 + read-write + + + RE + RE: Receiver enable +This bit enables the receiver. It is set and cleared by software. +-0: Receiver is disabled +-1: Receiver is enabled and begins searching for a start bit + 2 + 1 + read-write + + + TE + TE: Transmitter enable +This bit enables the transmitter. It is set and cleared by software. +-0: Transmitter is disabled +-1: Transmitter is enabled + 3 + 1 + read-write + + + IDLEIE + IDLEIE: IDLE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register + 4 + 1 + read-write + + + RXNEIE_RXFNEIE + RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever ORE=1 or RXNE/RXFNE=1 in the +USART_ISR register + 5 + 1 + read-write + + + TCIE + TCIE: Transmission complete interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TC=1 in the USART_ISR register + 6 + 1 + read-write + + + TXEIE_TXFNFIE + TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever TXE/TXFNF =1 in the USART_ISR register + 7 + 1 + read-write + + + PEIE + PEIE: PE interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated whenever PE=1 in the USART_ISR register + 8 + 1 + read-write + + + PS + PS: Parity selection +This bit selects the odd or even parity when the parity generation/detection is enabled (PCE +bit set). It is set and cleared by software. The parity will be selected after the current byte. +-0: Even parity +-1: Odd parity +This bit field can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + PCE + PCE: Parity control enable +This bit selects the hardware parity control (generation and detection). When the parity +control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit +if M=0) and parity is checked on the received data. This bit is set and cleared by software. +Once it is set, PCE is active after the current byte (in reception and in transmission). +-0: Parity control disabled +-1: Parity control enabled +This bit field can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + WAKE + WAKE: Receiver wakeup method +This bit determines the USART wakeup method from Mute mode. It is set or cleared by +software. +-0: Idle line +-1: Address mark +This bit field can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + M_0 + M0: Word length +This bit, with bit 28 (M1) determine the word length. It is set or cleared by software. See Bit +-28 (M1)description. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + MME + MME: Mute mode enable +This bit activates the mute mode function of the USART. When set, the USART can switch +between the active and mute modes, as defined by the WAKE bit. It is set and cleared by +software. +-0: Receiver in active mode permanently +-1: Receiver can switch between mute mode and active mode + 13 + 1 + read-write + + + CMIE + CMIE: Character match interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register. + 14 + 1 + read-write + + + OVER8 + OVER8: Oversampling mode +-0: Oversampling by 16 +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + DEDT + DEDT[4:0]: Driver Enable deassertion time +This 5-bit value defines the time between the end of the last stop bit, in a transmitted +message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample +time units (1/8 or 1/16 bit time, depending on the oversampling rate). +If the USART_TDR register is written during the DEDT time, the new data is transmitted only +when the DEDT and DEAT times have both elapsed. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 5 + read-write + + + DEAT + DEAT[4:0]: Driver Enable assertion time +This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and +the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, +depending on the oversampling rate). +This bit field can only be written when the USART is disabled (UE=0). + 21 + 5 + read-write + + + RTOIE + RTOIE: Receiver timeout interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register + 26 + 1 + read-write + + + EOBIE + EOBIE: End of Block interrupt enable +This bit is set and cleared by software. + + 27 + 1 + read-write + + + B_0x0 + Interrupt is inhibited + + 0x0 + + + B_0x1 + A USART interrupt is generated when the EOBF flag is set in the USART_ISR register + 0x1 + + + + + M_1 + Word length +This bit, with bit 12 (M0) determine the word length. It is set or cleared by software. +M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit +M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit +M[1:0] = 10: 1 Start bit, 7 Data bits, n Stop bit +This bit can only be written when the USART is disabled (UE=0).s + 28 + 1 + read-write + + + FIFOEN + FIFOEN :FIFO mode enable +This bit is set and cleared by software. +-0: FIFO mode is disabled. +-1: FIFO mode is enabled. + 29 + 1 + read-write + + + TXFEIE + TXFEIE :TXFIFO empty interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFE=1 in the USART_ISR register + 30 + 1 + read-write + + + RXFFIE + RXFFIE :RXFIFO Full interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when RXFF=1 in the USART_ISR register + 31 + 1 + read-write + + + + + CR2 + CR2 + CR2 register + 0x04 + 0x20 + read-write + 0x00000000 + + + SLVEN + SLVEN: Synchronous Slave mode enable +When the SLVEN bit is set, the synchronous slave mode is enabled. +-0: Slave mode disabled. +-1: Slave mode enabled. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value + 0 + 1 + read-write + + + DIS_NSS + DIS_NSS +When the DSI_NSS bit is set, the NSS pin input will be ignored. +-0: SPI slave selection depends on NSS input pin. +-1: SPI slave will be always selected and NSS input pin will be ignored. +Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value + 3 + 1 + read-write + + + ADDM7 + ADDM7:7-bit Address Detection/4-bit Address Detection +This bit is for selection between 4-bit address detection or 7-bit address detection. +-0: 4-bit address detection +-1: 7-bit address detection (in 8-bit data mode) +This bit can only be written when the USART is disabled (UE=0) + 4 + 1 + read-write + + + LBDL + LBDL: LIN break detection length +This bit is for selection between 11 bit or 10 bit break detection. +-0: 10-bit break detection +-1: 11-bit break detection +This bit can only be written when the USART is disabled (UE=0). + 5 + 1 + read-write + + + LBDIE + LBDIE: LIN break detection interrupt enable +Break interrupt mask (break detection using break delimiter). +-0: Interrupt is inhibited +-1: An interrupt is generated whenever LBDF=1 in the USART_ISR register + 6 + 1 + read-write + + + LBCL + LBCL: Last bit clock pulse +This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) +has to be output on the SCLK pin in synchronous mode. +-0: The clock pulse of the last data bit is not output to the SCLK pin +-1: The clock pulse of the last data bit is output to the SCLK pin +Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit +format selected by the M bit in the USART_CR1 register. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CPHA + CPHA: Clock phase +This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It +works in conjunction with the CPOL bit to produce the desired clock/data relationship (see +Figure 137 and Figure 138) +-0: The first clock transition is the first data capture edge +-1: The second clock transition is the first data capture edge +This bit can only be written when the USART is disabled (UE=0). + 9 + 1 + read-write + + + CPOL + CPOL: Clock polarity +This bit allows the user to select the polarity of the clock output on the SCLK pin in synchronous +mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship +-0: Steady low value on SCLK pin outside transmission window +-1: Steady high value on SCLK pin outside transmission window +This bit can only be written when the USART is disabled (UE=0). + 10 + 1 + read-write + + + CLKEN + CLKEN: Clock enable +This bit allows the user to enable the SCLK pin. +-0: SCLK pin disabled +-1: SCLK pin enabled +This bit can only be written when the USART is disabled (UE=0). +Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and forced +by hardware to 0. Please refer to Section 23.4: USART implementation on page 483. +Note: In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps +below must be respected: +- UE = 0 +- SCEN = 1 +- GTPR configuration +- CLKEN= 1 +- UE = 1 + 11 + 1 + read-write + + + STOP + STOP[1:0]: STOP bits +These bits are used for programming the stop bits. +-00: 1 stop bit +-01: 0.5 stop bit. +-10: 2 stop bits +-11: 1.5 stop bits +This bit field can only be written when the USART is disabled (UE=0). + 12 + 2 + read-write + + + LINEN + LINEN: LIN mode enable +This bit is set and cleared by software. +-0: LIN mode disabled +-1: LIN mode enabled +The LIN mode enables the capability to send LIN Synch Breaks (13 low bits) using the SBKRQ bit +in the USART_CR1 register, and to detect LIN Sync breaks. +This bit field can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + SWAP + SWAP: Swap TX/RX pins +This bit is set and cleared by software. +-0: TX/RX pins are used as defined in standard pinout +-1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired +connection to another UART. +This bit field can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + RXINV + RXINV: RX pin active level inversion +This bit is set and cleared by software. +-0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the RX line. +This bit field can only be written when the USART is disabled (UE=0). + 16 + 1 + read-write + + + TXINV + TXINV: TX pin active level inversion +This bit is set and cleared by software. +-0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark) +-1: TX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle). +This allows the use of an external inverter on the TX line. +This bit field can only be written when the USART is disabled (UE=0). + 17 + 1 + read-write + + + DATAINV + DATAINV: Binary data inversion +This bit is set and cleared by software. +-0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) +-1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The +parity bit is also inverted. +This bit field can only be written when the USART is disabled (UE=0). + 18 + 1 + read-write + + + MSBFIRST + MSBFIRST: Most significant bit first +This bit is set and cleared by software. +-0: data is transmitted/received with data bit 0 first, following the start bit. +-1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit. +This bit field can only be written when the USART is disabled (UE=0). + 19 + 1 + read-write + + + ABREN + ABREN: Auto baud rate enable +This bit is set and cleared by software. +-0: Auto baud rate detection is disabled. +-1: Auto baud rate detection is enabled. + 20 + 1 + read-write + + + ABRMOD + ABRMOD[1:0]: Auto baud rate mode +These bits are set and cleared by software. +-00: Measurement of the start bit is used to detect the baud rate. +-01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 -> +Frame = Start10xxxxxx) +-10: 0x7F frame detection. +-11: 0x55 frame detection +This bit field can only be written when ABREN = 0 or the USART is disabled (UE=0). + 21 + 2 + read-write + + + RTOEN + RTOEN: Receiver timeout enable +This bit is set and cleared by software. +-0: Receiver timeout feature disabled. +-1: Receiver timeout feature enabled. +When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle +(no reception) for the duration programmed in the RTOR (receiver timeout register). + 23 + 1 + read-write + + + ADD + ADD[7:0]: Address of the USART node +This bit-field gives the address of the USART node or a character code to be recognized. +This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7- +bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. +It may also be used for character detection during normal reception, Mute mode inactive (for +example, end of block detection in ModBus protocol). In this case, the whole received character (8- +bit) is compared to the ADD[7:0] value and CMF flag is set on match. +This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled +(UE=0) + 24 + 8 + read-write + + + + + CR3 + CR3 + CR3 register + 0x08 + 0x20 + read-write + 0x00000000 + + + EIE + EIE: Error interrupt enable +Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing +error, overrun error noise flag or SPI slave underrun error (FE=1 or ORE=1 or NF=1or UDR += 1 in the USART_ISR register). +-0: Interrupt is inhibited +-1: An interrupt is generated when FE=1 or ORE=1 or NF=1 or UDR = 1 (in SPI slave mode) +in the USART_ISR register. + 0 + 1 + read-write + + + IREN + IREN: IrDA mode enable +This bit is set and cleared by software. +-0: IrDA disabled +-1: IrDA enabled +This bit can only be written when the USART is disabled (UE=0). + 1 + 1 + read-write + + + IRLP + IRLP: IrDA low-power +This bit is used for selecting between normal and low-power IrDA modes +-0: Normal mode +-1: Low-power mode +This bit can only be written when the USART is disabled (UE=0). + 2 + 1 + read-write + + + HDSEL + HDSEL: Half-duplex selection +Selection of Single-wire Half-duplex mode +-0: Half duplex mode is not selected +-1: Half duplex mode is selected +This bit can only be written when the USART is disabled (UE=0). + 3 + 1 + read-write + + + NACK + NACK: Smartcard NACK enable +-0: NACK transmission in case of parity error is disabled +-1: NACK transmission during parity error is enabled +This bit field can only be written when the USART is disabled (UE=0). + 4 + 1 + read-write + + + SCEN + SCEN: Smartcard mode enable +This bit is used for enabling Smartcard mode. +-0: Smartcard Mode disabled +-1: Smartcard Mode enabled +This bit field can only be written when the USART is disabled (UE=0). + 5 + 1 + read-write + + + DMAR + DMAR: DMA enable receiver +This bit is set/reset by software +-1: DMA mode is enabled for reception +-0: DMA mode is disabled for reception + 6 + 1 + read-write + + + DMAT + DMAT: DMA enable transmitter +This bit is set/reset by software +-1: DMA mode is enabled for transmission +-0: DMA mode is disabled for transmission + 7 + 1 + read-write + + + RTSE + RTSE: RTS enable +-0: RTS hardware flow control disabled +-1: RTS output enabled, data is only requested when there is space in the receive buffer. The +transmission of data is expected to cease after the current character has been transmitted. +The nRTS output is asserted (pulled to 0) when data can be received. +This bit can only be written when the USART is disabled (UE=0). + 8 + 1 + read-write + + + CTSE + CTSE: CTS enable +-0: CTS hardware flow control disabled +-1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). +If the nCTS input is deasserted while data is being transmitted, then the transmission is +completed before stopping. If data is written into the data register while nCTS is asserted, +the transmission is postponed until nCTS is asserted. +This bit can only be written when the USART is disabled (UE=0) + 9 + 1 + read-write + + + CTSIE + CTSIE: CTS interrupt enable +-0: Interrupt is inhibited +-1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register + 10 + 1 + read-write + + + ONEBIT + ONEBIT: One sample bit method enable +This bit allows the user to select the sample method. When the one sample bit method is +selected the noise detection flag (NF) is disabled. +-0: Three sample bit method +-1: One sample bit method +This bit can only be written when the USART is disabled (UE=0). + 11 + 1 + read-write + + + OVRDIS + OVRDIS: Overrun Disable +This bit is used to disable the receive overrun detection. +-0: Overrun Error Flag, ORE, is set when received data is not read before receiving new +data. +-1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set +the ORE flag is not set and the new received data overwrites the previous content of the +USART_RDR register. When FIFO mode is enabled, the RXFIFO will be bypassed and data +will be written directly in USARTx_RDR register. Even when FIFO management is enabled, +the RXNE flag is to be used. +This bit can only be written when the USART is disabled (UE=0). + 12 + 1 + read-write + + + DDRE + DDRE: DMA Disable on Reception Error +-0: DMA is not disabled in case of reception error. The corresponding error flag is set but +RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not +asserted, so the erroneous data is not transferred (no DMA request), but next correct +received data will be transferred. (used for Smartcard mode) +-1: DMA is disabled following a reception error. The corresponding error flag is set, as well +as RXNE. The DMA request is masked until the error flag is cleared. This means that the +software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case +FIFO mode is enabled) before clearing the error flag. +This bit can only be written when the USART is disabled (UE=0). + 13 + 1 + read-write + + + DEM + DEM: Driver enable mode +This bit allows the user to activate the external transceiver control, through the DE signal. +-0: DE function is disabled. +-1: DE function is enabled. The DE signal is output on the RTS pin. +This bit can only be written when the USART is disabled (UE=0). + 14 + 1 + read-write + + + DEP + DEP: Driver enable polarity selection +-0: DE signal is active high. +-1: DE signal is active low. +This bit can only be written when the USART is disabled (UE=0). + 15 + 1 + read-write + + + SCARCNT + SCARCNT[2:0]: Smartcard auto-retry count +This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. +In transmission mode, it specifies the number of automatic retransmission retries, before +generating a transmission error (FE bit set). +In reception mode, it specifies the number or erroneous reception trials, before generating a +reception error (RXNE/RXFNE and PE bits set). +This bit field must be programmed only when the USART is disabled (UE=0). +When the USART is enabled (UE=1), this bit field may only be written to 0x0, in order to +stop retransmission. +-0x0: retransmission disabled - No automatic retransmission in transmit mode. +-0x1 to 0x7: number of automatic retransmission attempts (before signaling error) + 17 + 3 + read-write + + + TXFTIE + TXFTIE: TXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when TXFIFO reaches the threshold programmed in +TXFTCFG. + 23 + 1 + read-write + + + TCBGTIE + TCBGTIE: Transmission Complete before guard time, interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated whenever TCBGT=1 in the USARTx_ISR register + 24 + 1 + read-write + + + RXFTCFG + RXFTCFG: Receive FIFO threshold configuration +-000:Receive FIFO reaches 1/8 of its depth. +-001:Receive FIFO reaches 1/4 of its depth. +-010:Receive FIFO reaches 1/2 of its depth. +-011:Receive FIFO reaches 3/4 of its depth. +-100:Receive FIFO reaches 7/8 of its depth. +-101:Receive FIFO becomes full. +Remaining combinations: Reserved. + 25 + 3 + read-write + + + RXFTIE + RXFTIE: RXFIFO threshold interrupt enable +This bit is set and cleared by software. +-0: Interrupt is inhibited +-1: An USART interrupt is generated when Receive FIFO reaches the threshold +programmed in RXFTCFG. + 28 + 1 + read-write + + + TXFTCFG + TXFTCFG: TXFIFO threshold configuration +-000:TXFIFO reaches 1/8 of its depth. +-001:TXFIFO reaches 1/4 of its depth. +-010:TXFIFO reaches 1/2 of its depth. +-011:TXFIFO reaches 3/4 of its depth. +-100:TXFIFO reaches 7/8 of its depth. +-101:TXFIFO becomes empty. +Remaining combinations: Reserved. + 29 + 3 + read-write + + + + + BRR + BRR + BRR register + 0x0C + 0x20 + read-write + 0x00000000 + + + BRR + BRR[15:4] +BRR[15:4] = USARTDIV[15:4]BRR[3:0] +When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. +When OVER8 = 1: +BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. +BRR[3] must be kept cleared + 0 + 16 + read-write + + + + + GTPR + GTPR + GTPR register + 0x10 + 0x20 + read-write + 0x00000000 + + + PSC + PSC[7:0]: Prescaler value +In IrDA Low-power and normal IrDA mode: +PSC[7:0] = IrDA Normal and Low-Power Baud Rate +Used for programming the prescaler for dividing the USART source clock to achieve the lowpower +frequency: +The source clock is divided by the value given in the register (8 significant bits): +-00000000: Reserved - do not program this value +-00000001: divides the source clock by 1 +-00000010: divides the source clock by 2 +... +In Smartcard mode: +PSC[4:0]: Prescaler value +Used for programming the prescaler for dividing the USART source clock to provide the +Smartcard clock. +The value given in the register (5 significant bits) is multiplied by 2 to give the division factor +of the source clock frequency: +-00000: Reserved - do not program this value +-00001: divides the source clock by 2 +-00010: divides the source clock by 4 +-00011: divides the source clock by 6 +... +This bit field can only be written when the USART is disabled (UE=0). + 0 + 8 + read-write + + + GT + GT[7:0]: Guard time value +This bit-field is used to program the Guard time value in terms of number of baud clock +periods. +This is used in Smartcard mode. The Transmission Complete flag is set after this guard time +value. +This bit field can only be written when the USART is disabled (UE=0). + 8 + 8 + read-write + + + + + RTOR + RTOR + RTOR register + 0x14 + 0x20 + read-write + 0x00000000 + + + RTO + RTO[23:0]: Receiver timeout value +This bit-field gives the Receiver timeout value in terms of number of baud clocks. +In standard mode, the RTOF flag is set if, after the last received character, no new start bit is +detected for more than the RTO value. +In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard +chapter for more details. In the standard, the CWT/BWT measurement is done starting from +the Start Bit of the last received character. + 0 + 24 + read-write + + + BLEN + BLEN[7:0]: Block Length +This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number +of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. +Examples: +BLEN = 0 -> 0 information characters + LEC +BLEN = 1 -> 0 information characters + CRC +BLEN = 255 -> 254 information characters + CRC (total 256 characters)) +In Smartcard mode, the Block length counter is reset when TXE=0 (TXFE = 0 in case FIFO +mode is enabled). +This bit-field can be used also in other modes. In this case, the Block length counter is reset +when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1. + 24 + 8 + read-write + + + + + RQR + RQR + RQR register + 0x18 + 0x20 + read-write + 0x00000000 + + + ABRRQ + ABRRQ: Auto baud rate request +Writing 1 to this bit resets the ABRF flag in the USART_ISR and request an automatic baud +rate measurement on the next received data frame. + 0 + 1 + write-only + + + SBKRQ + SBKRQ: Send break request +Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as +the transmit machine is available. + 1 + 1 + write-only + + + MMRQ + MMRQ: Mute mode request +Writing 1 to this bit puts the USART in mute mode and resets the RWU flag. + 2 + 1 + write-only + + + RXFRQ + RXFRQ: Receive data flush request +Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. +This allows to discard the received data without reading them, and avoid an overrun +condition. + 3 + 1 + write-only + + + TXFRQ + TXFRQ: Transmit data flush request +When FIFO mode is disabled, Writing 1 to this bit sets the TXE flag. +This allows to discard the transmit data. This bit must be used only in Smartcard mode, +when data has not been sent due to errors (NACK) and the FE flag is active in the +USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved +and forced by hardware to 0 +When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO . This will set the flag TXFE +(Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is +supported in both UART and Smartcard modes. + 4 + 1 + write-only + + + + + ISR + ISR + ISR register + 0x1C + 0x20 + read-only + 0x000000C0 + + + PE + PE: Parity error +This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by +software, writing 1 to the PECF in the USART_ICR register. +An interrupt is generated if PEIE = 1 in the USART_CR1 register. +-0: No parity error +-1: Parity error + 0 + 1 + read-only + + + FE + FE: Framing error +This bit is set by hardware when a de-synchronization, excessive noise or a break character +is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. +In Smartcard mode, in transmission, this bit is set when the maximum number of transmit +attempts is reached without success (the card NACKs the data frame). +An interrupt is generated if EIE = 1 in the USART_CR1 register. +-0: No Framing error is detected +-1: Framing error or break character is detected + 1 + 1 + read-only + + + NF + NF: START bit Noise detection flag +This bit is set by hardware when noise is detected on a received frame. It is cleared by +software, writing 1 to the NFCF bit in the USART_ICR register. +-0: No noise is detected +-1: Noise is detected + 2 + 1 + read-only + + + ORE + ORE: Overrun error +This bit is set by hardware when the data currently being received in the shift register is +ready to be transferred into the USARTx_RDR register while RXNE=1 (RXFF = 1 in case +FIFO mode is enabled) . It is cleared by a software, writing 1 to the ORECF, in the +USARTx_ICR register. +An interrupt is generated if RXNEIE/ RXFNEIE=1 or EIE = 1 in the USARTx_CR1 register. +-0: No overrun error +-1: Overrun error is detected + 3 + 1 + read-only + + + IDLE + IDLE: Idle line detected +This bit is set by hardware when an Idle Line is detected. An interrupt is generated if +IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in +the USART_ICR register. +-0: No Idle line is detected +-1: Idle line is detected + 4 + 1 + read-only + + + RXNE_RXFNE + RXNE/RXFNE:Read data register not empty/RXFIFO not empty +RXNE bit is set by hardware when the content of the USARTx_RDR shift register has been +transferred +to the USARTx_RDR register. It is cleared by a read to the USARTx_RDR register. The +RXNE flag can also be cleared by writing 1 to the RXFRQ in the USARTx_RQR register. +RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from +the USART_RDR register. Every read of the USART_RDR frees a location in the RXFIFO. It +is cleared when the RXFIFO is empty. +The RXNE/RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR +register. +An interrupt is generated if RXNEIE/RXFNEIE=1 in the USART_CR1 register. +-0: Data is not received +-1: Received data is ready to be read. + 5 + 1 + read-only + + + TC + TC: Transmission complete +This bit indicates when the last data written in the USART_TDR has been transmitted out of +the shift register. +It is set by hardware if the transmission of a frame containing data is complete and if +TXE/TXFE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is +cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the +USART_TDR register. +An interrupt is generated if TCIE=1 in the USART_CR1 register. +-0: Transmission is not complete +-1: Transmission is complete + 6 + 1 + read-only + + + TXE_TXFNF + TXE/TXFNF: Transmit data register empty/TXFIFO not full +When FIFO mode is disabled, TXE is set by hardware when the content of the +USARTx_TDR register has been transferred into the shift register. It is cleared by a write to +the USARTx_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the +USART_RQR register, in order to discard the data (only in Smartcard T=0 mode, in case of +transmission failure). +When FIFO mode is enabled, TXFNF is set by hardware when TXFIFO is not full, and so +data can be written in the USART_TDR. Every write in the USART_TDR places the data in +the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag +is cleared indicating that data can not be written into the USART_TDR. +Note: The TXFNF is kept reset during the flush request until TXFIFO is empty . After +sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to +writing in TXFIFO. (TXFNF and TXFE will be set at the same time). +An interrupt is generated if the TXEIE/TXFNFIE bit =1 in the USART_CR1 register. +-0: Data register is full/Transmit FIFO is full. +-1: Data register/Transmit FIFO is not full + 7 + 1 + read-only + + + LBDF + LBDF: LIN break detection flag +This bit is set by hardware when the LIN break is detected. It is cleared by software, by +writing 1 to the LBDCF in the USART_ICR. +An interrupt is generated if LBDIE = 1 in the USART_CR2 register. +-0: LIN Break not detected +-1: LIN break detected + 8 + 1 + read-only + + + CTSIF + CTSIF: CTS interrupt flag +This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared +by software, by writing 1 to the CTSCF bit in the USART_ICR register. +An interrupt is generated if CTSIE=1 in the USART_CR3 register. +-0: No change occurred on the nCTS status line +-1: A change occurred on the nCTS status line + 9 + 1 + read-only + + + CTS + CTS: CTS flag +This bit is set/reset by hardware. It is an inverted copy of the status of the nCTS input pin. +-0: nCTS line set +-1: nCTS line reset + 10 + 1 + read-only + + + RTOF + RTOF: Receiver timeout +This bit is set by hardware when the timeout value, programmed in the RTOR register has +lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in +the USART_ICR register. +An interrupt is generated if RTOIE=1 in the USART_CR2 register. +In Smartcard mode, the timeout corresponds to the CWT or BWT timings. +-0: Timeout value not reached +-1: Timeout value reached without any data reception + 11 + 1 + read-only + + + EOBF + EOBF: End of block flag +This bit is set by hardware when a complete block has been received (for example T=1 +Smartcard mode). The detection is done when the number of received bytes (from the start +of the block, including the prologue) is equal or greater than BLEN + 4. +An interrupt is generated if the EOBIE=1 in the USART_CR2 register. +It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. +-0: End of Block not reached +-1: End of Block (number of characters) reached + 12 + 1 + read-only + + + UDR + UDR: SPI slave underrun error flag +In slave transmission mode, this flag is set when the first clock for data transmission appears +while the software has not yet loaded any value into USARTx_DR. +-0: No underrun error +-1: underrun error + 13 + 1 + read-only + + + ABRE + ABRE: Auto baud rate error +This bit is set by hardware if the baud rate measurement failed (baud rate out of range or +character comparison failed) +It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register + 14 + 1 + read-only + + + ABRF + ABRF: Auto baud rate flag +This bit is set by hardware when the automatic baud rate has been set (RXNE will also be +set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was +completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case) +It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to +the ABRRQ in the USART_RQR register. + 15 + 1 + read-only + + + BUSY + BUSY: Busy flag +This bit is set and reset by hardware. It is active when a communication is ongoing on the +RX line (successful start bit detected). It is reset at the end of the reception (successful or +not). +-0: USART is idle (no reception) +-1: Reception on going + 16 + 1 + read-only + + + CMF + CMF: Character match flag +This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is +cleared by software, writing 1 to the CMCF in the USART_ICR register. +An interrupt is generated if CMIE=1in the USART_CR1 register. +-0: No Character match detected +-1: Character Match detected + 17 + 1 + read-only + + + SBKF + SBKF: Send break flag +This bit indicates that a send break character was requested. It is set by software, by writing +1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during +the stop bit of break transmission. +-0: No break character is transmitted +-1: Break character will be transmitted + 18 + 1 + read-only + + + RWU + RWU: Receiver wakeup from Mute mode +This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a +wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE) +is selected by the WAKE bit in the USART_CR1 register. +When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the +MMRQ bit in the USART_RQR register. +-0: Receiver in active mode +-1: Receiver in mute mode + 19 + 1 + read-only + + + TEACK + TEACK: Transmit enable acknowledge flag +This bit is set/reset by hardware, when the Transmit Enable value is taken into account by +the USART. +It can be used when an idle frame request is generated by writing TE=0, followed by TE=1 +in the USART_CR1 register, in order to respect the TE=0 minimum period. + 21 + 1 + read-only + + + REACK + REACK: Receive enable acknowledge flag +This bit is set/reset by hardware, when the Receive Enable value is taken into account by +the USART. +It can be used to verify that the USART is ready for reception before entering Stop mode. + 22 + 1 + read-only + + + TXFE + TXFE: TXFIFO Empty +This bit is set by hardware when TXFIFO is Empty. When the TXFIFO contains at least one +data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in +the USART_RQR register. +An interrupt is generated if the TXFEIE bit =1 (bit 30) in the USART_CR1 register. +-0: TXFIFO is not empty. +-1: TXFIFO is empty. + 23 + 1 + read-only + + + RXFF + RXFF: RXFIFO Full +This bit is set by hardware when RXFIFO is Full. +An interrupt is generated if the RXFFIE bit =1 in the USART_CR1 register. +-0: RXFIFO is not Full. +-1: RXFIFO is Full. + 24 + 1 + read-only + + + TCBGT + TCBGT: Transmission complete before guard time flagl +This bit indicates when the last data written in the USART_TDR has been transmitted +correctly out of the shift register . +It is set by hardware in Smartcard mode, if the transmission of a frame containing data is +complete and if there is no NACK from the smartcard. An interrupt is generated if +TCBGTIE=1 in the USART_CR3 register. It is cleared by software, writing 1 to the +TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. +-0: Transmission is not complete or transmission is complete unsuccessfuly (i.e. a NACK is +received from the card) +-1: Transmission is complete successfully (before Guard time completion and there is no +NACK from the smart card). + 25 + 1 + read-only + + + RXFT + RXFT: RXFIFO threshold flag +This bit is set by hardware when the programmed threshold in RXFTCFG in USARTx_CR3 +register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and +one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit =1 (bit 27) in +the USART_CR3 register. +-0: Receive FIFO doesnt reach the programmed threshold. +-1: Receive FIFO reached the programmed threshold + 26 + 1 + read-only + + + TXFT + TXFT: TXFIFO threshold flag +This bit is set by hardware when the TXFIFO reaches the programmed threshold in TXFTCFG +in USARTx_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is +generated if the TXFTIE bit =1 (bit 31) in the USART_CR3 register. +-0: TXFIFO doesnt reach the programmed threshold. +-1: TXFIFO reached the programmed threshold + 27 + 1 + read-only + + + + + ICR + ICR + ICR register + 0x20 + 0x20 + read-write + 0x00000000 + + + PECF + PECF: Parity error clear flag +Writing 1 to this bit clears the PE flag in the USART_ISR register. + 0 + 1 + write-only + + + FECF + FECF: Framing error clear flag +Writing 1 to this bit clears the FE flag in the USART_ISR register + 1 + 1 + write-only + + + NECF + NECF: Noise detected clear flag +Writing 1 to this bit clears the NF flag in the USART_ISR register. + 2 + 1 + write-only + + + ORECF + ORECF: Overrun error clear flag +Writing 1 to this bit clears the ORE flag in the USART_ISR register. + 3 + 1 + write-only + + + IDLECF + IDLECF: Idle line detected clear flag +Writing 1 to this bit clears the IDLE flag in the USART_ISR register. + 4 + 1 + write-only + + + TXFECF + TXFECF: TXFIFO empty clear flag +Writing 1 to this bit clears the TXFE flag in the USART_ISR register + 5 + 1 + write-only + + + TCCF + TCCF: Transmission complete clear flag +Writing 1 to this bit clears the TC flag in the USART_ISR register + 6 + 1 + write-only + + + TCBGTCF + TCBGTCF: Transmission complete before Guard time clear flag +Writing 1 to this bit clears the TCBGT flag in the USART_ISR register. + 7 + 1 + write-only + + + LBDCF + LBDCF: LIN break detection clear flag +Writing 1 to this bit clears the LBDF flag in the USART_ISR register. + 8 + 1 + write-only + + + CTSCF + CTSCF: CTS clear flag +Writing 1 to this bit clears the CTSIF flag in the USART_ISR register + 9 + 1 + write-only + + + RTOCF + RTOCF: Receiver timeout clear flag +Writing 1 to this bit clears the RTOF flag in the USART_ISR register. + 11 + 1 + write-only + + + EOBCF + EOBCF: End of block clear flag +Writing 1 to this bit clears the EOBF flag in the USART_ISR register + 12 + 1 + write-only + + + UDRCF + UDRCF:SPI slave underrun clear flag +Writing 1 to this bit clears the UDRF flag in the USART_ISR register + 13 + 1 + write-only + + + CMCF + CMCF: Character match clear flag +Writing 1 to this bit clears the CMF flag in the USART_ISR register + 17 + 1 + write-only + + + + + RDR + RDR + RDR register + 0x24 + 0x20 + read-only + 0x0 + + + RDR + RDR[8:0]: Receive data value +Contains the received data character. +The RDR register provides the parallel interface between the input shift register and the +internal bus (see Figure 124). +When receiving with the parity enabled, the value read in the MSB bit is the received parity +bit. + 0 + 9 + read-only + + + + + TDR + TDR + TDR register + 0x28 + 0x20 + read-write + 0x0 + + + TDR + TDR[8:0]: Transmit data value +Contains the data character to be transmitted. +The USARTx_TDR register provides the parallel interface between the internal bus and the +output shift register (see Figure 124). +When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), +the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect +because it is replaced by the parity. +Note: This register must be written only when TXE/TXFNF=1. + 0 + 9 + read-write + + + + + PRESC + PRESC + PRESC register + 0x2C + 0x20 + read-write + 0x0 + + + PRESCALER + PRESCALER[3:0]: Clock prescaler +The USART input clock can be divided by a prescaler: +-0000: input clock not divided +-0001: input clock divided by 2 +-0010: input clock divided by 4 +-0011: input clock divided by 6 +-0100: input clock divided by 8 +-0101: input clock divided by 10 +-0110: input clock divided by 12 +-0111: input clock divided by 16 +-1000: input clock divided by 32 +-1001: input clock divided by 64 +-1010: input clock divided by 128 +-1011: input clock divided by 256 +Remaing combinations: Reserved. +Note: When PRESCALER is programmed with a value different of the allowed ones, +programmed prescaler value will be '1011' i.e. input clock divided by 256 + 0 + 4 + read-write + + + + + + +