diff --git a/CHANGELOG.md b/CHANGELOG.md index 218de1c2a..c7052b5ab 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Ticket | |:----:|:-------:|:--------|:------:| +| 14.06.2024 | 1.9.9.8 | minor rtl edits/cleanups; increase bootloader's auto-boot timeout from 8s to 10s | [#925](https://github.com/stnolting/neorv32/pull/925) | | 07.06.2024 | 1.9.9.7 | :sparkles: re-add TRNG "data available" interrupt | [#922](https://github.com/stnolting/neorv32/pull/922) | | 31.05.2024 | 1.9.9.6 | add "tag" signal to XBUS to provide additional access information (compatible to the AXI4 _ARPROT_ and _AWPROT_ signals) | [#917](https://github.com/stnolting/neorv32/pull/917) | | 30.05.2024 | 1.9.9.5 | :bug: fix uncached-vs-cached memory accesses (do not interrupt cache bursts by direct/uncached memory accesses) | [#915](https://github.com/stnolting/neorv32/pull/915) | diff --git a/docs/datasheet/software_bootloader.adoc b/docs/datasheet/software_bootloader.adoc index 5b92728ba..22d28c858 100644 --- a/docs/datasheet/software_bootloader.adoc +++ b/docs/datasheet/software_bootloader.adoc @@ -3,7 +3,7 @@ .Pre-Built Bootloader Image [IMPORTANT] -This section refers to the **default** NEORV32 bootloader. A pre-compiled memory image for the processor-internal +This section refers to the **default** NEORV32 bootloader. A pre-compiled memory image for the processor-internal <<_bootloader_rom_bootrom>> is available in the project's +rtl+ folder: `rtl/core/neorv32_bootloader_image.vhd`. This image is automatically inserted into the boot ROM when synthesizing the processor with the bootloader being enabled. **Note that the default bootloader image was compiled for a minimal `rv32i` + priv. ISA!** @@ -99,7 +99,7 @@ SOC: 0xffff402f IMEM: 0x00008000 DMEM: 0x00002000 -Autoboot in 8s. Press any key to abort. +Autoboot in 10s. Press any key to abort. ---- The start-up screen gives some brief information about the bootloader and several system configuration parameters: @@ -117,8 +117,8 @@ The start-up screen gives some brief information about the bootloader and severa | `DMEM` | Internal DMEM size in byte (via the `MEM` register from the <<_system_configuration_information_memory_sysinfo>>. |======================= -Now you have 8 seconds to press _any_ key. Otherwise, the bootloader starts the <<_auto_boot_sequence>>. When -you press any key within the 8 seconds, the actual bootloader user console starts: +Now you have 10 seconds to press _any_ key. Otherwise, the bootloader starts the <<_auto_boot_sequence>>. When +you press any key within the 10 seconds, the actual bootloader user console starts: [source] ---- @@ -133,7 +133,7 @@ SOC: 0xffff402f IMEM: 0x00008000 DMEM: 0x00002000 -Autoboot in 8s. Press any key to abort. <1> +Autoboot in 10s. Press any key to abort. <1> Aborted. Available CMDs: diff --git a/docs/userguide/customizing_the_bootloader.adoc b/docs/userguide/customizing_the_bootloader.adoc index 264f4ab61..32a4cbc48 100644 --- a/docs/userguide/customizing_the_bootloader.adoc +++ b/docs/userguide/customizing_the_bootloader.adoc @@ -22,14 +22,14 @@ minimal base & privileged ISA `rv32i_zicsr_zifencei` only to ensure it can work 4+^| Memory layout | `EXE_BASE_ADDR` | `0x00000000` | _any_ | Base address / boot address for the executable (see section "Address Space" in the NEORV32 data sheet) 4+^| Serial console interface -| `UART_EN` | `1` | `0`, `1` | Set to `0` to disable UART0 (no serial console at all) -| `UART_BAUD` | `19200` | _any_ | Baud rate of UART0 +| `UART_EN` | `1` | `0`, `1` | Set to `0` to disable UART0 (no serial console at all) +| `UART_BAUD` | `19200` | _any_ | Baud rate of UART0 | `UART_HW_HANDSHAKE_EN` | `0` | `0`, `1` | Set to `1` to enable UART0 hardware flow control 4+^| Status LED | `STATUS_LED_EN` | `1` | `0`, `1` | Enable bootloader status led ("heart beat") at `GPIO` output port pin #`STATUS_LED_PIN` when `1` | `STATUS_LED_PIN` | `0` | `0` ... `31` | `GPIO` output pin used for the high-active status LED 4+^| Auto-boot configuration -| `AUTO_BOOT_TIMEOUT` | `8` | _any_ | Time in seconds after the auto-boot sequence starts (if there is no UART input by the user); set to 0 to disabled auto-boot sequence +| `AUTO_BOOT_TIMEOUT` | `10` | _any_ | Time in seconds after the auto-boot sequence starts (if there is no UART input by the user); set to 0 to disabled auto-boot sequence 4+^| SPI configuration | `SPI_EN` | `1` | `0`, `1` | Set `1` to enable the usage of the SPI module (including load/store executables from/to SPI flash options) | `SPI_FLASH_CS` | `0` | `0` ... `7` | SPI chip select output (`spi_csn_o`) for selecting flash diff --git a/docs/userguide/executable_upload.adoc b/docs/userguide/executable_upload.adoc index 0f116b637..d7e29fc7e 100644 --- a/docs/userguide/executable_upload.adoc +++ b/docs/userguide/executable_upload.adoc @@ -39,7 +39,7 @@ following parameters: [start=4] . Also make sure that single chars are send from your computer _without_ any consecutive "new line" or "carriage return" commands. This is highly dependent on your terminal application of choice, TeraTerm only -sends the raw chars by default. In `cutecom`, change `LF` to `None` in the dropdown menu +sends the raw chars by default. In `cutecom`, change `LF` to `None` in the dropdown menu next to the input text box. . Press the NEORV32 reset button to restart the bootloader. The status LED starts blinking and the bootloader intro screen appears in your console. Hurry up and press any key (hit space!) to abort the @@ -60,7 +60,7 @@ SOC: 0xffff402f IMEM: 0x00008000 bytes @0x00000000 DMEM: 0x00002000 bytes @0x80000000 -Autoboot in 8s. Press any key to abort. +Autoboot in 10s. Press any key to abort. Aborted. Available CMDs: diff --git a/rtl/core/neorv32_bootloader_image.vhd b/rtl/core/neorv32_bootloader_image.vhd index e90a7ffd4..65ef96482 100644 --- a/rtl/core/neorv32_bootloader_image.vhd +++ b/rtl/core/neorv32_bootloader_image.vhd @@ -1,8 +1,8 @@ -- The NEORV32 RISC-V Processor: https://github.com/stnolting/neorv32 -- Auto-generated memory initialization file (for BOOTLOADER) from source file --- Size: 4056 bytes +-- Size: 4076 bytes -- MARCH: default --- Built: 15.03.2024 17:32:22 +-- Built: 14.06.2024 14:42:12 (dd.mm.yyyy hh:mm:ss) -- prototype defined in 'neorv32_package.vhd' package body neorv32_bootloader_image is @@ -42,7 +42,7 @@ x"00000e93", x"00000f13", x"00000f93", x"00001597", -x"f5458593", +x"f6858593", x"80004617", x"f7460613", x"80004697", @@ -103,7 +103,7 @@ x"01812c23", x"01912a23", x"01a12823", x"01b12623", -x"a0878793", +x"a1078793", x"30579073", x"e0802783", x"00d79713", @@ -139,7 +139,7 @@ x"000016b7", x"60068693", x"00d76733", x"00e7a023", -x"4a4000ef", +x"4ac000ef", x"00050863", x"00100793", x"c0f02423", @@ -152,10 +152,10 @@ x"ffff7637", x"00000793", x"5ff70713", x"a0060613", -x"20d76063", +x"20d76463", x"00000713", x"3fe00613", -x"20f66063", +x"20f66463", x"fff78793", x"000106b7", x"00679793", @@ -182,59 +182,61 @@ x"30479073", x"00800793", x"3007a073", x"ffffd537", -x"d9850513", -x"6a0000ef", +x"dac50513", +x"6a8000ef", x"f1302573", -x"624000ef", +x"62c000ef", x"ffffd537", -x"dd050513", -x"68c000ef", +x"de450513", +x"694000ef", x"e0002503", -x"610000ef", +x"618000ef", x"ffffd537", -x"dd850513", -x"678000ef", +x"dec50513", +x"680000ef", x"30102573", -x"5fc000ef", +x"604000ef", x"ffffd537", -x"de050513", -x"664000ef", +x"df450513", +x"66c000ef", x"fc002573", -x"5e8000ef", +x"5f0000ef", x"ffffd537", -x"de850513", -x"650000ef", +x"dfc50513", +x"658000ef", x"e0802503", x"00100413", x"ffffd937", -x"5cc000ef", +x"5d4000ef", x"ffffd537", -x"df050513", -x"634000ef", +x"e0450513", +x"63c000ef", x"e0404503", x"00a41533", x"ffc57513", -x"5b0000ef", +x"5b8000ef", x"ffffd537", -x"df850513", -x"618000ef", +x"e0c50513", +x"620000ef", x"e0504783", x"00f41533", x"ffc57513", -x"594000ef", -x"d9490513", -x"600000ef", +x"59c000ef", +x"da890513", +x"608000ef", x"e0802783", x"00f79713", -x"04075c63", +x"06075063", x"ffffd537", -x"e0050513", -x"5e8000ef", -x"2b4000ef", -x"e0002403", +x"e1450513", +x"5f0000ef", +x"2bc000ef", +x"e0002783", x"fffffa37", x"500a0a13", -x"00341413", +x"00279413", +x"00f40433", +x"00141413", x"00a409b3", x"0089b433", x"00b40433", @@ -246,18 +248,18 @@ x"00f79713", x"0c075063", x"ffffd537", x"004a2783", -x"e2c50513", +x"e4050513", x"5a0000ef", x"ffffdb37", -x"e38b0513", +x"e4cb0513", x"ffffd9b7", x"590000ef", x"ffffdab7", -x"f6498993", +x"f7898993", x"ffffdc37", x"ffffdcb7", x"ffffd7b7", -x"eb878513", +x"ecc78513", x"574000ef", x"fffff7b7", x"50078793", @@ -268,7 +270,7 @@ x"0047a403", x"0ff47413", x"00040513", x"4c0000ef", -x"d9490513", +x"da890513", x"548000ef", x"03f00793", x"20f40263", @@ -282,13 +284,13 @@ x"00042783", x"00078067", x"00c686b3", x"00178793", -x"df9ff06f", +x"df1ff06f", x"ffe70693", x"ffd6f693", x"00069863", x"0037d793", x"00170713", -x"dedff06f", +x"de5ff06f", x"0017d793", x"ff5ff06f", x"1c0000ef", @@ -296,34 +298,34 @@ x"f285e4e3", x"00b41463", x"f33560e3", x"00100513", -x"6fc000ef", -x"d9490513", +x"6f8000ef", +x"da890513", x"4d4000ef", x"00000513", -x"041000ef", +x"03d000ef", x"ffffc2b7", x"00028067", -x"e38b0513", +x"e4cb0513", x"4bc000ef", x"f3dff06f", x"00000513", -x"6d0000ef", +x"6cc000ef", x"f31ff06f", x"0044a403", x"00041863", x"ffffd537", -x"ec050513", +x"ed450513", x"fddff06f", -x"edcc0513", +x"ef0c0513", x"490000ef", x"00040513", x"414000ef", -x"ee4c8513", +x"ef8c8513", x"480000ef", x"00400537", x"404000ef", x"ffffd537", -x"efc50513", +x"f1050513", x"46c000ef", x"fffff7b7", x"50078793", @@ -341,7 +343,7 @@ x"00050663", x"00300513", x"488000ef", x"ffffd537", -x"f0850513", +x"f1c50513", x"424000ef", x"01045b93", x"00400a37", @@ -384,24 +386,24 @@ x"00850513", x"41a005b3", x"260000ef", x"ffffd537", -x"d7c50513", +x"d9050513", x"ebdff06f", x"00100513", x"ec1ff06f", x"0044a783", x"e8079ce3", x"ffffd7b7", -x"f1878513", +x"f2c78513", x"ea1ff06f", x"e0802783", x"2007f793", x"00079663", -x"f28a8513", +x"f3ca8513", x"e8dff06f", x"00100513", x"e75ff06f", x"ffffd7b7", -x"f3478513", +x"f4878513", x"e79ff06f", x"fffff7b7", x"40078793", @@ -591,7 +593,7 @@ x"07800513", x"ffffd4b7", x"fb9ff0ef", x"01c00413", -x"fb448493", +x"fc848493", x"ffc00993", x"008957b3", x"00f7f793", @@ -633,13 +635,13 @@ x"ff010113", x"00812423", x"00050413", x"ffffd537", -x"d3450513", +x"d3850513", x"00112623", x"f91ff0ef", x"00241793", x"ffffd537", x"008787b3", -x"fc450513", +x"fd850513", x"00f50533", x"f79ff0ef", x"00800793", @@ -672,7 +674,7 @@ x"01f12423", x"342024f3", x"800007b7", x"00778793", -x"0af49263", +x"0af49063", x"c4dff0ef", x"00050863", x"c0802783", @@ -680,7 +682,7 @@ x"0017c793", x"c0f02423", x"e0802783", x"00f79713", -x"02075a63", +x"02075863", x"ba9ff0ef", x"e0002783", x"fffff737", @@ -692,7 +694,6 @@ x"40d72423", x"00b787b3", x"40f72623", x"40a72423", -x"00000013", x"03c12403", x"04c12083", x"04812283", @@ -719,27 +720,27 @@ x"800007b7", x"0007a783", x"00078663", x"00100513", -x"e99ff0ef", +x"e9dff0ef", x"34102473", x"e0802783", x"00e79713", x"04075263", x"ffffd537", -x"d3c50513", -x"e25ff0ef", +x"d4050513", +x"e29ff0ef", x"00048513", -x"da9ff0ef", +x"dadff0ef", x"02000513", -x"d85ff0ef", +x"d89ff0ef", x"00040513", -x"d99ff0ef", +x"d9dff0ef", x"02000513", -x"d75ff0ef", +x"d79ff0ef", x"34302573", -x"d89ff0ef", +x"d8dff0ef", x"ffffd537", -x"d9450513", -x"df1ff0ef", +x"da850513", +x"df5ff0ef", x"00440413", x"34141073", x"f3dff06f", @@ -759,41 +760,41 @@ x"00fb2023", x"00050413", x"02051863", x"ffffd537", -x"d4850513", -x"d9dff0ef", +x"d4c50513", +x"da1ff0ef", x"004005b7", x"00040513", -x"b0dff0ef", +x"b11ff0ef", x"4788d7b7", x"afe78793", x"04f50663", x"00000513", x"0340006f", x"ffffd537", -x"d6850513", -x"d71ff0ef", +x"d6c50513", +x"d75ff0ef", x"00400537", -x"cf5ff0ef", +x"cf9ff0ef", x"ffffd537", -x"d7450513", -x"d5dff0ef", +x"d8850513", +x"d61ff0ef", x"e0802783", x"00d79713", x"00074663", x"00300513", -x"da1ff0ef", -x"bcdff0ef", +x"da5ff0ef", +x"bd1ff0ef", x"fa0504e3", x"ff1ff06f", x"004005b7", x"00458593", x"00040513", -x"aa9ff0ef", +x"aadff0ef", x"004005b7", x"00050993", x"00858593", x"00040513", -x"a95ff0ef", +x"a99ff0ef", x"00400ab7", x"00050a13", x"ffc9fb93", @@ -806,8 +807,8 @@ x"014484b3", x"00200513", x"fa0492e3", x"ffffd537", -x"d7c50513", -x"ce1ff0ef", +x"d9050513", +x"ce5ff0ef", x"02c12083", x"02812403", x"800007b7", @@ -823,7 +824,7 @@ x"00c12b83", x"03010113", x"00008067", x"00040513", -x"a1dff0ef", +x"a21ff0ef", x"00a92023", x"00a484b3", x"00490913", @@ -837,14 +838,14 @@ x"00000413", x"00050463", x"e0400437", x"ffffd537", -x"d8050513", -x"c65ff0ef", +x"d9450513", +x"c69ff0ef", x"00040513", -x"be9ff0ef", +x"bedff0ef", x"ffffd537", -x"d9050513", -x"c51ff0ef", -x"9a1ff0ef", +x"da450513", +x"c55ff0ef", +x"9a5ff0ef", x"00050663", x"c0002423", x"c0002623", @@ -868,9 +869,13 @@ x"202e2e2e", x"00000000", x"64616f4c", x"20676e69", -x"00004028", -x"2e2e2e29", -x"0000000a", +x"6d6f7266", +x"49505320", +x"616c6620", +x"40206873", +x"00000000", +x"0a2e2e2e", +x"00000000", x"00004b4f", x"746f6f42", x"20676e69", @@ -886,9 +891,9 @@ x"6f6c746f", x"72656461", x"0a3e3e20", x"444c420a", -x"4d203a56", -x"31207261", -x"30322035", +x"4a203a56", +x"31206e75", +x"30322034", x"480a3432", x"203a5657", x"00000020", @@ -907,14 +912,14 @@ x"00203a4d", x"7475410a", x"6f6f626f", x"6e692074", -x"2e733820", -x"65725020", -x"61207373", -x"6b20796e", -x"74207965", -x"6261206f", -x"2e74726f", -x"0000000a", +x"73303120", +x"7250202e", +x"20737365", +x"20796e61", +x"2079656b", +x"61206f74", +x"74726f62", +x"00000a2e", x"726f6241", x"2e646574", x"00000a0a", @@ -993,26 +998,26 @@ x"746c6f6e", x"2f676e69", x"726f656e", x"00323376", +x"ffffc5f8", +x"ffffc618", +x"ffffc618", +x"ffffc4a4", +x"ffffc618", +x"ffffc618", +x"ffffc618", x"ffffc5f0", -x"ffffc610", -x"ffffc610", +x"ffffc618", +x"ffffc618", +x"ffffc618", +x"ffffc618", +x"ffffc618", x"ffffc49c", -x"ffffc610", -x"ffffc610", -x"ffffc610", -x"ffffc5e8", -x"ffffc610", -x"ffffc610", -x"ffffc610", -x"ffffc610", -x"ffffc610", -x"ffffc494", -x"ffffc4b4", -x"ffffc610", -x"ffffc4a8", -x"ffffc610", -x"ffffc610", -x"ffffc604", +x"ffffc4bc", +x"ffffc618", +x"ffffc4b0", +x"ffffc618", +x"ffffc618", +x"ffffc60c", x"33323130", x"37363534", x"62613938", diff --git a/rtl/core/neorv32_cache.vhd b/rtl/core/neorv32_cache.vhd index bc63322c6..260a4b4eb 100644 --- a/rtl/core/neorv32_cache.vhd +++ b/rtl/core/neorv32_cache.vhd @@ -152,7 +152,7 @@ architecture neorv32_cache_rtl of neorv32_cache is -- cache memory module interface -- type cache_in_t is record addr : std_ulogic_vector(31 downto 0); - we : std_ulogic_vector(03 downto 0); + we : std_ulogic_vector(3 downto 0); swe : std_ulogic; wdata : std_ulogic_vector(31 downto 0); wstat : std_ulogic; diff --git a/rtl/core/neorv32_cpu_cp_fpu.vhd b/rtl/core/neorv32_cpu_cp_fpu.vhd index 21e96d6f7..1a58b1192 100644 --- a/rtl/core/neorv32_cpu_cp_fpu.vhd +++ b/rtl/core/neorv32_cpu_cp_fpu.vhd @@ -86,16 +86,16 @@ architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is rstn_i : in std_ulogic; -- global reset, low-active, async start_i : in std_ulogic; -- trigger operation abort_i : in std_ulogic; -- abort current operation - rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode + rmode_i : in std_ulogic_vector(2 downto 0); -- rounding mode funct_i : in std_ulogic; -- 0=signed, 1=unsigned -- input -- sign_i : in std_ulogic; -- sign - exponent_i : in std_ulogic_vector(07 downto 0); -- exponent + exponent_i : in std_ulogic_vector(7 downto 0); -- exponent mantissa_i : in std_ulogic_vector(22 downto 0); -- mantissa class_i : in std_ulogic_vector(09 downto 0); -- operand class -- output -- result_o : out std_ulogic_vector(31 downto 0); -- integer result - flags_o : out std_ulogic_vector(04 downto 0); -- exception flags + flags_o : out std_ulogic_vector(4 downto 0); -- exception flags done_o : out std_ulogic -- operation done ); end component; @@ -112,18 +112,18 @@ architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is rstn_i : in std_ulogic; -- global reset, low-active, async start_i : in std_ulogic; -- trigger operation abort_i : in std_ulogic; -- abort current operation - rmode_i : in std_ulogic_vector(02 downto 0); -- rounding mode + rmode_i : in std_ulogic_vector(2 downto 0); -- rounding mode funct_i : in std_ulogic; -- operating mode (0=norm&round, 1=int-to-float) -- input -- sign_i : in std_ulogic; -- sign - exponent_i : in std_ulogic_vector(08 downto 0); -- extended exponent + exponent_i : in std_ulogic_vector(8 downto 0); -- extended exponent mantissa_i : in std_ulogic_vector(47 downto 0); -- extended mantissa integer_i : in std_ulogic_vector(31 downto 0); -- integer input - class_i : in std_ulogic_vector(09 downto 0); -- input number class - flags_i : in std_ulogic_vector(04 downto 0); -- exception flags input + class_i : in std_ulogic_vector(9 downto 0); -- input number class + flags_i : in std_ulogic_vector(4 downto 0); -- exception flags input -- output -- result_o : out std_ulogic_vector(31 downto 0); -- result (float or int) - flags_o : out std_ulogic_vector(04 downto 0); -- exception flags + flags_o : out std_ulogic_vector(4 downto 0); -- exception flags done_o : out std_ulogic -- operation done ); end component; @@ -157,24 +157,24 @@ architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is type op_class_t is array (0 to 1) of std_ulogic_vector(09 downto 0); type fpu_operands_t is record rs1 : std_ulogic_vector(31 downto 0); -- operand 1 - rs1_class : std_ulogic_vector(09 downto 0); -- operand 1 number class + rs1_class : std_ulogic_vector(9 downto 0); -- operand 1 number class rs2 : std_ulogic_vector(31 downto 0); -- operand 2 - rs2_class : std_ulogic_vector(09 downto 0); -- operand 2 number class - frm : std_ulogic_vector(02 downto 0); -- rounding mode + rs2_class : std_ulogic_vector(9 downto 0); -- operand 2 number class + frm : std_ulogic_vector(2 downto 0); -- rounding mode end record; signal op_data : op_data_t; signal op_class : op_class_t; signal fpu_operands : fpu_operands_t; -- floating-point comparator -- - signal cmp_ff : std_ulogic_vector(01 downto 0); + signal cmp_ff : std_ulogic_vector(1 downto 0); signal comp_equal_ff : std_ulogic; signal comp_less_ff : std_ulogic; -- functional units interface -- type fu_interface_t is record result : std_ulogic_vector(31 downto 0); - flags : std_ulogic_vector(04 downto 0); + flags : std_ulogic_vector(4 downto 0); start : std_ulogic; done : std_ulogic; end record; @@ -203,14 +203,14 @@ architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is buf_ff : unsigned(47 downto 0); -- product buffer sign : std_ulogic; -- resulting sign product : std_ulogic_vector(47 downto 0); -- product - exp_sum : std_ulogic_vector(08 downto 0); -- incl 1x overflow/underflow bit - exp_res : std_ulogic_vector(09 downto 0); -- resulting exponent incl 2x overflow/underflow bit + exp_sum : std_ulogic_vector(8 downto 0); -- incl 1x overflow/underflow bit + exp_res : std_ulogic_vector(9 downto 0); -- resulting exponent incl 2x overflow/underflow bit -- - res_class : std_ulogic_vector(09 downto 0); - flags : std_ulogic_vector(04 downto 0); -- exception flags + res_class : std_ulogic_vector(9 downto 0); + flags : std_ulogic_vector(4 downto 0); -- exception flags -- start : std_ulogic; - latency : std_ulogic_vector(02 downto 0); -- unit latency + latency : std_ulogic_vector(2 downto 0); -- unit latency done : std_ulogic; end record; signal multiplier : multiplier_t; @@ -218,17 +218,17 @@ architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is -- adder/subtractor unit -- type addsub_t is record -- input comparison -- - exp_comp : std_ulogic_vector(01 downto 0); -- equal & less - small_exp : std_ulogic_vector(07 downto 0); + exp_comp : std_ulogic_vector(1 downto 0); -- equal & less + small_exp : std_ulogic_vector(7 downto 0); small_man : std_ulogic_vector(23 downto 0); -- mantissa + hidden one - large_exp : std_ulogic_vector(07 downto 0); + large_exp : std_ulogic_vector(7 downto 0); large_man : std_ulogic_vector(23 downto 0); -- mantissa + hidden one -- smaller mantissa alginment -- man_sreg : std_ulogic_vector(23 downto 0); -- mantissa + hidden one man_g_ext : std_ulogic; man_r_ext : std_ulogic; man_s_ext : std_ulogic; - exp_cnt : std_ulogic_vector(08 downto 0); + exp_cnt : std_ulogic_vector(8 downto 0); -- adder/subtractor stage -- man_comp : std_ulogic; man_s : std_ulogic_vector(26 downto 0); -- mantissa + hidden one + GRS @@ -237,11 +237,11 @@ architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is -- result -- res_sign : std_ulogic; res_sum : std_ulogic_vector(27 downto 0); -- mantissa sum (+1 bit) + GRS bits (for rounding) - res_class : std_ulogic_vector(09 downto 0); - flags : std_ulogic_vector(04 downto 0); -- exception flags + res_class : std_ulogic_vector(9 downto 0); + flags : std_ulogic_vector(4 downto 0); -- exception flags -- arbitration -- start : std_ulogic; - latency : std_ulogic_vector(04 downto 0); -- unit latency + latency : std_ulogic_vector(4 downto 0); -- unit latency done : std_ulogic; end record; signal addsub : addsub_t; @@ -251,12 +251,12 @@ architecture neorv32_cpu_cp_fpu_rtl of neorv32_cpu_cp_fpu is start : std_ulogic; mode : std_ulogic; sign : std_ulogic; - xexp : std_ulogic_vector(08 downto 0); + xexp : std_ulogic_vector(8 downto 0); xmantissa : std_ulogic_vector(47 downto 0); result : std_ulogic_vector(31 downto 0); - class : std_ulogic_vector(09 downto 0); - flags_in : std_ulogic_vector(04 downto 0); - flags_out : std_ulogic_vector(04 downto 0); + class : std_ulogic_vector(9 downto 0); + flags_in : std_ulogic_vector(4 downto 0); + flags_out : std_ulogic_vector(4 downto 0); done : std_ulogic; end record; signal normalizer : normalizer_t; diff --git a/rtl/core/neorv32_cpu_pmp.vhd b/rtl/core/neorv32_cpu_pmp.vhd index 8bb5752a7..2115dccd7 100644 --- a/rtl/core/neorv32_cpu_pmp.vhd +++ b/rtl/core/neorv32_cpu_pmp.vhd @@ -76,7 +76,7 @@ architecture neorv32_cpu_pmp_rtl of neorv32_cpu_pmp is type csr_cfg_rd32_t is array (0 to 03) of std_ulogic_vector(XLEN-1 downto 0); type csr_addr_rd_t is array (0 to 15) of std_ulogic_vector(XLEN-1 downto 0); type csr_t is record - we_cfg : std_ulogic_vector(03 downto 0); + we_cfg : std_ulogic_vector(3 downto 0); we_addr : std_ulogic_vector(15 downto 0); cfg : csr_cfg_t; addr : csr_addr_t; diff --git a/rtl/core/neorv32_crc.vhd b/rtl/core/neorv32_crc.vhd index 7141a34c3..e6d8e5d86 100644 --- a/rtl/core/neorv32_crc.vhd +++ b/rtl/core/neorv32_crc.vhd @@ -34,12 +34,12 @@ architecture neorv32_crc_rtl of neorv32_crc is -- CRC core -- type crc_t is record - mode : std_ulogic_vector(01 downto 0); + mode : std_ulogic_vector(1 downto 0); poly : std_ulogic_vector(31 downto 0); - data : std_ulogic_vector(07 downto 0); + data : std_ulogic_vector(7 downto 0); sreg : std_ulogic_vector(31 downto 0); -- - cnt : std_ulogic_vector(03 downto 0); + cnt : std_ulogic_vector(3 downto 0); msb : std_ulogic; end record; signal crc : crc_t; diff --git a/rtl/core/neorv32_debug_dm.vhd b/rtl/core/neorv32_debug_dm.vhd index 75c9d2c5e..3fd3f16cd 100644 --- a/rtl/core/neorv32_debug_dm.vhd +++ b/rtl/core/neorv32_debug_dm.vhd @@ -83,7 +83,7 @@ architecture neorv32_debug_dm_rtl of neorv32_debug_dm is dmcontrol_ndmreset : std_ulogic; dmcontrol_dmactive : std_ulogic; abstractauto_autoexecdata : std_ulogic; - abstractauto_autoexecprogbuf : std_ulogic_vector(01 downto 0); + abstractauto_autoexecprogbuf : std_ulogic_vector(1 downto 0); progbuf : progbuf_t; command : std_ulogic_vector(31 downto 0); -- @@ -107,11 +107,11 @@ architecture neorv32_debug_dm_rtl of neorv32_debug_dm is -- ********************************************************** -- DM configuration -- - constant nscratch_c : std_ulogic_vector(03 downto 0) := "0001"; -- number of dscratch registers in CPU (=1) - constant datasize_c : std_ulogic_vector(03 downto 0) := "0001"; -- number of data registers in memory/CSR space (=1) + constant nscratch_c : std_ulogic_vector(3 downto 0) := "0001"; -- number of dscratch registers in CPU (=1) + constant datasize_c : std_ulogic_vector(3 downto 0) := "0001"; -- number of data registers in memory/CSR space (=1) constant dataaddr_c : std_ulogic_vector(11 downto 0) := dm_data_base_c(11 downto 0); -- signed base address of data registers in memory/CSR space constant dataaccess_c : std_ulogic := '1'; -- 1: abstract data is memory-mapped, 0: abstract data is CSR-mapped - constant dm_version_c : std_ulogic_vector(03 downto 0) := cond_sel_suv_f(LEGACY_MODE, "0010", "0011"); -- version: v0.13 / v1.0 + constant dm_version_c : std_ulogic_vector(3 downto 0) := cond_sel_suv_f(LEGACY_MODE, "0010", "0011"); -- version: v0.13 / v1.0 -- debug module controller -- type dm_ctrl_state_t is (CMD_IDLE, CMD_CHECK, CMD_PREPARE, CMD_TRIGGER, CMD_BUSY, CMD_ERROR); @@ -124,7 +124,7 @@ architecture neorv32_debug_dm_rtl of neorv32_debug_dm is -- error flags -- illegal_state : std_ulogic; illegal_cmd : std_ulogic; - cmderr : std_ulogic_vector(02 downto 0); + cmderr : std_ulogic_vector(2 downto 0); -- hart status -- hart_halted : std_ulogic; hart_resume_req : std_ulogic; diff --git a/rtl/core/neorv32_debug_dtm.vhd b/rtl/core/neorv32_debug_dtm.vhd index 19dca571d..b6f8d6dde 100644 --- a/rtl/core/neorv32_debug_dtm.vhd +++ b/rtl/core/neorv32_debug_dtm.vhd @@ -16,7 +16,7 @@ use neorv32.neorv32_package.all; entity neorv32_debug_dtm is generic ( - IDCODE_VERSION : std_ulogic_vector(03 downto 0); -- version + IDCODE_VERSION : std_ulogic_vector(3 downto 0); -- version IDCODE_PARTID : std_ulogic_vector(15 downto 0); -- part number IDCODE_MANID : std_ulogic_vector(10 downto 0) -- manufacturer id ); @@ -39,9 +39,9 @@ end neorv32_debug_dtm; architecture neorv32_debug_dtm_rtl of neorv32_debug_dtm is -- DMI Configuration (fixed!) -- - constant dmi_idle_c : std_ulogic_vector(02 downto 0) := "000"; -- no idle cycles required - constant dmi_version_c : std_ulogic_vector(03 downto 0) := "0001"; -- debug spec. version (0.13 & 1.0) - constant dmi_abits_c : std_ulogic_vector(05 downto 0) := "000111"; -- number of DMI address bits (7) + constant dmi_idle_c : std_ulogic_vector(2 downto 0) := "000"; -- no idle cycles required + constant dmi_version_c : std_ulogic_vector(3 downto 0) := "0001"; -- debug spec. version (0.13 & 1.0) + constant dmi_abits_c : std_ulogic_vector(5 downto 0) := "000111"; -- number of DMI address bits (7) -- TAP data register addresses -- constant addr_idcode_c : std_ulogic_vector(4 downto 0) := "00001"; -- identifier @@ -71,7 +71,7 @@ architecture neorv32_debug_dtm_rtl of neorv32_debug_dtm is -- tap registers -- type tap_reg_t is record - ireg : std_ulogic_vector(04 downto 0); + ireg : std_ulogic_vector(4 downto 0); bypass : std_ulogic; idcode : std_ulogic_vector(31 downto 0); dtmcs, dtmcs_nxt : std_ulogic_vector(31 downto 0); @@ -89,13 +89,13 @@ architecture neorv32_debug_dtm_rtl of neorv32_debug_dtm is -- debug module interface controller -- type dmi_ctrl_t is record busy : std_ulogic; - op : std_ulogic_vector(01 downto 0); + op : std_ulogic_vector(1 downto 0); dmihardreset : std_ulogic; dmireset : std_ulogic; err : std_ulogic; rdata : std_ulogic_vector(31 downto 0); wdata : std_ulogic_vector(31 downto 0); - addr : std_ulogic_vector(06 downto 0); + addr : std_ulogic_vector(6 downto 0); end record; signal dmi_ctrl : dmi_ctrl_t; diff --git a/rtl/core/neorv32_dma.vhd b/rtl/core/neorv32_dma.vhd index 8886e366f..e6b3bb16b 100644 --- a/rtl/core/neorv32_dma.vhd +++ b/rtl/core/neorv32_dma.vhd @@ -64,11 +64,11 @@ architecture neorv32_dma_rtl of neorv32_dma is enable : std_ulogic; -- DMA enabled when set auto : std_ulogic; -- FIRQ-driven auto transfer fence : std_ulogic; -- issue FENCE operation when DMA is done - firq_sel : std_ulogic_vector(03 downto 0); -- FIRQ trigger select + firq_sel : std_ulogic_vector(3 downto 0); -- FIRQ trigger select src_base : std_ulogic_vector(31 downto 0); -- source base address dst_base : std_ulogic_vector(31 downto 0); -- destination base address num : std_ulogic_vector(23 downto 0); -- number of elements - qsel : std_ulogic_vector(01 downto 0); -- data quantity select + qsel : std_ulogic_vector(1 downto 0); -- data quantity select src_inc : std_ulogic; -- constant (0) or incrementing (1) source address dst_inc : std_ulogic; -- constant (0) or incrementing (1) destination address endian : std_ulogic; -- convert endianness when set @@ -333,16 +333,16 @@ begin else -- byte case engine.src_addr(1 downto 0) is when "00" => -- byte 0 - align_buf(07 downto 0) <= align_end(07 downto 00); - align_buf(31 downto 8) <= (others => (config.qsel(1) and align_end(07))); -- sign extension + align_buf(7 downto 0) <= align_end(7 downto 0); + align_buf(31 downto 8) <= (others => (config.qsel(1) and align_end(7))); -- sign extension when "01" => -- byte 1 - align_buf(07 downto 0) <= align_end(15 downto 08); + align_buf(7 downto 0) <= align_end(15 downto 8); align_buf(31 downto 8) <= (others => (config.qsel(1) and align_end(15))); -- sign extension when "10" => -- byte 2 - align_buf(07 downto 0) <= align_end(23 downto 16); + align_buf(7 downto 0) <= align_end(23 downto 16); align_buf(31 downto 8) <= (others => (config.qsel(1) and align_end(23))); -- sign extension when others => -- byte 3 - align_buf(07 downto 0) <= align_end(31 downto 24); + align_buf(7 downto 0) <= align_end(31 downto 24); align_buf(31 downto 8) <= (others => (config.qsel(1) and align_end(31))); -- sign extension end case; end if; @@ -355,8 +355,8 @@ begin begin dma_req_o.ben <= (others => '0'); -- default if (config.qsel = qsel_b2b_c) then -- byte - dma_req_o.data(07 downto 00) <= align_buf(7 downto 0); - dma_req_o.data(15 downto 08) <= align_buf(7 downto 0); + dma_req_o.data(7 downto 0) <= align_buf(7 downto 0); + dma_req_o.data(15 downto 8) <= align_buf(7 downto 0); dma_req_o.data(23 downto 16) <= align_buf(7 downto 0); dma_req_o.data(31 downto 24) <= align_buf(7 downto 0); dma_req_o.ben(to_integer(unsigned(engine.dst_addr(1 downto 0)))) <= '1'; diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index b3b5690b5..47e292287 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -29,7 +29,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090907"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090908"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width diff --git a/rtl/core/neorv32_pwm.vhd b/rtl/core/neorv32_pwm.vhd index 499214537..8813b0bd3 100644 --- a/rtl/core/neorv32_pwm.vhd +++ b/rtl/core/neorv32_pwm.vhd @@ -25,7 +25,7 @@ entity neorv32_pwm is bus_req_i : in bus_req_t; -- bus request bus_rsp_o : out bus_rsp_t; -- bus response clkgen_en_o : out std_ulogic; -- enable clock generator - clkgen_i : in std_ulogic_vector(07 downto 0); -- clock divider input + clkgen_i : in std_ulogic_vector(7 downto 0); -- clock divider input pwm_o : out std_ulogic_vector(11 downto 0) -- PWM output ); end neorv32_pwm; diff --git a/rtl/core/neorv32_spi.vhd b/rtl/core/neorv32_spi.vhd index 76320be7f..9edb73551 100644 --- a/rtl/core/neorv32_spi.vhd +++ b/rtl/core/neorv32_spi.vhd @@ -25,11 +25,11 @@ entity neorv32_spi is bus_req_i : in bus_req_t; -- bus request bus_rsp_o : out bus_rsp_t; -- bus response clkgen_en_o : out std_ulogic; -- enable clock generator - clkgen_i : in std_ulogic_vector(07 downto 0); + clkgen_i : in std_ulogic_vector(7 downto 0); spi_clk_o : out std_ulogic; -- SPI serial clock spi_dat_o : out std_ulogic; -- controller data out, peripheral data in spi_dat_i : in std_ulogic; -- controller data in, peripheral data out - spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS + spi_csn_o : out std_ulogic_vector(7 downto 0); -- SPI CS irq_o : out std_ulogic -- transmission done interrupt ); end neorv32_spi; diff --git a/rtl/core/neorv32_uart.vhd b/rtl/core/neorv32_uart.vhd index 6c9b3509d..31df07e86 100644 --- a/rtl/core/neorv32_uart.vhd +++ b/rtl/core/neorv32_uart.vhd @@ -28,7 +28,7 @@ entity neorv32_uart is bus_req_i : in bus_req_t; -- bus request bus_rsp_o : out bus_rsp_t; -- bus response clkgen_en_o : out std_ulogic; -- enable clock generator - clkgen_i : in std_ulogic_vector(07 downto 0); + clkgen_i : in std_ulogic_vector(7 downto 0); uart_txd_o : out std_ulogic; -- serial TX line uart_rxd_i : in std_ulogic; -- serial RX line uart_rts_o : out std_ulogic; -- UART.RX ready to receive ("RTR"), low-active, optional diff --git a/rtl/core/neorv32_xbus.vhd b/rtl/core/neorv32_xbus.vhd index 6e5d5de39..1200023cc 100644 --- a/rtl/core/neorv32_xbus.vhd +++ b/rtl/core/neorv32_xbus.vhd @@ -58,7 +58,7 @@ begin -- Configuration Info --------------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- assert not (TIMEOUT_VAL = 0) report - "[NEORV32] External Bus Interface (XBUS) - NO auto-timeout defined; can cause permanent CPU stall!" severity warning; + "[NEORV32] External Bus Interface (XBUS): NO auto-timeout defined - can cause permanent CPU stall!" severity warning; -- Register Stage ------------------------------------------------------------------------- @@ -72,10 +72,10 @@ begin bus_rsp_o <= rsp_terminate_c; elsif rising_edge(clk_i) then -- request -- - if (bus_req_i.stb = '1') then -- keep all signals stable... + if (bus_req_i.stb = '1') then -- keep all signals stable ... bus_req <= bus_req_i; end if; - bus_req.stb <= bus_req_i.stb; -- ...except for STB that is single-shot + bus_req.stb <= bus_req_i.stb; -- ... except for STB that is single-shot -- response -- bus_rsp_o <= bus_rsp; end if; @@ -94,18 +94,18 @@ begin arbiter: process(rstn_i, clk_i) begin if (rstn_i = '0') then - pending <= '0'; timeout_cnt <= (others => '0'); + pending <= '0'; bus_rw <= '0'; elsif rising_edge(clk_i) then if (pending = '0') then -- idle, waiting for request - pending <= bus_req.stb; timeout_cnt <= std_ulogic_vector(to_unsigned(TIMEOUT_VAL, index_size_f(TIMEOUT_VAL)+1)); + pending <= bus_req.stb; else -- busy, transfer in progress + timeout_cnt <= std_ulogic_vector(unsigned(timeout_cnt) - 1); if (xbus_ack_i = '1') or (xbus_err_i = '1') or (timeout = '1') then pending <= '0'; end if; - timeout_cnt <= std_ulogic_vector(unsigned(timeout_cnt) - 1); end if; bus_rw <= bus_req.rw; end if; diff --git a/sw/bootloader/bootloader.c b/sw/bootloader/bootloader.c index 47bf73597..5da038696 100644 --- a/sw/bootloader/bootloader.c +++ b/sw/bootloader/bootloader.c @@ -1,50 +1,23 @@ -// ################################################################################################# -// # << NEORV32 - Bootloader >> # -// # ********************************************************************************************* # -// # BSD 3-Clause License # -// # # -// # Copyright (c) 2024, Stephan Nolting. All rights reserved. # -// # # -// # Redistribution and use in source and binary forms, with or without modification, are # -// # permitted provided that the following conditions are met: # -// # # -// # 1. Redistributions of source code must retain the above copyright notice, this list of # -// # conditions and the following disclaimer. # -// # # -// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # -// # conditions and the following disclaimer in the documentation and/or other materials # -// # provided with the distribution. # -// # # -// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # -// # endorse or promote products derived from this software without specific prior written # -// # permission. # -// # # -// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # -// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # -// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # -// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # -// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # -// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # -// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # -// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # -// # OF THE POSSIBILITY OF SUCH DAMAGE. # -// # ********************************************************************************************* # -// # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # -// ################################################################################################# - - -/**********************************************************************//** +// ================================================================================ // +// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 // +// Copyright (c) NEORV32 contributors. // +// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. // +// Licensed under the BSD-3-Clause license, see LICENSE for details. // +// SPDX-License-Identifier: BSD-3-Clause // +// ================================================================================ // + +/** * @file bootloader.c * @author Stephan Nolting * @brief Default NEORV32 bootloader. - **************************************************************************/ + */ #include #include /**********************************************************************//** - * @name Bootloader configuration (override via console to customize) + * @name Bootloader configuration (override via console to customize); * default values are used if not explicitly customized **************************************************************************/ /**@{*/ @@ -89,7 +62,7 @@ /** Time until the auto-boot sequence starts (in seconds); 0 = disabled */ #ifndef AUTO_BOOT_TIMEOUT - #define AUTO_BOOT_TIMEOUT 8 + #define AUTO_BOOT_TIMEOUT 10 #endif /* -------- SPI configuration -------- */ @@ -568,9 +541,9 @@ void get_exe(int src) { } #if (SPI_EN != 0) else { - PRINT_TEXT("Loading (@"); + PRINT_TEXT("Loading from SPI flash @"); PRINT_XNUM(addr); - PRINT_TEXT(")...\n"); + PRINT_TEXT("...\n"); // flash checks if (((NEORV32_SYSINFO->SOC & (1<> # */ -/* # ********************************************************************************************* # */ -/* # BSD 3-Clause License # */ -/* # # */ -/* # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 # */ -/* # Copyright (c) 2024, Stephan Nolting. All rights reserved. # */ -/* # # */ -/* # Redistribution and use in source and binary forms, with or without modification, are # */ -/* # permitted provided that the following conditions are met: # */ -/* # # */ -/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */ -/* # conditions and the following disclaimer. # */ -/* # # */ -/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */ -/* # conditions and the following disclaimer in the documentation and/or other materials # */ -/* # provided with the distribution. # */ -/* # # */ -/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */ -/* # endorse or promote products derived from this software without specific prior written # */ -/* # permission. # */ -/* # # */ -/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */ -/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */ -/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */ -/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */ -/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */ -/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */ -/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */ -/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */ -/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */ -/* ################################################################################################# */ +// ================================================================================ // +// NEORV32 CPU - crt0.S Start-Up Code // +// -------------------------------------------------------------------------------- // +// The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 // +// Copyright (c) NEORV32 contributors. // +// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. // +// Licensed under the BSD-3-Clause license, see LICENSE for details. // +// SPDX-License-Identifier: BSD-3-Clause // +// ================================================================================ // .file "crt0.S" .section .text.crt0 diff --git a/sw/common/neorv32.ld b/sw/common/neorv32.ld index d33aaed50..d234b66b5 100644 --- a/sw/common/neorv32.ld +++ b/sw/common/neorv32.ld @@ -1,35 +1,12 @@ -/* ################################################################################################# */ -/* # << NEORV32 - RISC-V GCC Linker Script >> # */ -/* # ********************************************************************************************* # */ -/* # BSD 3-Clause License # */ -/* # # */ -/* # The NEORV32 RISC-V Processor, https://github.com/stnolting/neorv32 # */ -/* # Copyright (c) 2024, Stephan Nolting. All rights reserved. # */ -/* # # */ -/* # Redistribution and use in source and binary forms, with or without modification, are # */ -/* # permitted provided that the following conditions are met: # */ -/* # # */ -/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */ -/* # conditions and the following disclaimer. # */ -/* # # */ -/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */ -/* # conditions and the following disclaimer in the documentation and/or other materials # */ -/* # provided with the distribution. # */ -/* # # */ -/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */ -/* # endorse or promote products derived from this software without specific prior written # */ -/* # permission. # */ -/* # # */ -/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */ -/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */ -/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */ -/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */ -/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */ -/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */ -/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */ -/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */ -/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */ -/* ################################################################################################# */ +/* ================================================================================ */ +/* NEORV32 CPU - RISC-V GCC Linker Script */ +/* -------------------------------------------------------------------------------- */ +/* The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 */ +/* Copyright (c) NEORV32 contributors. */ +/* Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. */ +/* Licensed under the BSD-3-Clause license, see LICENSE for details. */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* ================================================================================ */ /* Copyright (C) 2014-2020 Free Software Foundation, Inc. * Copying and distribution of this script, with or without modification, diff --git a/sw/image_gen/uart_upload.sh b/sw/image_gen/uart_upload.sh index d41a0464a..877f8065f 100644 --- a/sw/image_gen/uart_upload.sh +++ b/sw/image_gen/uart_upload.sh @@ -10,7 +10,7 @@ then printf "Reset processor before starting the upload.\n\n" printf "Usage: sh uart_upload.sh \n" printf "Example: sh uart_upload.sh /dev/ttyS6 path/to/project/neorv32_exe.bin\n" - exit + exit 0 fi # configure serial port @@ -20,12 +20,12 @@ stty -F "$1" 19200 -hup raw -echo -echoe -echok -echoctl -echoke -ixon cs8 -csto printf " " > $1 # send any char that triggers no command # execute upload command and get response -exec 3<$1 # redirect serial output to fd 3 - cat <&3 > uart_upload.response.tmp & # redirect serial output to file - PID=$! # save pid to kill cat - printf "u" > $1 # send upload command to serial port - sleep 0.5s # wait for bootloader response - kill $PID # kill cat process +exec 3<$1 # redirect serial output to fd 3 +cat <&3 > uart_upload.response.tmp & # redirect serial output to file +PID=$! # save pid to kill cat later +printf "u" > $1 # send upload command to serial port +sleep 0.5s # wait for bootloader response +kill $PID # kill cat process exec 3<&- # free fd 3 @@ -35,17 +35,17 @@ then printf "Bootloader response error!\n" printf "Reset processor before starting the upload.\n" rm -f uart_upload.response.tmp - exit + exit 1 fi # send executable and get response printf "Uploading executable..." -exec 3<$1 # redirect serial output to fd 3 - cat <&3 > uart_upload.response.tmp & # redirect serial output to file - PID=$! # save pid to kill cat - cat "$2" > "$1" # send executable to serial port - sleep 3s # wait for bootloader response - kill $PID # kill cat process +exec 3<$1 # redirect serial output to fd 3 +cat <&3 > uart_upload.response.tmp & # redirect serial output to file +PID=$! # save pid to kill cat later +cat "$2" > "$1" # send executable to serial port +sleep 3s # wait for bootloader response +kill $PID # kill cat process exec 3<&- # free fd 3 @@ -53,11 +53,12 @@ exec 3<&- # free fd 3 if ! grep -Fq "OK" uart_upload.response.tmp; then printf " FAILED!\n" + rm -f uart_upload.response.tmp + exit 1 else printf " OK\n" echo "Starting application..." printf "e" > $1 + rm -f uart_upload.response.tmp + exit 0 fi - -rm -f uart_upload.response.tmp -exit