⚠️ Rework physical memory protection (PMP) [NAPOT -> TOR] #281
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comment/description and default value (now 4 bytes)
use a single PMP entry instead
replaced PMP's NAPOT mode by TOR mode (easier to use, much more flexible); CSR read access logic optimization/clean-up
stnolting
added
the
risc-v compliance
* rework PMP * replace PMP NAPOT mode by TOR mode * remove BUSKEEPER's NULL pointer check (access to address zero)
stnolting
changed the title
limiting the maximum amount of PMP regions to 16
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This PR is a complete rework of the CPU's Physical Memory Protection (PMP).
The optional physical memory protection allows to define access rights (read/write/execute) for custom memory regions. By default, all PMP rules only apply to user-mode but can also be enforced for machine-mode.
The pre-PR PMP only provided "NAPOT" mode, where protected memory regions had to be a naturally aligned power of two. This PR removes the NAPOT mode and replaces it by the "TOR" mode (top of region), which is a base and bound scheme that is easier to handle (and easier to understand).
The NEORV32 PMP (and the TOR mode) is compatible to the RISC-V privileged architecture specifications section 3.7.
✨ This PR adds a new demo program to illustrate PMP usage (
sw/example/demo_pmp).