SystemVerilog Generate Construct

[subbdue]

Please use this Discussions thread for questions and comments on the article SystemVerilog Generate Construct

[PietroFavalesi]

Hello,
I do not understand why we can control the assignment inside the generate with a signal. Isn't the generate only executed during elaboration time? Does it even mean anything the value of a signal during elaboration time?
Thank you for your time

[jigarsavla]

What will be generated in the final RTL will be 16 muxes with the i being a constant and the select as an input signal. In the form:

assign temp[0] = (select == 0) ? mux_in[0] : 0;
assign temp[1] = (select == 1) ? mux_in[1] : 0;
...
assign temp[15] = (select == 15) ? mux_in[15] : 0;

Hope this helps!

[sai974]

in the crc example why is the dfault crc different from the crc when the crc_sel is 0. since the default value of parameter is set at 0. I think there is no way to get the defualt crc. Or do we need to set the crc_sel to 2 for that?