Skip to content
Branch: master
Find file History
Fetching latest commit…
Cannot retrieve the latest commit at this time.
Type Name Latest commit message Commit time
Failed to load latest commit information.


SystemVerilog Generate Construct

Run instructions

Example 1: 16 input mux

This is a simple example. Compile and simulate like you usually would with your simulator of choice

vcs -sverilog -full64

Example 2.1: conditional generate

Related file is There's no sample TB for this example, it mainly meant for demonstration purposes. The code itself compiles though. Feel free to write a TB around it and experiment with the code.

Example 2.1: crc polynomial select

Related files are, and Makefile.

The Makefile is setup to run with Synopsys VCS. To run this example:

make run   -> Run without waves
make waves -> Dump waves if using Synopsys VCS
make clean -> Delete logs and working dirs
You can’t perform that action at this time.