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SystemVerilog Randomization & Random Number Generation


Commands to run examples

Run instructions:

This code has been run with Synopsys VCS and with Mentor Graphics Questa Sim. General format

./ +define+<example_number> +SEED=<seed>
./ +define+<example_number> +SEED=<seed>

For example:

./ +define+EX_1_1 +SEED=20
./ +define+EX_1_1 +SEED=20

ARG1 (Required): +define+<example_number>

The <example_number> argument corresponds to the example number in the article. So, to run example 1.2 you have to pass the command line arg +define+EX_1_2

ARG2 (Optional): +SEED=<seed>

This is an optional argument, use it if the example involves using it.

Commands to run example 1:

(use instead of to run with Mentor simulator):

example 1.1: ./ +define+EX_1_1 
example 1.2: ./ +define+EX_1_2
example 1.3: ./ +define+EX_1_3
example 1.4: ./ +define+EX_1_4
example 1.5A:./ +define+EX_1_5A +SEED=20
example 1.5B:./ +define+EX_1_5B +SEED=20

Commands to run example 2:

example 2.1: ./ +define+EX_2_1
example 2.2: ./ +define+EX_2_2 +SEED=20

Commands to run example 3:

example 3.1: ./ +define+EX_3_1
example 3.2: ./ +define+EX_3_2
example 3.3: ./ +define+EX_3_3
example 3.4: ./ +define+EX_3_4
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