We created QNICE-FPGA as a portable System-on-a-Chip, so that it should be possible to synthesize it for any suitably powerful FPGA board.
This folder contains the FPGA vendor specific and board (hardware instance) specific files necessary to synthesize the QNICE-FPGA bitstream. Currently we are supporting these vendor/board/toolchain combinations:
- Xilinx: Nexys4 DDR and Nexys A7 using Vivado or ISE
- Xilinx: MEGA65 using Vivado or ISE
Scroll down to the respective section to learn more about a particular supported combination. And if your hardware is not included here, please read on at the section "General advice for porting", which is at the very bottom of this README.md.
The structure of this folder is:
<fpga-vendor>/<board (hardware)>/<toolchain (IDE)>
Additionally there are hardware specific VHDL files in
Nexys 4 DDR and Nexys A7
Currently, our reference development board is a Nexys 4 DDR, which has been retired by Nexys but you can still get it on eBay. As far as we know, the sucessor Nexys A7 is compatible, so we currently assume, that you can use the Nexys 4 DDR files to also synthesize for the Nexys A7.
The top file for this platform is vhdl/hw/nexys4ddr/env1.vhd.
We created the original QNICE-FPGA using
Xilinx' ISE 14.7.
The free ISE WebPACK license is sufficient for working with QNICE-FPGA.
Open the project
hw/xilinx/nexys4ddr/ISE/env1.xise to synthesize using ISE.
Vivado 2019.2 (or newer)
Vivado is the successor of ISE. Even though ISE can still be downloaded for
free from Xilinx as the time of writing, Vivado is the way to go when developing
for Xilinx FPGAs. So we made a port of QNICE-FPGA to Vivado, which you can
download here; we recommend
to use the "HLx Editions" with the free Vivado WebPACK license.
Open the project
to synthesize using Vivado.
The MEGA65 is the 21st century realization of the Commodore 65 heritage: A complete 8-bit computer running around 50x faster than a C64 while being highly compatible. Go to mega65.org to learn more about it.
The MEGA65 is an open source / open hardware project available
here on GitHub. It supports multiple so called
"Cores", which means that you can upload your own hardware to MEGA65's FPGA,
which is a Xilinx Artix-7 in a
Hint: ISE or Vivado bitstreams (
.bit files) need to be converted into
MEGA65 Cores (
.cor files) by using the
tools/bit2core tool. The bitstream
needs to be in a specific format as described here
to work as a Core on the MEGA65.
For a quickstart, you can download the ready-made QNICE-FPGA Core for MEGA65 here. If you want to use the MEGA65 as a Q-TRIS Arcade machine, then download this Core. Have a look at doc/README.md to learn how to install and run the QNICE-FPGA core on the MEGA65.
Use the project
hw/xilinx/MEGA65/ISE/QNICE-MEGA65.xise to synthesize
for MEGA65 using ISE. The bitstream format is already configured to be
compatible with MEGA65 Cores. Right-click "Generate Programming File" in
ISE's process view and choose "Process Properties" to learn more.
The top file for MEGA65 using ISE is vhdl/hw/MEGA65/MEGA65_ISE.vhd.
Currently, HyperRAM is deactivated when synthesizing with ISE. Please have a look at doc/constraints.txt to learn more.
Vivado 2019.2 (or newer)
Use the project
hw/xilinx/MEGA65/Vivado/MEGA65.xpr to synthesize for MEGA65
using Vivado. The bitstream format is already configured to be compatible
with MEGA65 Cores. Look at the
XDC file, section
"## Configuration and Bitstream properties" to learn more.
The top file for MEGA65 using Vivado is vhdl/hw/MEGA65/MEGA65_Vivado.vhd.
MEGA65 board revisions and hardware versions
For the QNICE @ MEGA65 release at hand, we used the very first MEGA65 prototype computer, which has the board revision 2 (MEGA65R2). There where only a couple of those prototypes produced, so you will probably have a newer board revision: The first publicly available MEGA65 computer will be the MEGA65 DevKit with board revision 3 (MEGA65R3). And the final product for the market might have an even higher board revision.
For learning more about how QNICE-FPGA supports the different MEGA65 hardware versions, have a look at doc/README.md.
General advice for porting
In general, the code is written in a portable way and therefore is suitable as a good starting point for porting the QNICE-FPGA implementation for Digilent's Xilinx Virtex-7 based board "Nexys4 DDR": Create two new folders according to the folder structure mentioned above. Copy this top file into your own folder:
vhdl/hw/nexys4ddr/env1.vhd. You might want to rename it to match your hardware's or port's name. Start modifying this top file to fit your needs.
If you are not on Xilinx hardware, then the first thing you might want to do is to comment out everything related to the Xilinx
MMCMEbased generation of the 25.175 MHz VGA pixelclock in
env1.vhd. Even though the 25.175 MHz pixelclock generates a better and sharper image on most displays, the 25 MHz version is also absolutely OK and it is more portable, as it only relies on a simple clock divider to generate the pixelclock. So you might want to comment out the
UNISIMlibrary and the
MMCMEinstantiation that generates the signal
clk25MHzand comment in the clock divider process
generate_clk25MHz : process(SLOW_CLOCK)instead. Do not forget to set appropriate timing constraints for the clock in the IDE or development environment of your choice;
env1.ucfmight be an inspiration.
In the file
hw/xilinx/nexys4ddr/ISE/env1.ucfyou will find advice about how to do the mapping from the NETs to the hardware's pins and what kind of timing constraints you might want to use.
Make sure that you connect at least the IO pins for PS2, VGA, UART and the two switches (
The system is designed to run at 50 MHz. Other speeds would break various timings (see also TODO.txt to learn more).
env1expects to receive a 100 MHz clock, which it then divides down to the 50 MHz clock
EAE's combinatorial division networks take longer than the regular 50 MHz clock period, so be sure to specify a timing constraint for your specific hardware/toolchain combination.
hw/xilinx/nexys4ddr/ISE/env1.ucfcan be used as an inspiration.
env1_globals.vhdcontains several important global constants. You can for example define the content of the ROM there by changing
ROM_FILE. One application for this is to transform QNICE-FPGA into a "Q-TRIS Arcade Machine" by using
demos/q-tris.romcompiled with the define
QTRIS_STANDALONE. Another one might be to replace the "operating system" that we call "Monitor" (
monitor/monitor.rom) by something else. You can also use
env1_globals.vhdto reduce the amount of registers (the size of the register file) by changing
SHADOW_REGFILE_SIZE. But be aware that some QNICE programs may fail as the QNICE ISA demands the amount of shadow registers to be 256.