Support CSR_INSTRETH for insn counter high bits #624
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This completes the CSR performance counter implementation by adding the missing CSR_INSTRETH handler. This register provides access to the upper 32 bits of the retired instruction counter, maintaining symmetry with CSR_CYCLEH.
![cubic-dev-ai[bot]](https://avatars.githubusercontent.com/in/1082092?s=60&v=4){kind=small}
jserv
commented
Oct 20, 2025
Contributor
Author
jserv
left a comment
jserv
left a comment
There was a problem hiding this comment.
Benchmarks
| Benchmark suite | Current: 0fcee70 | Previous: 9074319 | Ratio |
|---|---|---|---|
Dhrystone |
1325 Average DMIPS over 10 runs |
1342 Average DMIPS over 10 runs |
1.01 |
Coremark |
965.132 Average iterations/sec over 10 runs |
961.709 Average iterations/sec over 10 runs |
1.00 |
This comment was automatically generated by workflow using github-action-benchmark.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This completes the CSR performance counter implementation by adding the missing CSR_INSTRETH handler. This register provides access to the upper 32 bits of the retired instruction counter, maintaining symmetry with CSR_CYCLEH.
Summary by cubic
Add CSR_INSTRETH support to read the high 32 bits of the retired instruction counter (instret). This mirrors CSR_CYCLEH and completes the CSR performance counter implementation.