From 0fcee7091b71914a7b001a8262abf342ea710ff8 Mon Sep 17 00:00:00 2001 From: Jim Huang Date: Tue, 21 Oct 2025 01:48:02 +0800 Subject: [PATCH] Support CSR_INSTRETH for insn counter high bits This completes the CSR performance counter implementation by adding the missing CSR_INSTRETH handler. This register provides access to the upper 32 bits of the retired instruction counter, maintaining symmetry with CSR_CYCLEH. --- src/emulate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/emulate.c b/src/emulate.c index 58585f8a..c1f42c41 100644 --- a/src/emulate.c +++ b/src/emulate.c @@ -131,6 +131,8 @@ static uint32_t *csr_get_ptr(riscv_t *rv, uint32_t csr) return &rv->csr_time[1]; case CSR_INSTRET: /* Number of Instructions Retired Counter */ return (uint32_t *) (&rv->csr_cycle); + case CSR_INSTRETH: /* Upper 32 bits of instructions retired */ + return &((uint32_t *) &rv->csr_cycle)[1]; #if RV32_HAS(EXT_F) case CSR_FFLAGS: return (uint32_t *) (&rv->csr_fcsr);