Reduce timer checking overhead with lazy evaluation

[jserv]

This reduces CPU overhead from timer interrupt checking by implementing:

1. Lazy timer checking: Cache next_interrupt_at (earliest interrupt time across all harts) to skip expensive checks when no interrupt is due.
2. Event-driven wait: Replace fixed 1ms periodic timer with dynamic one-shot timers (kqueue on macOS, timerfd on Linux) that wake exactly when next interrupt is due.

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Summary by cubic

Cuts CPU usage from timer checks by caching the next scheduled interrupt and switching from a 1ms polling timer to event-driven one-shot timers (with a 1ms fallback during boot). Improves idle performance without changing observable behavior.

• New Features

  • Cache next_interrupt_at (min mtimecmp across harts) in mtimer_state_t; added n_harts.
  • New helper aclint_mtimer_recalc_next_interrupt; called on mtimecmp writes, SBI set_timer, and after interrupts.
  • Lazy timer check in emu_update_timer_interrupt: skip work if time < next_interrupt_at; still sync hart->time.
  • Event-driven wait in semu_run: compute wait_ns (capped at 100ms) and arm one-shot timer (kqueue NOTE_USECONDS on macOS, timerfd on Linux); during boot, use a fixed 1ms timeout to avoid fake-timer vs wall-clock mismatch.

• Bug Fixes

  • Overflow-safe wait_ns calculation and UINT64_MAX handling to prevent zero-wait loops when the timer is disabled or far in the future.

^{Written for commit 90aa27d. Summary will update automatically on new commits.}

[jserv]

Closing this PR due to architectural incompatibility with the current master branch.

Analysis

After merging PR #110 (event-driven UART coroutine), the master branch has fundamentally changed from a polling-based architecture to a coroutine-based architecture. The refine-timer branch optimization was designed for the old polling architecture and cannot be directly rebased onto the new architecture.

Key Findings

1. Architectural conflict: The timer optimization in refine-timer assumes synchronous polling loops, while master now uses asynchronous coroutine scheduling
2. SMP=4 regression: Testing revealed that master branch currently has a regression where SMP=4 hangs during boot at "smp: Bringing up secondary CPUs ..." (likely introduced by PR Implement event-driven UART coroutine with CPU optimization #110)
3. refine-timer works correctly: The refine-timer branch itself has working SMP=4 support and boots successfully