vsi_hw: INFO: [DRC 23-27] Running DRC with 4 threads vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_GEN.DSP48E1_DEL/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_GEN.DSP48E1_DEL/DSP/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_GEN.DSP48E1_DEL/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_GEN.DSP48E1_DEL/DSP/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_GEN.DSP48E1_DEL/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_GEN.DSP48E1_DEL/DSP/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_GEN.DSP48E1_DEL/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_GEN.DSP48E1_DEL/DSP/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP2/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP2/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP2/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP2/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPIP-2] Input pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP input u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/min_max/inst/min_max_shmem_am_cud_U1/min_max_shmem_am_cud_DSP48_0_U/m output u96_pl_i/u96_pl/min_max/inst/min_max_shmem_am_cud_U1/min_max_shmem_am_cud_DSP48_0_U/m/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP/CARRYOUT[3:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP/PATTERNDETECT is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP/CARRYOUT[3:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP output u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/mul_ln715_fu_500_p2 output u96_pl_i/u96_pl/speedometer/inst/mul_ln715_fu_500_p2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/mul_ln715_fu_500_p2__0 output u96_pl_i/u96_pl/speedometer/inst/mul_ln715_fu_500_p2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-3] PREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/mul_ln715_fu_500_p2__1 output u96_pl_i/u96_pl/speedometer/inst/mul_ln715_fu_500_p2__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/min_max/inst/min_max_shmem_am_cud_U1/min_max_shmem_am_cud_DSP48_0_U/m multiplier stage u96_pl_i/u96_pl/min_max/inst/min_max_shmem_am_cud_U1/min_max_shmem_am_cud_DSP48_0_U/m/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP2/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP2/DSP/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP5/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP5/DSP/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP2/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP2/DSP/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP/PATTERNDETECT is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP5/DSP multiplier stage u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP5/DSP/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/mul_ln715_fu_500_p2 multiplier stage u96_pl_i/u96_pl/speedometer/inst/mul_ln715_fu_500_p2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/mul_ln715_fu_500_p2__0 multiplier stage u96_pl_i/u96_pl/speedometer/inst/mul_ln715_fu_500_p2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC DPOP-4] MREG Output pipelining: DSP u96_pl_i/u96_pl/speedometer/inst/mul_ln715_fu_500_p2__1 multiplier stage u96_pl_i/u96_pl/speedometer/inst/mul_ln715_fu_500_p2__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. vsi_hw: WARNING: [DRC RTSTAT-10] No routable loads: 258 net(s) have no routable loads. The problem bus(es) and/or net(s) are u96_pl_i/u96_pl/s2mm_min_max_done/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/p_u96_pl/vsi_common_interface_0/inst/axi_interconnect_0/m01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/p_u96_pl/vsi_common_interface_0/inst/axi_interconnect_0/m01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/p_u96_pl/vsi_common_interface_0/inst/axi_interconnect_0/m01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/p_u96_pl/vsi_common_interface_0/inst/axi_interconnect_0/m01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/p_u96_pl/vsi_common_interface_0/inst/axi_interconnect_0/m01_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/u96_pl/mm2s_min_max_start/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/u96_pl/mm2s_speedometer_start/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/u96_pl/mm2s_min_max_start/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/u96_pl/s2mm_min_max_done/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/u96_pl/mm2s_speedometer_start/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/u96_pl/s2mm_speedometer_done/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/u96_pl/s2mm_speedometer_done/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/p_u96_pl/vsi_common_interface_0/inst/input_interconnect/axi_interconnect_5/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, u96_pl_i/p_u96_pl/vsi_common_interface_0/inst/input_interconnect/axi_interconnect_5/s00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i... and (the first 15 of 166 listed). vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_GEN.DSP48E1_DEL/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_GEN.DSP48E1_DEL/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP2/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP5/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP0/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP1/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP2/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP3/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP4/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/DSP5/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-155] enum_AMULTSEL_BMULTSEL_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP: DSP48E2 is not using the D port (AMULTSEL = A and BMULTSEL = B). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_GEN.DSP48E1_DEL/DSP: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U1/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_ADD.DSP48E1_ADD/DSP: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/ALIGN_BLK/FRAC_ADDSUB/DSP_ADD.FRAC_ADDSUB/DSP48E1_GEN.DSP48E1_DEL/DSP: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_dEe_U2/draw_speedometer_ap_dadd_3_full_dsp_64_u/U0/i_synth/ADDSUB_OP.ADDSUB/LOGIC_SPEED.OP/NORM/ROUND/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U3/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.MULT/DSP48E2_SPD_DBL_VARIANT.FIX_MULT/FULL_MAX_USAGE.DSP_SIMD/DSP: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC AVAL-156] enum_USE_MULT_NONE__enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: u96_pl_i/u96_pl/speedometer/inst/draw_speedometer_eOg_U4/draw_speedometer_ap_dmul_3_max_dsp_64_u/U0/i_synth/MULT.OP/i_non_prim.R_AND_R/LOGIC.R_AND_R/DSP48_E1.DSP48E1_ADD.DSP48E1_ADD/DSP: DSP48E2 is not using the Multiplier (USE_MULT = NONE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. vsi_hw: INFO: [DRC REQP-1857] RAMB18E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/mm2s_min_max_start/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [DRC REQP-1857] RAMB18E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/mm2s_min_max_start/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [DRC REQP-1857] RAMB18E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/mm2s_speedometer_start/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [DRC REQP-1857] RAMB18E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/mm2s_speedometer_start/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [DRC REQP-1857] RAMB18E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/s2mm_min_max_done/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [DRC REQP-1857] RAMB18E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/s2mm_min_max_done/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [DRC REQP-1857] RAMB18E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/s2mm_speedometer_done/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [DRC REQP-1857] RAMB18E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/s2mm_speedometer_done/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [DRC REQP-1858] RAMB36E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/mm2s_min_max_start/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [DRC REQP-1858] RAMB36E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/mm2s_speedometer_start/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [DRC REQP-1858] RAMB36E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/mm2s_speedometer_start/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [DRC REQP-1858] RAMB36E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/s2mm_min_max_done/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [DRC REQP-1858] RAMB36E2_writefirst_collision_advisory: Synchronous clocking is detected for BRAM (u96_pl_i/u96_pl/s2mm_speedometer_done/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram) in SDP mode with WRITE_FIRST write-mode. It is strongly suggested to change this mode to NO_CHANGE for best power characteristics. However, both WRITE_FIRST and NO_CHANGE may exhibit address collisions if the same address appears on both read and write ports resulting in unknown or corrupted read data. It is suggested to confirm via simulation that an address collision never occurs and if so it is suggested to try and avoid this situation. If address collisions cannot be avoided, the write-mode may be set to READ_FIRST which guarantees that the read data is the prior contents of the memory at the cost of additional power in the design. See the FPGA Memory Resources User Guide for additional information. vsi_hw: INFO: [Vivado 12-3199] DRC finished with 0 Errors, 79 Warnings, 45 Advisories