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Swapped system_stm32f0xx.c for the one that come with the Discovery f…

…irmware
1 parent ba31e7b commit 55b8810f035871336b7427f70b7249f12c3f3b5d Mike Szczys committed Jun 29, 2012
Showing with 60 additions and 29 deletions.
  1. +60 −29 src/system_stm32f0xx.c
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@@ -6,14 +6,24 @@
* @date 23-March-2012
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F0xx devices,
- * and is generated by the clock configuration tool
- * STM32F0xx_Clock_Configuration_V1.0.0.xls
+ * and is customized for use with STM32F0-DISCOVERY Kit.
+ * The STM32F0xx is configured to run at 48 MHz, following the three
+ * configuration below:
+ * - PLL_SOURCE_HSI (default): HSI (~8MHz) used to clock the PLL, and
+ * the PLL is used as system clock source.
+ * - PLL_SOURCE_HSE : HSE (8MHz) used to clock the PLL, and
+ * the PLL is used as system clock source.
+ * - PLL_SOURCE_HSE_BYPASS : HSE bypassed with an external clock
+ * (8MHz, coming from ST-Link) used to clock
+ * the PLL, and the PLL is used as system
+ * clock source.
*
+ *
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
- * depending on the configuration made in the clock xls tool.
+ * depending on the configuration selected (see above).
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f0xx.s" file.
@@ -39,31 +49,6 @@
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
- * 5. This file configures the system clock as follows:
- *=============================================================================
- * System Clock Configuration
- *=============================================================================
- * System Clock source | PLL(HSE)
- *-----------------------------------------------------------------------------
- * SYSCLK | 48000000 Hz
- *-----------------------------------------------------------------------------
- * HCLK | 48000000 Hz
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB2 Prescaler | 1
- *-----------------------------------------------------------------------------
- * HSE Frequency | 8000000 Hz
- *-----------------------------------------------------------------------------
- * PLL MUL | 6
- *-----------------------------------------------------------------------------
- * VDD | 3.3 V
- *-----------------------------------------------------------------------------
- * Flash Latency | 1 WS
- *-----------------------------------------------------------------------------
- *=============================================================================
******************************************************************************
* @attention
*
@@ -113,6 +98,13 @@
/** @addtogroup STM32F0xx_System_Private_Defines
* @{
*/
+/* Select the PLL clock source */
+
+#define PLL_SOURCE_HSI // HSI (~8MHz) used to clock the PLL, and the PLL is used as system clock source
+//#define PLL_SOURCE_HSE // HSE (8MHz) used to clock the PLL, and the PLL is used as system clock source
+//#define PLL_SOURCE_HSE_BYPASS // HSE bypassed with an external clock (8MHz, coming from ST-Link) used to clock
+ // the PLL, and the PLL is used as system clock source
+
/**
* @}
*/
@@ -281,9 +273,47 @@ static void SetSysClock(void)
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
+#if defined (PLL_SOURCE_HSI)
+ /* At this stage the HSI is already enabled */
+
+ /* Enable Prefetch Buffer and set Flash Latency */
+ FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
+
+ /* PLL configuration = (HSI/2) * 12 = ~48 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12);
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+ {
+ }
+#else
+ #if defined (PLL_SOURCE_HSE)
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
+ #elif defined (PLL_SOURCE_HSE_BYPASS)
+ /* HSE oscillator bypassed with external clock */
+ RCC->CR |= (uint32_t)(RCC_CR_HSEON | RCC_CR_HSEBYP);
+ #endif /* PLL_SOURCE_HSE */
+
/* Wait till HSE is ready and if Time out is reached exit */
do
{
@@ -336,6 +366,7 @@ static void SetSysClock(void)
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
+#endif /* PLL_SOURCE_HSI */
}
/**

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