****************
Platform: X86 16bit (Intel syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	lea		cx, word ptr [si + 0x32]
0x1003:	or		byte ptr [bx + di], al
0x1005:	fadd		dword ptr [bx + di + 0x34c6]
0x1009:	adc		al, byte ptr [bx + si]
0x100b:

****************
Platform: X86 32bit (ATT syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	leal		8(%edx, %esi), %ecx
0x1004:	addl		%ebx, %eax
0x1006:	addl		$0x1234, %esi
0x100c:

****************
Platform: X86 32 (Intel syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	lea		ecx, dword ptr [edx + esi + 8]
0x1004:	add		eax, ebx
0x1006:	add		esi, 0x1234
0x100c:

****************
Platform: X86 64 (Intel syntax)
Code: 0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00 
Disasm:
0x1000:	push		rbp
0x1001:	mov		rax, qword ptr [rip + 0x13b8]
0x1008:

****************
Platform: ARM
Code: 0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 0xe5 0xf1 0x02 0x03 0x0e 0x00 0x00 0xa0 0xe3 0x02 0x30 0xc1 0xe7 0x00 0x00 0x53 0xe3 
Disasm:
0x1000:	bl		#0xfbc
0x1004:	str		lr, [sp, #-4]!
0x1008:	andeq		r0, r0, r0
0x100c:	str		r8, [r2, #-0x3e0]!
0x1010:	mcreq		p2, #0, r0, c3, c1, #7
0x1014:	mov		r0, #0
0x1018:	strb		r3, [r1, r2]
0x101c:	cmp		r3, #0
0x1020:

****************
Platform: THUMB-2
Code: 0x4f 0xf0 0x00 0x01 0xbd 0xe8 0x00 0x88 0xd1 0xe8 0x00 0xf0 
Disasm:
0x1000:	mov.w		r1, #0
0x1004:	pop.w		{fp, pc}
0x1008:	tbb		[r1, r0]
0x100c:

****************
Platform: ARM: Cortex-A15 + NEON
Code: 0x10 0xf1 0x10 0xe7 0x11 0xf2 0x31 0xe7 0xdc 0xa1 0x2e 0xf3 0xe8 0x4e 0x62 0xf3 
Disasm:
0x1000:	sdiv		r0, r0, r1
0x1004:	udiv		r1, r1, r2
0x1008:	vbit		q5, q15, q6
0x100c:	vcgt.f32		q10, q9, q12
0x1010:

****************
Platform: THUMB
Code: 0x70 0x47 0xeb 0x46 0x83 0xb0 0xc9 0x68 
Disasm:
0x1000:	bx		lr
0x1002:	mov		fp, sp
0x1004:	sub		sp, #0xc
0x1006:	ldr		r1, [r1, #0xc]
0x1008:

****************
Platform: Thumb-MClass
Code: 0xef 0xf3 0x02 0x80 
Disasm:
0x1000:	mrs		r0, eapsr
0x1004:

****************
Platform: Arm-V8
Code: 0xe0 0x3b 0xb2 0xee 0x42 0x00 0x01 0xe1 0x51 0xf0 0x7f 0xf5 
Disasm:
0x1000:	vcvtt.f64.f16		d3, s1
0x1004:	crc32b		r0, r1, r2
0x1008:	dmb		oshld
0x100c:

****************
Platform: MIPS-32 (Big-endian)
Code: 0x0c 0x10 0x00 0x97 0x00 0x00 0x00 0x00 0x24 0x02 0x00 0x0c 0x8f 0xa2 0x00 0x00 0x34 0x21 0x34 0x56 
Disasm:
0x1000:	lhu		$zero, 0x100c($t8)
0x1004:	nop		
0x1008:	jal		0x890
0x100c:	sync		0xa
0x1010:	bnel		$s1, $s4, 0x94e4
0x1014:

****************
Platform: MIPS-64-EL (Little-endian)
Code: 0x56 0x34 0x21 0x34 0xc2 0x17 0x01 0x00 
Disasm:
0x1000:	ori		$at, $at, 0x3456
0x1004:	srl		$v0, $at, 0x1f
0x1008:

****************
Platform: MIPS-32R6 | Micro (Big-endian)
****************
Platform: MIPS-32R6 | Micro (Big-endian)
Code: 0x00 0x07 0x00 0x07 0x00 0x11 0x93 0x7c 0x01 0x8c 0x8b 0x7c 0x00 0xc7 0x48 0xd0 
ERROR: Failed to disasm given code!

****************
Platform: MIPS-32R6 (Big-endian)
Code: 0xec 0x80 0x00 0x19 0x7c 0x43 0x22 0xa0 
Disasm:
0x1000:	blez		$t0, -0x1ec4c
0x1004:	sb		$v0, 0x437c($at)
0x1008:

****************
Platform: ARM-64
Code: 0x21 0x7c 0x02 0x9b 0x21 0x7c 0x00 0x53 0x00 0x40 0x21 0x4b 0xe1 0x0b 0x40 0xb9 
Disasm:
0x1000:	mul		x1, x1, x2
0x1004:	lsr		w1, w1, #0
0x1008:	sub		w0, w0, w1, uxtw
0x100c:	ldr		w1, [sp, #8]
0x1010:

****************
Platform: PPC-64
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 
Disasm:
0x1000:	lwz		r1, (0)
0x1004:	lwz		r1, (r31)
0x1008:	vpkpx		v2, v3, v4
0x100c:	stfs		f2, 0x80(r4)
0x1010:	crand		2, 3, 4
0x1014:	cmpwi		cr2, r3, 0x80
0x1018:	addc		r2, r3, r4
0x101c:	mulhd.		r2, r3, r4
0x1020:	bdnzlrl+		
0x1024:	bgelrl-		cr2
0x1028:

****************
Platform: PPC-64, print register with number only
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 
Disasm:
0x1000:	lwz		1, (0)
0x1004:	lwz		1, (31)
0x1008:	vpkpx		2, 3, 4
0x100c:	stfs		2, 0x80(4)
0x1010:	crand		2, 3, 4
0x1014:	cmpwi		2, 3, 0x80
0x1018:	addc		2, 3, 4
0x101c:	mulhd.		2, 3, 4
0x1020:	bdnzlrl+		
0x1024:	bgelrl-		cr2
0x1028:

****************
Platform: Sparc
Code: 0x80 0xa0 0x40 0x02 0x85 0xc2 0x60 0x08 0x85 0xe8 0x20 0x01 0x81 0xe8 0x00 0x00 0x90 0x10 0x20 0x01 0xd5 0xf6 0x10 0x16 0x21 0x00 0x00 0x0a 0x86 0x00 0x40 0x02 0x01 0x00 0x00 0x00 0x12 0xbf 0xff 0xff 0x10 0xbf 0xff 0xff 0xa0 0x02 0x00 0x09 0x0d 0xbf 0xff 0xff 0xd4 0x20 0x60 0x00 0xd4 0x4e 0x00 0x16 0x2a 0xc2 0x80 0x03 
Disasm:
0x1000:	cmp		%g1, %g2
0x1004:	jmpl		%o1+8, %g2
0x1008:	restore		%g0, 1, %g2
0x100c:	restore		
0x1010:	mov		1, %o0
0x1014:	casx		[%i0], %l6, %o2
0x1018:	sethi		0xa, %l0
0x101c:	add		%g1, %g2, %g3
0x1020:	nop		
0x1024:	bne		0x1020
0x1028:	ba		0x1024
0x102c:	add		%o0, %o1, %l0
0x1030:	fbg		0x102c
0x1034:	st		%o2, [%g1]
0x1038:	ldsb		[%i0+%l6], %o2
0x103c:	brnz,a,pn		%o2, 0x1048
0x1040:

****************
Platform: SparcV9
Code: 0x81 0xa8 0x0a 0x24 0x89 0xa0 0x10 0x20 0x89 0xa0 0x1a 0x60 0x89 0xa0 0x00 0xe0 
Disasm:
0x1000:	fcmps		%f0, %f4
0x1004:	fstox		%f0, %f4
0x1008:	fqtoi		%f0, %f4
0x100c:	fnegq		%f0, %f4
0x1010:

****************
Platform: SystemZ
Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 
Disasm:
0x1000:	adb		%f0, 0
0x1006:	a		%r0, 0xfff(%r15, %r1)
0x100a:	afi		%r0, -0x80000000
0x1010:	br		%r7
0x1012:	xiy		0x7ffff(%r15), 0x2a
0x1018:	xy		%r0, 0x7ffff(%r1, %r15)
0x101e:	stmg		%r0, %r0, 0(%r15)
0x1024:	ear		%r7, %a8
0x1028:

****************
Platform: XCore
Code: 0xfe 0x0f 0xfe 0x17 0x13 0x17 0xc6 0xfe 0xec 0x17 0x97 0xf8 0xec 0x4f 0x1f 0xfd 0xec 0x37 0x07 0xf2 0x45 0x5b 0xf9 0xfa 0x02 0x06 0x1b 0x10 
Disasm:
0x1000:	get		r11, ed
0x1002:	ldw		et, sp[4]
0x1004:	setd		res[r3], r4
0x1006:	init		t[r2]:lr, r1
0x100a:	divu		r9, r1, r3
0x100e:	lda16		r9, r3[-r11]
0x1012:	ldw		dp, dp[0x81c5]
0x1016:	lmul		r11, r0, r2, r5, r8, r10
0x101a:	add		r1, r2, r3
0x101c:

****************
Platform: ARM
Code:0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 0xe5 0xf1 0x02 0x03 0x0e 0x00 0x00 0xa0 0xe3 0x02 0x30 0xc1 0xe7 0x00 0x00 0x53 0xe3 0x00 0x02 0x01 0xf1 0x05 0x40 0xd0 0xe8 0xf4 0x80 0x00 0x00 
Disasm:
0x1000:	bl	#0xfbc
	op_count: 1
		operands[0].type: IMM = 0xfbc

0x1004:	str	lr, [sp, #-4]!
	op_count: 2
		operands[0].type: REG = lr
		operands[1].type: MEM
			operands[1].mem.base: REG = sp
			operands[1].mem.disp: 0xfffffffc
	Write-back: True

0x1008:	andeq	r0, r0, r0
	op_count: 3
		operands[0].type: REG = r0
		operands[1].type: REG = r0
		operands[2].type: REG = r0
	Code condition: 1

0x100c:	str	r8, [r2, #-0x3e0]!
	op_count: 2
		operands[0].type: REG = r8
		operands[1].type: MEM
			operands[1].mem.base: REG = r2
			operands[1].mem.disp: 0xfffffc20
	Write-back: True

0x1010:	mcreq	p2, #0, r0, c3, c1, #7
	op_count: 6
		operands[0].type: P-IMM = 2
		operands[1].type: IMM = 0x0
		operands[2].type: REG = r0
		operands[3].type: C-IMM = 3
		operands[4].type: C-IMM = 1
		operands[5].type: IMM = 0x7
	Code condition: 1

0x1014:	mov	r0, #0
	op_count: 2
		operands[0].type: REG = r0
		operands[1].type: IMM = 0x0

0x1018:	strb	r3, [r1, r2]
	op_count: 2
		operands[0].type: REG = r3
		operands[1].type: MEM
			operands[1].mem.base: REG = r1
			operands[1].mem.index: REG = r2

0x101c:	cmp	r3, #0
	op_count: 2
		operands[0].type: REG = r3
		operands[1].type: IMM = 0x0
	Update-flags: True

0x1020:	setend	be
	op_count: 1
		operands[0].type: SETEND = be

0x1024:	ldm	r0, {r0, r2, lr} ^
	op_count: 4
		operands[0].type: REG = r0
		operands[1].type: REG = r0
		operands[2].type: REG = r2
		operands[3].type: REG = lr
	User-mode: True

0x1028:	strdeq	r8, sb, [r0], -r4
	op_count: 4
		operands[0].type: REG = r8
		operands[1].type: REG = sb
		operands[2].type: MEM
			operands[2].mem.base: REG = r0
		operands[3].type: REG = r4
		Subtracted: True
	Code condition: 1
	Write-back: True

0x102c:

****************
Platform: Thumb
Code:0x70 0x47 0xeb 0x46 0x83 0xb0 0xc9 0x68 0x1f 0xb1 0x30 0xbf 0xaf 0xf3 0x20 0x84 
Disasm:
0x1000:	bx	lr
	op_count: 1
		operands[0].type: REG = lr

0x1002:	mov	fp, sp
	op_count: 2
		operands[0].type: REG = fp
		operands[1].type: REG = sp

0x1004:	sub	sp, #0xc
	op_count: 2
		operands[0].type: REG = sp
		operands[1].type: IMM = 0xc

0x1006:	ldr	r1, [r1, #0xc]
	op_count: 2
		operands[0].type: REG = r1
		operands[1].type: MEM
			operands[1].mem.base: REG = r1
			operands[1].mem.disp: 0xc

0x1008:	cbz	r7, #0x1012
	op_count: 2
		operands[0].type: REG = r7
		operands[1].type: IMM = 0x1012

0x100a:	wfi	

0x100c:	cpsie.w	f
	CPSI-mode: 2
	CPSI-flag: 1

0x1010:

****************
Platform: Thumb-mixed
Code:0xd1 0xe8 0x00 0xf0 0xf0 0x24 0x04 0x07 0x1f 0x3c 0xf2 0xc0 0x00 0x00 0x4f 0xf0 0x00 0x01 0x46 0x6c 
Disasm:
0x1000:	tbb	[r1, r0]
	op_count: 1
		operands[0].type: MEM
			operands[0].mem.base: REG = r1
			operands[0].mem.index: REG = r0

0x1004:	movs	r4, #0xf0
	op_count: 2
		operands[0].type: REG = r4
		operands[1].type: IMM = 0xf0
	Update-flags: True

0x1006:	lsls	r4, r0, #0x1c
	op_count: 3
		operands[0].type: REG = r4
		operands[1].type: REG = r0
		operands[2].type: IMM = 0x1c
	Update-flags: True

0x1008:	subs	r4, #0x1f
	op_count: 2
		operands[0].type: REG = r4
		operands[1].type: IMM = 0x1f
	Update-flags: True

0x100a:	stm	r0!, {r1, r4, r5, r6, r7}
	op_count: 6
		operands[0].type: REG = r0
		operands[1].type: REG = r1
		operands[2].type: REG = r4
		operands[3].type: REG = r5
		operands[4].type: REG = r6
		operands[5].type: REG = r7
	Write-back: True

0x100c:	movs	r0, r0
	op_count: 2
		operands[0].type: REG = r0
		operands[1].type: REG = r0
	Update-flags: True

0x100e:	mov.w	r1, #0
	op_count: 2
		operands[0].type: REG = r1
		operands[1].type: IMM = 0x0

0x1012:	ldr	r6, [r0, #0x44]
	op_count: 2
		operands[0].type: REG = r6
		operands[1].type: MEM
			operands[1].mem.base: REG = r0
			operands[1].mem.disp: 0x44

0x1014:

****************
Platform: Thumb-2 & register named with numbers
Code:0x4f 0xf0 0x00 0x01 0xbd 0xe8 0x00 0x88 0xd1 0xe8 0x00 0xf0 0x18 0xbf 0xad 0xbf 0xf3 0xff 0x0b 0x0c 0x86 0xf3 0x00 0x89 0x80 0xf3 0x00 0x8c 0x4f 0xfa 0x99 0xf6 0xd0 0xff 0xa2 0x01 
Disasm:
0x1000:	mov.w	r1, #0
	op_count: 2
		operands[0].type: REG = r1
		operands[1].type: IMM = 0x0

0x1004:	pop.w	{r11, pc}
	op_count: 2
		operands[0].type: REG = r11
		operands[1].type: REG = pc

0x1008:	tbb	[r1, r0]
	op_count: 1
		operands[0].type: MEM
			operands[0].mem.base: REG = r1
			operands[0].mem.index: REG = r0

0x100c:	it	ne
	Code condition: 2

0x100e:	iteet	ge
	Code condition: 11

0x1010:	vdupne.8	d16, d11[1]
	op_count: 2
		operands[0].type: REG = d16
		operands[1].type: REG = d11
		operands[1].vector_index = 1
	Code condition: 2
	Vector-size: 8

0x1014:	msr	cpsr_fc, r6
	op_count: 2
		operands[0].type: SYSREG = 144
		operands[1].type: REG = r6

0x1018:	msr	apsr_nzcvqg, r0
	op_count: 2
		operands[0].type: SYSREG = 259
		operands[1].type: REG = r0

0x101c:	sxtb.w	r6, r9, ror #8
	op_count: 2
		operands[0].type: REG = r6
		operands[1].type: REG = r9
			Shift: 4 = 8

0x1020:	vaddw.u16	q8, q8, d18
	op_count: 3
		operands[0].type: REG = q8
		operands[1].type: REG = q8
		operands[2].type: REG = d18
	Vector-data: 10

0x1024:

****************
Platform: Thumb-MClass
Code:0xef 0xf3 0x02 0x80 
Disasm:
0x1000:	mrs	r0, eapsr
	op_count: 2
		operands[0].type: REG = r0
		operands[1].type: SYSREG = 263

0x1004:

****************
Platform: Arm-V8
Code:0xe0 0x3b 0xb2 0xee 0x42 0x00 0x01 0xe1 0x51 0xf0 0x7f 0xf5 
Disasm:
0x1000:	vcvtt.f64.f16	d3, s1
	op_count: 2
		operands[0].type: REG = d3
		operands[1].type: REG = s1
	Vector-data: 17

0x1004:	crc32b	r0, r1, r2
	op_count: 3
		operands[0].type: REG = r0
		operands[1].type: REG = r1
		operands[2].type: REG = r2

0x1008:	dmb	oshld
	Memory-barrier: 2

0x100c:

****************
Platform: ARM-64
Code: 0x09 0x00 0x38 0xd5 0xbf 0x40 0x00 0xd5 0x0c 0x05 0x13 0xd5 0x20 0x50 0x02 0x0e 0x20 0xe4 0x3d 0x0f 0x00 0x18 0xa0 0x5f 0xa2 0x00 0xae 0x9e 0x9f 0x37 0x03 0xd5 0xbf 0x33 0x03 0xd5 0xdf 0x3f 0x03 0xd5 0x21 0x7c 0x02 0x9b 0x21 0x7c 0x00 0x53 0x00 0x40 0x21 0x4b 0xe1 0x0b 0x40 0xb9 0x20 0x04 0x81 0xda 0x20 0x08 0x02 0x8b 0x10 0x5b 0xe8 0x3c 
Disasm:
0x2c:	mrs	x9, midr_el1
	op_count: 2
		operands[0].type: REG = x9
		operands[1].type: REG_MRS = 0xc000

0x30:	msr	spsel, #0
	op_count: 2
		operands[0].type: PSTATE = 0x5
		operands[1].type: IMM = 0x0
	Update-flags: True

0x34:	msr	dbgdtrtx_el0, x12
	op_count: 2
		operands[0].type: REG_MSR = 0x9828
		operands[1].type: REG = x12

0x38:	tbx	v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b
	op_count: 5
		operands[0].type: REG = v0
			Vector Arrangement Specifier: 0x1
		operands[1].type: REG = v1
			Vector Arrangement Specifier: 0x2
		operands[2].type: REG = v2
			Vector Arrangement Specifier: 0x2
		operands[3].type: REG = v3
			Vector Arrangement Specifier: 0x2
		operands[4].type: REG = v2
			Vector Arrangement Specifier: 0x1

0x3c:	scvtf	v0.2s, v1.2s, #3
	op_count: 3
		operands[0].type: REG = v0
			Vector Arrangement Specifier: 0x5
		operands[1].type: REG = v1
			Vector Arrangement Specifier: 0x5
		operands[2].type: IMM = 0x3

0x40:	fmla	s0, s0, v0.s[3]
	op_count: 3
		operands[0].type: REG = s0
		operands[1].type: REG = s0
		operands[2].type: REG = v0
			Vector Element Size Specifier: 3
			Vector Index: 3

0x44:	fmov	x2, v5.d[1]
	op_count: 2
		operands[0].type: REG = x2
		operands[1].type: REG = v5
			Vector Element Size Specifier: 4
			Vector Index: 1

0x48:	dsb	nsh
	op_count: 1
		operands[0].type: BARRIER = 0x7

0x4c:	dmb	osh
	op_count: 1
		operands[0].type: BARRIER = 0x3

0x50:	isb	

0x54:	mul	x1, x1, x2
	op_count: 3
		operands[0].type: REG = x1
		operands[1].type: REG = x1
		operands[2].type: REG = x2

0x58:	lsr	w1, w1, #0
	op_count: 3
		operands[0].type: REG = w1
		operands[1].type: REG = w1
		operands[2].type: IMM = 0x0

0x5c:	sub	w0, w0, w1, uxtw
	op_count: 3
		operands[0].type: REG = w0
		operands[1].type: REG = w0
		operands[2].type: REG = w1
			Ext: 3

0x60:	ldr	w1, [sp, #8]
	op_count: 2
		operands[0].type: REG = w1
		operands[1].type: MEM
			operands[1].mem.base: REG = sp
			operands[1].mem.disp: 0x8

0x64:	cneg	x0, x1, ne
	op_count: 2
		operands[0].type: REG = x0
		operands[1].type: REG = x1
	Code-condition: 2

0x68:	add	x0, x1, x2, lsl #2
	op_count: 3
		operands[0].type: REG = x0
		operands[1].type: REG = x1
		operands[2].type: REG = x2
			Shift: type = 1, value = 2

0x6c:	ldr	q16, [x24, w8, uxtw #4]
	op_count: 2
		operands[0].type: REG = q16
		operands[1].type: MEM
			operands[1].mem.base: REG = x24
			operands[1].mem.index: REG = w8
			Shift: type = 1, value = 4
			Ext: 3

0x70:

****************
Platform: X86 16bit (Intel syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	lea		cx, word ptr [si + 0x32] // insn-ID: 315, insn-mnem: lea
0x1003:	or		byte ptr [bx + di], al // insn-ID: 325, insn-mnem: or
	Implicit registers modified: flags 
0x1005:	fadd		dword ptr [bx + di + 0x34c6] // insn-ID: 15, insn-mnem: fadd
	Implicit registers modified: fpsw 
0x1009:	adc		al, byte ptr [bx + si] // insn-ID: 6, insn-mnem: adc
	Implicit registers read: flags 
	Implicit registers modified: flags 
0x100b:

****************
Platform: X86 32bit (ATT syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	leal		8(%edx, %esi), %ecx // insn-ID: 315, insn-mnem: lea
	This instruction belongs to groups: not64bitmode 
0x1004:	addl		%ebx, %eax // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 
0x1006:	addl		$0x1234, %esi // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 
0x100c:

****************
Platform: X86 32 (Intel syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	lea		ecx, dword ptr [edx + esi + 8] // insn-ID: 315, insn-mnem: lea
	This instruction belongs to groups: not64bitmode 
0x1004:	add		eax, ebx // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 
0x1006:	add		esi, 0x1234 // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 
0x100c:

****************
Platform: X86 64 (Intel syntax)
Code: 0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00 
Disasm:
0x1000:	push		rbp // insn-ID: 580, insn-mnem: push
	Implicit registers read: rsp 
	Implicit registers modified: rsp 
	This instruction belongs to groups: mode64 
0x1001:	mov		rax, qword ptr [rip + 0x13b8] // insn-ID: 442, insn-mnem: mov
0x1008:

****************
Platform: ARM
Code: 0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 0xe5 0xf1 0x02 0x03 0x0e 0x00 0x00 0xa0 0xe3 0x02 0x30 0xc1 0xe7 0x00 0x00 0x53 0xe3 
Disasm:
0x1000:	bl		#0xfbc // insn-ID: 13, insn-mnem: bl
	Implicit registers read: pc 
	Implicit registers modified: lr 
	This instruction belongs to groups: arm jump 
0x1004:	str		lr, [sp, #-4]! // insn-ID: 212, insn-mnem: str
	This instruction belongs to groups: arm 
0x1008:	andeq		r0, r0, r0 // insn-ID: 8, insn-mnem: and
	This instruction belongs to groups: arm 
0x100c:	str		r8, [r2, #-0x3e0]! // insn-ID: 212, insn-mnem: str
	This instruction belongs to groups: arm 
0x1010:	mcreq		p2, #0, r0, c3, c1, #7 // insn-ID: 74, insn-mnem: mcr
	This instruction belongs to groups: arm 
0x1014:	mov		r0, #0 // insn-ID: 80, insn-mnem: mov
	This instruction belongs to groups: arm 
0x1018:	strb		r3, [r1, r2] // insn-ID: 203, insn-mnem: strb
	This instruction belongs to groups: arm 
0x101c:	cmp		r3, #0 // insn-ID: 23, insn-mnem: cmp
	Implicit registers modified: cpsr 
	This instruction belongs to groups: arm 
0x1020:

****************
Platform: THUMB-2
Code: 0x4f 0xf0 0x00 0x01 0xbd 0xe8 0x00 0x88 0xd1 0xe8 0x00 0xf0 
Disasm:
0x1000:	mov.w		r1, #0 // insn-ID: 80, insn-mnem: mov
	This instruction belongs to groups: thumb2 
0x1004:	pop.w		{fp, pc} // insn-ID: 425, insn-mnem: pop
	This instruction belongs to groups: thumb2 
0x1008:	tbb		[r1, r0] // insn-ID: 420, insn-mnem: tbb
	This instruction belongs to groups: thumb2 jump 
0x100c:

****************
Platform: ARM: Cortex-A15 + NEON
Code: 0x10 0xf1 0x10 0xe7 0x11 0xf2 0x31 0xe7 0xdc 0xa1 0x2e 0xf3 0xe8 0x4e 0x62 0xf3 
Disasm:
0x1000:	sdiv		r0, r0, r1 // insn-ID: 122, insn-mnem: sdiv
	This instruction belongs to groups: arm 
0x1004:	udiv		r1, r1, r2 // insn-ID: 231, insn-mnem: udiv
	This instruction belongs to groups: arm 
0x1008:	vbit		q5, q15, q6 // insn-ID: 274, insn-mnem: vbit
	This instruction belongs to groups: neon 
0x100c:	vcgt.f32		q10, q9, q12 // insn-ID: 278, insn-mnem: vcgt
	This instruction belongs to groups: neon 
0x1010:

****************
Platform: THUMB
Code: 0x70 0x47 0xeb 0x46 0x83 0xb0 0xc9 0x68 
Disasm:
0x1000:	bx		lr // insn-ID: 15, insn-mnem: bx
	This instruction belongs to groups: thumb jump 
0x1002:	mov		fp, sp // insn-ID: 80, insn-mnem: mov
	This instruction belongs to groups: thumb thumb1only 
0x1004:	sub		sp, #0xc // insn-ID: 213, insn-mnem: sub
	This instruction belongs to groups: thumb thumb1only 
0x1006:	ldr		r1, [r1, #0xc] // insn-ID: 73, insn-mnem: ldr
	This instruction belongs to groups: thumb thumb1only 
0x1008:

****************
Platform: Thumb-MClass
Code: 0xef 0xf3 0x02 0x80 
Disasm:
0x1000:	mrs		r0, eapsr // insn-ID: 87, insn-mnem: mrs
	This instruction belongs to groups: thumb mclass 
0x1004:

****************
Platform: Arm-V8
Code: 0xe0 0x3b 0xb2 0xee 0x42 0x00 0x01 0xe1 0x51 0xf0 0x7f 0xf5 
Disasm:
0x1000:	vcvtt.f64.f16		d3, s1 // insn-ID: 292, insn-mnem: vcvtt
	This instruction belongs to groups: fparmv8 dpvfp 
0x1004:	crc32b		r0, r1, r2 // insn-ID: 25, insn-mnem: crc32b
	This instruction belongs to groups: arm v8 crc 
0x1008:	dmb		oshld // insn-ID: 32, insn-mnem: dmb
	This instruction belongs to groups: arm databarrier 
0x100c:

****************
Platform: MIPS-32 (Big-endian)
Code: 0x0c 0x10 0x00 0x97 0x00 0x00 0x00 0x00 0x24 0x02 0x00 0x0c 0x8f 0xa2 0x00 0x00 0x34 0x21 0x34 0x56 0x00 0x80 0x04 0x08 
Disasm:
0x1000:	lhu		$zero, 0x100c($t8) // insn-ID: 347, insn-mnem: lhu
	This instruction belongs to groups: stdenc 
0x1004:	nop		 // insn-ID: 582, insn-mnem: nop
	This instruction belongs to groups: stdenc 
0x1008:	jal		0x890 // insn-ID: 322, insn-mnem: jal
	Implicit registers modified: ra 
	This instruction belongs to groups: stdenc 
0x100c:	sync		0xa // insn-ID: 554, insn-mnem: sync
	This instruction belongs to groups: stdenc mips32 
0x1010:	bnel		$s1, $s4, 0x94e4 // insn-ID: 107, insn-mnem: bnel
	Implicit registers modified: at 
	This instruction belongs to groups: stdenc jump 
0x1014:	j		0x120000 // insn-ID: 321, insn-mnem: j
	Implicit registers modified: at 
	This instruction belongs to groups: stdenc jump 
0x1018:

****************
Platform: MIPS-64-EL (Little-endian)
Code: 0x56 0x34 0x21 0x34 0xc2 0x17 0x01 0x00 
Disasm:
0x1000:	ori		$at, $at, 0x3456 // insn-ID: 445, insn-mnem: ori
	This instruction belongs to groups: stdenc 
0x1004:	srl		$v0, $at, 0x1f // insn-ID: 525, insn-mnem: srl
	This instruction belongs to groups: stdenc 
0x1008:

****************
Platform: MIPS-32R6 | Micro (Big-endian)
****************
Platform: MIPS-32R6 | Micro (Big-endian)
Code: 0x00 0x07 0x00 0x07 0x00 0x11 0x93 0x7c 0x01 0x8c 0x8b 0x7c 0x00 0xc7 0x48 0xd0 
ERROR: Failed to disasm given code!

****************
Platform: MIPS-32R6 (Big-endian)
Code: 0xec 0x80 0x00 0x19 0x7c 0x43 0x22 0xa0 
Disasm:
0x1000:	blez		$t0, -0x1ec4c // insn-ID: 86, insn-mnem: blez
	Implicit registers modified: at 
	This instruction belongs to groups: stdenc jump 
0x1004:	sb		$v0, 0x437c($at) // insn-ID: 475, insn-mnem: sb
	This instruction belongs to groups: stdenc 
0x1008:

****************
Platform: ARM-64
Code: 0x09 0x00 0x38 0xd5 0xbf 0x40 0x00 0xd5 0x0c 0x05 0x13 0xd5 0x20 0x50 0x02 0x0e 0x20 0xe4 0x3d 0x0f 0x00 0x18 0xa0 0x5f 0xa2 0x00 0xae 0x9e 0x9f 0x37 0x03 0xd5 0xbf 0x33 0x03 0xd5 0xdf 0x3f 0x03 0xd5 0x21 0x7c 0x02 0x9b 0x21 0x7c 0x00 0x53 0x00 0x40 0x21 0x4b 0xe1 0x0b 0x40 0xb9 0x20 0x04 0x81 0xda 0x20 0x08 0x02 0x8b 0x10 0x5b 0xe8 0x3c 
Disasm:
0x1000:	mrs		x9, midr_el1 // insn-ID: 192, insn-mnem: mrs
0x1004:	msr		spsel, #0 // insn-ID: 193, insn-mnem: msr
	Implicit registers modified: nzcv 
0x1008:	msr		dbgdtrtx_el0, x12 // insn-ID: 193, insn-mnem: msr
0x100c:	tbx		v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // insn-ID: 347, insn-mnem: tbx
	This instruction belongs to groups: neon 
0x1010:	scvtf		v0.2s, v1.2s, #3 // insn-ID: 234, insn-mnem: scvtf
	This instruction belongs to groups: neon 
0x1014:	fmla		s0, s0, v0.s[3] // insn-ID: 114, insn-mnem: fmla
	This instruction belongs to groups: neon 
0x1018:	fmov		x2, v5.d[1] // insn-ID: 116, insn-mnem: fmov
	This instruction belongs to groups: fparmv8 
0x101c:	dsb		nsh // insn-ID: 60, insn-mnem: dsb
0x1020:	dmb		osh // insn-ID: 58, insn-mnem: dmb
0x1024:	isb		 // insn-ID: 142, insn-mnem: isb
0x1028:	mul		x1, x1, x2 // insn-ID: 195, insn-mnem: mul
0x102c:	lsr		w1, w1, #0 // insn-ID: 184, insn-mnem: lsr
0x1030:	sub		w0, w0, w1, uxtw // insn-ID: 340, insn-mnem: sub
0x1034:	ldr		w1, [sp, #8] // insn-ID: 162, insn-mnem: ldr
0x1038:	cneg		x0, x1, ne // insn-ID: 440, insn-mnem: cneg
	Implicit registers read: nzcv 
0x103c:	add		x0, x1, x2, lsl #2 // insn-ID: 6, insn-mnem: add
0x1040:	ldr		q16, [x24, w8, uxtw #4] // insn-ID: 162, insn-mnem: ldr
0x1044:

****************
Platform: PPC-64
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 0x40 0x82 0x00 0x14 
Disasm:
0x1000:	lwz		r1, (0) // insn-ID: 347, insn-mnem: lwz
0x1004:	lwz		r1, (r31) // insn-ID: 347, insn-mnem: lwz
0x1008:	vpkpx		v2, v3, v4 // insn-ID: 570, insn-mnem: vpkpx
	This instruction belongs to groups: altivec 
0x100c:	stfs		f2, 0x80(r4) // insn-ID: 443, insn-mnem: stfs
0x1010:	crand		2, 3, 4 // insn-ID: 52, insn-mnem: crand
0x1014:	cmpwi		cr2, r3, 0x80 // insn-ID: 47, insn-mnem: cmpwi
0x1018:	addc		r2, r3, r4 // insn-ID: 2, insn-mnem: addc
	Implicit registers modified: ca 
0x101c:	mulhd.		r2, r3, r4 // insn-ID: 384, insn-mnem: mulhd
	Implicit registers modified: cr0 
0x1020:	bdnzlrl+		 // insn-ID: 28, insn-mnem: bdnzlrl
	Implicit registers read: ctr lr rm 
	Implicit registers modified: ctr 
0x1024:	bgelrl-		cr2 // insn-ID: 38, insn-mnem: blrl
	Implicit registers read: ctr lr rm 
	Implicit registers modified: lr ctr 
0x1028:	bne		0x103c // insn-ID: 13, insn-mnem: b
	Implicit registers read: ctr rm 
	Implicit registers modified: ctr 
0x102c:

****************
Platform: Sparc
Code: 0x80 0xa0 0x40 0x02 0x85 0xc2 0x60 0x08 0x85 0xe8 0x20 0x01 0x81 0xe8 0x00 0x00 0x90 0x10 0x20 0x01 0xd5 0xf6 0x10 0x16 0x21 0x00 0x00 0x0a 0x86 0x00 0x40 0x02 0x01 0x00 0x00 0x00 0x12 0xbf 0xff 0xff 0x10 0xbf 0xff 0xff 0xa0 0x02 0x00 0x09 0x0d 0xbf 0xff 0xff 0xd4 0x20 0x60 0x00 0xd4 0x4e 0x00 0x16 0x2a 0xc2 0x80 0x03 
Disasm:
0x1000:	cmp		%g1, %g2 // insn-ID: 33, insn-mnem: cmp
	Implicit registers modified: icc 
0x1004:	jmpl		%o1+8, %g2 // insn-ID: 194, insn-mnem: jmpl
0x1008:	restore		%g0, 1, %g2 // insn-ID: 226, insn-mnem: restore
0x100c:	restore		 // insn-ID: 226, insn-mnem: restore
0x1010:	mov		1, %o0 // insn-ID: 207, insn-mnem: mov
0x1014:	casx		[%i0], %l6, %o2 // insn-ID: 28, insn-mnem: casx
	This instruction belongs to groups: 64bit 
0x1018:	sethi		0xa, %l0 // insn-ID: 232, insn-mnem: sethi
0x101c:	add		%g1, %g2, %g3 // insn-ID: 6, insn-mnem: add
0x1020:	nop		 // insn-ID: 217, insn-mnem: nop
0x1024:	bne		0x1020 // insn-ID: 16, insn-mnem: b
	Implicit registers read: icc 
	This instruction belongs to groups: jump 
0x1028:	ba		0x1024 // insn-ID: 16, insn-mnem: b
	This instruction belongs to groups: jump 
0x102c:	add		%o0, %o1, %l0 // insn-ID: 6, insn-mnem: add
0x1030:	fbg		0x102c // insn-ID: 19, insn-mnem: fb
	Implicit registers read: fcc0 
	This instruction belongs to groups: jump 
0x1034:	st		%o2, [%g1] // insn-ID: 246, insn-mnem: st
0x1038:	ldsb		[%i0+%l6], %o2 // insn-ID: 198, insn-mnem: ldsb
0x103c:	brnz,a,pn		%o2, 0x1048 // insn-ID: 24, insn-mnem: brnz
	This instruction belongs to groups: 64bit jump 
0x1040:

****************
Platform: SparcV9
Code: 0x81 0xa8 0x0a 0x24 0x89 0xa0 0x10 0x20 0x89 0xa0 0x1a 0x60 0x89 0xa0 0x00 0xe0 
Disasm:
0x1000:	fcmps		%f0, %f4 // insn-ID: 70, insn-mnem: fcmps
0x1004:	fstox		%f0, %f4 // insn-ID: 181, insn-mnem: fstox
	This instruction belongs to groups: 64bit 
0x1008:	fqtoi		%f0, %f4 // insn-ID: 159, insn-mnem: fqtoi
	This instruction belongs to groups: hardquad 
0x100c:	fnegq		%f0, %f4 // insn-ID: 127, insn-mnem: fnegq
	This instruction belongs to groups: v9 
0x1010:

****************
Platform: SystemZ
Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 
Disasm:
0x1000:	adb		%f0, 0 // insn-ID: 2, insn-mnem: adb
	Implicit registers modified: cc 
0x1006:	a		%r0, 0xfff(%r15, %r1) // insn-ID: 1, insn-mnem: a
	Implicit registers modified: cc 
0x100a:	afi		%r0, -0x80000000 // insn-ID: 6, insn-mnem: afi
	Implicit registers modified: cc 
0x1010:	br		%r7 // insn-ID: 283, insn-mnem: br
	This instruction belongs to groups: jump 
0x1012:	xiy		0x7ffff(%r15), 0x2a // insn-ID: 678, insn-mnem: xiy
	Implicit registers modified: cc 
0x1018:	xy		%r0, 0x7ffff(%r1, %r15) // insn-ID: 681, insn-mnem: xy
	Implicit registers modified: cc 
0x101e:	stmg		%r0, %r0, 0(%r15) // insn-ID: 657, insn-mnem: stmg
0x1024:	ear		%r7, %a8 // insn-ID: 383, insn-mnem: ear
0x1028:

****************
Platform: XCore
Code: 0xfe 0x0f 0xfe 0x17 0x13 0x17 0xc6 0xfe 0xec 0x17 0x97 0xf8 0xec 0x4f 0x1f 0xfd 0xec 0x37 0x07 0xf2 0x45 0x5b 0xf9 0xfa 0x02 0x06 0x1b 0x10 
Disasm:
0x1000:	get		r11, ed // insn-ID: 43, insn-mnem: get
	Implicit registers modified: r11 
0x1002:	ldw		et, sp[4] // insn-ID: 66, insn-mnem: ldw
	Implicit registers read: sp 
0x1004:	setd		res[r3], r4 // insn-ID: 93, insn-mnem: setd
0x1006:	init		t[r2]:lr, r1 // insn-ID: 50, insn-mnem: init
0x100a:	divu		r9, r1, r3 // insn-ID: 26, insn-mnem: divu
0x100e:	lda16		r9, r3[-r11] // insn-ID: 62, insn-mnem: lda16
0x1012:	ldw		dp, dp[0x81c5] // insn-ID: 66, insn-mnem: ldw
0x1016:	lmul		r11, r0, r2, r5, r8, r10 // insn-ID: 68, insn-mnem: lmul
0x101a:	add		r1, r2, r3 // insn-ID: 1, insn-mnem: add
0x101c:

****************
Platform: X86 16bit (Intel syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	lea		cx, word ptr [si + 0x32] // insn-ID: 315, insn-mnem: lea
0x1003:	or		byte ptr [bx + di], al // insn-ID: 325, insn-mnem: or
	Implicit registers modified: flags 
0x1005:	fadd		dword ptr [bx + di + 0x34c6] // insn-ID: 15, insn-mnem: fadd
	Implicit registers modified: fpsw 
0x1009:	adc		al, byte ptr [bx + si] // insn-ID: 6, insn-mnem: adc
	Implicit registers read: flags 
	Implicit registers modified: flags 

****************
Platform: X86 32bit (ATT syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	leal		8(%edx, %esi), %ecx // insn-ID: 315, insn-mnem: lea
	This instruction belongs to groups: not64bitmode 
0x1004:	addl		%ebx, %eax // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 
0x1006:	addl		$0x1234, %esi // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 

****************
Platform: X86 32 (Intel syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	lea		ecx, dword ptr [edx + esi + 8] // insn-ID: 315, insn-mnem: lea
	This instruction belongs to groups: not64bitmode 
0x1004:	add		eax, ebx // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 
0x1006:	add		esi, 0x1234 // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 

****************
Platform: X86 64 (Intel syntax)
Code: 0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00 
Disasm:
0x1000:	push		rbp // insn-ID: 580, insn-mnem: push
	Implicit registers read: rsp 
	Implicit registers modified: rsp 
	This instruction belongs to groups: mode64 
0x1001:	mov		rax, qword ptr [rip + 0x13b8] // insn-ID: 442, insn-mnem: mov

****************
Platform: ARM
Code: 0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 0xe5 0xf1 0x02 0x03 0x0e 0x00 0x00 0xa0 0xe3 0x02 0x30 0xc1 0xe7 0x00 0x00 0x53 0xe3 
Disasm:
0x1000:	bl		#0xfbc // insn-ID: 13, insn-mnem: bl
	Implicit registers read: pc 
	Implicit registers modified: lr 
	This instruction belongs to groups: arm jump 
0x1004:	str		lr, [sp, #-4]! // insn-ID: 212, insn-mnem: str
	This instruction belongs to groups: arm 
0x1008:	andeq		r0, r0, r0 // insn-ID: 8, insn-mnem: and
	This instruction belongs to groups: arm 
0x100c:	str		r8, [r2, #-0x3e0]! // insn-ID: 212, insn-mnem: str
	This instruction belongs to groups: arm 
0x1010:	mcreq		p2, #0, r0, c3, c1, #7 // insn-ID: 74, insn-mnem: mcr
	This instruction belongs to groups: arm 
0x1014:	mov		r0, #0 // insn-ID: 80, insn-mnem: mov
	This instruction belongs to groups: arm 
0x1018:	strb		r3, [r1, r2] // insn-ID: 203, insn-mnem: strb
	This instruction belongs to groups: arm 
0x101c:	cmp		r3, #0 // insn-ID: 23, insn-mnem: cmp
	Implicit registers modified: cpsr 
	This instruction belongs to groups: arm 

****************
Platform: THUMB-2
Code: 0x4f 0xf0 0x00 0x01 0xbd 0xe8 0x00 0x88 0xd1 0xe8 0x00 0xf0 
Disasm:
0x1000:	mov.w		r1, #0 // insn-ID: 80, insn-mnem: mov
	This instruction belongs to groups: thumb2 
0x1004:	pop.w		{fp, pc} // insn-ID: 425, insn-mnem: pop
	This instruction belongs to groups: thumb2 
0x1008:	tbb		[r1, r0] // insn-ID: 420, insn-mnem: tbb
	This instruction belongs to groups: thumb2 jump 

****************
Platform: ARM: Cortex-A15 + NEON
Code: 0x10 0xf1 0x10 0xe7 0x11 0xf2 0x31 0xe7 0xdc 0xa1 0x2e 0xf3 0xe8 0x4e 0x62 0xf3 
Disasm:
0x1000:	sdiv		r0, r0, r1 // insn-ID: 122, insn-mnem: sdiv
	This instruction belongs to groups: arm 
0x1004:	udiv		r1, r1, r2 // insn-ID: 231, insn-mnem: udiv
	This instruction belongs to groups: arm 
0x1008:	vbit		q5, q15, q6 // insn-ID: 274, insn-mnem: vbit
	This instruction belongs to groups: neon 
0x100c:	vcgt.f32		q10, q9, q12 // insn-ID: 278, insn-mnem: vcgt
	This instruction belongs to groups: neon 

****************
Platform: THUMB
Code: 0x70 0x47 0xeb 0x46 0x83 0xb0 0xc9 0x68 
Disasm:
0x1000:	bx		lr // insn-ID: 15, insn-mnem: bx
	This instruction belongs to groups: thumb jump 
0x1002:	mov		fp, sp // insn-ID: 80, insn-mnem: mov
	This instruction belongs to groups: thumb thumb1only 
0x1004:	sub		sp, #0xc // insn-ID: 213, insn-mnem: sub
	This instruction belongs to groups: thumb thumb1only 
0x1006:	ldr		r1, [r1, #0xc] // insn-ID: 73, insn-mnem: ldr
	This instruction belongs to groups: thumb thumb1only 

****************
Platform: MIPS-32 (Big-endian)
Code: 0x0c 0x10 0x00 0x97 0x00 0x00 0x00 0x00 0x24 0x02 0x00 0x0c 0x8f 0xa2 0x00 0x00 0x34 0x21 0x34 0x56 0x00 0x80 0x04 0x08 
Disasm:
0x1000:	lhu		$zero, 0x100c($t8) // insn-ID: 347, insn-mnem: lhu
	This instruction belongs to groups: stdenc 
0x1004:	nop		 // insn-ID: 582, insn-mnem: nop
	This instruction belongs to groups: stdenc 
0x1008:	jal		0x890 // insn-ID: 322, insn-mnem: jal
	Implicit registers modified: ra 
	This instruction belongs to groups: stdenc 
0x100c:	sync		0xa // insn-ID: 554, insn-mnem: sync
	This instruction belongs to groups: stdenc mips32 
0x1010:	bnel		$s1, $s4, 0x94e4 // insn-ID: 107, insn-mnem: bnel
	Implicit registers modified: at 
	This instruction belongs to groups: stdenc jump 
0x1014:	j		0x120000 // insn-ID: 321, insn-mnem: j
	Implicit registers modified: at 
	This instruction belongs to groups: stdenc jump 

****************
Platform: MIPS-64-EL (Little-endian)
Code: 0x56 0x34 0x21 0x34 0xc2 0x17 0x01 0x00 
Disasm:
0x1000:	ori		$at, $at, 0x3456 // insn-ID: 445, insn-mnem: ori
	This instruction belongs to groups: stdenc 
0x1004:	srl		$v0, $at, 0x1f // insn-ID: 525, insn-mnem: srl
	This instruction belongs to groups: stdenc 

****************
Platform: ARM-64
Code: 0x09 0x00 0x38 0xd5 0xbf 0x40 0x00 0xd5 0x0c 0x05 0x13 0xd5 0x20 0x50 0x02 0x0e 0x20 0xe4 0x3d 0x0f 0x00 0x18 0xa0 0x5f 0xa2 0x00 0xae 0x9e 0x9f 0x37 0x03 0xd5 0xbf 0x33 0x03 0xd5 0xdf 0x3f 0x03 0xd5 0x21 0x7c 0x02 0x9b 0x21 0x7c 0x00 0x53 0x00 0x40 0x21 0x4b 0xe1 0x0b 0x40 0xb9 0x20 0x04 0x81 0xda 0x20 0x08 0x02 0x8b 0x10 0x5b 0xe8 0x3c 
Disasm:
0x1000:	mrs		x9, midr_el1 // insn-ID: 192, insn-mnem: mrs
0x1004:	msr		spsel, #0 // insn-ID: 193, insn-mnem: msr
	Implicit registers modified: nzcv 
0x1008:	msr		dbgdtrtx_el0, x12 // insn-ID: 193, insn-mnem: msr
0x100c:	tbx		v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // insn-ID: 347, insn-mnem: tbx
	This instruction belongs to groups: neon 
0x1010:	scvtf		v0.2s, v1.2s, #3 // insn-ID: 234, insn-mnem: scvtf
	This instruction belongs to groups: neon 
0x1014:	fmla		s0, s0, v0.s[3] // insn-ID: 114, insn-mnem: fmla
	This instruction belongs to groups: neon 
0x1018:	fmov		x2, v5.d[1] // insn-ID: 116, insn-mnem: fmov
	This instruction belongs to groups: fparmv8 
0x101c:	dsb		nsh // insn-ID: 60, insn-mnem: dsb
0x1020:	dmb		osh // insn-ID: 58, insn-mnem: dmb
0x1024:	isb		 // insn-ID: 142, insn-mnem: isb
0x1028:	mul		x1, x1, x2 // insn-ID: 195, insn-mnem: mul
0x102c:	lsr		w1, w1, #0 // insn-ID: 184, insn-mnem: lsr
0x1030:	sub		w0, w0, w1, uxtw // insn-ID: 340, insn-mnem: sub
0x1034:	ldr		w1, [sp, #8] // insn-ID: 162, insn-mnem: ldr
0x1038:	cneg		x0, x1, ne // insn-ID: 440, insn-mnem: cneg
	Implicit registers read: nzcv 
0x103c:	add		x0, x1, x2, lsl #2 // insn-ID: 6, insn-mnem: add
0x1040:	ldr		q16, [x24, w8, uxtw #4] // insn-ID: 162, insn-mnem: ldr

****************
Platform: PPC-64
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 0x40 0x82 0x00 0x14 
Disasm:
0x1000:	lwz		r1, (0) // insn-ID: 347, insn-mnem: lwz
0x1004:	lwz		r1, (r31) // insn-ID: 347, insn-mnem: lwz
0x1008:	vpkpx		v2, v3, v4 // insn-ID: 570, insn-mnem: vpkpx
	This instruction belongs to groups: altivec 
0x100c:	stfs		f2, 0x80(r4) // insn-ID: 443, insn-mnem: stfs
0x1010:	crand		2, 3, 4 // insn-ID: 52, insn-mnem: crand
0x1014:	cmpwi		cr2, r3, 0x80 // insn-ID: 47, insn-mnem: cmpwi
0x1018:	addc		r2, r3, r4 // insn-ID: 2, insn-mnem: addc
	Implicit registers modified: ca 
0x101c:	mulhd.		r2, r3, r4 // insn-ID: 384, insn-mnem: mulhd
	Implicit registers modified: cr0 
0x1020:	bdnzlrl+		 // insn-ID: 28, insn-mnem: bdnzlrl
	Implicit registers read: ctr lr rm 
	Implicit registers modified: ctr 
0x1024:	bgelrl-		cr2 // insn-ID: 38, insn-mnem: blrl
	Implicit registers read: ctr lr rm 
	Implicit registers modified: lr ctr 
0x1028:	bne		0x103c // insn-ID: 13, insn-mnem: b
	Implicit registers read: ctr rm 
	Implicit registers modified: ctr 

****************
Platform: Sparc
Code: 0x80 0xa0 0x40 0x02 0x85 0xc2 0x60 0x08 0x85 0xe8 0x20 0x01 0x81 0xe8 0x00 0x00 0x90 0x10 0x20 0x01 0xd5 0xf6 0x10 0x16 0x21 0x00 0x00 0x0a 0x86 0x00 0x40 0x02 0x01 0x00 0x00 0x00 0x12 0xbf 0xff 0xff 0x10 0xbf 0xff 0xff 0xa0 0x02 0x00 0x09 0x0d 0xbf 0xff 0xff 0xd4 0x20 0x60 0x00 0xd4 0x4e 0x00 0x16 0x2a 0xc2 0x80 0x03 
Disasm:
0x1000:	cmp		%g1, %g2 // insn-ID: 33, insn-mnem: cmp
	Implicit registers modified: icc 
0x1004:	jmpl		%o1+8, %g2 // insn-ID: 194, insn-mnem: jmpl
0x1008:	restore		%g0, 1, %g2 // insn-ID: 226, insn-mnem: restore
0x100c:	restore		 // insn-ID: 226, insn-mnem: restore
0x1010:	mov		1, %o0 // insn-ID: 207, insn-mnem: mov
0x1014:	casx		[%i0], %l6, %o2 // insn-ID: 28, insn-mnem: casx
	This instruction belongs to groups: 64bit 
0x1018:	sethi		0xa, %l0 // insn-ID: 232, insn-mnem: sethi
0x101c:	add		%g1, %g2, %g3 // insn-ID: 6, insn-mnem: add
0x1020:	nop		 // insn-ID: 217, insn-mnem: nop
0x1024:	bne		0x1020 // insn-ID: 16, insn-mnem: b
	Implicit registers read: icc 
	This instruction belongs to groups: jump 
0x1028:	ba		0x1024 // insn-ID: 16, insn-mnem: b
	This instruction belongs to groups: jump 
0x102c:	add		%o0, %o1, %l0 // insn-ID: 6, insn-mnem: add
0x1030:	fbg		0x102c // insn-ID: 19, insn-mnem: fb
	Implicit registers read: fcc0 
	This instruction belongs to groups: jump 
0x1034:	st		%o2, [%g1] // insn-ID: 246, insn-mnem: st
0x1038:	ldsb		[%i0+%l6], %o2 // insn-ID: 198, insn-mnem: ldsb
0x103c:	brnz,a,pn		%o2, 0x1048 // insn-ID: 24, insn-mnem: brnz
	This instruction belongs to groups: 64bit jump 

****************
Platform: SparcV9
Code: 0x81 0xa8 0x0a 0x24 0x89 0xa0 0x10 0x20 0x89 0xa0 0x1a 0x60 0x89 0xa0 0x00 0xe0 
Disasm:
0x1000:	fcmps		%f0, %f4 // insn-ID: 70, insn-mnem: fcmps
0x1004:	fstox		%f0, %f4 // insn-ID: 181, insn-mnem: fstox
	This instruction belongs to groups: 64bit 
0x1008:	fqtoi		%f0, %f4 // insn-ID: 159, insn-mnem: fqtoi
	This instruction belongs to groups: hardquad 
0x100c:	fnegq		%f0, %f4 // insn-ID: 127, insn-mnem: fnegq
	This instruction belongs to groups: v9 

****************
Platform: SystemZ
Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 
Disasm:
0x1000:	adb		%f0, 0 // insn-ID: 2, insn-mnem: adb
	Implicit registers modified: cc 
0x1006:	a		%r0, 0xfff(%r15, %r1) // insn-ID: 1, insn-mnem: a
	Implicit registers modified: cc 
0x100a:	afi		%r0, -0x80000000 // insn-ID: 6, insn-mnem: afi
	Implicit registers modified: cc 
0x1010:	br		%r7 // insn-ID: 283, insn-mnem: br
	This instruction belongs to groups: jump 
0x1012:	xiy		0x7ffff(%r15), 0x2a // insn-ID: 678, insn-mnem: xiy
	Implicit registers modified: cc 
0x1018:	xy		%r0, 0x7ffff(%r1, %r15) // insn-ID: 681, insn-mnem: xy
	Implicit registers modified: cc 
0x101e:	stmg		%r0, %r0, 0(%r15) // insn-ID: 657, insn-mnem: stmg
0x1024:	ear		%r7, %a8 // insn-ID: 383, insn-mnem: ear

****************
Platform: XCore
Code: 0xfe 0x0f 0xfe 0x17 0x13 0x17 0xc6 0xfe 0xec 0x17 0x97 0xf8 0xec 0x4f 0x1f 0xfd 0xec 0x37 0x07 0xf2 0x45 0x5b 0xf9 0xfa 0x02 0x06 0x1b 0x10 
Disasm:
0x1000:	get		r11, ed // insn-ID: 43, insn-mnem: get
	Implicit registers modified: r11 
0x1002:	ldw		et, sp[4] // insn-ID: 66, insn-mnem: ldw
	Implicit registers read: sp 
0x1004:	setd		res[r3], r4 // insn-ID: 93, insn-mnem: setd
0x1006:	init		t[r2]:lr, r1 // insn-ID: 50, insn-mnem: init
0x100a:	divu		r9, r1, r3 // insn-ID: 26, insn-mnem: divu
0x100e:	lda16		r9, r3[-r11] // insn-ID: 62, insn-mnem: lda16
0x1012:	ldw		dp, dp[0x81c5] // insn-ID: 66, insn-mnem: ldw
0x1016:	lmul		r11, r0, r2, r5, r8, r10 // insn-ID: 68, insn-mnem: lmul
0x101a:	add		r1, r2, r3 // insn-ID: 1, insn-mnem: add

****************
Platform: MIPS-32 (Big-endian)
Code:0x0c 0x10 0x00 0x97 0x00 0x00 0x00 0x00 0x24 0x02 0x00 0x0c 0x8f 0xa2 0x00 0x00 0x34 0x21 0x34 0x56 
Disasm:
0x1000:	lhu	$zero, 0x100c($t8)
	op_count: 2
		operands[0].type: REG = zero
		operands[1].type: MEM
			operands[1].mem.base: REG = t8
			operands[1].mem.disp: 0x100c

0x1004:	nop	

0x1008:	jal	0x890
	op_count: 1
		operands[0].type: IMM = 0x890

0x100c:	sync	0xa
	op_count: 1
		operands[0].type: IMM = 0xa

0x1010:	bnel	$s1, $s4, 0x94e4
	op_count: 3
		operands[0].type: REG = s1
		operands[1].type: REG = s4
		operands[2].type: IMM = 0x94e4

0x1014:

****************
Platform: MIPS-64-EL (Little-endian)
Code:0x56 0x34 0x21 0x34 0xc2 0x17 0x01 0x00 
Disasm:
0x1000:	ori	$at, $at, 0x3456
	op_count: 3
		operands[0].type: REG = at
		operands[1].type: REG = at
		operands[2].type: IMM = 0x3456

0x1004:	srl	$v0, $at, 0x1f
	op_count: 3
		operands[0].type: REG = v0
		operands[1].type: REG = at
		operands[2].type: IMM = 0x1f

0x1008:

****************
Platform: MIPS-32R6 | Micro (Big-endian)
Code:0x00 0x07 0x00 0x07 0x00 0x11 0x93 0x7c 0x01 0x8c 0x8b 0x7c 0x00 0xc7 0x48 0xd0 
ERROR: Failed to disasm given code!

****************
Platform: MIPS-32R6 (Big-endian)
Code:0xec 0x80 0x00 0x19 0x7c 0x43 0x22 0xa0 
Disasm:
0x1000:	blez	$t0, -0x1ec4c
	op_count: 2
		operands[0].type: REG = t0
		operands[1].type: IMM = 0xfffffffffffe13b4

0x1004:	sb	$v0, 0x437c($at)
	op_count: 2
		operands[0].type: REG = v0
		operands[1].type: MEM
			operands[1].mem.base: REG = at
			operands[1].mem.disp: 0x437c

0x1008:

****************
Platform: PPC-64
Code:0x43 0x20 0x0c 0x07 0x41 0x56 0xff 0x17 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 0x40 0x82 0x00 0x14 
Disasm:
0x1000:	bdnzla+	0xc04
	op_count: 1
		operands[0].type: IMM = 0xc04
	Branch hint: 1

0x1004:	bdztla	4*cr5+eq, 0xffffff14
	op_count: 2
		operands[0].type: CRX
			operands[0].crx.scale: 4
			operands[0].crx.reg: cr5
			operands[0].crx.cond: eq
		operands[1].type: IMM = 0xffffff14
	Branch hint: 1

0x1008:	lwz	r1, (0)
	op_count: 2
		operands[0].type: REG = r1
		operands[1].type: MEM
			operands[1].mem.base: REG = r0

0x100c:	lwz	r1, (r31)
	op_count: 2
		operands[0].type: REG = r1
		operands[1].type: MEM
			operands[1].mem.base: REG = r31

0x1010:	vpkpx	v2, v3, v4
	op_count: 3
		operands[0].type: REG = v2
		operands[1].type: REG = v3
		operands[2].type: REG = v4

0x1014:	stfs	f2, 0x80(r4)
	op_count: 2
		operands[0].type: REG = f2
		operands[1].type: MEM
			operands[1].mem.base: REG = r4
			operands[1].mem.disp: 0x80

0x1018:	crand	2, 3, 4
	op_count: 3
		operands[0].type: REG = r2
		operands[1].type: REG = r3
		operands[2].type: REG = r4

0x101c:	cmpwi	cr2, r3, 0x80
	op_count: 3
		operands[0].type: REG = cr2
		operands[1].type: REG = r3
		operands[2].type: IMM = 0x80

0x1020:	addc	r2, r3, r4
	op_count: 3
		operands[0].type: REG = r2
		operands[1].type: REG = r3
		operands[2].type: REG = r4

0x1024:	mulhd.	r2, r3, r4
	op_count: 3
		operands[0].type: REG = r2
		operands[1].type: REG = r3
		operands[2].type: REG = r4
	Update-CR0: True

0x1028:	bdnzlrl+	
	Branch hint: 1

0x102c:	bgelrl-	cr2
	op_count: 1
		operands[0].type: REG = cr2
	Branch code: 4
	Branch hint: 2

0x1030:	bne	0x1044
	op_count: 1
		operands[0].type: IMM = 0x1044
	Branch code: 68

0x1034:

****************
Platform: X86 32 (Intel syntax) - Skip data
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x00 0x91 0x92 
Disasm:
0x1000:	lea		ecx, dword ptr [edx + esi + 8]
0x1004:	add		eax, ebx
0x1006:	add		esi, 0x1234
0x100c:	.byte		0x00
0x100d:	xchg		eax, ecx
0x100e:	xchg		eax, edx
0x100f:

****************
Platform: Arm - Skip data
Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 
Disasm:
0x1000:	andeq		r0, r0, sp, ror #1
0x1004:	svceq		#0x5a1a00
0x1008:	stmibeq		r2, {r0, r1, r2, r3, r4, r8, sb, sl, fp, ip, sp, lr, pc} ^
0x100c:	andeq		r0, r0, r0, lsl #1
0x1010:	bhs		#0xffafec34
0x1014:	.byte		0xff, 0xff, 0x7f, 0x57
0x1018:	.byte		0xe3, 0x01, 0xff, 0xff
0x101c:	rsceq		r5, fp, pc, ror r7
0x1020:	strhs		r0, [r0], #-0xf0
0x1024:	stmdavc		r0, {r1, r4, r5, r7, r8, sb, sl, fp, lr}
0x1028:

****************
Platform: X86 32 (Intel syntax) - Skip data with custom mnemonic
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x00 0x91 0x92 
Disasm:
0x1000:	lea		ecx, dword ptr [edx + esi + 8]
0x1004:	add		eax, ebx
0x1006:	add		esi, 0x1234
0x100c:	db		0x00
0x100d:	xchg		eax, ecx
0x100e:	xchg		eax, edx
0x100f:

****************
Platform: Arm - Skip data with callback
Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 
Disasm:
0x1000:	andeq		r0, r0, sp, ror #1
0x1004:	svceq		#0x5a1a00
0x1008:	stmibeq		r2, {r0, r1, r2, r3, r4, r8, sb, sl, fp, ip, sp, lr, pc} ^
0x100c:	andeq		r0, r0, r0, lsl #1
0x1010:	bhs		#0xffafec34
0x1014:	db		0xff, 0xff
0x1016:	db		0x7f, 0x57
0x1018:	db		0xe3, 0x01
0x101a:	db		0xff, 0xff
0x101c:	rsceq		r5, fp, pc, ror r7
0x1020:	strhs		r0, [r0], #-0xf0
0x1024:	stmdavc		r0, {r1, r4, r5, r7, r8, sb, sl, fp, lr}
0x1028:

****************
Platform: Sparc
Code:0x80 0xa0 0x40 0x02 0x85 0xc2 0x60 0x08 0x85 0xe8 0x20 0x01 0x81 0xe8 0x00 0x00 0x90 0x10 0x20 0x01 0xd5 0xf6 0x10 0x16 0x21 0x00 0x00 0x0a 0x86 0x00 0x40 0x02 0x01 0x00 0x00 0x00 0x12 0xbf 0xff 0xff 0x10 0xbf 0xff 0xff 0xa0 0x02 0x00 0x09 0x0d 0xbf 0xff 0xff 0xd4 0x20 0x60 0x00 0xd4 0x4e 0x00 0x16 0x2a 0xc2 0x80 0x03 
Disasm:
0x1000:	cmp	%g1, %g2
	op_count: 2
		operands[0].type: REG = g1
		operands[1].type: REG = g2

0x1004:	jmpl	%o1+8, %g2
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = o1
			operands[0].mem.disp: 0x8
		operands[1].type: REG = g2

0x1008:	restore	%g0, 1, %g2
	op_count: 3
		operands[0].type: REG = g0
		operands[1].type: IMM = 0x1
		operands[2].type: REG = g2

0x100c:	restore	

0x1010:	mov	1, %o0
	op_count: 2
		operands[0].type: IMM = 0x1
		operands[1].type: REG = o0

0x1014:	casx	[%i0], %l6, %o2
	op_count: 3
		operands[0].type: MEM
			operands[0].mem.base: REG = i0
		operands[1].type: REG = l6
		operands[2].type: REG = o2

0x1018:	sethi	0xa, %l0
	op_count: 2
		operands[0].type: IMM = 0xa
		operands[1].type: REG = l0

0x101c:	add	%g1, %g2, %g3
	op_count: 3
		operands[0].type: REG = g1
		operands[1].type: REG = g2
		operands[2].type: REG = g3

0x1020:	nop	

0x1024:	bne	0x1020
	op_count: 1
		operands[0].type: IMM = 0x1020
	Code condition: 265

0x1028:	ba	0x1024
	op_count: 1
		operands[0].type: IMM = 0x1024

0x102c:	add	%o0, %o1, %l0
	op_count: 3
		operands[0].type: REG = o0
		operands[1].type: REG = o1
		operands[2].type: REG = l0

0x1030:	fbg	0x102c
	op_count: 1
		operands[0].type: IMM = 0x102c
	Code condition: 278

0x1034:	st	%o2, [%g1]
	op_count: 2
		operands[0].type: REG = o2
		operands[1].type: MEM
			operands[1].mem.base: REG = g1

0x1038:	ldsb	[%i0+%l6], %o2
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = i0
			operands[0].mem.index: REG = l6
		operands[1].type: REG = o2

0x103c:	brnz,a,pn	%o2, 0x1048
	op_count: 2
		operands[0].type: REG = o2
		operands[1].type: IMM = 0x1048
	Hint code: 5

0x1040:

****************
Platform: SparcV9
Code:0x81 0xa8 0x0a 0x24 0x89 0xa0 0x10 0x20 0x89 0xa0 0x1a 0x60 0x89 0xa0 0x00 0xe0 
Disasm:
0x1000:	fcmps	%f0, %f4
	op_count: 2
		operands[0].type: REG = f0
		operands[1].type: REG = f4

0x1004:	fstox	%f0, %f4
	op_count: 2
		operands[0].type: REG = f0
		operands[1].type: REG = f4

0x1008:	fqtoi	%f0, %f4
	op_count: 2
		operands[0].type: REG = f0
		operands[1].type: REG = f4

0x100c:	fnegq	%f0, %f4
	op_count: 2
		operands[0].type: REG = f0
		operands[1].type: REG = f4

0x1010:

****************
Platform: SystemZ
Code:0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 0xec 0x18 0x00 0x00 0xc1 0x7f 
Disasm:
0x1000:	adb	%f0, 0
	op_count: 2
		operands[0].type: REG = f0
		operands[1].type: IMM = 0x0

0x1006:	a	%r0, 0xfff(%r15, %r1)
	op_count: 2
		operands[0].type: REG = 0
		operands[1].type: MEM
			operands[1].mem.base: REG = 1
			operands[1].mem.index: REG = 15
			operands[1].mem.disp: 0xfff

0x100a:	afi	%r0, -0x80000000
	op_count: 2
		operands[0].type: REG = 0
		operands[1].type: IMM = 0xffffffff80000000

0x1010:	br	%r7
	op_count: 1
		operands[0].type: REG = 7

0x1012:	xiy	0x7ffff(%r15), 0x2a
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = 15
			operands[0].mem.disp: 0x7ffff
		operands[1].type: IMM = 0x2a

0x1018:	xy	%r0, 0x7ffff(%r1, %r15)
	op_count: 2
		operands[0].type: REG = 0
		operands[1].type: MEM
			operands[1].mem.base: REG = 15
			operands[1].mem.index: REG = 1
			operands[1].mem.disp: 0x7ffff

0x101e:	stmg	%r0, %r0, 0(%r15)
	op_count: 3
		operands[0].type: REG = 0
		operands[1].type: REG = 0
		operands[2].type: MEM
			operands[2].mem.base: REG = 15

0x1024:	ear	%r7, %a8
	op_count: 2
		operands[0].type: REG = 7
		operands[1].type: ACREG = 8

0x1028:	clije	%r1, 0xc1, 0x1028
	op_count: 3
		operands[0].type: REG = 1
		operands[1].type: IMM = 0xc1
		operands[2].type: IMM = 0x1028

0x102e:

****************
Platform: X86 16bit (Intel syntax)
Code:0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 
Disasm:
0x1000:	lea	cx, word ptr [si + 0x32]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x4c
	disp: 0x32
	op_count: 2
		operands[0].type: REG = cx
		operands[0].size: 2
		operands[1].type: MEM
			operands[1].mem.base: REG = si
			operands[1].mem.disp: 0x32
		operands[1].size: 2

0x1003:	or	byte ptr [bx + di], al
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x08 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x1
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
			operands[0].mem.index: REG = di
		operands[0].size: 1
		operands[1].type: REG = al
		operands[1].size: 1

0x1005:	fadd	dword ptr [bx + di + 0x34c6]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xd8 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x81
	disp: 0x34c6
	op_count: 1
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
			operands[0].mem.index: REG = di
			operands[0].mem.disp: 0x34c6
		operands[0].size: 4

0x1009:	adc	al, byte ptr [bx + si]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x12 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x0
	disp: 0x0
	op_count: 2
		operands[0].type: REG = al
		operands[0].size: 1
		operands[1].type: MEM
			operands[1].mem.base: REG = bx
			operands[1].mem.index: REG = si
		operands[1].size: 1

0x100b:	add	byte ptr [di], al
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x00 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x5
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = di
		operands[0].size: 1
		operands[1].type: REG = al
		operands[1].size: 1

0x100d:	and	ax, word ptr [bx + di]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x23 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x1
	disp: 0x0
	op_count: 2
		operands[0].type: REG = ax
		operands[0].size: 2
		operands[1].type: MEM
			operands[1].mem.base: REG = bx
			operands[1].mem.index: REG = di
		operands[1].size: 2

0x100f:	add	byte ptr [bx + si], al
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x00 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x0
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
			operands[0].mem.index: REG = si
		operands[0].size: 1
		operands[1].type: REG = al
		operands[1].size: 1

0x1011:	mov	ax, word ptr ss:[si + 0x2391]
	Prefix:0x00 0x36 0x00 0x00 
	Opcode:0x8b 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x84
	disp: 0x2391
	op_count: 2
		operands[0].type: REG = ax
		operands[0].size: 2
		operands[1].type: MEM
			operands[1].mem.segment: REG = ss
			operands[1].mem.base: REG = si
			operands[1].mem.disp: 0x2391
		operands[1].size: 2

0x1016:	add	word ptr [bx + si], ax
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x01 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x0
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
			operands[0].mem.index: REG = si
		operands[0].size: 2
		operands[1].type: REG = ax
		operands[1].size: 2

0x1018:	add	byte ptr [bx + di - 0x73], al
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x00 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x41
	disp: 0xffffff8d
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
			operands[0].mem.index: REG = di
			operands[0].mem.disp: 0xffffffffffffff8d
		operands[0].size: 1
		operands[1].type: REG = al
		operands[1].size: 1

0x101b:	test	byte ptr [bx + di], bh
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x84 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x39
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
			operands[0].mem.index: REG = di
		operands[0].size: 1
		operands[1].type: REG = bh
		operands[1].size: 1

0x101d:	mov	word ptr [bx], sp
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x89 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x67
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
		operands[0].size: 2
		operands[1].type: REG = sp
		operands[1].size: 2

0x1020:	add	byte ptr [di - 0x7679], cl
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x00 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x8d
	disp: 0xffff8987
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = di
			operands[0].mem.disp: 0xffffffffffff8987
		operands[0].size: 1
		operands[1].type: REG = cl
		operands[1].size: 1

0x1024:	add	byte ptr [eax], al
	Prefix:0x00 0x00 0x00 0x67 
	Opcode:0x00 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = eax
		operands[0].size: 1
		operands[1].type: REG = al
		operands[1].size: 1

0x1027:	mov	ah, 0xc6
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xb4 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x0
	disp: 0x0
	imm_count: 1
		imms[1]: 0xc6
	op_count: 2
		operands[0].type: REG = ah
		operands[0].size: 1
		operands[1].type: IMM = 0xc6
		operands[1].size: 1

0x1029:

****************
Platform: X86 32 (AT&T syntax)
Code:0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 
Disasm:
0x1000:	leal	8(%edx, %esi), %ecx
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x4c
	disp: 0x8
	sib: 0x32
		sib_base: edx
		sib_index: esi
		sib_scale: 1
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = edx
			operands[0].mem.index: REG = esi
			operands[0].mem.disp: 0x8
		operands[0].size: 4
		operands[1].type: REG = ecx
		operands[1].size: 4

0x1004:	addl	%ebx, %eax
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x01 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0xd8
	disp: 0x0
	sib: 0x0
	op_count: 2
		operands[0].type: REG = ebx
		operands[0].size: 4
		operands[1].type: REG = eax
		operands[1].size: 4

0x1006:	addl	$0x1234, %esi
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x81 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0xc6
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0x1234
	op_count: 2
		operands[0].type: IMM = 0x1234
		operands[0].size: 4
		operands[1].type: REG = esi
		operands[1].size: 4

0x100c:	addl	$0x123, %eax
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x05 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0x123
	op_count: 2
		operands[0].type: IMM = 0x123
		operands[0].size: 4
		operands[1].type: REG = eax
		operands[1].size: 4

0x1011:	movl	%ss:0x123(%ecx, %edx, 4), %eax
	Prefix:0x00 0x36 0x00 0x00 
	Opcode:0x8b 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x84
	disp: 0x123
	sib: 0x91
		sib_base: ecx
		sib_index: edx
		sib_scale: 4
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.segment: REG = ss
			operands[0].mem.base: REG = ecx
			operands[0].mem.index: REG = edx
			operands[0].mem.scale: 4
			operands[0].mem.disp: 0x123
		operands[0].size: 4
		operands[1].type: REG = eax
		operands[1].size: 4

0x1019:	incl	%ecx
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x41 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	op_count: 1
		operands[0].type: REG = ecx
		operands[0].size: 4

0x101a:	leal	0x6789(%ecx, %edi), %eax
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x84
	disp: 0x6789
	sib: 0x39
		sib_base: ecx
		sib_index: edi
		sib_scale: 1
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = ecx
			operands[0].mem.index: REG = edi
			operands[0].mem.disp: 0x6789
		operands[0].size: 4
		operands[1].type: REG = eax
		operands[1].size: 4

0x1021:	leal	0x6789(%edi), %eax
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x87
	disp: 0x6789
	sib: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = edi
			operands[0].mem.disp: 0x6789
		operands[0].size: 4
		operands[1].type: REG = eax
		operands[1].size: 4

0x1027:	movb	$0xc6, %ah
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xb4 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0xc6
	op_count: 2
		operands[0].type: IMM = 0xc6
		operands[0].size: 1
		operands[1].type: REG = ah
		operands[1].size: 1

0x1029:

****************
Platform: X86 32 (Intel syntax)
Code:0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 
Disasm:
0x1000:	lea	ecx, dword ptr [edx + esi + 8]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x4c
	disp: 0x8
	sib: 0x32
		sib_base: edx
		sib_index: esi
		sib_scale: 1
	op_count: 2
		operands[0].type: REG = ecx
		operands[0].size: 4
		operands[1].type: MEM
			operands[1].mem.base: REG = edx
			operands[1].mem.index: REG = esi
			operands[1].mem.disp: 0x8
		operands[1].size: 4

0x1004:	add	eax, ebx
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x01 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0xd8
	disp: 0x0
	sib: 0x0
	op_count: 2
		operands[0].type: REG = eax
		operands[0].size: 4
		operands[1].type: REG = ebx
		operands[1].size: 4

0x1006:	add	esi, 0x1234
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x81 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0xc6
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0x1234
	op_count: 2
		operands[0].type: REG = esi
		operands[0].size: 4
		operands[1].type: IMM = 0x1234
		operands[1].size: 4

0x100c:	add	eax, 0x123
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x05 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0x123
	op_count: 2
		operands[0].type: REG = eax
		operands[0].size: 4
		operands[1].type: IMM = 0x123
		operands[1].size: 4

0x1011:	mov	eax, dword ptr ss:[ecx + edx*4 + 0x123]
	Prefix:0x00 0x36 0x00 0x00 
	Opcode:0x8b 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x84
	disp: 0x123
	sib: 0x91
		sib_base: ecx
		sib_index: edx
		sib_scale: 4
	op_count: 2
		operands[0].type: REG = eax
		operands[0].size: 4
		operands[1].type: MEM
			operands[1].mem.segment: REG = ss
			operands[1].mem.base: REG = ecx
			operands[1].mem.index: REG = edx
			operands[1].mem.scale: 4
			operands[1].mem.disp: 0x123
		operands[1].size: 4

0x1019:	inc	ecx
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x41 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	op_count: 1
		operands[0].type: REG = ecx
		operands[0].size: 4

0x101a:	lea	eax, dword ptr [ecx + edi + 0x6789]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x84
	disp: 0x6789
	sib: 0x39
		sib_base: ecx
		sib_index: edi
		sib_scale: 1
	op_count: 2
		operands[0].type: REG = eax
		operands[0].size: 4
		operands[1].type: MEM
			operands[1].mem.base: REG = ecx
			operands[1].mem.index: REG = edi
			operands[1].mem.disp: 0x6789
		operands[1].size: 4

0x1021:	lea	eax, dword ptr [edi + 0x6789]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x87
	disp: 0x6789
	sib: 0x0
	op_count: 2
		operands[0].type: REG = eax
		operands[0].size: 4
		operands[1].type: MEM
			operands[1].mem.base: REG = edi
			operands[1].mem.disp: 0x6789
		operands[1].size: 4

0x1027:	mov	ah, 0xc6
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xb4 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0xc6
	op_count: 2
		operands[0].type: REG = ah
		operands[0].size: 1
		operands[1].type: IMM = 0xc6
		operands[1].size: 1

0x1029:

****************
Platform: X86 64 (Intel syntax)
Code:0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00 
Disasm:
0x1000:	push	rbp
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x55 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 8
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	op_count: 1
		operands[0].type: REG = rbp
		operands[0].size: 8

0x1001:	mov	rax, qword ptr [rip + 0x13b8]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8b 0x00 0x00 0x00 
	rex: 0x48
	addr_size: 8
	modrm: 0x5
	disp: 0x13b8
	sib: 0x0
	op_count: 2
		operands[0].type: REG = rax
		operands[0].size: 8
		operands[1].type: MEM
			operands[1].mem.base: REG = rip
			operands[1].mem.disp: 0x13b8
		operands[1].size: 8

0x1008:

****************
Platform: XCore
Code:0xfe 0x0f 0xfe 0x17 0x13 0x17 0xc6 0xfe 0xec 0x17 0x97 0xf8 0xec 0x4f 0x1f 0xfd 0xec 0x37 0x07 0xf2 0x45 0x5b 0xf9 0xfa 0x02 0x06 0x1b 0x10 0x09 0xfd 0xec 0xa7 
Disasm:
0x1000:	get	r11, ed
	op_count: 2
		operands[0].type: REG = r11
		operands[1].type: REG = ed

0x1002:	ldw	et, sp[4]
	op_count: 2
		operands[0].type: REG = et
		operands[1].type: MEM
			operands[1].mem.base: REG = sp
			operands[1].mem.disp: 0x4

0x1004:	setd	res[r3], r4
	op_count: 1
		operands[0].type: REG = r4

0x1006:	init	t[r2]:lr, r1
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = r2
			operands[0].mem.index: REG = lr
		operands[1].type: REG = r1

0x100a:	divu	r9, r1, r3
	op_count: 3
		operands[0].type: REG = r9
		operands[1].type: REG = r1
		operands[2].type: REG = r3

0x100e:	lda16	r9, r3[-r11]
	op_count: 1
		operands[0].type: REG = r9

0x1012:	ldw	dp, dp[0x81c5]
	op_count: 1
		operands[0].type: REG = dp

0x1016:	lmul	r11, r0, r2, r5, r8, r10
	op_count: 6
		operands[0].type: REG = r11
		operands[1].type: REG = r0
		operands[2].type: REG = r2
		operands[3].type: REG = r5
		operands[4].type: REG = r8
		operands[5].type: REG = r10

0x101a:	add	r1, r2, r3
	op_count: 3
		operands[0].type: REG = r1
		operands[1].type: REG = r2
		operands[2].type: REG = r3

0x101c:	ldaw	r8, r2[-9]
	op_count: 1
		operands[0].type: REG = r8

0x1020:

Leaving DriverEntry()