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Added 600mhz, 1.2ghz, and 1.3ghz clock speeds. Changed DVSINT1 to 112…

…5. Adjusted DVSARM settings. Fixed racing conservative governor.
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commit c2e794a37f428927ffd5b3a1e05b6a3bc8117f78 1 parent 7d49da6
@tanimn authored
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35 Kernel/arch/arm/mach-s5pv210/clock.c
@@ -42,14 +42,19 @@ extern unsigned int s5pc11x_cpufreq_index;
#if 0
/*APLL_FOUT, MPLL_FOUT, ARMCLK, HCLK_DSYS*/
static const u32 s5p_sysout_clk_tab_1GHZ[][4] = {
+
// APLL:1300,ARMCLK:1300,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
{1300* MHZ, 667 *MHZ, 1300 *MHZ, 166 *MHZ},
// APLL:1200,ARMCLK:1200,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
{1200* MHZ, 667 *MHZ, 1200 *MHZ, 166 *MHZ},
// APLL:1000,ARMCLK:1000,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
{1000* MHZ, 667 *MHZ, 1000 *MHZ, 166 *MHZ},
+ // APLL:800,ARMCLK:800,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
+ {800* MHZ, 667 *MHZ, 800 *MHZ, 166 *MHZ},
// APLL:800,ARMCLK:600,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
{800* MHZ, 667 *MHZ, 600 *MHZ, 166 *MHZ},
+ // APLL:800,ARMCLK:400,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
+ {800* MHZ, 667 *MHZ, 400 *MHZ, 166 *MHZ},
// APLL:800,ARMCLK:200,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
{800* MHZ, 667 *MHZ, 200 *MHZ, 166 *MHZ},
// APLL:800,ARMCLK:100,HCLK_MSYS:100,MPLL:667,HCLK_DSYS:83,HCLK_PSYS:66,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
@@ -65,7 +70,9 @@ static const u32 s5p_sys_clk_div0_tab_1GHZ[][DIV_TAB_MAX_FIELD] = {
{0, 6, 6, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 1.3ghz
{0, 5, 5, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 1.2ghz
{0, 4, 4, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 1.0ghz
+ {0, 3, 3, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 800mhz
{1, 3, 2, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 600mhz
+ {1, 3, 1, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 400mhz
{3, 3, 0, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 200mhz
{7, 3, 0, 0, 7, 0, 9, 0, 3, 3, 1, 4}, // 100mhz
};
@@ -75,8 +82,10 @@ static const u32 s5p_sys_clk_div0_tab_1GHZ[][DIV_TAB_MAX_FIELD] = {
static const u32 s5p_sys_clk_mps_tab_1GHZ[][6] = {
{325, 6, 1, 667, 12, 1}, // 1.3ghz
{300, 6, 1, 667, 12, 1}, // 1.2ghz
- {250, 6, 1, 667, 12, 1}, // 1ghz
+ {250, 6, 1, 667, 12, 1}, // 1.0ghz
+ {100, 3, 1, 667, 12, 1}, // 800mhz
{100, 3, 1, 667, 12, 1}, // 600mhz
+ {100, 3, 1, 667, 12, 1}, // 400mhz
{100, 3, 1, 667, 12, 1}, // 200mhz
{100, 3, 1, 667, 12, 1}, // 100mhz
};
@@ -163,6 +172,18 @@ struct S5PC110_clk_info clk_info[] = {
.dmc0_div6 = (3<<28),
},
{
+ // APLL:800,ARMCLK:800,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
+ .armclk = 800* MHZ,
+ .apllout = 800* MHZ,
+ .apll_mps = ((100<<16)|(3<<8)|1),
+ .msys_div0 = (0|(3<<4)|(3<<8)|(1<<12)),
+ .mpllout = 667* MHZ,
+ .mpll_mps = ((667<<16)|(12<<8)|(1)),
+ .psys_dsys_div0 = ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
+ .div2val = ((3<<0)|(3<<4)|(3<<8)),
+ .dmc0_div6 = (3<<28),
+},
+{
// APLL:800,ARMCLK:600,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
.armclk = 600* MHZ,
.apllout = 800* MHZ,
@@ -175,6 +196,18 @@ struct S5PC110_clk_info clk_info[] = {
.dmc0_div6 = (3<<28),
},
{
+ // APLL:800,ARMCLK:400,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
+ .armclk = 400* MHZ,
+ .apllout = 800* MHZ,
+ .apll_mps = ((100<<16)|(3<<8)|1),
+ .msys_div0 = (1|(3<<4)|(1<<8)|(1<<12)),
+ .mpllout = 667* MHZ,
+ .mpll_mps = ((667<<16)|(12<<8)|(1)),
+ .psys_dsys_div0 = ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
+ .div2val = ((3<<0)|(3<<4)|(3<<8)),
+ .dmc0_div6 = (3<<28),
+},
+{
// APLL:800,ARMCLK:200,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
.armclk = 200* MHZ,
.apllout = 800* MHZ,
View
BIN  Kernel/arch/arm/mach-s5pv210/victory/.max8998_consumer.c.swp
Binary file not shown
View
51 Kernel/arch/arm/mach-s5pv210/victory/cpu-freq.c
@@ -46,8 +46,8 @@
unsigned int dvfs_change_direction;
#define CLIP_LEVEL(a, b) (a > b ? b : a)
-unsigned int MAXFREQ_LEVEL_SUPPORTED = 5;
-unsigned int S5PC11X_MAXFREQLEVEL = 5;
+unsigned int MAXFREQ_LEVEL_SUPPORTED = 7;
+unsigned int S5PC11X_MAXFREQLEVEL = 7;
unsigned int S5PC11X_FREQ_TAB;
static spinlock_t g_dvfslock = SPIN_LOCK_UNLOCKED;
static unsigned int s5pc11x_cpufreq_level = 3;
@@ -83,20 +83,23 @@ static struct cpufreq_frequency_table s5pc110_freq_table_1GHZ[] = {
{L0, 1300*1000},
{L1, 1200*1000},
{L2, 1000*1000},
- {L3, 600*1000},
- {L4, 200*1000},
- {L5, 100*1000},
+ {L3, 800*1000},
+ {L4, 600*1000},
+ {L5, 400*1000},
+ {L6, 200*1000},
+ {L7, 100*1000},
{0, CPUFREQ_TABLE_END},
};
/*Assigning different index for fast scaling up*/
static unsigned char transition_state_1GHZ[][2] = {
- {1, 0},
- {2, 1},
- {2, 0},
- {3, 1},
- {4, 2},
- {4, 3},
+ {1, 0}, // ->1.3ghz
+ {2, 0}, // ->1.2ghz
+ {3, 0}, // ->1.0ghz
+ {4, 1}, // ->800mhz
+ {5, 2}, // ->600mhz
+ {6, 3}, // ->400mhz
+ {7, 4}, // ->200mhz

Shoud define transition for 100mhz

@tanimn Owner
tanimn added a note

Thanks. coulda sworn I started with 4 of those.

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};
/* frequency */
@@ -132,12 +135,14 @@ static struct cpufreq_frequency_table *s5pc110_freq_table[] = {
};
static unsigned int s5pc110_thres_table_1GHZ[][2] = {
- {60, 80},
- {60, 80},
- {50, 90},
- {30, 90},
- {40, 90},
- {20, 80},
+ {60, 80}, // 1.3ghz
+ {60, 80}, // 1.2ghz
+ {60, 80}, // 1.0ghz
+ {50, 90}, // 800mhz
+ {50, 90}, // 600mhz
+ {50, 90}, // 400mhz
+ {40, 90}, // 200mhz
+ {40, 90}, // 100mhz
};
static unsigned int s5pc110_thres_table_1d2GHZ[][2] = {
@@ -170,9 +175,15 @@ static int get_dvfs_perf_level(enum freq_level_states freq_level, unsigned int *
case LEV_1000MHZ:
freq = 1000 * 1000;
break;
+ case LEV_800MHZ:
+ freq = 800 * 1000;
+ break;
case LEV_600MHZ:
freq = 600 * 1000;
break;
+ case LEV_400MHZ:
+ freq = 400 * 1000;
+ break;
case LEV_200MHZ:
freq = 200 * 1000;
break;
@@ -717,9 +728,9 @@ static int __init s5pc110_cpu_init(struct cpufreq_policy *policy)
g_dvfs_high_lock_limit = 5;
#else
S5PC11X_FREQ_TAB = 0;
- S5PC11X_MAXFREQLEVEL = 5;
- MAXFREQ_LEVEL_SUPPORTED = 6;
- g_dvfs_high_lock_limit = 5;
+ S5PC11X_MAXFREQLEVEL = 7;
+ MAXFREQ_LEVEL_SUPPORTED = 8;
+ g_dvfs_high_lock_limit = 7;
#endif
printk("S5PC11X_FREQ_TAB=%d , S5PC11X_MAXFREQLEVEL=%d\n",S5PC11X_FREQ_TAB,S5PC11X_MAXFREQLEVEL);
View
26 Kernel/arch/arm/mach-s5pv210/victory/max8998_consumer.c
@@ -87,10 +87,12 @@ enum PMIC_VOLTAGE {
static const unsigned int frequency_match_1GHZ[][4] = {
/* frequency, Mathced VDD ARM voltage , Matched VDD INT*/
#if 1
- {1300000, 1325, 1100, 0},
- {1200000, 1325, 1100, 0},
- {100000, 1225, 1100, 1},
- {600000, 1125, 1100, 2},
+ {1300000, 1325, 1125, 0},
+ {1200000, 1325, 1125, 0},
+ {100000, 1200, 1125, 1},
@gzub
gzub added a note

This looks like a typo to me... shouldn't it be 1000000

@tanimn Owner
tanimn added a note

Thanks for the catch. Must have stumbled a few keystrokes on the way there. :)

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+ {800000, 1200, 1125, 2},
+ {600000, 1100, 1125, 2},
+ {400000, 1100, 1125, 2},
{200000, 950, 1000, 4},
{100000, 950, 1000, 5},
#else //just for dvs test
@@ -146,10 +148,11 @@ static const unsigned int dvs_volt_table_1GHZ[][3] = {
{L0, DVSARM1, DVSINT1}, // 1.3ghz
{L1, DVSARM1, DVSINT1}, // 1.2ghz
{L2, DVSARM2, DVSINT1}, // 1.0ghz
- {L3, DVSARM3, DVSINT1}, // 600mhz
- {L4, DVSARM4, DVSINT2}, // 200mhz
- {L5, DVSARM4, DVSINT2}, // 100mhz
-// {L6, DVSARM4, DVSINT2},
+ {L3, DVSARM2, DVSINT1}, // 800mhz
+ {L4, DVSARM3, DVSINT1}, // 600mhz
+ {L5, DVSARM3, DVSINT1}, // 400mhz
+ {L6, DVSARM4, DVSINT2}, // 200mhz
+ {L7, DVSARM4, DVSINT2}, // 100mhz
};
@@ -160,10 +163,10 @@ const unsigned int (*dvs_volt_table[2])[3] = {
static const unsigned int dvs_arm_voltage_set[][2] = {
{DVSARM1, 1325},
- {DVSARM2, 1225},
- {DVSARM3, 1125},
+ {DVSARM2, 1200},
+ {DVSARM3, 1100},
{DVSARM4, 950},
- {DVSINT1, 1100},
+ {DVSINT1, 1125},
{DVSINT2, 1000},
};
#endif
@@ -327,6 +330,7 @@ int set_gpio_dvs(enum perf_level p_lv)
case L4:
case L5:
case L6:
+ case L7:
//writel(((readl(S5PV210_GPH0DAT) & ~PMIC_SET_MASK) | PMIC_SET1_BIT | PMIC_SET2_BIT | PMIC_SET3_BIT), S5PV210_GPH0DAT);
//BUCK_1_EN_A enabled
gpio_set_value(S5PV210_GPB(6),1);
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