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Variable undervolting via sysfs UV_mV_table from raspdeep.

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commit faf312174604de2be598874115851335f18cd932 1 parent a8560f3
@tanimn authored
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98 Kernel/arch/arm/mach-s5pv210/clock.c
@@ -71,7 +71,7 @@ static const u32 s5p_sys_clk_div0_tab_1GHZ[][DIV_TAB_MAX_FIELD] = {
{0, 5, 5, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 1.2ghz
{0, 4, 4, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 1.0ghz
{0, 3, 3, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 800mhz
- {1, 3, 2, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 600mhz
+ {0, 2, 2, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 600mhz
{1, 3, 1, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 400mhz
{3, 3, 0, 1, 3, 1, 4, 1, 3, 3, 0, 3}, // 200mhz
{7, 3, 0, 0, 7, 0, 9, 0, 3, 3, 1, 4}, // 100mhz
@@ -139,97 +139,97 @@ struct S5PC110_clk_info clk_info[] = {
// APLL:1300,ARMCLK:1300,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
.armclk = 1300* MHZ,
.apllout = 1300* MHZ,
- .apll_mps = ((325<<16)|(6<<8)|1),
- .msys_div0 = (0|(6<<4)|(6<<8)|(1<<12)),
+ .apll_mps = 0x1450601, // ((325<<16)|(6<<8)|1),
+ .msys_div0 = 0x1660, // (0|(6<<4)|(6<<8)|(1<<12)),
.mpllout = 667* MHZ,
- .mpll_mps = ((667<<16)|(12<<8)|(1)),
- .psys_dsys_div0 = ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
- .div2val = ((3<<0)|(3<<4)|(3<<8)),
- .dmc0_div6 = (3<<28),
+ .mpll_mps = 0x29B0C01, // ((667<<16)|(12<<8)|(1)),
+ .psys_dsys_div0 = 0x14130000, // ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
+ .div2val = 0x333, // ((3<<0)|(3<<4)|(3<<8)),
+ .dmc0_div6 = 0x30000000, // (3<<28),
},
{
// APLL:1200,ARMCLK:1200,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
.armclk = 1200* MHZ,
.apllout = 1200* MHZ,
- .apll_mps = ((300<<16)|(6<<8)|1),
- .msys_div0 = (0|(5<<4)|(5<<8)|(1<<12)),
+ .apll_mps = 0x12C0601, // 0x960301, // ((300<<16)|(6<<8)|1),
+ .msys_div0 = 0x1550, // (0|(5<<4)|(5<<8)|(1<<12)),
.mpllout = 667* MHZ,
- .mpll_mps = ((667<<16)|(12<<8)|(1)),
- .psys_dsys_div0 = ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
- .div2val = ((3<<0)|(3<<4)|(3<<8)),
- .dmc0_div6 = (3<<28),
+ .mpll_mps = 0x29B0C01, // ((667<<16)|(12<<8)|(1)),
+ .psys_dsys_div0 = 0x14130000, // ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
+ .div2val = 0x333, // ((3<<0)|(3<<4)|(3<<8)),
+ .dmc0_div6 = 0x30000000, // (3<<28),
},
{
// APLL:1000,ARMCLK:1000,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
.armclk = 1000* MHZ,
.apllout = 1000* MHZ,
- .apll_mps = ((250<<16)|(6<<8)|1),
- .msys_div0 = (0|(4<<4)|(4<<8)|(1<<12)),
+ .apll_mps = 0xFA0601, // ((250<<16)|(6<<8)|1),
+ .msys_div0 = 0x1440, // (0|(4<<4)|(4<<8)|(1<<12)),
.mpllout = 667* MHZ,
- .mpll_mps = ((667<<16)|(12<<8)|(1)),
- .psys_dsys_div0 = ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
- .div2val = ((3<<0)|(3<<4)|(3<<8)),
- .dmc0_div6 = (3<<28),
+ .mpll_mps = 0x29B0C01, // ((667<<16)|(12<<8)|(1)),
+ .psys_dsys_div0 = 0x14130000, // ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
+ .div2val = 0x333, // ((3<<0)|(3<<4)|(3<<8)),
+ .dmc0_div6 = 0x30000000, // (3<<28),
},
{
// APLL:800,ARMCLK:800,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
.armclk = 800* MHZ,
.apllout = 800* MHZ,
- .apll_mps = ((100<<16)|(3<<8)|1),
- .msys_div0 = (0|(3<<4)|(3<<8)|(1<<12)),
+ .apll_mps = 0x640301, // ((100<<16)|(3<<8)|1),
+ .msys_div0 = 0x1330, // (0|(3<<4)|(3<<8)|(1<<12)),
.mpllout = 667* MHZ,
- .mpll_mps = ((667<<16)|(12<<8)|(1)),
- .psys_dsys_div0 = ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
- .div2val = ((3<<0)|(3<<4)|(3<<8)),
- .dmc0_div6 = (3<<28),
+ .mpll_mps = 0x29B0C01, // ((667<<16)|(12<<8)|(1)),
+ .psys_dsys_div0 = 0x14130000, // ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
+ .div2val = 0x333, // ((3<<0)|(3<<4)|(3<<8)),
+ .dmc0_div6 = 0x30000000, // (3<<28),
},
{
// APLL:800,ARMCLK:600,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
.armclk = 600* MHZ,
.apllout = 800* MHZ,
- .apll_mps = ((100<<16)|(3<<8)|1),
- .msys_div0 = (1|(3<<4)|(2<<8)|(1<<12)),
+ .apll_mps = 0x640301, // ((100<<16)|(3<<8)|1),
+ .msys_div0 = 0x1221, // (1|(2<<4)|(2<<8)|(1<<12)),
.mpllout = 667* MHZ,
- .mpll_mps = ((667<<16)|(12<<8)|(1)),
- .psys_dsys_div0 = ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
- .div2val = ((3<<0)|(3<<4)|(3<<8)),
- .dmc0_div6 = (3<<28),
+ .mpll_mps = 0x29B0C01, // ((667<<16)|(12<<8)|(1)),
+ .psys_dsys_div0 = 0x14130000, // ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
+ .div2val = 0x333, // ((3<<0)|(3<<4)|(3<<8)),
+ .dmc0_div6 = 0x30000000, // (3<<28),
},
{
// APLL:800,ARMCLK:400,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
.armclk = 400* MHZ,
.apllout = 800* MHZ,
- .apll_mps = ((100<<16)|(3<<8)|1),
- .msys_div0 = (1|(3<<4)|(1<<8)|(1<<12)),
+ .apll_mps = 0x640301, // ((100<<16)|(3<<8)|1),
+ .msys_div0 = 0x1131, // (1|(3<<4)|(1<<8)|(1<<12)),
.mpllout = 667* MHZ,
- .mpll_mps = ((667<<16)|(12<<8)|(1)),
- .psys_dsys_div0 = ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
- .div2val = ((3<<0)|(3<<4)|(3<<8)),
- .dmc0_div6 = (3<<28),
+ .mpll_mps = 0x29B0C01, // ((667<<16)|(12<<8)|(1)),
+ .psys_dsys_div0 = 0x14130000, // ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
+ .div2val = 0x333, // ((3<<0)|(3<<4)|(3<<8)),
+ .dmc0_div6 = 0x30000000, // (3<<28),
},
{
// APLL:800,ARMCLK:200,HCLK_MSYS:200,MPLL:667,HCLK_DSYS:166,HCLK_PSYS:133,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
.armclk = 200* MHZ,
.apllout = 800* MHZ,
- .apll_mps = ((100<<16)|(3<<8)|1),
- .msys_div0 = (3|(3<<4)|(0<<8)|(1<<12)),
+ .apll_mps = 0x640301, // ((100<<16)|(3<<8)|1),
+ .msys_div0 = 0x1033, // (3|(3<<4)|(0<<8)|(1<<12)),
.mpllout = 667* MHZ,
- .mpll_mps = ((667<<16)|(12<<8)|(1)),
- .psys_dsys_div0 = ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
- .div2val = ((3<<0)|(3<<4)|(3<<8)),
- .dmc0_div6 = (3<<28),
+ .mpll_mps = 0x29B0C01, // ((667<<16)|(12<<8)|(1)),
+ .psys_dsys_div0 = 0x14130000, // ((3<<16)|(1<<20)|(4<<24)|(1<<28)),
+ .div2val = 0x333, // ((3<<0)|(3<<4)|(3<<8)),
+ .dmc0_div6 = 0x30000000, // (3<<28),
},
{
// APLL:800,ARMCLK:100,HCLK_MSYS:100,MPLL:667,HCLK_DSYS:83,HCLK_PSYS:66,PCLK_MSYS:100,PCLK_DSYS:83,PCLK_PSYS:66
.armclk = 100* MHZ,
.apllout = 800* MHZ,
- .apll_mps = ((100<<16)|(3<<8)|1),
- .msys_div0 = (7|(3<<4)|(0<<8)|(0<<12)),
+ .apll_mps = 0x640301, // ((100<<16)|(3<<8)|1),
+ .msys_div0 = 0x37, // (7|(3<<4)|(0<<8)|(0<<12)),
.mpllout = 667* MHZ,
- .mpll_mps = ((667<<16)|(12<<8)|(1)),
- .psys_dsys_div0 = ((7<<16)|(0<<20)|(9<<24)|(0<<28)),
- .div2val = ((3<<0)|(3<<4)|(3<<8)),
- .dmc0_div6 = (7<<28),
+ .mpll_mps = 0x29B0C01, // ((667<<16)|(12<<8)|(1)),
+ .psys_dsys_div0 = 0x9070000, // ((7<<16)|(0<<20)|(9<<24)|(0<<28)),
+ .div2val = 0x333, // ((3<<0)|(3<<4)|(3<<8)),
+ .dmc0_div6 = 0x70000000, // (7<<28),
}
};
View
4 Kernel/arch/arm/mach-s5pv210/victory/cpu-freq.c
@@ -37,7 +37,7 @@
#define ENABLE_DVFS_LOCK_HIGH 1
#define USE_DVS
-#define GPIO_BASED_DVS
+// #define GPIO_BASED_DVS
#define DBG(fmt...)
//#define DBG(fmt...) printk(fmt)
@@ -99,7 +99,7 @@ static unsigned char transition_state_1GHZ[][2] = {
{4, 1}, // ->800mhz
{5, 2}, // ->600mhz
{6, 3}, // ->400mhz
- {7, 4}, // ->200mhz
+ {7, 3}, // ->200mhz
};
/* frequency */
View
18 Kernel/arch/arm/mach-s5pv210/victory/max8998_consumer.c
@@ -43,7 +43,7 @@
#define PMIC_INT 1
#define PMIC_BOTH 2
-#define DECREASE_DVFS_DELAY
+// #define DECREASE_DVFS_DELAY
#ifdef DECREASE_DVFS_DELAY
#define PMIC_SET_MASK (0x38) //(0x7 << 3)
@@ -51,11 +51,13 @@
#define PMIC_SET2_BIT (0x10) //(0x1 << 4)
#define PMIC_SET3_BIT (0x20) //(0x1 << 5)
#else
-#define PMIC_ARM_MASK (0x3 << 3)
-#define PMIC_SET1_HIGH (0x1 << 3)
-#define PMIC_SET2_HIGH (0x1 << 4)
+#define PMIC_ARM_MASK (0x18) // (0x3 << 3)
+#define PMIC_SET1_HIGH (0x8) // (0x1 << 3)
+#define PMIC_SET2_HIGH (0x10) // (0x1 << 4)
#endif
+extern int exp_UV_mV[8];
+
#ifndef CONFIG_CPU_FREQ
unsigned int S5PC11X_FREQ_TAB = 1;
#endif
@@ -132,6 +134,8 @@ static struct regulator *Reg_Arm = NULL, *Reg_Int = NULL;
static unsigned int s_arm_voltage=0, s_int_voltage=0;
+unsigned long set1_gpio, set2_gpio, set3_gpio;
+
#ifndef DECREASE_DVFS_DELAY
/*only 4 Arm voltages and 2 internal voltages possible*/
static const unsigned int dvs_volt_table_800MHZ[][3] = {
@@ -181,14 +185,14 @@ static int set_max8998(unsigned int pwr, enum perf_level p_lv)
DBG("%s : p_lv = %d : pwr = %d \n", __FUNCTION__, p_lv,pwr);
if(pwr == PMIC_ARM) {
- voltage = frequency_match_tab[p_lv][pwr + 1];
+ voltage = frequency_match_tab[p_lv][pwr + 1] - exp_UV_mV[p_lv];
if(voltage == s_arm_voltage)
return ret;
pmic_val = voltage * 1000;
- DBG("regulator_set_voltage =%d\n",voltage);
+ DBG("regulator_set_voltage =%dmA @ %dMHz-%d UV=%d\n",voltage,frequency_match_tab[p_lv][pwr]/1000,p_lv,exp_UV_mV[p_lv]);
/*set Arm voltage*/
ret = regulator_set_voltage(Reg_Arm,pmic_val,pmic_val);
if(ret != 0)
@@ -409,7 +413,7 @@ int set_voltage_dvs(enum perf_level p_lv)
set_gpio_dvs(p_lv);
udelay(delay);
- DBG("[PWR] %s : level (%d -> %d), delay (%u)\n", __func__, step_curr, p_lv, delay);
+ DBG("[PWR] %s : level (%d -> %d), delay (%u)\n", __func__, frequency_match_tab[step_curr][0], frequency_match_tab[p_lv][0], delay);
step_curr = p_lv;
View
18 Kernel/drivers/cpufreq/cpufreq.c
@@ -32,6 +32,7 @@
#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_CORE, \
"cpufreq-core", msg)
+int exp_UV_mV[8];
/**
* The "cpufreq driver" - the arch- or hardware-dependent low
* level driver of CPUFreq support, and its spinlock. This lock
@@ -573,6 +574,21 @@ static ssize_t show_scaling_governor(struct cpufreq_policy *policy, char *buf)
return -EINVAL;
}
+static ssize_t show_UV_mV_table(struct cpufreq_policy *policy, char *buf)
+{
+ return sprintf(buf, "%d %d %d %d %d %d %d %d\n", exp_UV_mV[0],exp_UV_mV[1],exp_UV_mV[2],exp_UV_mV[3],exp_UV_mV[4],exp_UV_mV[5],exp_UV_mV[6],exp_UV_mV[7]);
+}
+
+static ssize_t store_UV_mV_table(struct cpufreq_policy *policy, const char *buf, size_t count)
+{
+ unsigned int ret =-EINVAL;
+
+ ret = sscanf(buf, "%d %d %d %d %d %d %d %d", &exp_UV_mV[0],&exp_UV_mV[1],&exp_UV_mV[2],&exp_UV_mV[3],&exp_UV_mV[4],&exp_UV_mV[5],&exp_UV_mV[6],&exp_UV_mV[7]);
+ if (ret != 1)
+ return -EINVAL;
+ else
+ return count;
+}
/**
* store_scaling_governor - store policy for the specified CPU
@@ -746,6 +762,7 @@ define_one_ro(affected_cpus);
define_one_rw(scaling_min_freq);
define_one_rw(scaling_max_freq);
define_one_rw(scaling_governor);
+define_one_rw(UV_mV_table);
define_one_rw(scaling_setspeed);
define_one_rw(scaling_setlog);
#if defined SET_AUDIO_LOG
@@ -761,6 +778,7 @@ static struct attribute *default_attrs[] = {
&affected_cpus.attr,
&related_cpus.attr,
&scaling_governor.attr,
+ &UV_mV_table.attr,
&scaling_driver.attr,
&scaling_available_governors.attr,
&scaling_setspeed.attr,
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