System on Chip SPARC V8 using leon3 CPU by Gaisler. C++, vhdl, v files.
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Author:   GNSS Sensor Limited
license:  GPL

  The main objective of this project is to provide a reference 
C++ design for the development of the processor system, which is
build on the Leon3 core by Aeroflex Gaisler and includes our
proprietary GNSS navigation module. This software allows:
  - Load execution code into SoC simulator's internal SRAM using 
    only compilation output file (.elf).
  - generates test-bench patterns of the whole system or
    any single module and use them directly during RTL 
    simulation as reference or use them to compute switching 
  - JTAG and UART signals generators are also included.
  - Intertial sensors simulators implemented as SPI slave devices

Project structure:
  +-- source:- lib: Is a cycle truth C++ system simulator, which includes
  |       |         CPU Leon3 + DSU3; MMU with caches; Internal SRAM; JTAG;
  |       |         APB bridge; APB UART; IRQ controller and Timer Unit.
  |       |         RF front-end and inertial sensors controllers.
  |       |         GNSS module (only by request)
  |       |
  |       +--- app: This is a Control application which includes: 
  |       |         Elf file loader integrated with the disassembler function;
  |       |         JTAG and UART ports transmitters.
  |       |
  |       |         Software makes simulation of the next SoC external signals:
  |       |           1. Common: SRESETn, SCLK(66MHz)
  |       |           2. JTAG signals: TCK, TMS, TDO, TRESET;
  |       |           3. UART signals: TX, RX, CTS, RTS
  |       |           4. SPI modules for the MAX2769 RF chip
  |       |           5. GNSS signals: AdcClk, I, Q;
  |       |           6. SPI interfaces of the MEMS (gyroscope and accelerometer)
  |       |
  |       +--- firmware: Firmware source code and makefiles to
  |       |         generate *.elf file.
  |       |
  |       |         Example "Hello, world" firmware:
  |       |            1. It makes UART initialization and formatted output;
  |       |            2. IRQ table initialization
  |       |
  |       +--- common: Common constants and interface structure description
  +-- vhdl:- Source VHDL code by Aeroflex Gaisler
  |                    It contains VHDL testbenches files which is using
  |                    generated reference patterns.
  +-- ProjectFiles2005:- MS Visual Studio 2005 project files