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Merge pull request #101 from prattmic/master

Add support for all core registers on the STM32F4DISCOVERY, including floating point registers.
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commit fde8b6b24e8c3b9201195c78663a40f05fa93d1e 2 parents b9eeab4 + c6274f0
@texane authored
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3  AUTHORS
@@ -14,4 +14,5 @@ bravikov@gmail.com
jnosky - codegrinder69@hotmail.com
marpe@mimuw.edu.pl
marco.cassinerio@gmail.com
-jserv@0xlab.org
+jserv@0xlab.org
+michael@pratt.im
View
115 gdbserver/gdb-server.c
@@ -192,6 +192,71 @@ int main(int argc, char** argv) {
return 0;
}
+static const char* const target_description_F4 =
+ "<?xml version=\"1.0\"?>"
+ "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
+ "<target version=\"1.0\">"
+ " <architecture>arm</architecture>"
+ " <feature name=\"org.gnu.gdb.arm.m-profile\">"
+ " <reg name=\"r0\" bitsize=\"32\"/>"
+ " <reg name=\"r1\" bitsize=\"32\"/>"
+ " <reg name=\"r2\" bitsize=\"32\"/>"
+ " <reg name=\"r3\" bitsize=\"32\"/>"
+ " <reg name=\"r4\" bitsize=\"32\"/>"
+ " <reg name=\"r5\" bitsize=\"32\"/>"
+ " <reg name=\"r6\" bitsize=\"32\"/>"
+ " <reg name=\"r7\" bitsize=\"32\"/>"
+ " <reg name=\"r8\" bitsize=\"32\"/>"
+ " <reg name=\"r9\" bitsize=\"32\"/>"
+ " <reg name=\"r10\" bitsize=\"32\"/>"
+ " <reg name=\"r11\" bitsize=\"32\"/>"
+ " <reg name=\"r12\" bitsize=\"32\"/>"
+ " <reg name=\"sp\" bitsize=\"32\" type=\"data_ptr\"/>"
+ " <reg name=\"lr\" bitsize=\"32\"/>"
+ " <reg name=\"pc\" bitsize=\"32\" type=\"code_ptr\"/>"
+ " <reg name=\"xpsr\" bitsize=\"32\" regnum=\"25\"/>"
+ " <reg name=\"msp\" bitsize=\"32\" regnum=\"26\" type=\"data_ptr\" group=\"general\" />"
+ " <reg name=\"psp\" bitsize=\"32\" regnum=\"27\" type=\"data_ptr\" group=\"general\" />"
+ " <reg name=\"control\" bitsize=\"8\" regnum=\"28\" type=\"int\" group=\"general\" />"
+ " <reg name=\"faultmask\" bitsize=\"8\" regnum=\"29\" type=\"int\" group=\"general\" />"
+ " <reg name=\"basepri\" bitsize=\"8\" regnum=\"30\" type=\"int\" group=\"general\" />"
+ " <reg name=\"primask\" bitsize=\"8\" regnum=\"31\" type=\"int\" group=\"general\" />"
+ " <reg name=\"s0\" bitsize=\"32\" regnum=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s1\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s2\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s3\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s4\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s5\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s6\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s7\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s8\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s9\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s10\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s11\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s12\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s13\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s14\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s15\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s16\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s17\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s18\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s19\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s20\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s21\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s22\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s23\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s24\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s25\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s26\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s27\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s28\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s29\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s30\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"s31\" bitsize=\"32\" type=\"float\" group=\"float\" />"
+ " <reg name=\"fpscr\" bitsize=\"32\" type=\"int\" group=\"float\" />"
+ " </feature>"
+ "</target>";
+
static const char* const memory_map_template_F4 =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
@@ -649,7 +714,12 @@ int serve(stlink_t *sl, int port) {
#endif
if(!strcmp(queryName, "Supported")) {
- reply = strdup("PacketSize=3fff;qXfer:memory-map:read+");
+ if(sl->chip_id==STM32_CHIPID_F4) {
+ reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+");
+ }
+ else {
+ reply = strdup("PacketSize=3fff;qXfer:memory-map:read+");
+ }
} else if(!strcmp(queryName, "Xfer")) {
char *type, *op, *__s_addr, *s_length;
char *tok = params;
@@ -674,6 +744,9 @@ int serve(stlink_t *sl, int port) {
if(!strcmp(type, "memory-map") && !strcmp(op, "read"))
data = current_memory_map;
+ if(!strcmp(type, "features") && !strcmp(op, "read"))
+ data = target_description_F4;
+
if(data) {
unsigned data_length = strlen(data);
if(addr + length > data_length)
@@ -881,6 +954,30 @@ int serve(stlink_t *sl, int port) {
} else if(id == 0x19) {
stlink_read_reg(sl, 16, &regp);
myreg = htonl(regp.xpsr);
+ } else if(id == 0x1A) {
+ stlink_read_reg(sl, 17, &regp);
+ myreg = htonl(regp.main_sp);
+ } else if(id == 0x1B) {
+ stlink_read_reg(sl, 18, &regp);
+ myreg = htonl(regp.process_sp);
+ } else if(id == 0x1C) {
+ stlink_read_unsupported_reg(sl, id, &regp);
+ myreg = htonl(regp.control);
+ } else if(id == 0x1D) {
+ stlink_read_unsupported_reg(sl, id, &regp);
+ myreg = htonl(regp.faultmask);
+ } else if(id == 0x1E) {
+ stlink_read_unsupported_reg(sl, id, &regp);
+ myreg = htonl(regp.basepri);
+ } else if(id == 0x1F) {
+ stlink_read_unsupported_reg(sl, id, &regp);
+ myreg = htonl(regp.primask);
+ } else if(id >= 0x20 && id < 0x40) {
+ stlink_read_unsupported_reg(sl, id, &regp);
+ myreg = htonl(regp.s[id-0x20]);
+ } else if(id == 0x40) {
+ stlink_read_unsupported_reg(sl, id, &regp);
+ myreg = htonl(regp.fpscr);
} else {
reply = strdup("E00");
}
@@ -902,6 +999,22 @@ int serve(stlink_t *sl, int port) {
stlink_write_reg(sl, ntohl(value), reg);
} else if(reg == 0x19) {
stlink_write_reg(sl, ntohl(value), 16);
+ } else if(reg == 0x1A) {
+ stlink_write_reg(sl, ntohl(value), 17);
+ } else if(reg == 0x1B) {
+ stlink_write_reg(sl, ntohl(value), 18);
+ } else if(reg == 0x1C) {
+ stlink_write_unsupported_reg(sl, ntohl(value), reg, &regp);
+ } else if(reg == 0x1D) {
+ stlink_write_unsupported_reg(sl, ntohl(value), reg, &regp);
+ } else if(reg == 0x1E) {
+ stlink_write_unsupported_reg(sl, ntohl(value), reg, &regp);
+ } else if(reg == 0x1F) {
+ stlink_write_unsupported_reg(sl, ntohl(value), reg, &regp);
+ } else if(reg >= 0x20 && reg < 0x40) {
+ stlink_write_unsupported_reg(sl, ntohl(value), reg, &regp);
+ } else if(reg == 0x40) {
+ stlink_write_unsupported_reg(sl, ntohl(value), reg, &regp);
} else {
reply = strdup("E00");
}
View
47 src/stlink-common.c
@@ -577,6 +577,11 @@ void stlink_read_all_regs(stlink_t *sl, reg *regp) {
sl->backend->read_all_regs(sl, regp);
}
+void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) {
+ DLOG("*** stlink_read_all_unsupported_regs ***\n");
+ sl->backend->read_all_unsupported_regs(sl, regp);
+}
+
void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
DLOG("*** stlink_write_reg\n");
sl->backend->write_reg(sl, reg, idx);
@@ -594,6 +599,48 @@ void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
sl->backend->read_reg(sl, r_idx, regp);
}
+void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) {
+ int r_convert;
+
+ DLOG("*** stlink_read_unsupported_reg\n");
+ DLOG(" (%d) ***\n", r_idx);
+
+ /* Convert to values used by DCRSR */
+ if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
+ r_convert = 0x14;
+ } else if (r_idx == 0x40) { /* FPSCR */
+ r_convert = 0x21;
+ } else if (r_idx >= 0x20 && r_idx < 0x40) {
+ r_convert = 0x40 + (r_idx - 0x20);
+ } else {
+ fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
+ return;
+ }
+
+ sl->backend->read_unsupported_reg(sl, r_convert, regp);
+}
+
+void stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) {
+ int r_convert;
+
+ DLOG("*** stlink_write_unsupported_reg\n");
+ DLOG(" (%d) ***\n", r_idx);
+
+ /* Convert to values used by DCRSR */
+ if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
+ r_convert = r_idx; /* The backend function handles this */
+ } else if (r_idx == 0x40) { /* FPSCR */
+ r_convert = 0x21;
+ } else if (r_idx >= 0x20 && r_idx < 0x40) {
+ r_convert = 0x40 + (r_idx - 0x20);
+ } else {
+ fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
+ return;
+ }
+
+ sl->backend->write_unsupported_reg(sl, val, r_convert, regp);
+}
+
unsigned int is_core_halted(stlink_t *sl) {
/* return non zero if core is halted */
stlink_status(sl);
View
14 src/stlink-common.h
@@ -112,6 +112,8 @@ extern "C" {
/* Cortex™-M3 Technical Reference Manual */
/* Debug Halting Control and Status Register */
#define DHCSR 0xe000edf0
+#define DCRSR 0xe000edf4
+#define DCRDR 0xe000edf8
#define DBGKEY 0xa05f0000
/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
@@ -238,11 +240,17 @@ extern "C" {
typedef struct {
uint32_t r[16];
+ uint32_t s[32];
uint32_t xpsr;
uint32_t main_sp;
uint32_t process_sp;
uint32_t rw;
uint32_t rw2;
+ uint8_t control;
+ uint8_t faultmask;
+ uint8_t basepri;
+ uint8_t primask;
+ uint32_t fpscr;
} reg;
typedef uint32_t stm32_addr_t;
@@ -295,6 +303,9 @@ extern "C" {
void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
void (*read_all_regs) (stlink_t *sl, reg * regp);
void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
+ void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
+ void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
+ void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
void (*step) (stlink_t * stl);
int (*current_mode) (stlink_t * stl);
@@ -360,7 +371,10 @@ extern "C" {
void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
void stlink_read_all_regs(stlink_t *sl, reg *regp);
+ void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
+ void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
+ void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
void stlink_step(stlink_t *sl);
int stlink_current_mode(stlink_t *sl);
View
81 src/stlink-usb.c
@@ -576,6 +576,84 @@ void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) {
}
}
+/* See section C1.6 of the ARMv7-M Architecture Reference Manual */
+void _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) {
+ uint32_t r;
+
+ sl->q_buf[0] = (unsigned char) r_idx;
+ for (int i = 1; i < 4; i++) {
+ sl->q_buf[i] = 0;
+ }
+
+ _stlink_usb_write_mem32(sl, DCRSR, 4);
+ _stlink_usb_read_mem32(sl, DCRDR, 4);
+
+ r = read_uint32(sl->q_buf, 0);
+ DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r);
+
+ switch (r_idx) {
+ case 0x14:
+ regp->primask = (uint8_t) (r & 0xFF);
+ regp->basepri = (uint8_t) ((r>>8) & 0xFF);
+ regp->faultmask = (uint8_t) ((r>>16) & 0xFF);
+ regp->control = (uint8_t) ((r>>24) & 0xFF);
+ break;
+ case 0x21:
+ regp->fpscr = r;
+ break;
+ default:
+ regp->s[r_idx - 0x40] = r;
+ break;
+ }
+}
+
+void _stlink_usb_read_all_unsupported_regs(stlink_t *sl, reg *regp) {
+ _stlink_usb_read_unsupported_reg(sl, 0x14, regp);
+ _stlink_usb_read_unsupported_reg(sl, 0x21, regp);
+
+ for (int i = 0; i < 32; i++) {
+ _stlink_usb_read_unsupported_reg(sl, 0x40+i, regp);
+ }
+}
+
+/* See section C1.6 of the ARMv7-M Architecture Reference Manual */
+void _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) {
+ if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
+ /* These are held in the same register */
+ _stlink_usb_read_unsupported_reg(sl, 0x14, regp);
+
+ val = (uint8_t) (val>>24);
+
+ switch (r_idx) {
+ case 0x1C: /* control */
+ val = (((uint32_t) val) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) regp->primask);
+ break;
+ case 0x1D: /* faultmask */
+ val = (((uint32_t) regp->control) << 24) | (((uint32_t) val) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) regp->primask);
+ break;
+ case 0x1E: /* basepri */
+ val = (((uint32_t) regp->control) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) val) << 8) | ((uint32_t) regp->primask);
+ break;
+ case 0x1F: /* primask */
+ val = (((uint32_t) regp->control) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) val);
+ break;
+ }
+
+ r_idx = 0x14;
+ }
+
+ write_uint32(sl->q_buf, val);
+
+ _stlink_usb_write_mem32(sl, DCRDR, 4);
+
+ sl->q_buf[0] = (unsigned char) r_idx;
+ sl->q_buf[1] = 0;
+ sl->q_buf[2] = 0x01;
+ sl->q_buf[3] = 0;
+
+ _stlink_usb_write_mem32(sl, DCRSR, 4);
+}
+
void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) {
struct stlink_libusb * const slu = sl->backend_data;
unsigned char* const data = sl->q_buf;
@@ -616,6 +694,9 @@ stlink_backend_t _stlink_usb_backend = {
_stlink_usb_write_mem8,
_stlink_usb_read_all_regs,
_stlink_usb_read_reg,
+ _stlink_usb_read_all_unsupported_regs,
+ _stlink_usb_read_unsupported_reg,
+ _stlink_usb_write_unsupported_reg,
_stlink_usb_write_reg,
_stlink_usb_step,
_stlink_usb_current_mode,
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