{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":369551840,"defaultBranch":"main","name":"Multicore_processor_SystemVerilog_design","ownerLogin":"tharinduSamare","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2021-05-21T13:55:01.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/56247986?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1627743713.6312902","currentOid":""},"activityList":{"items":[],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"","startCursor":null,"endCursor":null}},"title":"Activity ยท tharinduSamare/Multicore_processor_SystemVerilog_design"}