Need support for SDCC syntax on index-registers and explicit accumulator

[bengalack]

SDCC is a widely used compiler (http://sdcc.sourceforge.net/). It produces asm files (from C), and accepts asm-files. It has a special syntax on the index-registers:

I'm citing Konamiman here:

The syntax for offsets when using index registers is n(ix), where in other assemblers it's usually (ix+n)

Currently, when using SDCC-code, and the extension comes across this produced code:

`

ld	-1 (ix), e
ld	a, #0x1f
sub	a, -1 (ix)
ld	0 (iy), a

`

... there are two lines which the extension doesn't count, and it is hard to get the overview of the total time spent.

Gettting support for this would make a great extension even better :-)

[theNestruo]

I'm not familiar with SDCC... I think I can fin some source code examples, but I'd like to known which of the following are allowed:

• 3(ix) and 3 (ix): ok
• scrwidth(ix) and scrwidth (ix): ??? (using symbolic constants)
• scrwidth-32(ix), (scrwidth-32)(ix), etc.: ??? (using symbolic constants and expressions)

Thanks!

[bengalack]

Great!

• 3(ix) and 3 (ix): ok
• scrwidth(ix) and scrwidth (ix): ??? (using symbolic constants)
• scrwidth-32(ix), (scrwidth-32)(ix), etc.: ??? (using symbolic constants and expressions)

As for point 2: I have not used that one before, but I tested, and it works (makes sense as symbols probably are fixed up front in a preprosessor). Point 3: Same here, not tested it before today, but it works.

This is a general substitution made across the board for the index registers. So, it affects all places where there is a reference, like "iy+n" (or "iy-n") and "ix+n" (or "ix-n").

We can get the overview of the commands if we write "iy+" and "ix+" in the search field on this page:
http://map.grauw.nl/resources/z80instr.php

Also, I just realised another peculiar thing with SDCC output: Some instructions have the accumulator explicitly stated, like these:

xor n becomes xor a, n
sub n becomes sub a, n
and n becomes and a, n
or n becomes or a, n
cp n becomes cp a, n

The extension does not recognise these either.

I've tried to find information about this syntax, but couldn`t really find anything so far. I will try to reach out to the SDCC devs and ask if there is any documentation on this.

Thank you, so far!

[theNestruo]

Thanks for the info!
I need to twist a little bit the instruction parser for the index registers syntax, so give me a couple or days to look at it.
The explicit accumulator syntax support is easier to add (I've just uploaded a tentative solution), but I guess it's useless without the index registers syntax support, so I'll pack both fixes in a single release.

[bengalack]

I got this from SDCC:

Our assembler is a fork of asxxxx. There is some documentation of z80 syntax for asxxxx at:
https://shop-pdp.net/ashtml/asz80.htm

And indeed, what I just descibed to you is documented fully on that page under "Z80 INSTRUCTION SET".

[theNestruo]

I got this from SDCC:

Our assembler is a fork of asxxxx. There is some documentation of z80 syntax for asxxxx at:
https://shop-pdp.net/ashtml/asz80.htm

And indeed, what I just descibed to you is documented fully on that page under "Z80 INSTRUCTION SET".

If I'm understading it right, their syntax is arguably sick :D dec b can be written as dec a,b? srl c can be written as srl a,c? Even if the register a is not involved at all in the operation!?

But it makes parsing actually easier, so here we go!
Thanks for the reference!

[bengalack]

Hmm, those dec and inc with included reference to the accumulator is indeed strange, and does not make sense (as A-reg is not part of the command...). I have lots of code produced by SDCC, and they don't use that as output, they use the normal variant in the second column. Same with RL*/RR*/SL*/SR*, SDCC outputs the second column so far in all my code . So, no, parsing not easier :-)

I guess this means that it can accept both as input, but what it produces (from C code) is a mix of the two.

[theNestruo]

Would you mind testing this build: z80-asm-meter-1.4.0-nightly.zip ?
It should cover both index registers indirections syntax and explicit accumulator syntax

[bengalack]

Nice, I can test. But I have some news too. This seemed so stupid that I had to give them a try. It was too early to conclude and this is the result from what SDCC accepts as input (from "Implicit Operand Instructions"):

adc     a,b
add     a,b
and     a,b
cp      a,b
; dec     a,b ; DOES NOT WORK
; inc     a,b ; DOES NOT WORK
or      a,b
rl      a,b
rlc     a,b
rr      a,b
rrc     a,b
sbc     a,b
sla     a,b
sra     a,b
srl     a,b
sub     a,b
xor     a,b

All but two, actually. Strange again. But this is real life testing :)

[bengalack]

I would have to do a more thorough test later. One thing is testing the new stuff, that is easy. What about testing not breaking existing stuff? Do you have that covered, or should I do an overall test?

That said, I tend to use a lot of spaces or tabs to align commands and make them easily readable, so I spotted this one:

ld a, 0 ( iy )

(8 MSX cycles) is not the same as

ld a, 0 (iy)

(21 MSX cycles)

[theNestruo]

Don't worry too much about overall testing; explicit accumulator syntax may affect existing code (but manual tests seems to look ok), and index register indirections code shouldn't affect existing code...

This should fix the issues with spacing: z80-asm-meter-1.4.0-nightly.zip (btw, are artifacts from actions publicly downloadable?)

I'll be offline until wednesday, so if you find anything else wrong with the SDCC syntax detection, please let me a note here in the issue. On wednesday, if everything seems OK, I'll make a new release :D

Thank you very much!
I really appreciate your real-life tests and all the info and examples :)

[bengalack]

I'll test the new file. As for the link, it looks like this:

Thanks for the fast response on this :)

[bengalack]

I did testing on the new ones. Most of them work, but the following either show nothing, or show the wrong timing / identification:

AND a, -1 ( IY )
OR a, -1 ( IY )
SLA a, -1 ( IY )
SRA a, -1 ( IY )
SRL a, -1 ( IY )
SUB a, -1 ( IY )
XOR a, -1 ( IY )

(same of IX)

I did some random testing of other stuff too. I found some shortcomings when it comes to spaces inside parenthesis:

ld  a, ( hl ) ; ==> wrong timings and wrong identification
ld  r, ( hl ) ; ==> timings are correct, but instruction assumed is LD r,n

[theNestruo]

Oops... There was a missing .trim() when extracting the indirection. This nightly version should fix your latest comment issues.

[bengalack]

Great! I have checked the ones I reported, and they all work well :) Thank you. This looks good now👍

[theNestruo]

Release 1.4.0 published with SDCC syntax support.
I'll close the issue; but feel free to re-open it if any problem arises