From 99473f3200cbfc2016ca9fcb4f17a680aa0a26c2 Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 15:48:29 +0100 Subject: [PATCH 01/14] rimage: add initial support for sue creek. Build tested. Signed-off-by: Liam Girdwood --- rimage/manifest.c | 21 +++++++++++++++++++++ rimage/rimage.c | 1 + rimage/rimage.h | 2 ++ 3 files changed, 24 insertions(+) diff --git a/rimage/manifest.c b/rimage/manifest.c index dc883cc2faaa..d988f16be4c1 100644 --- a/rimage/manifest.c +++ b/rimage/manifest.c @@ -828,6 +828,11 @@ static int man_write_fw_meu(struct image *image) #define CNL_DSP_IMR_BASE_ENTRY 0xb0038000 #define CNL_DSP_HP_BASE_ENTRY 0xbe040000 +#define ADSP_SUE_DSP_ROM_BASE 0xBEFE0000 +#define ADSP_SUE_DSP_ROM_SIZE 0x00002000 +#define SUE_DSP_IMR_BASE_ENTRY 0xb0038000 +#define SUE_DSP_HP_BASE_ENTRY 0xbe000000 + #define ADSP_ICL_DSP_ROM_BASE 0xBEFE0000 #define ADSP_ICL_DSP_ROM_SIZE 0x00002000 #define ICL_DSP_IMR_BASE_ENTRY 0xb0038000 @@ -879,3 +884,19 @@ const struct adsp machine_icl = { .write_firmware_meu = man_write_fw_meu, .man = &cnl_manifest, // use the same as CNL }; + +const struct adsp machine_sue = { + .name = "sue", + .rom_base = ADSP_SUE_DSP_ROM_BASE, + .rom_size = ADSP_SUE_DSP_ROM_SIZE, + .imr_base = SUE_DSP_IMR_BASE_ENTRY, + .imr_size = 0x100000, + .sram_base = SUE_DSP_HP_BASE_ENTRY, + .sram_size = 0x100000, + .image_size = 0x100000, + .dram_offset = 0, + .machine_id = MACHINE_SUECREEK, + .write_firmware = man_write_fw, + .write_firmware_meu = man_write_fw_meu, + .man = &cnl_manifest, +}; diff --git a/rimage/rimage.c b/rimage/rimage.c index b67819646a3f..e5affadebbac 100644 --- a/rimage/rimage.c +++ b/rimage/rimage.c @@ -32,6 +32,7 @@ static const struct adsp *machine[] = { &machine_apl, &machine_cnl, &machine_icl, + &machine_sue, }; static void usage(char *name) diff --git a/rimage/rimage.h b/rimage/rimage.h index 4aeae29d3c5f..3ee8940905a1 100644 --- a/rimage/rimage.h +++ b/rimage/rimage.h @@ -41,6 +41,7 @@ enum machine_id { MACHINE_APOLLOLAKE, MACHINE_CANNONLAKE, MACHINE_ICELAKE, + MACHINE_SUECREEK, MACHINE_MAX }; @@ -177,5 +178,6 @@ extern const struct adsp machine_bdw; extern const struct adsp machine_apl; extern const struct adsp machine_cnl; extern const struct adsp machine_icl; +extern const struct adsp machine_sue; #endif From 6d4e923955da80b86fa695603f1737d34290b0bb Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 15:49:38 +0100 Subject: [PATCH 02/14] xtensa: boot: Don't initialise SRAM windows for sue creek Sue Creek has no SRAM windows so no need to init. Signed-off-by: Liam Girdwood --- src/arch/xtensa/boot_entry.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/arch/xtensa/boot_entry.S b/src/arch/xtensa/boot_entry.S index f00155c074f3..a11f0d7cd145 100644 --- a/src/arch/xtensa/boot_entry.S +++ b/src/arch/xtensa/boot_entry.S @@ -68,6 +68,7 @@ l2_cache_pref: sof_stack_base: .word SOF_STACK_BASE +#if !defined CONFIG_SUECREEK wnd0_base: .word DMWBA(0) @@ -85,6 +86,7 @@ wnd0_status_address: wnd0_error_address: .word HP_SRAM_WIN0_BASE | 0x4 +#endif fw_loaded_status_value: .word 0x00000005 @@ -112,6 +114,7 @@ boot_init: l32r a3, sof_stack_base mov sp, a3 +#if !defined CONFIG_SUECREEK /* set status register to 0x00000005 in wnd0 */ l32r a3, fw_loaded_status_value l32r a5, wnd0_status_address @@ -132,6 +135,7 @@ boot_init: l32r a5, wnd0_base_val s32i a5, a3, 0 memw +#endif #if (XCHAL_DCACHE_IS_COHERENT || XCHAL_LOOP_BUFFER_SIZE) && \ XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0 From 1ea7b575e2c7ea2f608c69d701df75d4a18326a0 Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 15:56:50 +0100 Subject: [PATCH 03/14] xtensa: boot loader: sue creek has no IMR so use different base address Signed-off-by: Liam Girdwood --- src/arch/xtensa/boot_loader.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/arch/xtensa/boot_loader.c b/src/arch/xtensa/boot_loader.c index 841c93d850c9..b877201d1971 100644 --- a/src/arch/xtensa/boot_loader.c +++ b/src/arch/xtensa/boot_loader.c @@ -36,6 +36,12 @@ #include #include +#if defined CONFIG_SUECREEK +#define MANIFEST_BASE BOOT_LDR_MANIFEST_BASE +#else +#define MANIFEST_BASE IMR_BOOT_LDR_MANIFEST_BASE +#endif + /* entry point to main firmware */ extern void _ResetVector(void); @@ -105,7 +111,7 @@ static void parse_module(struct sof_man_fw_header *hdr, static void parse_manifest(void) { struct sof_man_fw_desc *desc = - (struct sof_man_fw_desc *)IMR_BOOT_LDR_MANIFEST_BASE; + (struct sof_man_fw_desc *)MANIFEST_BASE; struct sof_man_fw_header *hdr = &desc->header; struct sof_man_module *mod; int i; @@ -121,7 +127,8 @@ static void parse_manifest(void) #endif /* power on HPSRAM */ -#if defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) +#if defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) \ + || defined(CONFIG_SUECREEK) static int32_t hp_sram_init(void) { int delay_count = 256; From 43cebe0cb0a64b9fc28b4c2e8bf4552b073a4082 Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 16:00:09 +0100 Subject: [PATCH 04/14] sue: clocks: Add clock config for suecreek. Signed-off-by: Liam Girdwood --- src/drivers/intel/cavs/clk.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/drivers/intel/cavs/clk.c b/src/drivers/intel/cavs/clk.c index 2d08558a0e8a..785ec7e98e51 100644 --- a/src/drivers/intel/cavs/clk.c +++ b/src/drivers/intel/cavs/clk.c @@ -77,7 +77,8 @@ static const struct freq_table cpu_freq[] = { {200000000, 200000, 0x1}, {400000000, 400000, 0x0}, /* default */ }; -#elif defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) +#elif defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) \ + || defined(CONFIG_SUECREEK) static const struct freq_table cpu_freq[] = { {120000000, 120000, 0x0}, {400000000, 400000, 0x4}, @@ -93,7 +94,7 @@ static const struct freq_table ssp_freq[] = { {19200000, 19200, }, /* default */ {24576000, 24576, }, }; -#elif defined(CONFIG_CANNONLAKE) +#elif defined(CONFIG_CANNONLAKE) || defined(CONFIG_SUECREEK) static const struct freq_table ssp_freq[] = { {19200000, 19200, }, {24000000, 24000, }, /* default */ @@ -108,7 +109,8 @@ static const struct freq_table ssp_freq[] = { #if defined(CONFIG_APOLLOLAKE) #define CPU_DEFAULT_IDX 2 #define SSP_DEFAULT_IDX 0 -#elif defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) +#elif defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) \ + || defined(CONFIG_SUECREEK) #define CPU_DEFAULT_IDX 1 #define SSP_DEFAULT_IDX 1 #endif From 489cfb5f0f20d5715be773b63c88bed4cf8bb0f1 Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 16:01:29 +0100 Subject: [PATCH 05/14] sue: dw-dma: Add support for suecreek Signed-off-by: Liam Girdwood --- src/drivers/intel/dw-dma.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/drivers/intel/dw-dma.c b/src/drivers/intel/dw-dma.c index 8f3c6ca9b338..d6c56f1b9a20 100644 --- a/src/drivers/intel/dw-dma.c +++ b/src/drivers/intel/dw-dma.c @@ -200,7 +200,7 @@ #define DW_CFG_HIGH_DEF 0x0 #elif defined(CONFIG_APOLLOLAKE) || defined(CONFIG_CANNONLAKE) \ - || defined(CONFIG_ICELAKE) + || defined(CONFIG_ICELAKE) || defined CONFIG_SUECREEK /* CTL_LO */ #define DW_CTLL_S_GATH_EN (1 << 17) @@ -245,7 +245,7 @@ /* HW Linked list support, only enabled for APL/CNL at the moment */ #if defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE \ - || defined CONFIG_ICELAKE + || defined CONFIG_ICELAKE || defined CONFIG_SUECREEK #define DW_USE_HW_LLI 1 #else #define DW_USE_HW_LLI 0 @@ -803,7 +803,7 @@ static int dw_dma_set_config(struct dma *dma, int channel, /* set transfer size of element */ #if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL \ || defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE \ - || defined CONFIG_ICELAKE + || defined CONFIG_ICELAKE || defined CONFIG_SUECREEK lli_desc->ctrl_hi = DW_CTLH_CLASS(p->class) | (sg_elem->size & DW_CTLH_BLOCK_TS_MASK); #elif defined CONFIG_BROADWELL || defined CONFIG_HASWELL @@ -923,7 +923,7 @@ static inline void dw_dma_chan_reload_next(struct dma *dma, int channel, /* set transfer size of element */ #if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL \ || defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE \ - || defined CONFIG_ICELAKE + || defined CONFIG_ICELAKE || defined CONFIG_SUECREEK lli->ctrl_hi = DW_CTLH_CLASS(p->class) | (next->size & DW_CTLH_BLOCK_TS_MASK); #elif defined CONFIG_BROADWELL || defined CONFIG_HASWELL @@ -994,7 +994,7 @@ static void dw_dma_setup(struct dma *dma) for (i = 0; i < DW_MAX_CHAN; i++) { #if defined CONFIG_BAYTRAIL || defined CONFIG_CHERRYTRAIL \ || defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE \ - || defined CONFIG_ICELAKE + || defined CONFIG_ICELAKE || defined CONFIG_SUECREEK dw_write(dma, DW_CTRL_HIGH(i), DW_CTLH_CLASS(dp->chan[i].class)); #elif defined CONFIG_BROADWELL || defined CONFIG_HASWELL From 7b64a5fde81fd2ba2db5c52a4ef4bfa2b3d60854 Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 16:07:37 +0100 Subject: [PATCH 06/14] sue: dmic: Add support for sue creek. Signed-off-by: Liam Girdwood --- src/include/sof/dmic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/sof/dmic.h b/src/include/sof/dmic.h index cb5f1e2ad861..9bbf491ad84d 100644 --- a/src/include/sof/dmic.h +++ b/src/include/sof/dmic.h @@ -51,7 +51,7 @@ #define DMIC_HW_IOCLK 19200000 #endif -#if defined CONFIG_CANNONLAKE +#if defined CONFIG_CANNONLAKE || defined CONFIG_SUECREEK #define DMIC_HW_VERSION 1 #define DMIC_HW_CONTROLLERS 2 #define DMIC_HW_IOCLK 24000000 From 95a6e304cc297f19bb13bd001ff17ed3ccc4e699 Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 16:10:27 +0100 Subject: [PATCH 07/14] sue: Add SSP defs for Sue Creek Signed-off-by: Liam Girdwood --- src/include/sof/ssp.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/include/sof/ssp.h b/src/include/sof/ssp.h index 20e66c52f071..a9defcf2697e 100644 --- a/src/include/sof/ssp.h +++ b/src/include/sof/ssp.h @@ -132,7 +132,7 @@ extern const struct dai_ops ssp_ops; #define SSCR2_ASRC_FRM_CNRT_EN BIT(10) #define SSCR2_ASRC_INTR_MASK BIT(11) #elif defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE \ - || defined CONFIG_ICELAKE \ + || defined CONFIG_ICELAKE || defined CONFIG_SUECREEK \ || defined CONFIG_HASWELL || defined CONFIG_BROADWELL #define SSCR2_TURM1 BIT(1) #define SSCR2_PSPSRWFDFD BIT(3) @@ -173,7 +173,7 @@ extern const struct dai_ops ssp_ops; #define SSPSP2_FEP_MASK 0xff #if defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE \ - || defined CONFIG_ICELAKE + || defined CONFIG_ICELAKE || defined CONFIG_SUECREEK #define SSCR3 0x48 #define SSIOC 0x4C @@ -211,6 +211,7 @@ extern const struct dai_ops ssp_ops; #define SFIFOL_RFL(x) ((x) >> 16) #if defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE \ + || defined CONFIG_SUECREEK \ || defined CONFIG_ICELAKE \ || defined CONFIG_HASWELL || defined CONFIG_BROADWELL #define SSTSA_TSEN BIT(8) @@ -229,7 +230,7 @@ extern const struct dai_ops ssp_ops; #endif #if defined CONFIG_APOLLOLAKE || defined CONFIG_CANNONLAKE \ - || defined CONFIG_ICELAKE + || defined CONFIG_ICELAKE || defined CONFIG_SUECREEK #define MNDSS(x) ((x) << 20) #define MCDSS(x) ((x) << 16) #endif From 5b321dd57d4925cd39d0c70503899cc7cca73f28 Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 16:15:03 +0100 Subject: [PATCH 08/14] sue: Add support for Suecreek platform Suecreek is Intel S1000 SoC audio DSP. Host connection is via SPI. Signed-off-by: Liam Girdwood --- src/platform/Makefile.am | 4 + src/platform/suecreek/Makefile.am | 38 ++ src/platform/suecreek/base_module.c | 54 ++ src/platform/suecreek/boot_ldr.x.in | 230 +++++++ src/platform/suecreek/boot_module.c | 54 ++ src/platform/suecreek/include/Makefile.am | 1 + .../suecreek/include/arch/Makefile.am | 1 + .../suecreek/include/arch/xtensa/Makefile.am | 1 + .../include/arch/xtensa/config/Makefile.am | 8 + .../include/arch/xtensa/config/core-isa.h | 565 ++++++++++++++++++ .../include/arch/xtensa/config/core-matmap.h | 320 ++++++++++ .../include/arch/xtensa/config/defs.h | 46 ++ .../include/arch/xtensa/config/specreg.h | 114 ++++ .../include/arch/xtensa/config/system.h | 278 +++++++++ .../include/arch/xtensa/config/tie-asm.h | 247 ++++++++ .../suecreek/include/arch/xtensa/config/tie.h | 177 ++++++ .../suecreek/include/platform/Makefile.am | 12 + src/platform/suecreek/include/platform/clk.h | 42 ++ src/platform/suecreek/include/platform/dma.h | 63 ++ src/platform/suecreek/include/platform/idc.h | 46 ++ .../suecreek/include/platform/interrupt.h | 206 +++++++ .../suecreek/include/platform/mailbox.h | 95 +++ .../suecreek/include/platform/memory.h | 326 ++++++++++ .../suecreek/include/platform/platcfg.h | 40 ++ .../suecreek/include/platform/platform.h | 185 ++++++ .../suecreek/include/platform/pm_runtime.h | 73 +++ src/platform/suecreek/include/platform/shim.h | 324 ++++++++++ .../suecreek/include/platform/timer.h | 49 ++ src/platform/suecreek/suecreek.x.in | 558 +++++++++++++++++ 29 files changed, 4157 insertions(+) create mode 100644 src/platform/suecreek/Makefile.am create mode 100644 src/platform/suecreek/base_module.c create mode 100644 src/platform/suecreek/boot_ldr.x.in create mode 100644 src/platform/suecreek/boot_module.c create mode 100644 src/platform/suecreek/include/Makefile.am create mode 100644 src/platform/suecreek/include/arch/Makefile.am create mode 100644 src/platform/suecreek/include/arch/xtensa/Makefile.am create mode 100644 src/platform/suecreek/include/arch/xtensa/config/Makefile.am create mode 100644 src/platform/suecreek/include/arch/xtensa/config/core-isa.h create mode 100644 src/platform/suecreek/include/arch/xtensa/config/core-matmap.h create mode 100644 src/platform/suecreek/include/arch/xtensa/config/defs.h create mode 100644 src/platform/suecreek/include/arch/xtensa/config/specreg.h create mode 100644 src/platform/suecreek/include/arch/xtensa/config/system.h create mode 100644 src/platform/suecreek/include/arch/xtensa/config/tie-asm.h create mode 100644 src/platform/suecreek/include/arch/xtensa/config/tie.h create mode 100644 src/platform/suecreek/include/platform/Makefile.am create mode 100644 src/platform/suecreek/include/platform/clk.h create mode 100644 src/platform/suecreek/include/platform/dma.h create mode 100644 src/platform/suecreek/include/platform/idc.h create mode 100644 src/platform/suecreek/include/platform/interrupt.h create mode 100644 src/platform/suecreek/include/platform/mailbox.h create mode 100644 src/platform/suecreek/include/platform/memory.h create mode 100644 src/platform/suecreek/include/platform/platcfg.h create mode 100644 src/platform/suecreek/include/platform/platform.h create mode 100644 src/platform/suecreek/include/platform/pm_runtime.h create mode 100644 src/platform/suecreek/include/platform/shim.h create mode 100644 src/platform/suecreek/include/platform/timer.h create mode 100644 src/platform/suecreek/suecreek.x.in diff --git a/src/platform/Makefile.am b/src/platform/Makefile.am index c6952aa9b9fc..c62e95ec0a07 100644 --- a/src/platform/Makefile.am +++ b/src/platform/Makefile.am @@ -24,6 +24,10 @@ if BUILD_CANNONLAKE SUBDIRS += cannonlake endif +if BUILD_SUECREEK +SUBDIRS += suecreek +endif + if BUILD_ICELAKE SUBDIRS += icelake endif diff --git a/src/platform/suecreek/Makefile.am b/src/platform/suecreek/Makefile.am new file mode 100644 index 000000000000..f6f8f2bf70c8 --- /dev/null +++ b/src/platform/suecreek/Makefile.am @@ -0,0 +1,38 @@ +SUBDIRS = include + +EXTRA_DIST = \ + suecreek.x.in \ + boot_ldr.x.in + +noinst_LTLIBRARIES = libplatform.la + +libplatform_la_LIBADD = ../intel/cavs/libcavsplatform.la + +libplatform_la_SOURCES = + +libplatform_la_CFLAGS = \ + $(AM_CFLAGS) \ + $(ARCH_CFLAGS) \ + $(ARCH_INCDIR) \ + $(PLATFORM_INCDIR) \ + $(SOF_INCDIR) + +noinst_PROGRAMS = module boot_module + +module_SOURCES = \ + base_module.c + +module_CFLAGS = \ + $(AM_CFLAGS) \ + $(ARCH_INCDIR) \ + $(PLATFORM_INCDIR) \ + $(SOF_INCDIR) + +boot_module_SOURCES = \ + boot_module.c + +boot_module_CFLAGS = \ + $(AM_CFLAGS) \ + $(ARCH_INCDIR) \ + $(PLATFORM_INCDIR) \ + $(SOF_INCDIR) diff --git a/src/platform/suecreek/base_module.c b/src/platform/suecreek/base_module.c new file mode 100644 index 000000000000..9f3cb9c73e29 --- /dev/null +++ b/src/platform/suecreek/base_module.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood + */ + +#include +#include + +/* + * Each module has an entry in the FW manifest header. This is NOT part of + * the SOF executable image but is inserted by object copy as a ELF section + * for parsing by rimage (to genrate the manifest). + */ +struct sof_man_module_manifest cnl_manifest = { + .module = { + .name = "BASEFW", + .uuid = {0x32, 0x8c, 0x39, 0x0e, 0xde, 0x5a, 0x4b, 0xba, + 0x93, 0xb1, 0xc5, 0x04, 0x32, 0x28, 0x0e, 0xe4}, + .entry_point = SOF_TEXT_START, + .type = { + .load_type = SOF_MAN_MOD_TYPE_MODULE, + .domain_ll = 1, + }, + .affinity_mask = 3, + }, +}; + +/* not used, but stops linker complaining */ +int _start; diff --git a/src/platform/suecreek/boot_ldr.x.in b/src/platform/suecreek/boot_ldr.x.in new file mode 100644 index 000000000000..c5a3446d2713 --- /dev/null +++ b/src/platform/suecreek/boot_ldr.x.in @@ -0,0 +1,230 @@ +/* + * Linker Script for Cannonlake Bootloader. + * + * This script is run through the GNU C preprocessor to align the memory + * offsets with headers. + * + * Use spaces for formatting as cpp ignore tab sizes. + */ + +#include +#include + +OUTPUT_ARCH(xtensa) + +MEMORY +{ + boot_entry_text : + org = BOOT_LDR_TEXT_ENTRY_BASE, + len = BOOT_LDR_TEXT_ENTRY_SIZE + boot_entry_lit : + org = BOOT_LDR_LIT_BASE, + len = BOOT_LDR_LIT_SIZE + sof_text : + org = BOOT_LDR_TEXT_BASE, + len = BOOT_LDR_TEXT_SIZE, + sof_data : + org = BOOT_LDR_DATA_BASE, + len = BOOT_LDR_DATA_SIZE + sof_bss_data : + org = BOOT_LDR_BSS_BASE, + len = BOOT_LDR_BSS_SIZE + sof_stack : + org = SOF_STACK_END, + len = SOF_STACK_BASE - SOF_STACK_END +} + +PHDRS +{ + boot_entry_text_phdr PT_LOAD; + boot_entry_lit_phdr PT_LOAD; + sof_text_phdr PT_LOAD; + sof_data_phdr PT_LOAD; + sof_bss_data_phdr PT_LOAD; + sof_stack_phdr PT_LOAD; +} + +/* Default entry point: */ +ENTRY(boot_entry) +EXTERN(reset_vector) + +SECTIONS +{ + .boot_entry.text : ALIGN(4) + { + _boot_entry_text_start = ABSOLUTE(.); + KEEP (*(.boot_entry.text)) + _boot_entry_text_end = ABSOLUTE(.); + } >boot_entry_text :boot_entry_text_phdr + + .boot_entry.literal : ALIGN(4) + { + _boot_entry_literal_start = ABSOLUTE(.); + *(.boot_entry.literal) + *(.literal .literal.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + _boot_entry_literal_end = ABSOLUTE(.); + } >boot_entry_lit :boot_entry_lit_phdr + + .text : ALIGN(4) + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.entry.text) + *(.init.literal) + KEEP(*(.init)) + *( .text .text.*) + *(.fini.literal) + KEEP(*(.fini)) + *(.gnu.version) + KEEP (*(.ResetVector.text)) + KEEP (*(.ResetHandler.text)) + _text_end = ABSOLUTE(.); + _etext = .; + } >sof_text :sof_text_phdr + + .rodata : ALIGN(4) + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); + KEEP (*(.xt_except_table)) + KEEP (*(.gcc_except_table)) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + KEEP (*(.eh_frame)) + /* C++ constructor and destructor tables, properly ordered: */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); /* this table MUST be 4-byte aligned */ + _bss_table_start = ABSOLUTE(.); + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + } >sof_data :sof_data_phdr + + .data : ALIGN(4) + { + _data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + KEEP(*(.gnu.linkonce.d.*personality*)) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + KEEP(*(.jcr)) + _data_end = ABSOLUTE(.); + } >sof_data :sof_data_phdr + + .lit4 : ALIGN(4) + { + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + } >sof_data :sof_data_phdr + + .bss (NOLOAD) : ALIGN(8) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } >sof_bss_data :sof_bss_data_phdr + + _man = 0x1234567; + + PROVIDE(_memmap_vecbase_reset = HP_SRAM_VECBASE_RESET); + + _memmap_cacheattr_wbna_trapnull = 0xFF42FFF2; + PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull); + + __stack = SOF_STACK_BASE; + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } +} diff --git a/src/platform/suecreek/boot_module.c b/src/platform/suecreek/boot_module.c new file mode 100644 index 000000000000..c6a4c668a6f4 --- /dev/null +++ b/src/platform/suecreek/boot_module.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood + */ + +#include +#include + +/* + * Each module has an entry in the FW manifest header. This is NOT part of + * the SOF executable image but is inserted by object copy as a ELF section + * for parsing by rimage (to genrate the manifest). + */ +struct sof_man_module_manifest sue_bootldr_manifest = { + .module = { + .name = "BRNGUP", + .uuid = {0xf3, 0xe4, 0x79, 0x2b, 0x75, 0x46, 0x49, 0xf6, + 0x89, 0xdf, 0x3b, 0xc1, 0x94, 0xa9, 0x1a, 0xeb}, + .entry_point = BOOT_LDR_TEXT_ENTRY_BASE, + .type = { + .load_type = SOF_MAN_MOD_TYPE_MODULE, + .domain_ll = 1, + }, + .affinity_mask = 3, + }, +}; + +/* not used, but stops linker complaining */ +int _start; diff --git a/src/platform/suecreek/include/Makefile.am b/src/platform/suecreek/include/Makefile.am new file mode 100644 index 000000000000..c5113a413355 --- /dev/null +++ b/src/platform/suecreek/include/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = arch platform diff --git a/src/platform/suecreek/include/arch/Makefile.am b/src/platform/suecreek/include/arch/Makefile.am new file mode 100644 index 000000000000..63616bfa4617 --- /dev/null +++ b/src/platform/suecreek/include/arch/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = xtensa diff --git a/src/platform/suecreek/include/arch/xtensa/Makefile.am b/src/platform/suecreek/include/arch/xtensa/Makefile.am new file mode 100644 index 000000000000..a85a5bb53ea0 --- /dev/null +++ b/src/platform/suecreek/include/arch/xtensa/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = config diff --git a/src/platform/suecreek/include/arch/xtensa/config/Makefile.am b/src/platform/suecreek/include/arch/xtensa/config/Makefile.am new file mode 100644 index 000000000000..99c21a5f09f0 --- /dev/null +++ b/src/platform/suecreek/include/arch/xtensa/config/Makefile.am @@ -0,0 +1,8 @@ +noinst_HEADERS = \ + core-isa.h \ + core-matmap.h \ + defs.h \ + specreg.h \ + system.h \ + tie.h \ + tie-asm.h diff --git a/src/platform/suecreek/include/arch/xtensa/config/core-isa.h b/src/platform/suecreek/include/arch/xtensa/config/core-isa.h new file mode 100644 index 000000000000..8a027681bb32 --- /dev/null +++ b/src/platform/suecreek/include/arch/xtensa/config/core-isa.h @@ -0,0 +1,565 @@ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + + Customer ID=10631; Build=0x60f88; Copyright (c) 1999-2016 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#if !defined __XCC__ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 64 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +/* TODO: CP is 1 - need assembler support */ +#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_SW_VERSION 1100003 /* sw version of this header */ + +#define XCHAL_CORE_ID "cavs21_LX6HiFi3_RF3_WB16" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x00060F88 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC2F3FBFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x1CC60F88 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 260003 /* major*100+minor */ +#define XCHAL_HW_REL_LX6 1 +#define XCHAL_HW_REL_LX6_0 1 +#define XCHAL_HW_REL_LX6_0_3 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 64 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 64 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 6 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 2 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 1 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 1 /* Dcache dynamic way support */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ +#define XCHAL_HAVE_AXI 0 /* AXI bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 6 +#define XCHAL_DCACHE_SETWIDTH 8 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS 3 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY XTHAL_MEMEP_ECC +#define XCHAL_DCACHE_ECC_PARITY XTHAL_MEMEP_ECC + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 8 +#define XCHAL_DCACHE_ACCESS_SIZE 8 + +#define XCHAL_DCACHE_BANKS 1 /* number of banks */ + +/* Number of encoded cache attr bits (see for decoded bits): */ +#define XCHAL_CA_BITS 4 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 21 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 8 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 5 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x0000000F +#define XCHAL_INTLEVEL2_MASK 0x000000F0 +#define XCHAL_INTLEVEL3_MASK 0x00000F00 +#define XCHAL_INTLEVEL4_MASK 0x00007000 +#define XCHAL_INTLEVEL5_MASK 0x000F8000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00100000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000000F +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000000FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00007FFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x000FFFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x000FFFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x001FFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 2 +#define XCHAL_INT5_LEVEL 2 +#define XCHAL_INT6_LEVEL 2 +#define XCHAL_INT7_LEVEL 2 +#define XCHAL_INT8_LEVEL 3 +#define XCHAL_INT9_LEVEL 3 +#define XCHAL_INT10_LEVEL 3 +#define XCHAL_INT11_LEVEL 3 +#define XCHAL_INT12_LEVEL 4 +#define XCHAL_INT13_LEVEL 4 +#define XCHAL_INT14_LEVEL 4 +#define XCHAL_INT15_LEVEL 5 +#define XCHAL_INT16_LEVEL 5 +#define XCHAL_INT17_LEVEL 5 +#define XCHAL_INT18_LEVEL 5 +#define XCHAL_INT19_LEVEL 5 +#define XCHAL_INT20_LEVEL 7 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_NMI + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFE00000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0008D999 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x00072444 +#define XCHAL_INTTYPE_MASK_TIMER 0x00000222 +#define XCHAL_INTTYPE_MASK_NMI 0x00100000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 5 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 9 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 20 /* non-maskable interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL7_NUM 20 +/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 6 /* (intlevel 2) */ +#define XCHAL_EXTINT2_NUM 10 /* (intlevel 3) */ +#define XCHAL_EXTINT3_NUM 13 /* (intlevel 4) */ +#define XCHAL_EXTINT4_NUM 16 /* (intlevel 5) */ +#define XCHAL_EXTINT5_NUM 17 /* (intlevel 5) */ +#define XCHAL_EXTINT6_NUM 18 /* (intlevel 5) */ +#define XCHAL_EXTINT7_NUM 20 /* (intlevel 7) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT2_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT6_EXTNUM 1 /* (intlevel 2) */ +#define XCHAL_INT10_EXTNUM 2 /* (intlevel 3) */ +#define XCHAL_INT13_EXTNUM 3 /* (intlevel 4) */ +#define XCHAL_INT16_EXTNUM 4 /* (intlevel 5) */ +#define XCHAL_INT17_EXTNUM 5 /* (intlevel 5) */ +#define XCHAL_INT18_EXTNUM 6 /* (intlevel 5) */ +#define XCHAL_INT20_EXTNUM 7 /* (intlevel 7) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 1 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 1 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0xBEFE0800 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0xBEFE0800 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0xBEFE0000 +#define XCHAL_RESET_VECTOR0_PADDR 0xBEFE0000 +#define XCHAL_RESET_VECTOR1_VADDR 0xBE800000 +#define XCHAL_RESET_VECTOR1_PADDR 0xBE800000 +#define XCHAL_RESET_VECTOR_VADDR 0xBEFE0000 +#define XCHAL_RESET_VECTOR_PADDR 0xBEFE0000 +#define XCHAL_MEMERROR_VECTOR0_VADDR 0xBEFE0400 +#define XCHAL_MEMERROR_VECTOR0_PADDR 0xBEFE0400 +#define XCHAL_MEMERROR_VECTOR1_VADDR 0xBE800400 +#define XCHAL_MEMERROR_VECTOR1_PADDR 0xBE800400 +#define XCHAL_MEMERROR_VECTOR_VADDR 0xBEFE0400 +#define XCHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400 +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0xBEFE0B40 +#define XCHAL_USER_VECTOR_PADDR 0xBEFE0B40 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0xBEFE0B00 +#define XCHAL_KERNEL_VECTOR_PADDR 0xBEFE0B00 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xBEFE0BC0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0xBEFE0BC0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0xBEFE0800 +#define XCHAL_WINDOW_VECTORS_PADDR 0xBEFE0800 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xBEFE0980 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0xBEFE0980 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xBEFE09C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0xBEFE09C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xBEFE0A00 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xBEFE0A00 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xBEFE0A40 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0xBEFE0A40 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xBEFE0A80 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0xBEFE0A80 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0xBEFE0AC0 +#define XCHAL_NMI_VECTOR_PADDR 0xBEFE0AC0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/suecreek/include/arch/xtensa/config/core-matmap.h b/src/platform/suecreek/include/arch/xtensa/config/core-matmap.h new file mode 100644 index 000000000000..ad0f0d7fa180 --- /dev/null +++ b/src/platform/suecreek/include/arch/xtensa/config/core-matmap.h @@ -0,0 +1,320 @@ +/* + * xtensa/config/core-matmap.h -- Memory access and translation mapping + * parameters (CHAL) of the Xtensa processor core configuration. + * + * If you are using Xtensa Tools, see (which includes + * this file) for more details. + * + * In the Xtensa processor products released to date, all parameters + * defined in this file are derivable (at least in theory) from + * information contained in the core-isa.h header file. + * In particular, the following core configuration parameters are relevant: + * XCHAL_HAVE_CACHEATTR + * XCHAL_HAVE_MIMIC_CACHEATTR + * XCHAL_HAVE_XLT_CACHEATTR + * XCHAL_HAVE_PTP_MMU + * XCHAL_ITLB_ARF_ENTRIES_LOG2 + * XCHAL_DTLB_ARF_ENTRIES_LOG2 + * XCHAL_DCACHE_IS_WRITEBACK + * XCHAL_ICACHE_SIZE (presence of I-cache) + * XCHAL_DCACHE_SIZE (presence of D-cache) + * XCHAL_HW_VERSION_MAJOR + * XCHAL_HW_VERSION_MINOR + */ + +/* Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#if !defined __XCC__ + +#ifndef XTENSA_CONFIG_CORE_MATMAP_H +#define XTENSA_CONFIG_CORE_MATMAP_H + + +/*---------------------------------------------------------------------- + CACHE (MEMORY ACCESS) ATTRIBUTES + ----------------------------------------------------------------------*/ + + +/* Cache Attribute encodings -- lists of access modes for each cache attribute: */ +#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_CACHED XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION +#define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_CACHED XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_ISOLATE XCHAL_SEP \ + XTHAL_LAM_EXCEPTION +#define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \ + XTHAL_SAM_WRITETHRU XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_WRITEBACK XCHAL_SEP \ + XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_ISOLATE XCHAL_SEP \ + XTHAL_SAM_EXCEPTION + + +/* + * Specific encoded cache attribute values of general interest. + * If a specific cache mode is not available, the closest available + * one is returned instead (eg. writethru instead of writeback, + * bypass instead of writethru). + */ +#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */ +#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */ +#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */ +#define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */ +#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 /* write-back no-allocate availability */ +#define XCHAL_CA_WRITEBACK_NOALLOC 5 /* cache enabled (write-back no-allocate) mode */ +#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */ +#define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* + * General notes on MMU parameters. + * + * Terminology: + * ASID = address-space ID (acts as an "extension" of virtual addresses) + * VPN = virtual page number + * PPN = physical page number + * CA = encoded cache attribute (access modes) + * TLB = translation look-aside buffer (term is stretched somewhat here) + * I = instruction (fetch accesses) + * D = data (load and store accesses) + * way = each TLB (ITLB and DTLB) consists of a number of "ways" + * that simultaneously match the virtual address of an access; + * a TLB successfully translates a virtual address if exactly + * one way matches the vaddr; if none match, it is a miss; + * if multiple match, one gets a "multihit" exception; + * each way can be independently configured in terms of number of + * entries, page sizes, which fields are writable or constant, etc. + * set = group of contiguous ways with exactly identical parameters + * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE + * from the page table and storing it in one of the auto-refill ways; + * if this PTE load also misses, a miss exception is posted for s/w. + * min-wired = a "min-wired" way can be used to map a single (minimum-sized) + * page arbitrarily under program control; it has a single entry, + * is non-auto-refill (some other way(s) must be auto-refill), + * all its fields (VPN, PPN, ASID, CA) are all writable, and it + * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current + * restriction is that this be the only page size it supports). + * + * TLB way entries are virtually indexed. + * TLB ways that support multiple page sizes: + * - must have all writable VPN and PPN fields; + * - can only use one page size at any given time (eg. setup at startup), + * selected by the respective ITLBCFG or DTLBCFG special register, + * whose bits n*4+3 .. n*4 index the list of page sizes for way n + * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); + * this list may be sparse for auto-refill ways because auto-refill + * ways have independent lists of supported page sizes sharing a + * common encoding with PTE entries; the encoding is the index into + * this list; unsupported sizes for a given way are zero in the list; + * selecting unsupported sizes results in undefined hardware behaviour; + * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). + */ + +#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ +#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */ +#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ +#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ +#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */ +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */ + + +/*** Instruction TLB: ***/ + +#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */ +#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */ +#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_ITLB_WAY0_SET 0 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* ITLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */ +#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000 +#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000 +#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000 +#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000 +#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000 +#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000 +#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000 +#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000 +/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */ +#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000 +#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000 +#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000 +#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000 +#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000 +#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000 +#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000 +#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000 +/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */ +#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02 + + +/*** Data TLB: ***/ + +#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */ +#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */ +#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_DTLB_WAY0_SET 0 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* DTLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */ +#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000 +#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000 +#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000 +#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000 +#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000 +#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000 +#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000 +#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000 +/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */ +#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000 +#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000 +#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000 +#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000 +#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000 +#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000 +#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000 +#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000 +/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */ +#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 + + + + +#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/suecreek/include/arch/xtensa/config/defs.h b/src/platform/suecreek/include/arch/xtensa/config/defs.h new file mode 100644 index 000000000000..c2ef1d994fb3 --- /dev/null +++ b/src/platform/suecreek/include/arch/xtensa/config/defs.h @@ -0,0 +1,46 @@ +/* Definitions for Xtensa instructions, types, and protos. */ + +/* Customer ID=4313; Build=0x5483b; Copyright (c) 2003-2004 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* NOTE: This file exists only for backward compatibility with T1050 + and earlier Xtensa releases. It includes only a subset of the + available header files. */ + +#if !defined __XCC__ + +#ifndef _XTENSA_BASE_HEADER +#define _XTENSA_BASE_HEADER + +#ifdef __XTENSA__ + +#include +#include +#include + +#endif /* __XTENSA__ */ +#endif /* !_XTENSA_BASE_HEADER */ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/suecreek/include/arch/xtensa/config/specreg.h b/src/platform/suecreek/include/arch/xtensa/config/specreg.h new file mode 100644 index 000000000000..c99cda683a50 --- /dev/null +++ b/src/platform/suecreek/include/arch/xtensa/config/specreg.h @@ -0,0 +1,114 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ + +/* Customer ID=4313; Build=0x5483b; Copyright (c) 1998-2002 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#if !defined __XCC__ + +#ifndef XTENSA_SPECREG_H +#define XTENSA_SPECREG_H + +/* Include these special register bitfield definitions, for historical reasons: */ +#include + + +/* Special registers: */ +#define LBEG 0 +#define LEND 1 +#define LCOUNT 2 +#define SAR 3 +#define BR 4 +#define SCOMPARE1 12 +#define WINDOWBASE 72 +#define WINDOWSTART 73 +#define IBREAKENABLE 96 +#define ATOMCTL 99 +#define DDR 104 +#define IBREAKA_0 128 +#define IBREAKA_1 129 +#define DBREAKA_0 144 +#define DBREAKA_1 145 +#define DBREAKC_0 160 +#define DBREAKC_1 161 +#define EPC_1 177 +#define EPC_2 178 +#define EPC_3 179 +#define EPC_4 180 +#define EPC_5 181 +#define EPC_6 182 +#define EPC_7 183 +#define DEPC 192 +#define EPS_2 194 +#define EPS_3 195 +#define EPS_4 196 +#define EPS_5 197 +#define EPS_6 198 +#define EPS_7 199 +#define EXCSAVE_1 209 +#define EXCSAVE_2 210 +#define EXCSAVE_3 211 +#define EXCSAVE_4 212 +#define EXCSAVE_5 213 +#define EXCSAVE_6 214 +#define EXCSAVE_7 215 +#define CPENABLE 224 +#define INTERRUPT 226 +#define INTENABLE 228 +#define PS 230 +#define VECBASE 231 +#define EXCCAUSE 232 +#define DEBUGCAUSE 233 +#define CCOUNT 234 +#define PRID 235 +#define ICOUNT 236 +#define ICOUNTLEVEL 237 +#define EXCVADDR 238 +#define CCOMPARE_0 240 +#define CCOMPARE_1 241 +#define CCOMPARE_2 242 +#define MISC_REG_0 244 +#define MISC_REG_1 245 + +/* Special cases (bases of special register series): */ +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 +#define EPC 176 +#define EPS 192 +#define EXCSAVE 208 +#define CCOMPARE 240 + +/* Special names for read-only and write-only interrupt registers: */ +#define INTREAD 226 +#define INTSET 226 +#define INTCLEAR 227 + +#endif /* XTENSA_SPECREG_H */ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/suecreek/include/arch/xtensa/config/system.h b/src/platform/suecreek/include/arch/xtensa/config/system.h new file mode 100644 index 000000000000..f1fd8a0c201c --- /dev/null +++ b/src/platform/suecreek/include/arch/xtensa/config/system.h @@ -0,0 +1,278 @@ +/* + * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration + * + * NOTE: The location and contents of this file are highly subject to change. + * + * Source for configuration-independent binaries (which link in a + * configuration-specific HAL library) must NEVER include this file. + * The HAL itself has historically included this file in some instances, + * but this is not appropriate either, because the HAL is meant to be + * core-specific but system independent. + */ + +/* Customer ID=4313; Build=0x5483b; Copyright (c) 2000-2010 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#if !defined __XCC__ + +#ifndef XTENSA_CONFIG_SYSTEM_H +#define XTENSA_CONFIG_SYSTEM_H + +/*#include */ + + + +/*---------------------------------------------------------------------- + CONFIGURED SOFTWARE OPTIONS + ----------------------------------------------------------------------*/ + +#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ + +#define XSHAL_ABI XTHAL_ABI_CALL0 /* (sw-only option, selected ABI) */ +/* The above maps to one of the following constants: */ +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 +/* Alternatives: */ +/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */ +/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */ + +#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */ +/* The above maps to one of the following constants: */ +#define XTHAL_CLIB_NEWLIB 0 +#define XTHAL_CLIB_UCLIBC 1 +#define XTHAL_CLIB_XCLIB 2 +/* Alternatives: */ +/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */ +/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */ +/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */ + +#define XSHAL_USE_FLOATING_POINT 1 + +#define XSHAL_FLOATING_POINT_ABI 0 + +/*---------------------------------------------------------------------- + DEVICE ADDRESSES + ----------------------------------------------------------------------*/ + +/* + * Strange place to find these, but the configuration GUI + * allows moving these around to account for various core + * configurations. Specific boards (and their BSP software) + * will have specific meanings for these components. + */ + +/* I/O Block areas: */ +#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 + +#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000 +#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000 +#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 + +/* System ROM: */ +#define XSHAL_ROM_VADDR 0x50000000 +#define XSHAL_ROM_PADDR 0x50000000 +#define XSHAL_ROM_SIZE 0x01000000 +/* Largest available area (free of vectors): */ +#define XSHAL_ROM_AVAIL_VADDR 0x50000300 +#define XSHAL_ROM_AVAIL_VSIZE 0x00FFFD00 + +/* System RAM: */ +#define XSHAL_RAM_VADDR 0x60000000 +#define XSHAL_RAM_PADDR 0x60000000 +#define XSHAL_RAM_VSIZE 0x04000000 +#define XSHAL_RAM_PSIZE 0x04000000 +#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE +/* Largest available area (free of vectors): */ +#define XSHAL_RAM_AVAIL_VADDR 0x60000400 +#define XSHAL_RAM_AVAIL_VSIZE 0x03FFFC00 + +/* + * Shadow system RAM (same device as system RAM, at different address). + * (Emulation boards need this for the SONIC Ethernet driver + * when data caches are configured for writeback mode.) + * NOTE: on full MMU configs, this points to the BYPASS virtual address + * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual + * addresses are viewed through the BYPASS static map rather than + * the CACHED static map. + */ +#define XSHAL_RAM_BYPASS_VADDR 0xA0000000 +#define XSHAL_RAM_BYPASS_PADDR 0xA0000000 +#define XSHAL_RAM_BYPASS_PSIZE 0x04000000 + +/* Alternate system RAM (different device than system RAM): */ +/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/ +/*#define XSHAL_ALTRAM_SIZE ...not configured...*/ + +/* Some available location in which to place devices in a simulation (eg. XTMP): */ +#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000 +#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000 +#define XSHAL_SIMIO_PADDR 0xC0000000 +#define XSHAL_SIMIO_SIZE 0x20000000 + + +/*---------------------------------------------------------------------- + * For use by reference testbench exit and diagnostic routines. + */ +#define XSHAL_MAGIC_EXIT 0x0 + +/*---------------------------------------------------------------------- + * DEVICE-ADDRESS DEPENDENT... + * + * Values written to CACHEATTR special register (or its equivalent) + * to enable and disable caches in various modes. + *----------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------- + BACKWARD COMPATIBILITY ... + ----------------------------------------------------------------------*/ + +/* + * NOTE: the following two macros are DEPRECATED. Use the latter + * board-specific macros instead, which are specially tuned for the + * particular target environments' memory maps. + */ +#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ +#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ + +/*---------------------------------------------------------------------- + GENERIC + ----------------------------------------------------------------------*/ + +/* For the following, a 512MB region is used if it contains a system (PIF) RAM, + * system (PIF) ROM, local memory, or XLMI. */ + +/* These set any unused 512MB region to cache-BYPASS attribute: */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22224442 /* enable caches in write-back mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */ +#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ +#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/* These set any unused 512MB region to ILLEGAL attribute: */ +#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF444F /* enable caches in write-back mode */ +#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */ +#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */ +#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */ +#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch + * NULL-pointer dereference bugs; all other unused 512MB regions are set + * to cache-BYPASS attribute: */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222444F /* enable caches in write-back mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */ +#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */ +#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +/*---------------------------------------------------------------------- + ISS (Instruction Set Simulator) SPECIFIC ... + ----------------------------------------------------------------------*/ + +/* For now, ISS defaults to the TRAPNULL settings: */ +#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK +#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC +#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU +#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS +#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK + +#define XSHAL_ISS_PIPE_REGIONS 0 +#define XSHAL_ISS_SDRAM_REGIONS 0 + + +/*---------------------------------------------------------------------- + XT2000 BOARD SPECIFIC ... + ----------------------------------------------------------------------*/ + +/* For the following, a 512MB region is used if it contains any system RAM, + * system ROM, local memory, XLMI, or other XT2000 board device or memory. + * Regions containing devices are forced to cache-BYPASS mode regardless + * of whether the macro is _WRITEBACK vs. _BYPASS etc. */ + +/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ +#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22444F /* enable caches in write-back mode */ +#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */ +#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */ +#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ +#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ + +#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ +#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */ + + +/*---------------------------------------------------------------------- + VECTOR INFO AND SIZES + ----------------------------------------------------------------------*/ + +#define XSHAL_VECTORS_PACKED 0 +#define XSHAL_STATIC_VECTOR_SELECT 0 +#define XSHAL_RESET_VECTOR_VADDR 0x50000000 +#define XSHAL_RESET_VECTOR_PADDR 0x50000000 + +/* + * Sizes allocated to vectors by the system (memory map) configuration. + * These sizes are constrained by core configuration (eg. one vector's + * code cannot overflow into another vector) but are dependent on the + * system or board (or LSP) memory map configuration. + * + * Whether or not each vector happens to be in a system ROM is also + * a system configuration matter, sometimes useful, included here also: + */ +#define XSHAL_RESET_VECTOR_SIZE 0x00000300 +#define XSHAL_RESET_VECTOR_ISROM 1 +#define XSHAL_USER_VECTOR_SIZE 0x00000038 +#define XSHAL_USER_VECTOR_ISROM 0 +#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038 +#define XSHAL_KERNEL_VECTOR_ISROM 0 +#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ +#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040 +#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0 +#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 +#define XSHAL_WINDOW_VECTORS_ISROM 0 +#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL2_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL3_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL4_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL5_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038 +#define XSHAL_INTLEVEL6_VECTOR_ISROM 0 +#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE +#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM +#define XSHAL_NMI_VECTOR_SIZE 0x00000038 +#define XSHAL_NMI_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE + + +#endif /*XTENSA_CONFIG_SYSTEM_H*/ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/suecreek/include/arch/xtensa/config/tie-asm.h b/src/platform/suecreek/include/arch/xtensa/config/tie-asm.h new file mode 100644 index 000000000000..706545aeed86 --- /dev/null +++ b/src/platform/suecreek/include/arch/xtensa/config/tie-asm.h @@ -0,0 +1,247 @@ +/* + * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file contains assembly-language definitions (assembly + macros, etc.) for this specific Xtensa processor's TIE extensions + and options. It is customized to this Xtensa processor configuration. + + Copyright (c) 1999-2015 Cadence Design Systems Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#if !defined __XCC__ + +#ifndef _XTENSA_CORE_TIE_ASM_H +#define _XTENSA_CORE_TIE_ASM_H + +/* Selection parameter values for save-area save/restore macros: */ +/* Option vs. TIE: */ +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ +/* Whether used automatically by compiler: */ +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ +/* ABI handling across function calls: */ +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ +/* Misc */ +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ +#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ + | ((ccuse) & XTHAL_SAS_ANYCC) \ + | ((abi) & XTHAL_SAS_ANYABI) ) + + + /* + * Macro to store all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger store sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to store. Defaults to next available space + * (or 0 if is 0). + * select Select what category(ies) of registers to store, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in , space for + * the corresponding registers is skipped without doing any load. + */ + .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Optional caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr.BR \at1 // boolean option + l32i \at1, \ptr, .Lxchal_ofs_+4 + wsr.SCOMPARE1 \at1 // conditional store option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .endif + .endm // xchal_ncp_load + + +#define XCHAL_NCP_NUM_ATMPS 1 + + /* + * Macro to store the state of TIE coprocessor AudioEngineLX. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 8 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_store. + */ +#define xchal_cp_AudioEngineLX_store xchal_cp1_store + .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 0, 8, 8 + rur.AE_OVF_SAR \at1 // ureg 240 + s32i \at1, \ptr, .Lxchal_ofs_+0 + rur.AE_BITHEAD \at1 // ureg 241 + s32i \at1, \ptr, .Lxchal_ofs_+4 + rur.AE_TS_FTS_BU_BP \at1 // ureg 242 + s32i \at1, \ptr, .Lxchal_ofs_+8 + rur.AE_SD_NO \at1 // ureg 243 + s32i \at1, \ptr, .Lxchal_ofs_+12 + ae_sp24x2s.i aep0, \ptr, .Lxchal_ofs_+16 + ae_sp24x2s.i aep1, \ptr, .Lxchal_ofs_+24 + ae_sp24x2s.i aep2, \ptr, .Lxchal_ofs_+32 + ae_sp24x2s.i aep3, \ptr, .Lxchal_ofs_+40 + ae_sp24x2s.i aep4, \ptr, .Lxchal_ofs_+48 + ae_sp24x2s.i aep5, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_sp24x2s.i aep6, \ptr, .Lxchal_ofs_+0 + ae_sp24x2s.i aep7, \ptr, .Lxchal_ofs_+8 + ae_sq56s.i aeq0, \ptr, .Lxchal_ofs_+16 + ae_sq56s.i aeq1, \ptr, .Lxchal_ofs_+24 + ae_sq56s.i aeq2, \ptr, .Lxchal_ofs_+32 + ae_sq56s.i aeq3, \ptr, .Lxchal_ofs_+40 + .set .Lxchal_pofs_, .Lxchal_pofs_ + 64 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 48 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 0, 8, 8 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 112 + .endif + .endm // xchal_cp1_store + + /* + * Macro to load the state of TIE coprocessor AudioEngineLX. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 8 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_load. + */ +#define xchal_cp_AudioEngineLX_load xchal_cp1_load + .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Custom caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 0, 8, 8 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.AE_OVF_SAR \at1 // ureg 240 + l32i \at1, \ptr, .Lxchal_ofs_+4 + wur.AE_BITHEAD \at1 // ureg 241 + l32i \at1, \ptr, .Lxchal_ofs_+8 + wur.AE_TS_FTS_BU_BP \at1 // ureg 242 + l32i \at1, \ptr, .Lxchal_ofs_+12 + wur.AE_SD_NO \at1 // ureg 243 + ae_lp24x2.i aep0, \ptr, .Lxchal_ofs_+16 + ae_lp24x2.i aep1, \ptr, .Lxchal_ofs_+24 + ae_lp24x2.i aep2, \ptr, .Lxchal_ofs_+32 + ae_lp24x2.i aep3, \ptr, .Lxchal_ofs_+40 + ae_lp24x2.i aep4, \ptr, .Lxchal_ofs_+48 + ae_lp24x2.i aep5, \ptr, .Lxchal_ofs_+56 + addi \ptr, \ptr, 64 + ae_lp24x2.i aep6, \ptr, .Lxchal_ofs_+0 + ae_lp24x2.i aep7, \ptr, .Lxchal_ofs_+8 + addi \ptr, \ptr, 16 + ae_lq56.i aeq0, \ptr, .Lxchal_ofs_+0 + ae_lq56.i aeq1, \ptr, .Lxchal_ofs_+8 + ae_lq56.i aeq2, \ptr, .Lxchal_ofs_+16 + ae_lq56.i aeq3, \ptr, .Lxchal_ofs_+24 + .set .Lxchal_pofs_, .Lxchal_pofs_ + 80 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 0, 8, 8 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 112 + .endif + .endm // xchal_cp1_load + +#define XCHAL_CP1_NUM_ATMPS 1 +#define XCHAL_SA_NUM_ATMPS 1 + + /* Empty macros for unconfigured coprocessors: */ + .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + +#endif /*_XTENSA_CORE_TIE_ASM_H*/ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/suecreek/include/arch/xtensa/config/tie.h b/src/platform/suecreek/include/arch/xtensa/config/tie.h new file mode 100644 index 000000000000..b5fd4c9566e4 --- /dev/null +++ b/src/platform/suecreek/include/arch/xtensa/config/tie.h @@ -0,0 +1,177 @@ +/* + * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file describes this specific Xtensa processor's TIE extensions + that extend basic Xtensa core functionality. It is customized to this + Xtensa processor configuration. + + Copyright (c) 1999-2015 Cadence Design Systems Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#if !defined __XCC__ + +#ifndef _XTENSA_CORE_TIE_H +#define _XTENSA_CORE_TIE_H + +#define XCHAL_CP_NUM 1 /* number of coprocessors */ +#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ + +/* Basic parameters of each coprocessor: */ +#define XCHAL_CP1_NAME "AudioEngineLX" +#define XCHAL_CP1_IDENT AudioEngineLX +#define XCHAL_CP1_SA_SIZE 112 /* size of state save area */ +#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */ +#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ + +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ +#define XCHAL_CP0_SA_SIZE 0 +#define XCHAL_CP0_SA_ALIGN 1 +#define XCHAL_CP2_SA_SIZE 0 +#define XCHAL_CP2_SA_ALIGN 1 +#define XCHAL_CP3_SA_SIZE 0 +#define XCHAL_CP3_SA_ALIGN 1 +#define XCHAL_CP4_SA_SIZE 0 +#define XCHAL_CP4_SA_ALIGN 1 +#define XCHAL_CP5_SA_SIZE 0 +#define XCHAL_CP5_SA_ALIGN 1 +#define XCHAL_CP6_SA_SIZE 0 +#define XCHAL_CP6_SA_ALIGN 1 +#define XCHAL_CP7_SA_SIZE 0 +#define XCHAL_CP7_SA_ALIGN 1 + +/* Save area for non-coprocessor optional and custom (TIE) state: */ +#define XCHAL_NCP_SA_SIZE 8 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ +#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */ + +/* + * Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, + * dbnum,base,regnum,bitsz,gapsz,reset,x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see ) + * base = reg shortname w/o index (or sr=special, ur=TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind,p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 2 +#define XCHAL_NCP_SA_LIST(s) \ + XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) + +#define XCHAL_CP0_SA_NUM 0 +#define XCHAL_CP0_SA_LIST(s) /* empty */ + +#define XCHAL_CP1_SA_NUM 16 +#define XCHAL_CP1_SA_LIST(s) \ + XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0) + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ +#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8 +/* Byte length of instruction from its first byte, per FLIX. */ +#define XCHAL_BYTE0_FORMAT_LENGTHS \ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8 + +#endif /*_XTENSA_CORE_TIE_H*/ + +#else + +#error "xcc should not use this header" + +#endif /* __XCC__ */ diff --git a/src/platform/suecreek/include/platform/Makefile.am b/src/platform/suecreek/include/platform/Makefile.am new file mode 100644 index 000000000000..a12dd72ec90a --- /dev/null +++ b/src/platform/suecreek/include/platform/Makefile.am @@ -0,0 +1,12 @@ +noinst_HEADERS = \ + clk.h \ + dma.h \ + idc.h \ + interrupt.h \ + mailbox.h \ + memory.h \ + platcfg.h \ + platform.h \ + pm_runtime.h \ + shim.h \ + timer.h diff --git a/src/platform/suecreek/include/platform/clk.h b/src/platform/suecreek/include/platform/clk.h new file mode 100644 index 000000000000..8b5ee82f883e --- /dev/null +++ b/src/platform/suecreek/include/platform/clk.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifndef __PLATFORM_CLOCK__ +#define __PLATFORM_CLOCK__ + +#define CLK_CPU 0 +#define CLK_SSP 1 + +#define CLK_DEFAULT_CPU_HZ 120000000 +#define CLK_MAX_CPU_HZ 400000000 + +#endif diff --git a/src/platform/suecreek/include/platform/dma.h b/src/platform/suecreek/include/platform/dma.h new file mode 100644 index 000000000000..28dbce11c4aa --- /dev/null +++ b/src/platform/suecreek/include/platform/dma.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifndef __PLATFORM_DMA_H__ +#define __PLATFORM_DMA_H__ + +#include + +/* available DMACs */ +#define DMA_GP_LP_DMAC0 0 +#define DMA_GP_LP_DMAC1 1 +#define DMA_GP_LP_DMAC2 2 + + +/* mappings - TODO improve API to get type */ +#define DMA_ID_DMAC0 DMA_GP_LP_DMAC0 +#define DMA_ID_DMAC1 DMA_GP_LP_DMAC1 +#define DMA_ID_DMAC2 DMA_GP_LP_DMAC1 + +/* handshakes */ +#define DMA_HANDSHAKE_DMIC_CH0 0 +#define DMA_HANDSHAKE_DMIC_CH1 1 +#define DMA_HANDSHAKE_SSP0_RX 2 +#define DMA_HANDSHAKE_SSP0_TX 3 +#define DMA_HANDSHAKE_SSP1_RX 4 +#define DMA_HANDSHAKE_SSP1_TX 5 +#define DMA_HANDSHAKE_SSP2_RX 6 +#define DMA_HANDSHAKE_SSP2_TX 7 +#define DMA_HANDSHAKE_SSP3_RX 8 +#define DMA_HANDSHAKE_SSP3_TX 9 + +int dmac_init(void); + +#endif diff --git a/src/platform/suecreek/include/platform/idc.h b/src/platform/suecreek/include/platform/idc.h new file mode 100644 index 000000000000..d57713dc1145 --- /dev/null +++ b/src/platform/suecreek/include/platform/idc.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2018, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Tomasz Lauda + */ + +#ifndef __INCLUDE_PLATFORM_IDC_H__ +#define __INCLUDE_PLATFORM_IDC_H__ + +#include + +static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode) +{ + return arch_idc_send_msg(msg, mode); +} + +static inline void idc_init(void) +{ + arch_idc_init(); +} + +#endif diff --git a/src/platform/suecreek/include/platform/interrupt.h b/src/platform/suecreek/include/platform/interrupt.h new file mode 100644 index 000000000000..a3c778cdde40 --- /dev/null +++ b/src/platform/suecreek/include/platform/interrupt.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifndef __INCLUDE_PLATFORM_INTERRUPT__ +#define __INCLUDE_PLATFORM_INTERRUPT__ + +#include +#include + +#define PLATFORM_IRQ_CHILDREN 32 + +/* IRQ numbers - wrt Tensilica DSP */ +#define IRQ_NUM_SOFTWARE0 0 /* level 1 */ +#define IRQ_NUM_TIMER1 1 /* level 1 */ +#define IRQ_NUM_EXT_LEVEL1 2 /* level 1 */ +#define IRQ_NUM_SOFTWARE1 3 /* level 1 */ +#define IRQ_NUM_SOFTWARE2 4 /* level 2 */ +#define IRQ_NUM_TIMER2 5 /* level 2 */ +#define IRQ_NUM_EXT_LEVEL2 6 /* level 2 */ +#define IRQ_NUM_SOFTWARE3 7 /* level 2 */ +#define IRQ_NUM_SOFTWARE4 8 /* level 3 */ +#define IRQ_NUM_TIMER3 9 /* level 3 */ +#define IRQ_NUM_EXT_LEVEL3 10 /* level 3 */ +#define IRQ_NUM_SOFTWARE5 11 /* level 3 */ +#define IRQ_NUM_SOFTWARE6 12 /* level 4 */ +#define IRQ_NUM_EXT_LEVEL4 13 /* level 4 */ +#define IRQ_NUM_SOFTWARE7 14 /* level 4 */ +#define IRQ_NUM_SOFTWARE8 15 /* level 5 */ +#define IRQ_NUM_EXT_LEVEL5 16 /* level 5 */ +#define IRQ_NUM_EXT_LEVEL6 17 /* level 5 */ +#define IRQ_NUM_EXT_LEVEL7 18 /* level 5 */ +#define IRQ_NUM_SOFTWARE9 19 /* level 5 */ +#define IRQ_NUM_NMI 20 /* level 7 */ + +/* IRQ Level 2 bits */ +#define IRQ_BIT_LVL2_HP_GP_DMA0(x) (x + 24) +#define IRQ_BIT_LVL2_WALL_CLK1 23 +#define IRQ_BIT_LVL2_WALL_CLK0 22 +#define IRQ_BIT_LVL2_L2_MEMERR 21 +#define IRQ_BIT_LVL2_SHA256 16 +#define IRQ_BIT_LVL2_L2_CACHE 15 +#define IRQ_BIT_LVL2_IDC 8 +#define IRQ_BIT_LVL2_USB 7 +#define IRQ_BIT_LVL2_HOST_IPC 7 +#define IRQ_BIT_LVL2_CSME_IPC 6 +#define IRQ_BIT_LVL2_PMC_IPC 5 + +/* IRQ Level 3 bits EXT10 */ +#define IRQ_BIT_LVL3_CODE_LOADER 31 +#define IRQ_BIT_LVL3_HOST_STREAM_OUT(x) (16 + x) +#define IRQ_BIT_LVL3_HOST_STREAM_IN(x) (0 + x) +#define IRQ_BIT_LVL3_HPGPDMA 15 + +/* IRQ Level 4 bits EXT13 */ +#define IRQ_BIT_LVL4_LINK_STREAM_OUT(x) (16 + x) +#define IRQ_BIT_LVL4_LINK_STREAM_IN(x) (0 + x) + +/* IRQ Level 5 bits EXT16 */ +#define IRQ_BIT_LVL5_LP_GP_DMA1 15 +#define IRQ_BIT_LVL5_LP_GP_DMA0 16 +#define IRQ_BIT_LVL5_DMIC 6 +#define IRQ_BIT_LVL5_SSP(x) (0 + x) + +/* Priority 2 Peripheral IRQ mappings */ +#define IRQ_EXT_HP_GPDMA_LVL2(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL2_HP_GP_DMA0(0), 2, xcpu, IRQ_NUM_EXT_LEVEL2) +#define IRQ_EXT_IDC_LVL2(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL2_IDC, 2, xcpu, IRQ_NUM_EXT_LEVEL2) +#define IRQ_EXT_IPC_LVL2(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL2_HOST_IPC, 2, xcpu, IRQ_NUM_EXT_LEVEL2) +#define IRQ_EXT_TSTAMP1_LVL2(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL2_WALL_CLK1, 2, xcpu, IRQ_NUM_EXT_LEVEL2) +#define IRQ_EXT_TSTAMP0_LVL2(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL2_WALL_CLK0, 2, xcpu, IRQ_NUM_EXT_LEVEL2) +#define IRQ_EXT_MERR_LVL2(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL2_L2_MEMERR, 2, xcpu, IRQ_NUM_EXT_LEVEL2) +#define IRQ_EXT_L2CACHE_LVL2(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL2_L2_CACHE, 2, xcpu, IRQ_NUM_EXT_LEVEL2) +#define IRQ_EXT_SHA256_LVL2(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL2_SHA256, 2, xcpu, IRQ_NUM_EXT_LEVEL2) + +/* Priority 3 Peripheral IRQ mappings */ +#define IRQ_EXT_CODE_DMA_LVL3(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL3_CODE_LOADER, 3, xcpu, IRQ_NUM_EXT_LEVEL3) +#define IRQ_EXT_HOST_DMA_IN_LVL3(xcpu, channel) \ + SOF_IRQ(IRQ_BIT_LVL3_HOST_STREAM_IN(channel), 3, xcpu, IRQ_NUM_EXT_LEVEL3) +#define IRQ_EXT_HOST_DMA_OUT_LVL3(xcpu, channel) \ + SOF_IRQ(IRQ_BIT_LVL3_HOST_STREAM_OUT(channel), 3, xcpu, IRQ_NUM_EXT_LEVEL3) + +/* Priority 4 Peripheral IRQ mappings */ +#define IRQ_EXT_LINK_DMA_IN_LVL4(xcpu, channel) \ + SOF_IRQ(IRQ_BIT_LVL4_LINK_STREAM_IN(channel), 4, xcpu, IRQ_NUM_EXT_LEVEL4) +#define IRQ_EXT_LINK_DMA_OUT_LVL4(xcpu, channel) \ + SOF_IRQ(IRQ_BIT_LVL4_LINK_STREAM_OUT(channel), 4, xcpu, IRQ_NUM_EXT_LEVEL4) + +/* Priority 5 Peripheral IRQ mappings */ +#define IRQ_EXT_LP_GPDMA0_LVL5(xcpu, channel) \ + SOF_ID_IRQ(0, IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5) +#define IRQ_EXT_LP_GPDMA1_LVL5(xcpu, channel) \ + SOF_ID_IRQ(1, IRQ_BIT_LVL5_LP_GP_DMA0, 5, xcpu, IRQ_NUM_EXT_LEVEL5) +#define IRQ_EXT_SSP0_LVL5(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL5_SSP(0), 5, xcpu, IRQ_NUM_EXT_LEVEL5) +#define IRQ_EXT_SSP1_LVL5(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL5_SSP(1), 5, xcpu, IRQ_NUM_EXT_LEVEL5) +#define IRQ_EXT_SSP2_LVL5(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL5_SSP(2), 5, xcpu, IRQ_NUM_EXT_LEVEL5) +#define IRQ_EXT_SSP3_LVL5(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL5_SSP(3), 5, xcpu, IRQ_NUM_EXT_LEVEL5) +#define IRQ_EXT_DMIC_LVL5(xcpu) \ + SOF_IRQ(IRQ_BIT_LVL5_DMIC, 5, xcpu, IRQ_NUM_EXT_LEVEL5) + + +/* IRQ Masks */ +#define IRQ_MASK_SOFTWARE0 (1 << IRQ_NUM_SOFTWARE0) +#define IRQ_MASK_TIMER1 (1 << IRQ_NUM_TIMER1) +#define IRQ_MASK_EXT_LEVEL1 (1 << IRQ_NUM_EXT_LEVEL1) +#define IRQ_MASK_SOFTWARE1 (1 << IRQ_NUM_SOFTWARE1) +#define IRQ_MASK_SOFTWARE2 (1 << IRQ_NUM_SOFTWARE2) +#define IRQ_MASK_TIMER2 (1 << IRQ_NUM_TIMER2) +#define IRQ_MASK_EXT_LEVEL2 (1 << IRQ_NUM_EXT_LEVEL2) +#define IRQ_MASK_SOFTWARE3 (1 << IRQ_NUM_SOFTWARE3) +#define IRQ_MASK_SOFTWARE4 (1 << IRQ_NUM_SOFTWARE4) +#define IRQ_MASK_TIMER3 (1 << IRQ_NUM_TIMER3) +#define IRQ_MASK_EXT_LEVEL3 (1 << IRQ_NUM_EXT_LEVEL3) +#define IRQ_MASK_SOFTWARE5 (1 << IRQ_NUM_SOFTWARE5) +#define IRQ_MASK_SOFTWARE6 (1 << IRQ_NUM_SOFTWARE6) +#define IRQ_MASK_EXT_LEVEL4 (1 << IRQ_NUM_EXT_LEVEL4) +#define IRQ_MASK_SOFTWARE7 (1 << IRQ_NUM_SOFTWARE7) +#define IRQ_MASK_SOFTWARE8 (1 << IRQ_NUM_SOFTWARE8) +#define IRQ_MASK_EXT_LEVEL5 (1 << IRQ_NUM_EXT_LEVEL5) +#define IRQ_MASK_EXT_LEVEL6 (1 << IRQ_NUM_EXT_LEVEL6) +#define IRQ_MASK_EXT_LEVEL7 (1 << IRQ_NUM_EXT_LEVEL7) +#define IRQ_MASK_SOFTWARE9 (1 << IRQ_NUM_SOFTWARE9) + + +/* platform interrupt control */ +#define SUE_DW_ICTL_BASE_ADDR 0x00081800 +#define SUE_DW_ICTL_IRQ_INTEN_L (0x00 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_INTEN_H (0x04 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_INTMASK_L (0x08 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_INTMASK_H (0x0C + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_INTFORCE_L (0x10 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_INTFORCE_H (0x14 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_RAWSTATUS_L (0x18 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_RAWSTATUS_H (0x1C + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_STATUS_L (0x20 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_STATUS_H (0x24 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_MASKSTATUS_L (0x28 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_MASKSTATUS_H (0x2C + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_FINALSTATUS_L (0x30 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_FINALSTATUS_H (0x34 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR (0x38 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_0 (0x40 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_1 (0x48 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_2 (0x50 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_3 (0x58 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_4 (0x60 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_5 (0x68 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_6 (0x70 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_7 (0x78 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_8 (0x80 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_9 (0x88 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_10 (0x90 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_11 (0x98 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_12 (0xA0 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_13 (0xA8 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_14 (0xB0 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_VECTOR_15 (0xB8 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_FIQ_INTEN (0xC0 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_FIQ_INTMASK (0xC4 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_FIQ_INTFORCE (0xC8 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_FIQ_RAWSTATUS (0xCC + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_FIQ_STATUS (0xD0 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_FIQ_FINALSTATUS (0xD4 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_IRQ_FIQ_PLEVEL (0xD8 + SUE_DW_ICTL_BASE_ADDR) +#define SUE_DW_ICTL_PR_N(x) (0xE8 + x*4 + SUE_DW_ICTL_BASE_ADDR) +#endif diff --git a/src/platform/suecreek/include/platform/mailbox.h b/src/platform/suecreek/include/platform/mailbox.h new file mode 100644 index 000000000000..a493e2493ff3 --- /dev/null +++ b/src/platform/suecreek/include/platform/mailbox.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifndef __INCLUDE_PLATFORM_MAILBOX__ +#define __INCLUDE_PLATFORM_MAILBOX__ + +#include + +/* TODO: no SHM mailbox on SUE, must be sent via SPI */ +#if 0 +#define MAILBOX_HOST_OFFSET 0x144000 + +#define MAILBOX_OUTBOX_OFFSET 0x0 +#define MAILBOX_OUTBOX_SIZE 0x400 +#define MAILBOX_OUTBOX_BASE \ + (MAILBOX_BASE + MAILBOX_OUTBOX_OFFSET) + +#define MAILBOX_INBOX_OFFSET MAILBOX_OUTBOX_SIZE +#define MAILBOX_INBOX_SIZE 0x400 +#define MAILBOX_INBOX_BASE \ + (MAILBOX_BASE + MAILBOX_INBOX_OFFSET) + +#define MAILBOX_EXCEPTION_OFFSET \ + (MAILBOX_INBOX_SIZE + MAILBOX_OUTBOX_SIZE) +#define MAILBOX_EXCEPTION_SIZE 0x100 +#define MAILBOX_EXCEPTION_BASE \ + (MAILBOX_BASE + MAILBOX_EXCEPTION_OFFSET) + +#define MAILBOX_DEBUG_OFFSET \ + (MAILBOX_EXCEPTION_SIZE + MAILBOX_EXCEPTION_OFFSET) +#define MAILBOX_DEBUG_SIZE 0x100 +#define MAILBOX_DEBUG_BASE \ + (MAILBOX_BASE + MAILBOX_DEBUG_OFFSET) + +#define MAILBOX_STREAM_OFFSET \ + (MAILBOX_DEBUG_SIZE + MAILBOX_DEBUG_OFFSET) +#define MAILBOX_STREAM_SIZE 0x200 +#define MAILBOX_STREAM_BASE \ + (MAILBOX_BASE + MAILBOX_STREAM_OFFSET) + +#define MAILBOX_TRACE_OFFSET \ + (MAILBOX_STREAM_SIZE + MAILBOX_STREAM_OFFSET) +#define MAILBOX_TRACE_SIZE 0x380 +#define MAILBOX_TRACE_BASE \ + (MAILBOX_BASE + MAILBOX_TRACE_OFFSET) + +#endif + +// TODO need added to linker map + +#define MAILBOX_DEBUG_SIZE 0 +#define MAILBOX_DEBUG_BASE 0 + +#define MAILBOX_HOSTBOX_SIZE 0 +#define MAILBOX_HOSTBOX_BASE 0 + +#define MAILBOX_DSPBOX_SIZE 0 +#define MAILBOX_DSPBOX_BASE 0 + +#define MAILBOX_TRACE_SIZE 0 +#define MAILBOX_TRACE_BASE 0 + +#define MAILBOX_EXCEPTION_SIZE 0 +#define MAILBOX_EXCEPTION_BASE 0 + +#endif diff --git a/src/platform/suecreek/include/platform/memory.h b/src/platform/suecreek/include/platform/memory.h new file mode 100644 index 000000000000..6ba9908e80a3 --- /dev/null +++ b/src/platform/suecreek/include/platform/memory.h @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifndef __PLATFORM_MEMORY_H__ +#define __PLATFORM_MEMORY_H__ + +#include + +/* physical DSP addresses */ + +/* shim */ +#define SHIM_BASE 0x00071F00 +#define SHIM_SIZE 0x00000100 + +/* cmd IO to audio codecs */ +#define CMD_BASE 0x00001100 +#define CMD_SIZE 0x00000010 + +/* resource allocation */ +#define RES_BASE 0x00001110 +#define RES_SIZE 0x00000010 + +/* IPC to the host */ +#define IPC_HOST_BASE 0x00071E00 +#define IPC_HOST_SIZE 0x00000020 + +/* intra DSP IPC */ +#define IPC_DSP_SIZE 0x00000080 +#define IPC_DSP_BASE(x) (0x00001200 + x * IPC_DSP_SIZE) + +/* SRAM window for HOST */ +#define HOST_WIN_SIZE 0x00000008 +#define HOST_WIN_BASE(x) (0x00071A00 + x * HOST_WIN_SIZE) + +/* IRQ controller */ +#define IRQ_BASE 0x00078800 +#define IRQ_SIZE 0x00000200 + +/* time stamping */ +#define TIME_BASE 0x00071800 +#define TIME_SIZE 0x00000200 + +/* M/N dividers */ +#define MN_BASE 0x00078C00 +#define MN_SIZE 0x00000200 + +/* low power DMA position */ +#define LP_GP_DMA_LINK_SIZE 0x00000080 +#define LP_GP_DMA_LINK_BASE(x) (0x00001C00 + x * LP_GP_DMA_LINK_SIZE) + +/* high performance DMA position */ +#define HP_GP_DMA_LINK_SIZE 0x00000800 +#define HP_GP_DMA_LINK_BASE(x) (0x00001D00 + x * HP_GP_DMA_LINK_SIZE) + +/* link DMAC stream */ +#define GTW_LINK_OUT_STREAM_SIZE 0x00000020 +#define GTW_LINK_OUT_STREAM_BASE(x) \ + (0x00072400 + x * GTW_LINK_OUT_STREAM_SIZE) + +#define GTW_LINK_IN_STREAM_SIZE 0x00000020 +#define GTW_LINK_IN_STREAM_BASE(x) \ + (0x00072600 + x * GTW_LINK_IN_STREAM_SIZE) + +/* host DMAC stream */ +#define GTW_HOST_OUT_STREAM_SIZE 0x00000040 +#define GTW_HOST_OUT_STREAM_BASE(x) \ + (0x00072800 + x * GTW_HOST_OUT_STREAM_SIZE) + +#define GTW_HOST_IN_STREAM_SIZE 0x00000040 +#define GTW_HOST_IN_STREAM_BASE(x) \ + (0x00072C00 + x * GTW_HOST_IN_STREAM_SIZE) + +/* code loader */ +#define GTW_CODE_LDR_SIZE 0x00000040 +#define GTW_CODE_LDR_BASE 0x00002BC0 + +/* L2 TLBs */ +#define L2_HP_SRAM_TLB_SIZE 0x00001000 +#define L2_HP_SRAM_TLB_BASE 0x00003000 + +/* DMICs */ +#define DMIC_BASE 0x00010000 +#define DMIC_SIZE 0x00008000 + +/* SSP */ +#define SSP_BASE(x) (0x00077000 + x * SSP_SIZE) +#define SSP_SIZE 0x0000200 + +/* low power DMACs */ +#define LP_GP_DMA_SIZE 0x00001000 +#define LP_GP_DMA_BASE(x) (0x0007C000 + x * LP_GP_DMA_SIZE) + +/* high performance DMACs */ +#define HP_GP_DMA_SIZE 0x00001000 +#define HP_GP_DMA_BASE(x) (0x0000E000 + x * HP_GP_DMA_SIZE) + +/* ROM */ +#define ROM_BASE 0xBEFE0000 +#define ROM_SIZE 0x00002000 + +#define LOG_ENTRY_ELF_BASE 0x20000000 +#define LOG_ENTRY_ELF_SIZE 0x2000000 + +/* + * The HP SRAM Region on Sue Creek is organised like this :- + * +--------------------------------------------------------------------------+ + * | Offset | Region | Size | + * +---------------------+----------------+-----------------------------------+ + * | HP_SRAM_BASE | RO Data | REEF_DATA_SIZE | + * | | Data | | + * | | BSS | | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_END | Stack | SOF_STACK_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_BASE | | | + * +---------------------+----------------+-----------------------------------+ + */ + +/* HP SRAM */ +#define SRAM_ALIAS_OFFSET 0x20000000 +#define HP_SRAM_BASE 0xBE000000 +#define HP_SRAM_SIZE 0x002F0000 /* Should be 48 * 64 - 0x300000 ?? */ + +/* HP SRAM Base */ +#define HP_SRAM_VECBASE_RESET (HP_SRAM_BASE + 0x40000) + +/* Heap section sizes for module pool */ +#define HEAP_RT_COUNT64 256 +#define HEAP_RT_COUNT128 32 +#define HEAP_RT_COUNT256 64 +#define HEAP_RT_COUNT512 32 + +#define L2_VECTOR_SIZE 0x2000 + +#define SOF_TEXT_START (HP_SRAM_BASE + L2_VECTOR_SIZE) +#define SOF_TEXT_START_SIZE 0x400 +#define SOF_TEXT_BASE (SOF_TEXT_START + SOF_TEXT_START_SIZE) +#define SOF_TEXT_SIZE (0x40000 - SOF_TEXT_START_SIZE) + +/* initialized data */ +#if defined CONFIG_DMIC +#define SOF_DATA_SIZE 0x1b000 +#else +#define SOF_DATA_SIZE 0x19000 +#endif + +/* bss data */ +#define SOF_BSS_DATA_SIZE 0x10900 + +/* Heap configuration */ +/* Heap configuration */ +#define HEAP_SYSTEM_0_BASE \ + (SOF_TEXT_BASE + SOF_TEXT_SIZE +\ + SOF_DATA_SIZE + SOF_BSS_DATA_SIZE) +#define HEAP_SYSTEM_0_SIZE 0x8000 + +#define HEAP_SYSTEM_1_BASE (HEAP_SYSTEM_0_BASE + HEAP_SYSTEM_0_SIZE) +#define HEAP_SYSTEM_1_SIZE 0x1000 + +#define HEAP_SYSTEM_T_SIZE (HEAP_SYSTEM_0_SIZE + HEAP_SYSTEM_1_SIZE) + +#define HEAP_RUNTIME_BASE (HEAP_SYSTEM_1_BASE + HEAP_SYSTEM_1_SIZE) +#define HEAP_RUNTIME_SIZE \ + (HEAP_RT_COUNT64 * 64 + HEAP_RT_COUNT128 * 128 + \ + HEAP_RT_COUNT256 * 256 + HEAP_RT_COUNT512 * 512) + +/* Stack configuration */ +#define SOF_STACK_SIZE 0x2000 +#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE) +#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_SIZE) + +#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE) +#define HEAP_BUFFER_SIZE \ + (SOF_STACK_END - HEAP_BUFFER_BASE) +#define HEAP_BUFFER_BLOCK_SIZE 0x180 +#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE) + +#define HEAP_HP_BUFFER_COUNT 0 +#define HEAP_HP_BUFFER_BLOCK_SIZE 0 +#define HEAP_HP_BUFFER_BASE 0 +#define HEAP_HP_BUFFER_SIZE 0 + + +/* + * The LP SRAM Heap and Stack on Suecreek are organised like this :- + * + * +--------------------------------------------------------------------------+ + * | Offset | Region | Size | + * +---------------------+----------------+-----------------------------------+ + * | LP_SRAM_BASE | RO Data | SOF_LP_DATA_SIZE | + * | | Data | | + * | | BSS | | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_LP_SYSTEM_BASE | System Heap | HEAP_LP_SYSTEM_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_LP_RUNTIME_BASE| Runtime Heap | HEAP_LP_RUNTIME_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_LP_BUFFER_BASE | Module Buffers | HEAP_LP_BUFFER_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_LP_STACK_END | Stack | SOF_LP_STACK_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_BASE | | | + * +---------------------+----------------+-----------------------------------+ + */ + +/* LP SRAM */ +#define LP_SRAM_BASE 0xBE800000 +#define LP_SRAM_SIZE 0x00010000 + +/* Heap section sizes for module pool */ +#define HEAP_RT_LP_COUNT8 0 +#define HEAP_RT_LP_COUNT16 256 +#define HEAP_RT_LP_COUNT32 128 +#define HEAP_RT_LP_COUNT64 64 +#define HEAP_RT_LP_COUNT128 32 +#define HEAP_RT_LP_COUNT256 16 +#define HEAP_RT_LP_COUNT512 8 +#define HEAP_RT_LP_COUNT1024 4 + +/* Heap configuration */ +#define SOF_LP_DATA_SIZE 0x4000 + +#define HEAP_LP_SYSTEM_BASE (LP_SRAM_BASE + SOF_LP_DATA_SIZE) +#define HEAP_LP_SYSTEM_SIZE 0x1000 + +#define HEAP_LP_RUNTIME_BASE (HEAP_LP_SYSTEM_BASE + HEAP_LP_SYSTEM_SIZE) +#define HEAP_LP_RUNTIME_SIZE \ + (HEAP_RT_LP_COUNT8 * 8 + HEAP_RT_LP_COUNT16 * 16 + \ + HEAP_RT_LP_COUNT32 * 32 + HEAP_RT_LP_COUNT64 * 64 + \ + HEAP_RT_LP_COUNT128 * 128 + HEAP_RT_LP_COUNT256 * 256 + \ + HEAP_RT_LP_COUNT512 * 512 + HEAP_RT_LP_COUNT1024 * 1024) + +#define HEAP_LP_BUFFER_BASE (HEAP_LP_RUNTIME_BASE + HEAP_LP_RUNTIME_SIZE) +#define HEAP_LP_BUFFER_SIZE \ + (LP_SRAM_SIZE - HEAP_LP_RUNTIME_SIZE - SOF_LP_STACK_SIZE - HEAP_LP_SYSTEM_SIZE) + +#define HEAP_LP_BUFFER_BLOCK_SIZE 0x180 +#define HEAP_LP_BUFFER_COUNT (HEAP_LP_BUFFER_SIZE / HEAP_LP_BUFFER_BLOCK_SIZE) + + +#define PLATFORM_HEAP_SYSTEM 2 /* one per core */ +#define PLATFORM_HEAP_RUNTIME 1 +#define PLATFORM_HEAP_BUFFER 3 + +/* Stack configuration */ +#define SOF_LP_STACK_SIZE 0x1000 +#define SOF_LP_STACK_BASE (LP_SRAM_BASE + LP_SRAM_SIZE) +#define SOF_LP_STACK_END (SOF_LP_STACK_BASE - SOF_LP_STACK_SIZE) + + +/* Vector and literal sizes - do not use core-isa.h */ +#define SOF_MEM_VECBASE HP_SRAM_VECBASE_RESET +#define SOF_MEM_VECT_LIT_SIZE 0x8 +#define SOF_MEM_VECT_TEXT_SIZE 0x38 +#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE) + +#define SOF_MEM_ERROR_TEXT_SIZE 0x180 +#define SOF_MEM_ERROR_LIT_SIZE 0x8 + +#define SOF_MEM_RESET_TEXT_SIZE 0x268 +#define SOF_MEM_RESET_LIT_SIZE 0x8 +#define SOF_MEM_VECBASE_LIT_SIZE 0x178 + +#define SOF_MEM_RO_SIZE 0x8 + +/* code loader */ +#define BOOT_LDR_TEXT_ENTRY_BASE 0xBE000000 +#define BOOT_LDR_TEXT_ENTRY_SIZE 0x400 +#define BOOT_LDR_LIT_BASE (BOOT_LDR_TEXT_ENTRY_BASE + BOOT_LDR_TEXT_ENTRY_SIZE) +#define BOOT_LDR_LIT_SIZE 0x400 +#define BOOT_LDR_TEXT_BASE (BOOT_LDR_LIT_BASE + BOOT_LDR_LIT_SIZE) +#define BOOT_LDR_TEXT_SIZE 0x800 +#define BOOT_LDR_DATA_BASE (BOOT_LDR_TEXT_BASE + BOOT_LDR_TEXT_SIZE) +#define BOOT_LDR_DATA_SIZE 0x1000 +#define BOOT_LDR_BSS_BASE (BOOT_LDR_DATA_BASE + BOOT_LDR_DATA_SIZE) +#define BOOT_LDR_BSS_SIZE 0x100 + +/* TODO: set this value */ +#define BOOT_LDR_MANIFEST_BASE 0x55aa55aa + +/* code lodar entry point for base fw */ +#define SRAM_VECBASE_RESET (BOOT_LDR_BSS_BASE + BOOT_LDR_BSS_SIZE) + +//TODO: confirm mapping +#define SRAM_ALIAS_OFFSET 0x20000000 +#define uncache_to_cache(address) \ + ((__typeof__((address)))((uint32_t)((address)) + SRAM_ALIAS_OFFSET)) +#define cache_to_uncache(address) \ + ((__typeof__((address)))((uint32_t)((address)) - SRAM_ALIAS_OFFSET)) + +#endif diff --git a/src/platform/suecreek/include/platform/platcfg.h b/src/platform/suecreek/include/platform/platcfg.h new file mode 100644 index 000000000000..f455ff20331c --- /dev/null +++ b/src/platform/suecreek/include/platform/platcfg.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2018, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood + */ + +#ifndef __PLATFORM_PLATCFG_H__ +#define __PLATFORM_PLATCFG_H__ + +#define PLATFORM_RESET_MHE_AT_BOOT 1 + +#define PLATFORM_CORE_COUNT 4 + +#define PLATFORM_MASTER_CORE_ID 0 + +#endif diff --git a/src/platform/suecreek/include/platform/platform.h b/src/platform/suecreek/include/platform/platform.h new file mode 100644 index 000000000000..138513824c01 --- /dev/null +++ b/src/platform/suecreek/include/platform/platform.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + * Xiuli Pan + */ + +#ifndef __PLATFORM_PLATFORM_H__ +#define __PLATFORM_PLATFORM_H__ + +#include +#include +#include +#include +#include + +struct sof; + +/*! \def PLATFORM_DEFAULT_CLOCK + * \brief clock source for audio pipeline + * + * There are two types of clock: cpu clock which is a internal clock in + * xtensa core, and ssp clock which is provided by external HW IP. + * The choice depends on HW features on different platform + */ +#define PLATFORM_DEFAULT_CLOCK CLK_SSP + +/*! \def PLATFORM_WORKQ_DEFAULT_TIMEOUT + * \brief work queue default timeout in microseconds + */ +#define PLATFORM_WORKQ_DEFAULT_TIMEOUT 1000 + +#define PLATFORM_WAITI_DELAY 1 + +#define PLATFORM_SSP_COUNT 3 +#define MAX_GPDMA_COUNT 2 + +/* DGMBS align value */ +#define PLATFORM_HDA_BUFFER_ALIGNMENT 0x20 + +/* Host page size */ +#define HOST_PAGE_SIZE 4096 +#define PLATFORM_PAGE_TABLE_SIZE 256 + +/* IDC Interrupt */ +#define PLATFORM_IDC_INTERRUPT(x) IRQ_EXT_IDC_LVL2(x) + +/* IPC Interrupt */ +#define PLATFORM_IPC_INTERRUPT IRQ_EXT_IPC_LVL2(0) + +/* pipeline IRQ */ +#define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE4 + +#define PLATFORM_IRQ_TASK_HIGH IRQ_NUM_SOFTWARE3 +#define PLATFORM_IRQ_TASK_MED IRQ_NUM_SOFTWARE2 +#define PLATFORM_IRQ_TASK_LOW IRQ_NUM_SOFTWARE1 + +#define PLATFORM_SCHEDULE_COST 200 + +/* maximum preload pipeline depth */ +#define MAX_PRELOAD_SIZE 20 + +/* DMA treats PHY addresses as host address unless within DSP region */ +#define PLATFORM_HOST_DMA_MASK 0x00000000 + +/* Platform stream capabilities */ +#define PLATFORM_MAX_CHANNELS 4 +#define PLATFORM_MAX_STREAMS 5 + +/* clock source used by scheduler for deadline calculations */ +#define PLATFORM_SCHED_CLOCK PLATFORM_DEFAULT_CLOCK + +/* DMA channel drain timeout in microseconds - TODO: caclulate based on topology */ +#define PLATFORM_DMA_TIMEOUT 1333 + +/* DMA host transfer timeouts in microseconds */ +#define PLATFORM_HOST_DMA_TIMEOUT 50 + +/* WorkQ window size in microseconds */ +#define PLATFORM_WORKQ_WINDOW 2000 + +/* platform WorkQ clock */ +#define PLATFORM_WORKQ_CLOCK PLATFORM_DEFAULT_CLOCK + +/* Host finish work schedule delay in microseconds */ +#define PLATFORM_HOST_FINISH_DELAY 100 + +/* Host finish work(drain from host to dai) timeout in microseconds */ +#define PLATFORM_HOST_FINISH_TIMEOUT 50000 + +/* local buffer size of DMA tracing */ +#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE + +/* trace bytes flushed during panic */ +#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2) + +/* the interval of DMA trace copying */ +#define DMA_TRACE_PERIOD 500000 + +/* + * the interval of reschedule DMA trace copying in special case like half + * fullness of local DMA trace buffer + */ +#define DMA_TRACE_RESCHEDULE_TIME 100 + +/* DSP should be idle in this time frame */ +#define PLATFORM_IDLE_TIME 750000 + +/* baud-rate used for uart port trace log */ +#define PATFORM_TRACE_UART_BAUDRATE 115200 + +/* DSP default delay in cycles */ +#define PLATFORM_DEFAULT_DELAY 12 + +/* minimal L1 exit time in cycles */ +#define PLATFORM_FORCE_L1_EXIT_TIME 985 + +/* the SSP port fifo depth */ +#define SSP_FIFO_DEPTH 16 + +/* the watermark for the SSP fifo depth setting */ +#define SSP_FIFO_WATERMARK 8 + +/* minimal SSP port stop delay in cycles */ +#define PLATFORM_SSP_STOP_DELAY 3000 + +// TODO: need UART versions +#if 0 +/* Platform defined trace code */ +static inline void platform_panic(uint32_t p) +{ + mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p & 0x3fffffff); + ipc_write(IPC_DIPCIDD, MAILBOX_EXCEPTION_OFFSET + 2 * 0x20000); + ipc_write(IPC_DIPCIDR, 0x80000000 | (p & 0x3fffffff)); +} + +/* Platform defined trace code */ +#define platform_trace_point(__x) \ + mailbox_sw_reg_write(SRAM_REG_FW_TRACEP, (__x)) +#else +static inline void platform_panic(uint32_t p) +{ +} + +/* Platform defined trace code */ +#define platform_trace_point(__x) +#endif +extern struct timer *platform_timer; + +/* + * APIs declared here are defined for every platform and IPC mechanism. + */ + +int platform_ssp_set_mn(uint32_t ssp_port, uint32_t source, uint32_t rate, + uint32_t bclk_fs); + +void platform_ssp_disable_mn(uint32_t ssp_port); + +#endif diff --git a/src/platform/suecreek/include/platform/pm_runtime.h b/src/platform/suecreek/include/platform/pm_runtime.h new file mode 100644 index 000000000000..2158f99a5caf --- /dev/null +++ b/src/platform/suecreek/include/platform/pm_runtime.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2018, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Tomasz Lauda + */ + +/** + * \file platform/cannonlake/include/platform/pm_runtime.h + * \brief Runtime power management header file for Cannonlake + * \author Tomasz Lauda + */ + +#ifndef __INCLUDE_PLATFORM_PM_RUNTIME__ +#define __INCLUDE_PLATFORM_PM_RUNTIME__ + +#include + +/** \brief Platform specific runtime power management data. */ +struct platform_pm_runtime_data { + /* TBD */ +}; + +/** + * \brief Initializes platform specific runtime power management. + * \param[in,out] prd Runtime power management data. + */ +void platform_pm_runtime_init(struct pm_runtime_data *prd); + +/** + * \brief Retrieves platform specific power management resource. + * + * \param[in] context Type of power management context. + * \param[in] index Index of the device. + * \param[in] flags Flags, set of RPM_... + */ +void platform_pm_runtime_get(enum pm_runtime_context context, uint32_t index, + uint32_t flags); + +/** + * \brief Releases platform specific power management resource. + * + * \param[in] context Type of power management context. + * \param[in] index Index of the device. + * \param[in] flags Flags, set of RPM_... + */ +void platform_pm_runtime_put(enum pm_runtime_context context, uint32_t index, + uint32_t flags); + +#endif /* __INCLUDE_PLATFORM_PM_RUNTIME__ */ diff --git a/src/platform/suecreek/include/platform/shim.h b/src/platform/suecreek/include/platform/shim.h new file mode 100644 index 000000000000..2a3f91baff16 --- /dev/null +++ b/src/platform/suecreek/include/platform/shim.h @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifndef __PLATFORM_SHIM_H__ +#define __PLATFORM_SHIM_H__ + +#include + +#ifndef ASSEMBLY +#include +#endif + +/* DSP IPC for Host Registers */ +#define IPC_DIPCTDR 0x00 +#define IPC_DIPCTDA 0x04 +#define IPC_DIPCTDD 0x08 +#define IPC_DIPCIDR 0x10 +#define IPC_DIPCIDA 0x14 +#define IPC_DIPCIDD 0x18 +#define IPC_DIPCCTL 0x28 + + +/* DIPCTDR */ +#define IPC_DIPCTDR_BUSY (1 << 31) +#define IPC_DIPCTDR_MSG_MASK 0x7FFFFFFF + +/* DIPCTDA */ +#define IPC_DIPCTDA_BUSY (1 << 31) +#define IPC_DIPCTDA_MSG_MASK 0x7FFFFFFF + +/* DIPCTE */ +#define IPC_DIPCTE_MSG_MASK 0x3FFFFFFF + +/* DIPCIDA*/ +#define IPC_DIPCIDA_DONE (1 << 31) + +/* DIPCIDR */ +#define IPC_DIPCIDR_BUSY (1 << 31) +#define IPC_DIPCIDR_MSG_MASK 0x7FFFFFFF + +/* DIPCIE */ +#define IPC_DIPCIE_DONE (1 << 31) +#define IPC_DIPCIE_MSG_MASK 0x3FFFFFFF + +/* DIPCCTL */ +#define IPC_DIPCCTL_IPCIDIE (1 << 1) +#define IPC_DIPCCTL_IPCTBIE (1 << 0) + +#define IPC_DSP_OFFSET 0x10 + +/* DSP IPC for intra DSP communication */ +#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET) +#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET) +#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET) +#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET) +#define IPC_IDCCTL 0x50 + +/* IDCTFC */ +#define IPC_IDCTFC_BUSY (1 << 31) +#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF + +/* IDCTEFC */ +#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF + +/* IDCITC */ +#define IPC_IDCITC_BUSY (1 << 31) +#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF + +/* IDCIETC */ +#define IPC_IDCIETC_DONE (1 << 30) +#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF + +/* IDCCTL */ +#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x)) +#define IPC_IDCCTL_IDCTBIE(x) (0x1 << (x)) + +#define IRQ_CPU_OFFSET 0x40 + +#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET)) +#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET)) +#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET)) +#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET)) + +/* all mask valid bits */ +#define REG_IRQ_IL2MD_ALL 0x03F181F0 + +#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET)) +#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET)) +#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET)) +#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET)) + +/* all mask valid bits */ +#define REG_IRQ_IL3MD_ALL 0x807F81FF + +#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET)) +#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET)) +#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET)) +#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET)) + +/* all mask valid bits */ +#define REG_IRQ_IL4MD_ALL 0x807F81FF + +#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET)) +#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET)) +#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET)) +#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET)) + +/* all mask valid bits */ +#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF + +#define REG_IRQ_IL2RSD 0x100 +#define REG_IRQ_IL3RSD 0x104 +#define REG_IRQ_IL4RSD 0x108 +#define REG_IRQ_IL5RSD 0x10c + +#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16) +#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24) + +/* DSP Shim Registers */ +#define SHIM_DSPWC 0x20 /* DSP Wall Clock */ +#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */ +#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */ +#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */ + +#define SHIM_DSPWCTCS_T1T (0x1 << 5) /* Timer 1 triggered */ +#define SHIM_DSPWCTCS_T0T (0x1 << 4) /* Timer 0 triggered */ +#define SHIM_DSPWCTCS_T1A (0x1 << 1) /* Timer 1 armed */ +#define SHIM_DSPWCTCS_T0A (0x1 << 0) /* Timer 0 armed */ + +#define SHIM_CLKCTL 0x78 +#define SHIM_CLKSTS 0x7C + +#define SHIM_PWRCTL 0x90 +#define SHIM_PWRSTS 0x92 +#define SHIM_PWRCTL_TCPDSP0PG (0x1 << 0) + +/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */ +#define SHIM_CLKCTL_LPGPDMAFDCGB(x) (0x1 << (26 + x)) +#define SHIM_CLKCTL_TCPLCG(x) (0x1 << (16 + x)) + +/* Core clock PLL divisor */ +#define SHIM_CLKCTL_DPCS_MASK(x) (0x1 << 2) + +/* Prevent Audio PLL Shutdown */ +#define SHIM_CLKCTL_TCPAPLLS (0x1 << 7) + +/* 0--from PLL, 1--from oscillator */ +#define SHIM_CLKCTL_HDCS (0x1 << 4) + +/* Oscillator select */ +#define SHIM_CLKCTL_HDOCS (0x1 << 2) + +/* HP memory clock PLL divisor */ +#define SHIM_CLKCTL_HPMPCS (0x1 << 0) + +#define GPDMA_CLKCTL(x) (0x78404 + x*0x100) +#define GPDMA_FDCGB (0x1 << 0) + +#define L2LMCAP 0x71D00 +#define L2MPAT 0x71D04 + +#define HSPGCTL0 0x71D10 +#define HSRMCTL0 0x71D14 +#define HSPGISTS0 0x71D18 + +#define HSPGCTL1 0x71D20 +#define HSRMCTL1 0x71D24 +#define HSPGISTS1 0x71D28 + +#define LSPGCTL 0x71D50 +#define LSRMCTL 0x71D54 +#define LSPGISTS 0x71D58 + +#define SHIM_L2_MECS (SHIM_BASE + 0xd0) + +#define SHIM_LDOCTL 0xA4 +#define SHIM_HPMEM_POWER_ON (0x3 << 0) +#define SHIM_LPMEM_POWER_BYPASS (0x1 << 0) + +#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x)) +#define LPGPDMA_CTLOSEL_FLAG (1 << 15) +#define LPGPDMA_CHOSEL_FLAG (0xFF) + +#define DSP_INIT_IOPO 0x71A68 +#define IOPO_DMIC_FLAG (1 << 0) +#define IOPO_I2S_FLAG (7 << 8) + +#define DSP_INIT_GENO 0x71A6C +#define GENO_MDIVOSEL (1 << 1) +#define GENO_DIOPTOSEL (1 << 2) + +#define DSP_INIT_ALHO 0x71A70 +#define ALHO_ASO_FLAG (1 << 0) +#define ALHO_CSO_FLAG (1 << 1) +#define ALHO_CFO_FLAG (1 << 2) + +#define SHIM_SVCFG 0xF4 +#define SHIM_SVCFG_FORCE_L1_EXIT (0x1 << 1) + +/* host windows */ +#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0) +#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4) + +#define DMWBA_ENABLE (1 << 0) +#define DMWBA_READONLY (1 << 1) + +#ifndef ASSEMBLY + +static inline uint16_t shim_read16(uint16_t reg) +{ + return *((volatile uint16_t*)(SHIM_BASE + reg)); +} + +static inline void shim_write16(uint16_t reg, uint16_t val) +{ + *((volatile uint16_t*)(SHIM_BASE + reg)) = val; +} + +static inline uint32_t shim_read(uint32_t reg) +{ + return *((volatile uint32_t*)(SHIM_BASE + reg)); +} + +static inline void shim_write(uint32_t reg, uint32_t val) +{ + *((volatile uint32_t*)(SHIM_BASE + reg)) = val; +} + +static inline uint64_t shim_read64(uint32_t reg) +{ + return *((volatile uint64_t*)(SHIM_BASE + reg)); +} + +static inline void shim_write64(uint32_t reg, uint64_t val) +{ + *((volatile uint64_t*)(SHIM_BASE + reg)) = val; +} + +// TODO: this should be BUILD_MAILBOX +#if !defined CONFIG_SUECREEK +static inline uint32_t sw_reg_read(uint32_t reg) +{ + return *((volatile uint32_t*)((SRAM_SW_REG_BASE - + SRAM_ALIAS_OFFSET) + reg)); +} + +static inline void sw_reg_write(uint32_t reg, uint32_t val) +{ + *((volatile uint32_t*)((SRAM_SW_REG_BASE - + SRAM_ALIAS_OFFSET) + reg)) = val; +} +#endif + +static inline uint32_t mn_reg_read(uint32_t reg) +{ + return *((volatile uint32_t*)(MN_BASE + reg)); +} + +static inline void mn_reg_write(uint32_t reg, uint32_t val) +{ + *((volatile uint32_t*)(MN_BASE + reg)) = val; +} + +static inline uint32_t irq_read(uint32_t reg) +{ + return *((volatile uint32_t*)(IRQ_BASE + reg)); +} + +static inline void irq_write(uint32_t reg, uint32_t val) +{ + *((volatile uint32_t*)(IRQ_BASE + reg)) = val; +} + +static inline uint32_t ipc_read(uint32_t reg) +{ + return *((volatile uint32_t*)(IPC_HOST_BASE + reg)); +} + +static inline void ipc_write(uint32_t reg, uint32_t val) +{ + *((volatile uint32_t*)(IPC_HOST_BASE + reg)) = val; +} + +static inline uint32_t idc_read(uint32_t reg, uint32_t core_id) +{ + return *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)); +} + +static inline void idc_write(uint32_t reg, uint32_t core_id, uint32_t val) +{ + *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)) = val; +} +#endif + +#endif diff --git a/src/platform/suecreek/include/platform/timer.h b/src/platform/suecreek/include/platform/timer.h new file mode 100644 index 000000000000..7586c4f52ab1 --- /dev/null +++ b/src/platform/suecreek/include/platform/timer.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifndef __PLATFORM_TIMER_H__ +#define __PLATFORM_TIMER_H__ + +#include +#include +#include + +#define TIMER_COUNT 5 + +/* timer numbers must use associated IRQ number */ +#define TIMER0 IRQ_NUM_TIMER1 +#define TIMER1 IRQ_NUM_TIMER2 +#define TIMER2 IRQ_NUM_TIMER3 +#define TIMER3 IRQ_EXT_TSTAMP0_LVL2(0) +#define TIMER4 IRQ_EXT_TSTAMP1_LVL2(0) + +#endif diff --git a/src/platform/suecreek/suecreek.x.in b/src/platform/suecreek/suecreek.x.in new file mode 100644 index 000000000000..cab4f55d21ce --- /dev/null +++ b/src/platform/suecreek/suecreek.x.in @@ -0,0 +1,558 @@ +/* + * Linker Script for Suecreek. + * + * This script is run through the GNU C preprocessor to align the memory + * offsets with headers. + * + * Use spaces for formatting as cpp ignore tab sizes. + */ + +#include +#include + +OUTPUT_ARCH(xtensa) + +MEMORY +{ + vector_reset_text : + org = XCHAL_RESET_VECTOR0_PADDR, + len = SOF_MEM_RESET_TEXT_SIZE + vector_reset_lit : + org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE, + len = SOF_MEM_RESET_LIT_SIZE + vector_memory_lit : + org = XCHAL_MEMERROR_VECTOR_PADDR + SOF_MEM_ERROR_LIT_SIZE, + len = SOF_MEM_ERROR_LIT_SIZE + vector_memory_text : + org = XCHAL_MEMERROR_VECTOR_PADDR, + len = SOF_MEM_ERROR_TEXT_SIZE + vector_base_text : + org = SOF_MEM_VECBASE, + len = SOF_MEM_VECBASE_LIT_SIZE + vector_int2_lit : + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int2_text : + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL2_VECOFS, + len = SOF_MEM_VECT_TEXT_SIZE + vector_int3_lit : + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int3_text : + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL3_VECOFS, + len = SOF_MEM_VECT_TEXT_SIZE + vector_int4_lit : + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int4_text : + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL4_VECOFS, + len = SOF_MEM_VECT_TEXT_SIZE + vector_int5_lit : + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int5_text : + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL5_VECOFS, + len = SOF_MEM_VECT_TEXT_SIZE + vector_int6_lit : + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int6_text : + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL6_VECOFS, + len = SOF_MEM_VECT_TEXT_SIZE + vector_int7_lit : + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int7_text : + org = SOF_MEM_VECBASE + XCHAL_INTLEVEL7_VECOFS, + len = SOF_MEM_VECT_TEXT_SIZE + vector_kernel_lit : + org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_kernel_text : + org = SOF_MEM_VECBASE + XCHAL_KERNEL_VECOFS, + len = SOF_MEM_VECT_TEXT_SIZE + vector_user_lit : + org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_user_text : + org = SOF_MEM_VECBASE + XCHAL_USER_VECOFS, + len = SOF_MEM_VECT_TEXT_SIZE + vector_double_lit : + org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_double_text : + org = SOF_MEM_VECBASE + XCHAL_DOUBLEEXC_VECOFS, + len = SOF_MEM_VECT_TEXT_SIZE + sof_text_start : + org = SOF_TEXT_START, + len = SOF_TEXT_START_SIZE, + sof_text : + org = SOF_TEXT_BASE, + len = SOF_TEXT_SIZE, + sof_data : + org = SOF_TEXT_BASE + SOF_TEXT_SIZE, + len = SOF_DATA_SIZE + sof_bss_data : + org = SOF_TEXT_BASE + SOF_TEXT_SIZE + SOF_DATA_SIZE, + len = SOF_BSS_DATA_SIZE + system_heap : + org = HEAP_SYSTEM_0_BASE, + len = HEAP_SYSTEM_T_SIZE + runtime_heap : + org = HEAP_RUNTIME_BASE, + len = HEAP_RUNTIME_SIZE + buffer_heap : + org = HEAP_BUFFER_BASE, + len = HEAP_BUFFER_SIZE + sof_stack : + org = SOF_STACK_END, + len = SOF_STACK_BASE - SOF_STACK_END + buffer_hp_heap : + org = HEAP_HP_BUFFER_BASE, + len = HEAP_HP_BUFFER_SIZE + static_log_entries_seg (!ari) : + org = LOG_ENTRY_ELF_BASE, + len = LOG_ENTRY_ELF_SIZE +} + +PHDRS +{ + vector_reset_text_phdr PT_LOAD; + vector_reset_lit_phdr PT_LOAD; + vector_memory_lit_phdr PT_LOAD; + vector_memory_text_phdr PT_LOAD; + vector_base_text_phdr PT_LOAD; + vector_int2_lit_phdr PT_LOAD; + vector_int2_text_phdr PT_LOAD; + vector_int3_lit_phdr PT_LOAD; + vector_int3_text_phdr PT_LOAD; + vector_int4_lit_phdr PT_LOAD; + vector_int4_text_phdr PT_LOAD; + vector_int5_lit_phdr PT_LOAD; + vector_int5_text_phdr PT_LOAD; + vector_int6_lit_phdr PT_LOAD; + vector_int6_text_phdr PT_LOAD; + vector_int7_lit_phdr PT_LOAD; + vector_int7_text_phdr PT_LOAD; + vector_kernel_lit_phdr PT_LOAD; + vector_kernel_text_phdr PT_LOAD; + vector_user_lit_phdr PT_LOAD; + vector_user_text_phdr PT_LOAD; + vector_double_lit_phdr PT_LOAD; + vector_double_text_phdr PT_LOAD; + sof_text_start_phdr PT_LOAD; + sof_text_phdr PT_LOAD; + sof_data_phdr PT_LOAD; + sof_bss_data_phdr PT_LOAD; + system_heap_phdr PT_LOAD; + runtime_heap_phdr PT_LOAD; + buffer_heap_phdr PT_LOAD; + sof_stack_phdr PT_LOAD; + buffer_hp_heap_phdr PT_LOAD; + static_log_entries_phdr PT_NOTE; +} + +/* Default entry point: */ +ENTRY(_ResetVector) +_rom_store_table = 0; + +/* ABI0 does not use Window base */ +PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR); + +/* Various memory-map dependent cache attribute settings: */ +_memmap_cacheattr_wb_base = 0x44024000; +_memmap_cacheattr_wt_base = 0x11021000; +_memmap_cacheattr_bp_base = 0x22022000; +_memmap_cacheattr_unused_mask = 0x00F00FFF; +_memmap_cacheattr_wb_trapnull = 0x4422422F; +_memmap_cacheattr_wba_trapnull = 0x4422422F; +_memmap_cacheattr_wbna_trapnull = 0x25222222; +_memmap_cacheattr_wt_trapnull = 0x1122122F; +_memmap_cacheattr_bp_trapnull = 0x2222222F; +_memmap_cacheattr_wb_strict = 0x44F24FFF; +_memmap_cacheattr_wt_strict = 0x11F21FFF; +_memmap_cacheattr_bp_strict = 0x22F22FFF; +_memmap_cacheattr_wb_allvalid = 0x44224222; +_memmap_cacheattr_wt_allvalid = 0x11221222; +_memmap_cacheattr_bp_allvalid = 0x22222222; +_memmap_cacheattr_sue_creek = 0xf2ff4242; +PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_sue_creek); + +SECTIONS +{ + .ResetVector.text : ALIGN(4) + { + _ResetVector_text_start = ABSOLUTE(.); + KEEP (*(.ResetVector.text)) + _ResetVector_text_end = ABSOLUTE(.); + } >vector_reset_text :vector_reset_text_phdr + + .ResetVector.literal : ALIGN(4) + { + _ResetVector_literal_start = ABSOLUTE(.); + *(.ResetVector.literal) + _ResetVector_literal_end = ABSOLUTE(.); + } >vector_reset_lit :vector_reset_lit_phdr + + .MemoryExceptionVector.literal : ALIGN(4) + { + _MemoryExceptionVector_literal_start = ABSOLUTE(.); + KEEP (*(.MemoryExceptionVector.literal)) + _MemoryExceptionVector_literal_end = ABSOLUTE(.); + } >vector_memory_lit :vector_memory_lit_phdr + + .MemoryExceptionVector.text : ALIGN(4) + { + _MemoryExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.MemoryExceptionVector.text)) + _MemoryExceptionVector_text_end = ABSOLUTE(.); + } >vector_memory_text :vector_memory_text_phdr + + .WindowVectors.text : ALIGN(4) + { + _WindowVectors_text_start = ABSOLUTE(.); + KEEP (*(.WindowVectors.text)) + _WindowVectors_text_end = ABSOLUTE(.); + } >vector_base_text :vector_base_text_phdr + + .Level2InterruptVector.literal : ALIGN(4) + { + _Level2InterruptVector_literal_start = ABSOLUTE(.); + *(.Level2InterruptVector.literal) + _Level2InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int2_lit :vector_int2_lit_phdr + + .Level2InterruptVector.text : ALIGN(4) + { + _Level2InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level2InterruptVector.text)) + _Level2InterruptVector_text_end = ABSOLUTE(.); + } >vector_int2_text :vector_int2_text_phdr + + .Level3InterruptVector.literal : ALIGN(4) + { + _Level3InterruptVector_literal_start = ABSOLUTE(.); + *(.Level3InterruptVector.literal) + _Level3InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int3_lit :vector_int3_lit_phdr + + .Level3InterruptVector.text : ALIGN(4) + { + _Level3InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level3InterruptVector.text)) + _Level3InterruptVector_text_end = ABSOLUTE(.); + } >vector_int3_text :vector_int3_text_phdr + + .Level4InterruptVector.literal : ALIGN(4) + { + _Level4InterruptVector_literal_start = ABSOLUTE(.); + *(.Level4InterruptVector.literal) + _Level4InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int4_lit :vector_int4_lit_phdr + + .Level4InterruptVector.text : ALIGN(4) + { + _Level4InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level4InterruptVector.text)) + _Level4InterruptVector_text_end = ABSOLUTE(.); + } >vector_int4_text :vector_int4_text_phdr + + .Level5InterruptVector.literal : ALIGN(4) + { + _Level5InterruptVector_literal_start = ABSOLUTE(.); + *(.Level5InterruptVector.literal) + _Level5InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int5_lit :vector_int5_lit_phdr + + .Level5InterruptVector.text : ALIGN(4) + { + _Level5InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level5InterruptVector.text)) + _Level5InterruptVector_text_end = ABSOLUTE(.); + } >vector_int5_text :vector_int5_text_phdr + + .DebugExceptionVector.literal : ALIGN(4) + { + _DebugExceptionVector_literal_start = ABSOLUTE(.); + *(.DebugExceptionVector.literal) + _DebugExceptionVector_literal_end = ABSOLUTE(.); + } >vector_int6_lit :vector_int6_lit_phdr + + .DebugExceptionVector.text : ALIGN(4) + { + _DebugExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DebugExceptionVector.text)) + _DebugExceptionVector_text_end = ABSOLUTE(.); + } >vector_int6_text :vector_int6_text_phdr + + .NMIExceptionVector.literal : ALIGN(4) + { + _NMIExceptionVector_literal_start = ABSOLUTE(.); + *(.NMIExceptionVector.literal) + _NMIExceptionVector_literal_end = ABSOLUTE(.); + } >vector_int7_lit :vector_int7_lit_phdr + + .NMIExceptionVector.text : ALIGN(4) + { + _NMIExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.NMIExceptionVector.text)) + _NMIExceptionVector_text_end = ABSOLUTE(.); + } >vector_int7_text :vector_int7_text_phdr + + .KernelExceptionVector.literal : ALIGN(4) + { + _KernelExceptionVector_literal_start = ABSOLUTE(.); + *(.KernelExceptionVector.literal) + _KernelExceptionVector_literal_end = ABSOLUTE(.); + } >vector_kernel_lit :vector_kernel_lit_phdr + + .KernelExceptionVector.text : ALIGN(4) + { + _KernelExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.KernelExceptionVector.text)) + _KernelExceptionVector_text_end = ABSOLUTE(.); + } >vector_kernel_text :vector_kernel_text_phdr + + .UserExceptionVector.literal : ALIGN(4) + { + _UserExceptionVector_literal_start = ABSOLUTE(.); + *(.UserExceptionVector.literal) + _UserExceptionVector_literal_end = ABSOLUTE(.); + } >vector_user_lit :vector_user_lit_phdr + + .UserExceptionVector.text : ALIGN(4) + { + _UserExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.UserExceptionVector.text)) + _UserExceptionVector_text_end = ABSOLUTE(.); + } >vector_user_text :vector_user_text_phdr + + .DoubleExceptionVector.literal : ALIGN(4) + { + _DoubleExceptionVector_literal_start = ABSOLUTE(.); + *(.DoubleExceptionVector.literal) + _DoubleExceptionVector_literal_end = ABSOLUTE(.); + } >vector_double_lit :vector_double_lit_phdr + + .DoubleExceptionVector.text : ALIGN(4) + { + _DoubleExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DoubleExceptionVector.text)) + _DoubleExceptionVector_text_end = ABSOLUTE(.); + } >vector_double_text :vector_double_text_phdr + + .ResetHandler.text : ALIGN(4) + { + _ResetHandler_text_start = ABSOLUTE(.); + KEEP (*(.ResetHandler.text)) + _ResetHandler_text_end = ABSOLUTE(.); + } >sof_text_start :sof_text_start_phdr + + .text : ALIGN(4) + { + _stext = .; + _text_start = ABSOLUTE(.); + KEEP (*(.MainEntry.text)) + *(.entry.text) + *(.init.literal) + KEEP(*(.init)) + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.fini.literal) + KEEP(*(.fini)) + *(.gnu.version) + KEEP (*(.ResetHandler.text)) + _text_end = ABSOLUTE(.); + _etext = .; + } >sof_text :sof_text_phdr + + .rodata : ALIGN(4) + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); + KEEP (*(.xt_except_table)) + KEEP (*(.gcc_except_table)) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + KEEP (*(.eh_frame)) + /* C++ constructor and destructor tables, properly ordered: */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); /* this table MUST be 4-byte aligned */ + _bss_table_start = ABSOLUTE(.); + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + } >sof_data :sof_data_phdr + + .data : ALIGN(4) + { + _data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + KEEP(*(.gnu.linkonce.d.*personality*)) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + KEEP(*(.jcr)) + _data_end = ABSOLUTE(.); + } >sof_data :sof_data_phdr + + .lit4 : ALIGN(4) + { + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + } >sof_data :sof_data_phdr + + .bss (NOLOAD) : ALIGN(8) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } >sof_bss_data :sof_bss_data_phdr + + /* stack */ + _end = SOF_STACK_END; + PROVIDE(end = SOF_STACK_END); + _stack_sentry = SOF_STACK_END; + __stack = SOF_STACK_BASE; + + /* System Heap */ + _system_heap = HEAP_SYSTEM_0_BASE; + + + /* module heap */ + _module_heap = HEAP_RUNTIME_BASE; + + /* buffer heap */ + _buffer_heap = HEAP_BUFFER_BASE; + _buffer_heap_end = _stack_sentry; + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } + + .system_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _system_heap_start = ABSOLUTE(.); + . = . + HEAP_SYSTEM_T_SIZE; + _system_heap_end = ABSOLUTE(.); + } >system_heap :system_heap_phdr + + .runtime_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _runtime_heap_start = ABSOLUTE(.); + . = . + HEAP_RUNTIME_SIZE; + _runtime_heap_end = ABSOLUTE(.); + } >runtime_heap :runtime_heap_phdr + + .buffer_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _buffer_heap_start = ABSOLUTE(.); + . = . + HEAP_BUFFER_SIZE; + _buffer_heap_end = ABSOLUTE(.); + } >buffer_heap :buffer_heap_phdr + + .sof_stack (NOLOAD) : ALIGN(8) + { + . = ALIGN (4096); + _sof_stack_start = ABSOLUTE(.); + . = . + SOF_STACK_SIZE; + _sof_stack_end = ABSOLUTE(.); + } >sof_stack :sof_stack_phdr + + .static_log_entries (COPY) : ALIGN(1024) + { + *(*.static_log*) + } > static_log_entries_seg :static_log_entries_phdr +} From c03f120d642be53645befc6449a9fd61b4b92f3a Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 16:16:02 +0100 Subject: [PATCH 09/14] sue: Add initial support for suecreek IPC. IPC will be via SPI on Suecreek. Signed-off-by: Liam Girdwood --- src/ipc/Makefile.am | 8 +++ src/ipc/sue-ipc.c | 171 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 179 insertions(+) create mode 100644 src/ipc/sue-ipc.c diff --git a/src/ipc/Makefile.am b/src/ipc/Makefile.am index 7d74b46f3fe4..b671484072de 100644 --- a/src/ipc/Makefile.am +++ b/src/ipc/Makefile.am @@ -68,6 +68,14 @@ libsof_ipc_a_SOURCES = \ dma-copy.c endif +if BUILD_SUECREEK +libsof_ipc_a_SOURCES = \ + ipc.c \ + handler.c \ + sue-ipc.c \ + dma-copy.c +endif + if BUILD_ICELAKE libsof_ipc_a_SOURCES = \ ipc.c \ diff --git a/src/ipc/sue-ipc.c b/src/ipc/sue-ipc.c new file mode 100644 index 000000000000..f9d7040950d7 --- /dev/null +++ b/src/ipc/sue-ipc.c @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2017, Intel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Intel Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Liam Girdwood + * Keyon Jie + Rander Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern struct ipc *_ipc; + +/* test code to check working IRQ */ +static void irq_handler(void *arg) +{ +} + +void ipc_platform_do_cmd(struct ipc *ipc) +{ + struct intel_ipc_data *iipc = ipc_get_drvdata(ipc); + struct sof_ipc_reply reply; + int32_t err; + + trace_ipc("Cmd"); + + /* perform command and return any error */ + err = ipc_cmd(); + if (err > 0) { + goto done; /* reply created and copied by cmd() */ + } else if (err < 0) { + /* send std error reply */ + reply.error = err; + } else if (err == 0) { + /* send std reply */ + reply.error = 0; + } + + /* send std error/ok reply */ + reply.hdr.cmd = SOF_IPC_GLB_REPLY; + reply.hdr.size = sizeof(reply); + mailbox_hostbox_write(0, &reply, sizeof(reply)); + +done: + ipc->host_pending = 0; + + // TODO: signal audio work to enter D3 in normal context + /* are we about to enter D3 ? */ + if (iipc->pm_prepare_D3) { + while (1) + wait_for_interrupt(0); + } + + tracev_ipc("CmD"); +} + +void ipc_platform_send_msg(struct ipc *ipc) +{ + struct ipc_msg *msg; + uint32_t flags; + + spin_lock_irq(&ipc->lock, flags); + + /* any messages to send ? */ + if (list_is_empty(&ipc->shared_ctx->msg_list)) { + ipc->shared_ctx->dsp_pending = 0; + goto out; + } + + /* now send the message */ + msg = list_first_item(&ipc->shared_ctx->msg_list, struct ipc_msg, + list); + mailbox_dspbox_write(0, msg->tx_data, msg->tx_size); + list_item_del(&msg->list); + ipc->shared_ctx->dsp_msg = msg; + tracev_ipc("Msg"); + + /* now interrupt host to tell it we have message sent */ + + list_item_append(&msg->list, &ipc->shared_ctx->empty_list); + +out: + spin_unlock_irq(&ipc->lock, flags); +} + +int platform_ipc_init(struct ipc *ipc) +{ + struct intel_ipc_data *iipc; + uint32_t dir, caps, dev; + + _ipc = ipc; + + /* init ipc data */ + iipc = rzalloc(RZONE_SYS, SOF_MEM_CAPS_RAM, + sizeof(struct intel_ipc_data)); + ipc_set_drvdata(_ipc, iipc); + + /* schedule */ + schedule_task_init(&_ipc->ipc_task, ipc_process_task, _ipc); + schedule_task_config(&_ipc->ipc_task, 0, 0); + +#ifdef CONFIG_HOST_PTABLE + /* allocate page table buffer */ + iipc->page_table = rballoc(RZONE_SYS, SOF_MEM_CAPS_RAM, + HOST_PAGE_SIZE); + if (iipc->page_table) + bzero(iipc->page_table, HOST_PAGE_SIZE); +#endif + + /* request HDA DMA with shared access privilege */ + caps = 0; + dir = DMA_DIR_HMEM_TO_LMEM; + dev = DMA_DEV_HOST; + iipc->dmac = dma_get(dir, caps, dev, DMA_ACCESS_SHARED); + + /* PM */ + iipc->pm_prepare_D3 = 0; + + /* configure interrupt */ + interrupt_register(PLATFORM_IPC_INTERRUPT, IRQ_AUTO_UNMASK, + irq_handler, NULL); + interrupt_enable(PLATFORM_IPC_INTERRUPT); + + /* enable IPC interrupts from host */ + + return 0; +} From 630e988a975025c3f36acc2da5b1266bbf5b2a8e Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 16:18:13 +0100 Subject: [PATCH 10/14] sue: scripts: Add sue creek support into buildall Signed-off-by: Liam Girdwood --- scripts/xtensa-build-all.sh | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/scripts/xtensa-build-all.sh b/scripts/xtensa-build-all.sh index 7732d4326ed9..1f0936a3e487 100755 --- a/scripts/xtensa-build-all.sh +++ b/scripts/xtensa-build-all.sh @@ -1,6 +1,6 @@ #!/bin/bash -SUPPORTED_PLATFORMS=(byt cht bdw hsw apl cnl icl) +SUPPORTED_PLATFORMS=(byt cht bdw hsw apl cnl sue icl) if [ "$#" -eq 0 ] then PLATFORMS=${SUPPORTED_PLATFORMS[@]} @@ -116,6 +116,14 @@ do HOST="xtensa-cnl-elf" XTENSA_TOOLS_VERSION="RF-2016.4-linux" fi + if [ $j == "sue" ] + then + PLATFORM="suecreek" + XTENSA_CORE="X6H3CNL_2016_4_linux" + ROOT="$pwd/../xtensa-root/xtensa-cnl-elf" + HOST="xtensa-cnl-elf" + XTENSA_TOOLS_VERSION="RF-2016.4-linux" + fi if [ $j == "icl" ] then PLATFORM="icelake" From 244d30769b410e08a3fcaaabcc202a1fd9bb4ce0 Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 20:55:49 +0100 Subject: [PATCH 11/14] sue: platform: Add platform init for Sue Creek Sue creek has no SRAM windows. Signed-off-by: Liam Girdwood --- src/platform/intel/cavs/platform.c | 41 +++++++--- .../suecreek/include/platform/mailbox.h | 79 +++++++------------ .../suecreek/include/platform/memory.h | 27 ++++++- 3 files changed, 86 insertions(+), 61 deletions(-) diff --git a/src/platform/intel/cavs/platform.c b/src/platform/intel/cavs/platform.c index 45009e8ae403..4155e7551efc 100644 --- a/src/platform/intel/cavs/platform.c +++ b/src/platform/intel/cavs/platform.c @@ -59,7 +59,7 @@ #if defined(CONFIG_APOLLOLAKE) #define SSP_COUNT PLATFORM_NUM_SSP #define SSP_CLOCK_FREQUENCY 19200000 -#elif defined(CONFIG_CANNONLAKE) +#elif defined(CONFIG_CANNONLAKE) || defined(CONFIG_SUECREEK) #define SSP_COUNT PLATFORM_SSP_COUNT #define SSP_CLOCK_FREQUENCY 24000000 #elif defined(CONFIG_ICELAKE) @@ -82,6 +82,7 @@ static const struct sof_ipc_fw_ready ready = { }, }; +#if !defined(CONFIG_SUECREEK) #define SRAM_WINDOW_HOST_OFFSET(x) (0x80000 + x * 0x20000) #define NUM_WINDOWS 7 @@ -146,6 +147,7 @@ static const struct sof_ipc_window sram_window = { }, }, }; +#endif struct work_queue_timesource platform_generic_queue[] = { { @@ -170,7 +172,8 @@ struct work_queue_timesource platform_generic_queue[] = { .timer_clear = platform_timer_clear, .timer_get = platform_timer_get, }, -#if defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) +#if defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) \ + || defined(CONFIG_SUECREEK) { .timer = { .id = TIMER3, /* external timer */ @@ -199,6 +202,15 @@ struct work_queue_timesource platform_generic_queue[] = { struct timer *platform_timer = &platform_generic_queue[PLATFORM_MASTER_CORE_ID].timer; +#if defined(CONFIG_SUECREEK) +int platform_boot_complete(uint32_t boot_message) +{ + mailbox_dspbox_write(0, &ready, sizeof(ready)); + return 0; +} + +#else + int platform_boot_complete(uint32_t boot_message) { mailbox_dspbox_write(0, &ready, sizeof(ready)); @@ -220,7 +232,9 @@ int platform_boot_complete(uint32_t boot_message) return 0; } +#endif +#if !defined(CONFIG_SUECREEK) static void platform_memory_windows_init(void) { /* window0, for fw status & outbox/uplink mbox */ @@ -253,8 +267,10 @@ static void platform_memory_windows_init(void) io_reg_write(DMWBA(3), HP_SRAM_WIN3_BASE | DMWBA_READONLY | DMWBA_ENABLE); } +#endif -#if defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) +#if defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) \ + || defined(CONFIG_SUECREEK) /* init HW */ static void platform_init_hw(void) { @@ -280,16 +296,19 @@ int platform_init(struct sof *sof) struct dai *dmic0; int i, ret; - #if defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) +#if defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) \ + || defined(CONFIG_SUECREEK) trace_point(TRACE_BOOT_PLATFORM_ENTRY); platform_init_hw(); - #endif +#endif platform_interrupt_init(); trace_point(TRACE_BOOT_PLATFORM_MBOX); - platform_memory_windows_init(); +#if !defined(CONFIG_SUECREEK) + platform_memory_windows_init(); +#endif trace_point(TRACE_BOOT_PLATFORM_SHIM); /* init work queues and clocks */ @@ -317,7 +336,7 @@ int platform_init(struct sof *sof) trace_point(TRACE_BOOT_PLATFORM_IPC); ipc_init(sof); - #if defined(CONFIG_APOLLOLAKE) +#if defined(CONFIG_APOLLOLAKE) /* disable PM for boot */ shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) | SHIM_CLKCTL_LPGPDMAFDCGB(0) | @@ -336,7 +355,10 @@ int platform_init(struct sof *sof) SHIM_CLKCTL_TCPLCG(0) | SHIM_CLKCTL_TCPLCG(1)); shim_write(SHIM_LPSCTL, shim_read(SHIM_LPSCTL)); - #elif defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) + +#elif defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) \ + || defined(CONFIG_SUECREEK) + /* prevent Core0 clock gating. */ shim_write(SHIM_CLKCTL, shim_read(SHIM_CLKCTL) | SHIM_CLKCTL_TCPLCG(0)); @@ -347,7 +369,7 @@ int platform_init(struct sof *sof) /* prevent DSP Common power gating */ shim_write16(SHIM_PWRCTL, SHIM_PWRCTL_TCPDSP0PG); - #endif +#endif /* init DMACs */ trace_point(TRACE_BOOT_PLATFORM_DMA); @@ -355,7 +377,6 @@ int platform_init(struct sof *sof) if (ret < 0) return -ENODEV; - /* init SSP ports */ trace_point(TRACE_BOOT_PLATFORM_SSP); for (i = 0; i < SSP_COUNT; i++) { diff --git a/src/platform/suecreek/include/platform/mailbox.h b/src/platform/suecreek/include/platform/mailbox.h index a493e2493ff3..b33a8fa3822b 100644 --- a/src/platform/suecreek/include/platform/mailbox.h +++ b/src/platform/suecreek/include/platform/mailbox.h @@ -35,61 +35,42 @@ #include -/* TODO: no SHM mailbox on SUE, must be sent via SPI */ -#if 0 -#define MAILBOX_HOST_OFFSET 0x144000 - -#define MAILBOX_OUTBOX_OFFSET 0x0 -#define MAILBOX_OUTBOX_SIZE 0x400 -#define MAILBOX_OUTBOX_BASE \ - (MAILBOX_BASE + MAILBOX_OUTBOX_OFFSET) - -#define MAILBOX_INBOX_OFFSET MAILBOX_OUTBOX_SIZE -#define MAILBOX_INBOX_SIZE 0x400 -#define MAILBOX_INBOX_BASE \ - (MAILBOX_BASE + MAILBOX_INBOX_OFFSET) - -#define MAILBOX_EXCEPTION_OFFSET \ - (MAILBOX_INBOX_SIZE + MAILBOX_OUTBOX_SIZE) -#define MAILBOX_EXCEPTION_SIZE 0x100 -#define MAILBOX_EXCEPTION_BASE \ - (MAILBOX_BASE + MAILBOX_EXCEPTION_OFFSET) - -#define MAILBOX_DEBUG_OFFSET \ - (MAILBOX_EXCEPTION_SIZE + MAILBOX_EXCEPTION_OFFSET) -#define MAILBOX_DEBUG_SIZE 0x100 -#define MAILBOX_DEBUG_BASE \ - (MAILBOX_BASE + MAILBOX_DEBUG_OFFSET) - -#define MAILBOX_STREAM_OFFSET \ - (MAILBOX_DEBUG_SIZE + MAILBOX_DEBUG_OFFSET) -#define MAILBOX_STREAM_SIZE 0x200 -#define MAILBOX_STREAM_BASE \ - (MAILBOX_BASE + MAILBOX_STREAM_OFFSET) - -#define MAILBOX_TRACE_OFFSET \ - (MAILBOX_STREAM_SIZE + MAILBOX_STREAM_OFFSET) -#define MAILBOX_TRACE_SIZE 0x380 -#define MAILBOX_TRACE_BASE \ - (MAILBOX_BASE + MAILBOX_TRACE_OFFSET) +/* + * The Window Region on Suecreek HPSRAM is organised like this :- + * +--------------------------------------------------------------------------+ + * | Offset | Region | Size | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_TRACE_BASE | Trace Buffer | SRAM_TRACE_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_DEBUG_BASE | Debug data | SRAM_DEBUG_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_INBOX_BASE | Inbox | SRAM_INBOX_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_OUTBOX_BASE | Outbox | SRAM_MAILBOX_SIZE | + * +---------------------+----------------+-----------------------------------+ + */ -#endif +#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE +#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE -// TODO need added to linker map +#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE +#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE -#define MAILBOX_DEBUG_SIZE 0 -#define MAILBOX_DEBUG_BASE 0 +#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE +#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE +#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE -#define MAILBOX_HOSTBOX_SIZE 0 -#define MAILBOX_HOSTBOX_BASE 0 +#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE +#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE +#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE) -#define MAILBOX_DSPBOX_SIZE 0 -#define MAILBOX_DSPBOX_BASE 0 +#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE +#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE -#define MAILBOX_TRACE_SIZE 0 -#define MAILBOX_TRACE_BASE 0 +#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE +#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE -#define MAILBOX_EXCEPTION_SIZE 0 -#define MAILBOX_EXCEPTION_BASE 0 +#define MAILBOX_SW_REG_SIZE 0 +#define MAILBOX_SW_REG_BASE 0 #endif diff --git a/src/platform/suecreek/include/platform/memory.h b/src/platform/suecreek/include/platform/memory.h index 6ba9908e80a3..baa299243b52 100644 --- a/src/platform/suecreek/include/platform/memory.h +++ b/src/platform/suecreek/include/platform/memory.h @@ -182,11 +182,34 @@ /* bss data */ #define SOF_BSS_DATA_SIZE 0x10900 -/* Heap configuration */ +/* Mailbox configuration */ +#define SRAM_OUTBOX_BASE (SOF_TEXT_BASE + SOF_TEXT_SIZE \ + + SOF_DATA_SIZE + SOF_BSS_DATA_SIZE) +#define SRAM_OUTBOX_SIZE 0x1000 + +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x1000 + +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_DEBUG_SIZE 0x800 + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x800 + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x1000 + +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#define SRAM_TRACE_SIZE 0x1000 + +#define SOF_MAILBOX_SIZE (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \ + + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \ + + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE) + /* Heap configuration */ #define HEAP_SYSTEM_0_BASE \ (SOF_TEXT_BASE + SOF_TEXT_SIZE +\ - SOF_DATA_SIZE + SOF_BSS_DATA_SIZE) + SOF_DATA_SIZE + SOF_BSS_DATA_SIZE + SOF_MAILBOX_SIZE) #define HEAP_SYSTEM_0_SIZE 0x8000 #define HEAP_SYSTEM_1_BASE (HEAP_SYSTEM_0_BASE + HEAP_SYSTEM_0_SIZE) From 36b85943a8c380ca135ac68c3b63694bda6254ef Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 21:06:25 +0100 Subject: [PATCH 12/14] sue: dma: Add Sue Creek DMAC platform data. Signed-off-by: Liam Girdwood --- src/platform/intel/cavs/dma.c | 58 +++++++++++++++++++++++++++++++++-- 1 file changed, 55 insertions(+), 3 deletions(-) diff --git a/src/platform/intel/cavs/dma.c b/src/platform/intel/cavs/dma.c index 0e6bfea53431..4a79ee1c59ed 100644 --- a/src/platform/intel/cavs/dma.c +++ b/src/platform/intel/cavs/dma.c @@ -40,20 +40,24 @@ #include #include -#define CAVS_PLATFORM_NUM_DMACS 6 - #if defined(CONFIG_APOLLOLAKE) #define DMAC0_CLASS 1 #define DMAC1_CLASS 2 #define DMAC_HOST_OUT_CHANNELS_COUNT 6 #define DMAC_LINK_IN_CHANNELS_COUNT 8 #define DMAC_LINK_OUT_CHANNELS_COUNT 8 +#define CAVS_PLATFORM_NUM_DMACS 6 #elif defined(CONFIG_CANNONLAKE) || defined(CONFIG_ICELAKE) #define DMAC0_CLASS 6 #define DMAC1_CLASS 7 #define DMAC_HOST_OUT_CHANNELS_COUNT 9 #define DMAC_LINK_IN_CHANNELS_COUNT 9 #define DMAC_LINK_OUT_CHANNELS_COUNT 7 +#define CAVS_PLATFORM_NUM_DMACS 6 +#elif defined(CONFIG_SUECREEK) +#define DMAC0_CLASS 6 +#define DMAC1_CLASS 7 +#define CAVS_PLATFORM_NUM_DMACS 3 #endif static struct dw_drv_plat_data dmac0 = { @@ -126,7 +130,54 @@ static struct dw_drv_plat_data dmac1 = { }, }; -static struct dma dma[CAVS_PLATFORM_NUM_DMACS] = { +#if defined(CONFIG_SUECREEK) +struct dma dma[CAVS_PLATFORM_NUM_DMACS] = { +{ /* LP GP DMAC 0 */ + .plat_data = { + .id = DMA_GP_LP_DMAC0, + .dir = DMA_DIR_MEM_TO_MEM | DMA_DIR_MEM_TO_DEV | + DMA_DIR_DEV_TO_MEM | DMA_DIR_DEV_TO_DEV, + .caps = DMA_CAP_GP_LP, + .devs = DMA_DEV_SSP | DMA_DEV_DMIC, + .base = LP_GP_DMA_BASE(0), + .channels = 8, + .irq = IRQ_EXT_LP_GPDMA0_LVL5(0, 0), + .drv_plat_data = &dmac0, + }, + .ops = &dw_dma_ops, +}, +{ /* LP GP DMAC 1 */ + .plat_data = { + .id = DMA_GP_LP_DMAC1, + .dir = DMA_DIR_MEM_TO_MEM | DMA_DIR_MEM_TO_DEV | + DMA_DIR_DEV_TO_MEM | DMA_DIR_DEV_TO_DEV, + .caps = DMA_CAP_GP_LP, + .devs = DMA_DEV_SSP | DMA_DEV_DMIC, + .base = LP_GP_DMA_BASE(1), + .channels = 8, + .irq = IRQ_EXT_LP_GPDMA1_LVL5(0, 0), + .drv_plat_data = &dmac1, + }, + .ops = &dw_dma_ops, +}, +{ /* LP GP DMAC 2 */ + .plat_data = { + .id = DMA_GP_LP_DMAC2, + .dir = DMA_DIR_MEM_TO_MEM | DMA_DIR_MEM_TO_DEV | + DMA_DIR_DEV_TO_MEM | DMA_DIR_DEV_TO_DEV, + .caps = DMA_CAP_GP_LP, + .devs = DMA_DEV_SSP | DMA_DEV_DMIC, + .base = LP_GP_DMA_BASE(1), + .channels = 8, + .irq = IRQ_EXT_LP_GPDMA1_LVL5(0, 0), + .drv_plat_data = &dmac1, + }, + .ops = &dw_dma_ops, +}, +}; + +#else +struct dma dma[CAVS_PLATFORM_NUM_DMACS] = { { /* Low Power GP DMAC 0 */ .plat_data = { .id = DMA_GP_LP_DMAC0, @@ -207,6 +258,7 @@ static struct dma dma[CAVS_PLATFORM_NUM_DMACS] = { }, .ops = &hda_link_dma_ops, },}; +#endif /* Initialize all platform DMAC's */ int dmac_init(void) From 41a61bcdc11f2d4c46588dd72dac87eeba46ba1a Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 21:32:13 +0100 Subject: [PATCH 13/14] sue: Add build support for Sue Creek platform Signed-off-by: Liam Girdwood --- configure.ac | 33 ++++++++++++++++++++++++---- src/arch/xtensa/smp/hal/Makefile.am | 9 ++++++++ src/arch/xtensa/smp/xtos/Makefile.am | 6 +++++ src/arch/xtensa/up/hal/Makefile.am | 10 +++++++++ 4 files changed, 54 insertions(+), 4 deletions(-) diff --git a/configure.ac b/configure.ac index 8788c385b81e..02c2579a5bad 100644 --- a/configure.ac +++ b/configure.ac @@ -296,6 +296,24 @@ case "$with_platform" in AC_DEFINE([CONFIG_IRQ_MAP], [1], [Configure IRQ maps]) AC_DEFINE([CONFIG_DMA_GW], [1], [Configure DMA Gateway]) ;; + suecreek*) + + PLATFORM_LDSCRIPT="suecreek.x" + AC_SUBST(PLATFORM_LDSCRIPT) + + PLATFORM="suecreek" + AC_SUBST(PLATFORM) + + FW_NAME="sue" + AC_SUBST(FW_NAME) + + XTENSA_CORE="hifi4_std" + AC_SUBST(XTENSA_CORE) + + AC_DEFINE([CONFIG_SUECREEK], [1], [Configure for Suecreek]) + AC_DEFINE([CONFIG_BOOT_LOADER], [1], [Configure Boot Loader]) + AC_DEFINE([CONFIG_IRQ_MAP], [1], [Configure IRQ maps]) + ;; icelake*) PLATFORM_LDSCRIPT="icelake.x" @@ -333,11 +351,12 @@ AM_CONDITIONAL(BUILD_HASWELL, test "$FW_NAME" = "hsw") AM_CONDITIONAL(BUILD_BROADWELL, test "$FW_NAME" = "bdw") AM_CONDITIONAL(BUILD_APOLLOLAKE, test "$FW_NAME" = "apl") AM_CONDITIONAL(BUILD_CANNONLAKE, test "$FW_NAME" = "cnl") +AM_CONDITIONAL(BUILD_SUECREEK, test "$FW_NAME" = "sue") AM_CONDITIONAL(BUILD_ICELAKE, test "$FW_NAME" = "icl") -AM_CONDITIONAL(BUILD_BOOTLOADER, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl" -o "$FW_NAME" = "icl") -AM_CONDITIONAL(BUILD_CAVS, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl" -o "$FW_NAME" = "icl") -AM_CONDITIONAL(BUILD_MODULE, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl" -o "$FW_NAME" = "icl") -AM_CONDITIONAL(BUILD_APL_SSP, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl" -o "$FW_NAME" = "icl") +AM_CONDITIONAL(BUILD_BOOTLOADER, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl" -o "$FW_NAME" = "icl" -o "$FW_NAME" = "sue") +AM_CONDITIONAL(BUILD_CAVS, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl" -o "$FW_NAME" = "icl" -o "$FW_NAME" = "sue") +AM_CONDITIONAL(BUILD_MODULE, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl" -o "$FW_NAME" = "icl" -o "$FW_NAME" = "sue") +AM_CONDITIONAL(BUILD_APL_SSP, test "$FW_NAME" = "apl" -o "$FW_NAME" = "cnl" -o "$FW_NAME" = "icl" -o "$FW_NAME" = "sue") # DSP core support (Optional) AC_ARG_WITH([dsp-core], @@ -533,6 +552,12 @@ AC_CONFIG_FILES([ src/platform/cannonlake/include/arch/xtensa/Makefile src/platform/cannonlake/include/arch/xtensa/config/Makefile src/platform/cannonlake/include/platform/Makefile + src/platform/suecreek/Makefile + src/platform/suecreek/include/Makefile + src/platform/suecreek/include/arch/Makefile + src/platform/suecreek/include/arch/xtensa/Makefile + src/platform/suecreek/include/arch/xtensa/config/Makefile + src/platform/suecreek/include/platform/Makefile src/platform/icelake/Makefile src/platform/icelake/include/Makefile src/platform/icelake/include/arch/Makefile diff --git a/src/arch/xtensa/smp/hal/Makefile.am b/src/arch/xtensa/smp/hal/Makefile.am index 8d4219e3bd0a..e95d8da60222 100644 --- a/src/arch/xtensa/smp/hal/Makefile.am +++ b/src/arch/xtensa/smp/hal/Makefile.am @@ -204,6 +204,15 @@ PLATFORM_DEFS = \ $(CACHE_DEFS) endif +if BUILD_SUECREEK +PLATFORM_DEFS = \ + $(STATE_DEFS_CNL) \ + $(DISASS_DEFS) \ + $(MISC_DEFS) \ + $(INTERRUPTS_DEFS) \ + $(CACHE_DEFS) +endif + noinst_LIBRARIES = libhal.a libhal_a_SOURCES = \ diff --git a/src/arch/xtensa/smp/xtos/Makefile.am b/src/arch/xtensa/smp/xtos/Makefile.am index b7557ef1c27a..25ead3a45a6f 100644 --- a/src/arch/xtensa/smp/xtos/Makefile.am +++ b/src/arch/xtensa/smp/xtos/Makefile.am @@ -58,6 +58,12 @@ noinst_LIBRARIES += libxlevel6.a VECTOR_DEFS += -D__SPLIT__level6 endif +if BUILD_SUECREEK +PLATFORM_DEFS = $(VECTOR_DEFS) +noinst_LIBRARIES += libxlevel6.a +VECTOR_DEFS += -D__SPLIT__level6 +endif + LEVEL_SRC = \ int-handler.S \ int-vector.S \ diff --git a/src/arch/xtensa/up/hal/Makefile.am b/src/arch/xtensa/up/hal/Makefile.am index 82f942422452..364073d6f847 100644 --- a/src/arch/xtensa/up/hal/Makefile.am +++ b/src/arch/xtensa/up/hal/Makefile.am @@ -204,6 +204,16 @@ PLATFORM_DEFS = \ $(CACHE_DEFS) endif +if BUILD_SUECREEK +PLATFORM_DEFS = \ + $(STATE_DEFS_CNL) \ + $(DISASS_DEFS) \ + $(MISC_DEFS) \ + $(INTERRUPTS_DEFS) \ + $(CACHE_DEFS) +endif + + noinst_LIBRARIES = libhal.a libhal_a_SOURCES = \ From eded228beb209cc9513ccc89050111ae478c8494 Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Fri, 28 Sep 2018 21:32:30 +0100 Subject: [PATCH 14/14] gitignore: ignore shared object .so files Signed-off-by: Liam Girdwood --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 1620e3433853..b2891b4d6deb 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,6 @@ *.o *.Po +*.so* *~ *.a *.la