From cbf5199d74656a7578bfb170e0696345a2627ed2 Mon Sep 17 00:00:00 2001 From: Michal Bukowski Date: Thu, 9 Feb 2023 12:15:02 +0100 Subject: [PATCH] cavs: memory bank powerup flow adjustment Memory banks enablement flow is adjusted to recommended approach. Power status should be read twice to ensure ebb readiness Signed-off-by: Michal Bukowski --- .../intel/cavs/include/cavs/lib/pm_memory.h | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/src/platform/intel/cavs/include/cavs/lib/pm_memory.h b/src/platform/intel/cavs/include/cavs/lib/pm_memory.h index 8223e1df33bd..74196c431f99 100644 --- a/src/platform/intel/cavs/include/cavs/lib/pm_memory.h +++ b/src/platform/intel/cavs/include/cavs/lib/pm_memory.h @@ -72,17 +72,22 @@ static inline void cavs_pm_memory_hp_sram_mask_set(uint32_t mask, int segment, { uint32_t expected = enabled ? 0 : mask; uint32_t delay = 0; + uint32_t i; io_reg_update_bits(SHIM_HSPGCTL(segment), mask, enabled ? 0 : mask); io_reg_update_bits(SHIM_HSRMCTL(segment), mask, enabled ? 0 : mask); - idelay(MEMORY_POWER_CHANGE_DELAY); - - while ((io_reg_read(SHIM_HSPGISTS(segment)) & mask) != expected) { + /* Double check of PG status needed to confirm EBB readiness */ + for (i = 0; i < 2; i++) { idelay(MEMORY_POWER_CHANGE_DELAY); - delay += MEMORY_POWER_CHANGE_DELAY; - if (delay >= MEMORY_POWER_CHANGE_TIMEOUT) - platform_panic(SOF_IPC_PANIC_MEM); + + while ((io_reg_read(SHIM_HSPGISTS(segment)) & mask) != expected) { + idelay(MEMORY_POWER_CHANGE_DELAY); + delay += MEMORY_POWER_CHANGE_DELAY; + if (delay >= MEMORY_POWER_CHANGE_TIMEOUT) + platform_panic(SOF_IPC_PANIC_MEM); + } + delay = 0; } }