diff --git a/CODEOWNERS b/CODEOWNERS index ae2639e4e9d4..da18df317d1b 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -40,7 +40,6 @@ src/audio/codec_adapter/* @cujomalainey @abonislawski @dbaluta src/audio/google/* @thesofproject/google # platforms -src/platform/haswell/* @randerwang src/platform/suecreek/* @lyakh src/arch/xtensa/debug/gdb/* @abonislawski src/platform/imx8/** @dbaluta @@ -50,7 +49,6 @@ src/platform/mt8195/** @yaochunhung @kuanhsuncheng # drivers src/drivers/intel/dmic.c @singalsu src/drivers/intel/cavs/sue-iomux.c @lyakh -src/drivers/intel/haswell/* @randerwang src/drivers/imx/** @dbaluta src/drivers/dw/* @lyakh src/drivers/amd/* @bhiregoudar @sunilkumardommati diff --git a/scripts/docker_build/sof_builder/Dockerfile b/scripts/docker_build/sof_builder/Dockerfile index 022b3a874335..07efb57be9b3 100644 --- a/scripts/docker_build/sof_builder/Dockerfile +++ b/scripts/docker_build/sof_builder/Dockerfile @@ -88,7 +88,7 @@ RUN cd "$HOME" && \ git clone $CLONE_DEFAULTS --branch sof-gcc10x $CT_NG_REPO && \ cd crosstool-ng && \ ./bootstrap && ./configure --prefix=`pwd` && make && make install && \ - for arch in hsw apl cnl imx imx8m imx8ulp rn rmb mt8186 mt8195; do \ + for arch in apl cnl imx imx8m imx8ulp rn rmb mt8186 mt8195; do \ echo "$arch: ct-ng build start..." && \ cp config-${arch}-gcc10.2-gdb9 .config && \ # replace the build dist to save space @@ -99,7 +99,6 @@ RUN cd "$HOME" && \ done && \ echo "Stage2: xtensa-overlay, crosstool-ng are done!" -ENV PATH="/home/sof/work/xtensa-hsw-elf/bin:${PATH}" ENV PATH="/home/sof/work/xtensa-apl-elf/bin:${PATH}" ENV PATH="/home/sof/work/xtensa-cnl-elf/bin:${PATH}" ENV PATH="/home/sof/work/xtensa-rn-elf/bin:${PATH}" @@ -114,7 +113,7 @@ ARG NEWLIB_REPO=https://github.com/jcmvbkbc/newlib-xtensa.git RUN cd "$HOME" && \ git clone $CLONE_DEFAULTS --branch xtensa $NEWLIB_REPO && \ cd newlib-xtensa && \ - for arch in hsw apl cnl imx imx8m imx8ulp rn rmb mt8186 mt8195; do \ + for arch in apl cnl imx imx8m imx8ulp rn rmb mt8186 mt8195; do \ ./configure --target=xtensa-${arch}-elf \ --prefix=/home/sof/work/xtensa-root && \ make && make install && \ diff --git a/scripts/qemu-check.sh b/scripts/qemu-check.sh index 461f17567f5c..0775e502dc14 100755 --- a/scripts/qemu-check.sh +++ b/scripts/qemu-check.sh @@ -3,7 +3,7 @@ # Copyright(c) 2018 Intel Corporation. All rights reserved. set -e -SUPPORTED_PLATFORMS=(bdw hsw apl icl skl kbl cnl imx8 imx8x imx8m) +SUPPORTED_PLATFORMS=(apl icl skl kbl cnl imx8 imx8x imx8m) SOF_DIR=$(cd "$(dirname "$0")" && cd .. && pwd) @@ -81,23 +81,6 @@ do has_rom=false case "$platform" in - bdw) - READY_IPC="00 3c 01 80" - OUTBOX_OFFSET="9e000" - SHM_IPC_REG=qemu-bridge-shim-io - SHM_MBOX=qemu-bridge-dram-mem - ;; - hsw) - # This READY_IPC value comes from: - # shim_write(SHIM_IPCD, outbox | SHIM_IPCD_BUSY); - # outbox=MAILBOX_HOST_OFFSET >> 3; - # MAILBOX_HOST_OFFSET>>3 = 0xFC00 - # IPC_DIPCIDR_BUSY = BIT(31) - READY_IPC="00 fc 00 80" - OUTBOX_OFFSET="7e000" - SHM_IPC_REG=qemu-bridge-shim-io - SHM_MBOX=qemu-bridge-dram-mem # some DMA traces visible here - ;; apl) # This READY_IPC value comes from: # ipc_write(IPC_DIPCIDR, IPC_DIPCIDR_BUSY | header); diff --git a/scripts/xtensa-build-all.sh b/scripts/xtensa-build-all.sh index a8832b96c6af..e84f46540004 100755 --- a/scripts/xtensa-build-all.sh +++ b/scripts/xtensa-build-all.sh @@ -24,7 +24,7 @@ SUPPORTED_PLATFORMS+=( mt8188 ) # Not actually "supported" in the main branch anymore (go to stable-v2.3 # instead) but kept here for historical reasons and experimentation # convenience. -SUPPORTED_PLATFORMS+=( hsw bdw apl skl kbl cnl sue icl jsl ) +SUPPORTED_PLATFORMS+=( apl skl kbl cnl sue icl jsl ) BUILD_ROM=no BUILD_DEBUG=no @@ -204,18 +204,6 @@ do PLATFORM_PRIVATE_KEY='' case $platform in - bdw) - PLATFORM="broadwell" - XTENSA_CORE="LX4_langwell_audio_17_8" - HOST="xtensa-hsw-elf" - XTENSA_TOOLS_VERSION="RG-2017.8-linux" - ;; - hsw) - PLATFORM="haswell" - XTENSA_CORE="LX4_langwell_audio_17_8" - HOST="xtensa-hsw-elf" - XTENSA_TOOLS_VERSION="RG-2017.8-linux" - ;; apl) PLATFORM="apollolake" XTENSA_CORE="X4H3I16w2D48w3a_2017_8" diff --git a/src/arch/xtensa/CMakeLists.txt b/src/arch/xtensa/CMakeLists.txt index 55f5e84eb052..1a0e0ab7a5e6 100644 --- a/src/arch/xtensa/CMakeLists.txt +++ b/src/arch/xtensa/CMakeLists.txt @@ -2,11 +2,7 @@ # platform-specific values -if(CONFIG_HASWELL) - set(platform_folder haswell) -elseif(CONFIG_BROADWELL) - set(platform_folder haswell) -elseif(CONFIG_APOLLOLAKE) +if(CONFIG_APOLLOLAKE) set(platform_folder apollolake) elseif(CONFIG_CANNONLAKE) set(platform_folder cannonlake) @@ -545,7 +541,7 @@ add_custom_target( # Keep lists below in sync with rimage/config/*.toml # .ri not signed: nothing variable in it to erase. -set(UNSIGNED_RI hsw bdw sue) +set(UNSIGNED_RI sue) # NXP list(APPEND UNSIGNED_RI imx8 imx8x imx8m imx8ulp) # AMD diff --git a/src/arch/xtensa/configs/broadwell_defconfig b/src/arch/xtensa/configs/broadwell_defconfig deleted file mode 100644 index 839688c778ed..000000000000 --- a/src/arch/xtensa/configs/broadwell_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_BROADWELL=y -CONFIG_COMP_ASRC=n -CONFIG_HAVE_AGENT=n -CONFIG_COMP_SRC_TINY=y -CONFIG_COMP_LEGACY_INTERFACE=y -CONFIG_COMP_MFCC=n diff --git a/src/arch/xtensa/configs/haswell_defconfig b/src/arch/xtensa/configs/haswell_defconfig deleted file mode 100644 index c018fce4a52d..000000000000 --- a/src/arch/xtensa/configs/haswell_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_HASWELL=y -CONFIG_COMP_ASRC=n -CONFIG_HAVE_AGENT=n -CONFIG_COMP_SRC_TINY=y -CONFIG_COMP_MFCC=n diff --git a/src/drivers/dw/dma.c b/src/drivers/dw/dma.c index f978d9d23ba8..5e3afb3ca7f0 100644 --- a/src/drivers/dw/dma.c +++ b/src/drivers/dw/dma.c @@ -477,34 +477,6 @@ static int dw_dma_status(struct dma_chan_data *channel, return 0; } -/* mask address for dma to identify memory space. - * It is requested by HSW, BDW. For other - * platforms, the mask is zero. - */ -static void dw_dma_mask_address(struct dma_sg_elem *sg_elem, - struct dw_lli *lli_desc, uint32_t direction) -{ - lli_desc->sar = sg_elem->src; - lli_desc->dar = sg_elem->dest; - - switch (direction) { - case DMA_DIR_LMEM_TO_HMEM: - case DMA_DIR_MEM_TO_DEV: - lli_desc->sar |= PLATFORM_DW_DMA_HOST_MASK; - break; - case DMA_DIR_HMEM_TO_LMEM: - case DMA_DIR_DEV_TO_MEM: - lli_desc->dar |= PLATFORM_DW_DMA_HOST_MASK; - break; - case DMA_DIR_MEM_TO_MEM: - lli_desc->sar |= PLATFORM_DW_DMA_HOST_MASK; - lli_desc->dar |= PLATFORM_DW_DMA_HOST_MASK; - break; - default: - break; - } -} - /* set the DMA channel configuration, source/target address, buffer sizes */ static int dw_dma_set_config(struct dma_chan_data *channel, struct dma_sg_config *config) @@ -737,8 +709,6 @@ static int dw_dma_set_config(struct dma_chan_data *channel, goto out; } - dw_dma_mask_address(sg_elem, lli_desc, config->direction); - if (sg_elem->size > DW_CTLH_BLOCK_TS_MASK) { tr_err(&dwdma_tr, "dw_dma_set_config(): dma %d channel %d block size too big %d", channel->dma->plat_data.id, diff --git a/src/drivers/intel/CMakeLists.txt b/src/drivers/intel/CMakeLists.txt index 3ffe0694b8e0..ca84ad500a82 100644 --- a/src/drivers/intel/CMakeLists.txt +++ b/src/drivers/intel/CMakeLists.txt @@ -1,8 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause -if(CONFIG_HASWELL OR CONFIG_BROADWELL) - add_subdirectory(haswell) -elseif(CONFIG_CAVS) +if(CONFIG_CAVS) add_subdirectory(cavs) endif() diff --git a/src/drivers/intel/haswell/CMakeLists.txt b/src/drivers/intel/haswell/CMakeLists.txt deleted file mode 100644 index 2582290b7786..000000000000 --- a/src/drivers/intel/haswell/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -add_local_sources(sof - interrupt.c - ssp.c - ipc.c - timer.c -) diff --git a/src/drivers/intel/haswell/interrupt.c b/src/drivers/intel/haswell/interrupt.c deleted file mode 100644 index fb32a65e670d..000000000000 --- a/src/drivers/intel/haswell/interrupt.c +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2018 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood -// Keyon Jie -// Janusz Jankowski - -#include -#include - -#include - -void platform_interrupt_init(void) {} - -void platform_interrupt_set(uint32_t irq) -{ - arch_interrupt_set(irq); -} - -/* clear mask in PISR, bits are W1C in docs but some bits need preserved ?? */ -void platform_interrupt_clear(uint32_t irq, uint32_t mask) -{ - switch (irq) { -#if CONFIG_XT_INTERRUPT_LEVEL_1 - case IRQ_NUM_EXT_SSP0: - case IRQ_NUM_EXT_SSP1: - case IRQ_NUM_EXT_IA: - case IRQ_NUM_SOFTWARE1: -#endif -#if CONFIG_XT_INTERRUPT_LEVEL_2 - case IRQ_NUM_EXT_DMAC0: -#endif -#if CONFIG_XT_INTERRUPT_LEVEL_3 - case IRQ_NUM_EXT_DMAC1: - case IRQ_NUM_SOFTWARE2: -#endif -#if CONFIG_XT_INTERRUPT_LEVEL_1 || CONFIG_XT_INTERRUPT_LEVEL_2 || \ - CONFIG_XT_INTERRUPT_LEVEL_3 - arch_interrupt_clear(irq); - break; -#endif - default: - break; - } -} - -/* TODO: expand this to 64 bit - should we just return mask of IRQ numbers */ -uint32_t platform_interrupt_get_enabled(void) -{ - return shim_read(SHIM_IMRD); -} - -void interrupt_mask(uint32_t irq, unsigned int cpu) -{ - switch (irq) { -#if CONFIG_XT_INTERRUPT_LEVEL_1 - case IRQ_NUM_EXT_SSP0: - shim_write(SHIM_IMRD, SHIM_IMRD_SSP0); - break; - case IRQ_NUM_EXT_SSP1: - shim_write(SHIM_IMRD, SHIM_IMRD_SSP1); - break; -#endif -#if CONFIG_XT_INTERRUPT_LEVEL_2 - case IRQ_NUM_EXT_DMAC0: - shim_write(SHIM_IMRD, SHIM_IMRD_DMAC0); - break; -#endif -#if CONFIG_XT_INTERRUPT_LEVEL_3 - case IRQ_NUM_EXT_DMAC1: - shim_write(SHIM_IMRD, SHIM_IMRD_DMAC1); - break; -#endif - default: - break; - } -} - -void interrupt_unmask(uint32_t irq, unsigned int cpu) -{ - switch (irq) { -#if CONFIG_XT_INTERRUPT_LEVEL_1 - case IRQ_NUM_EXT_SSP0: - shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_SSP0); - break; - case IRQ_NUM_EXT_SSP1: - shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_SSP1); - break; -#endif -#if CONFIG_XT_INTERRUPT_LEVEL_2 - case IRQ_NUM_EXT_DMAC0: - shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_DMAC0); - break; -#endif -#if CONFIG_XT_INTERRUPT_LEVEL_3 - case IRQ_NUM_EXT_DMAC1: - shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_DMAC1); - break; -#endif - default: - break; - } -} diff --git a/src/drivers/intel/haswell/ipc.c b/src/drivers/intel/haswell/ipc.c deleted file mode 100644 index b66986925b60..000000000000 --- a/src/drivers/intel/haswell/ipc.c +++ /dev/null @@ -1,268 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2016 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* 092355d4-b1b8-4868-9942-da19427a3249 */ -DECLARE_SOF_UUID("ipc-task", ipc_task_uuid, 0x092355d4, 0xb1b8, 0x4868, - 0x99, 0x42, 0xda, 0x19, 0x42, 0x7a, 0x32, 0x49); - -/* private data for IPC */ -struct ipc_data { - struct ipc_data_host_buffer dh_buffer; -}; - -static void irq_handler(void *arg) -{ - struct ipc *ipc = arg; - uint32_t isr, imrd; - - /* Interrupt arrived, check src */ - isr = shim_read(SHIM_ISRD); - imrd = shim_read(SHIM_IMRD); - - tr_dbg(&ipc_tr, "ipc: irq isr 0x%x", isr); - - if (isr & SHIM_ISRD_DONE) { - - /* Mask Done interrupt before return */ - shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) | SHIM_IMRD_DONE); - - /* clear DONE bit - tell Host we have completed */ - shim_write(SHIM_IPCD, 0); - - ipc->is_notification_pending = false; - - /* unmask Done interrupt */ - shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_DONE); - } - - if (isr & SHIM_ISRD_BUSY && !(imrd & SHIM_IMRD_BUSY)) { - - /* Mask Busy interrupt before return */ - shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) | SHIM_IMRD_BUSY); - - ipc_schedule_process(ipc); - } -} - -int ipc_platform_compact_write_msg(struct ipc_cmd_hdr *hdr, int words) -{ - return 0; /* number of words read - not currently used on this platform */ -} - -int ipc_platform_compact_read_msg(struct ipc_cmd_hdr *hdr, int words) -{ - return 0; /* number of words read - not currently used on this platform */ -} - -enum task_state ipc_platform_do_cmd(struct ipc *ipc) -{ - struct ipc_cmd_hdr *hdr; - /* Use struct ipc_data *iipc = ipc_get_drvdata(ipc); if needed */ - - /* perform command */ - hdr = mailbox_validate(); - ipc_cmd(hdr); - - return SOF_TASK_STATE_COMPLETED; -} - -void ipc_platform_complete_cmd(struct ipc *ipc) -{ - /* clear BUSY bit and set DONE bit - accept new messages */ - shim_write(SHIM_IPCX, SHIM_IPCX_DONE); - - /* unmask busy interrupt */ - shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_BUSY); - - // TODO: signal audio work to enter D3 in normal context - /* are we about to enter D3 ? */ - if (ipc->pm_prepare_D3) { - while (1) - /* - * Note, that this function is now called with - * interrupts disabled, so this wait will never even - * return anyway - */ - wait_for_interrupt(0); - } - -} - -int ipc_platform_send_msg(const struct ipc_msg *msg) -{ - struct ipc *ipc = ipc_get(); - - /* can't send nofication when one is in progress */ - if (ipc->is_notification_pending || - shim_read(SHIM_IPCD) & (SHIM_IPCD_BUSY | SHIM_IPCD_DONE)) { - return -EBUSY; - } - - /* now send the message */ - mailbox_dspbox_write(0, msg->tx_data, msg->tx_size); - - tr_dbg(&ipc_tr, "ipc: msg tx -> 0x%x", msg->header); - - ipc->is_notification_pending = true; - - /* now interrupt host to tell it we have message sent */ - shim_write(SHIM_IPCD, SHIM_IPCD_BUSY); - - return 0; -} - -struct ipc_data_host_buffer *ipc_platform_get_host_buffer(struct ipc *ipc) -{ - struct ipc_data *iipc = ipc_get_drvdata(ipc); - - return &iipc->dh_buffer; -} - -int platform_ipc_init(struct ipc *ipc) -{ - struct ipc_data *iipc; - uint32_t imrd, dir, caps, dev; - - /* init ipc data */ - iipc = rzalloc(SOF_MEM_ZONE_SYS, 0, SOF_MEM_CAPS_RAM, - sizeof(struct ipc_data)); - ipc_set_drvdata(ipc, iipc); - - /* schedule */ - schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_uuid), - &ipc_task_ops, ipc, 0, 0); - -#if CONFIG_HOST_PTABLE - /* allocate page table buffer */ - iipc->dh_buffer.page_table = rzalloc(SOF_MEM_ZONE_SYS, 0, - SOF_MEM_CAPS_RAM, - PLATFORM_PAGE_TABLE_SIZE); - if (iipc->dh_buffer.page_table) - bzero(iipc->dh_buffer.page_table, PLATFORM_PAGE_TABLE_SIZE); -#endif - - /* request GP DMA with shared access privilege */ - caps = 0; - dir = DMA_DIR_HMEM_TO_LMEM; - dev = DMA_DEV_HOST; - iipc->dh_buffer.dmac = dma_get(dir, caps, dev, DMA_ACCESS_SHARED); - - /* configure interrupt */ - interrupt_register(PLATFORM_IPC_INTERRUPT, irq_handler, ipc); - interrupt_enable(PLATFORM_IPC_INTERRUPT, ipc); - - /* Unmask Busy and Done interrupts */ - imrd = shim_read(SHIM_IMRD); - imrd &= ~(SHIM_IMRD_BUSY | SHIM_IMRD_DONE); - shim_write(SHIM_IMRD, imrd); - - return 0; -} - -#if CONFIG_IPC_POLLING - -int ipc_platform_poll_init(void) -{ - return 0; -} - -/* tell host we have completed command */ -void ipc_platform_poll_set_cmd_done(void) -{ - /* clear BUSY bit and set DONE bit - accept new messages */ - shim_write(SHIM_IPCX, SHIM_IPCX_DONE); - - /* unmask busy interrupt */ - shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_BUSY); -} - -/* read the IPC register for any new command messages */ -int ipc_platform_poll_is_cmd_pending(void) -{ - uint32_t isr, imrd; - - /* Interrupt arrived, check src */ - isr = shim_read(SHIM_ISRD); - imrd = shim_read(SHIM_IMRD); - - if (isr & SHIM_ISRD_BUSY && !(imrd & SHIM_IMRD_BUSY)) { - - /* Mask Busy interrupt before return */ - shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) | SHIM_IMRD_BUSY); - - /* new message */ - return 1; - } - - /* no new message */ - return 0; -} - -int ipc_platform_poll_is_host_ready(void) -{ - uint32_t isr; - - /* Interrupt arrived, check src */ - isr = shim_read(SHIM_ISRD); - - if (isr & SHIM_ISRD_DONE) { - - /* Mask Done interrupt before return */ - shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) | SHIM_IMRD_DONE); - - /* clear DONE bit - tell Host we have completed */ - shim_write(SHIM_IPCD, 0); - - /* unmask Done interrupt */ - shim_write(SHIM_IMRD, shim_read(SHIM_IMRD) & ~SHIM_IMRD_DONE); - - /* host done */ - return 1; - } - - /* host still pending */ - return 0; -} - -int ipc_platform_poll_tx_host_msg(struct ipc_msg *msg) -{ - /* can't send nofication when one is in progress */ - if (shim_read(SHIM_IPCD) & (SHIM_IPCD_BUSY | SHIM_IPCD_DONE)) - return 0; - - /* now send the message */ - mailbox_dspbox_write(0, msg->tx_data, msg->tx_size); - - /* now interrupt host to tell it we have message sent */ - shim_write(SHIM_IPCD, SHIM_IPCD_BUSY); - - /* message sent */ - return 1; -} - -#endif diff --git a/src/drivers/intel/haswell/ssp.c b/src/drivers/intel/haswell/ssp.c deleted file mode 100644 index 7ea7d489d34c..000000000000 --- a/src/drivers/intel/haswell/ssp.c +++ /dev/null @@ -1,538 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2018 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood -// Keyon Jie - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Digital Audio interface formatting */ -static int ssp_set_config(struct dai *dai, struct ipc_config_dai *common_config, - const void *spec_config) -{ - const struct sof_ipc_dai_config *config = spec_config; - struct ssp_pdata *ssp = dai_get_drvdata(dai); - uint32_t sscr0; - uint32_t sscr1; - uint32_t sscr2; - uint32_t sspsp; - uint32_t sspsp2; - uint32_t mdiv; - uint32_t bdiv; - uint32_t data_size; - uint32_t start_delay; - uint32_t frame_end_padding; - uint32_t slot_end_padding; - uint32_t frame_len = 0; - uint32_t bdiv_min; - uint32_t format; - bool inverted_frame = false; - int ret = 0; - k_spinlock_key_t key; - - key = k_spin_lock(&dai->lock); - - /* is playback/capture already running */ - if (ssp->state[DAI_DIR_PLAYBACK] == COMP_STATE_ACTIVE || - ssp->state[DAI_DIR_CAPTURE] == COMP_STATE_ACTIVE) { - dai_info(dai, "ssp_set_config(): playback/capture active. Ignore config"); - goto out; - } - - dai_info(dai, "ssp_set_config()"); - - /* disable clock */ - shim_update_bits(SHIM_CLKCTL, SHIM_CLKCTL_EN_SSP(dai->index), 0); - - /* enable MCLK */ - shim_update_bits(SHIM_CLKCTL, SHIM_CLKCTL_SMOS(0x3), - SHIM_CLKCTL_SMOS(0x3)); - - /* reset SSP settings */ - /* sscr0 dynamic settings are DSS, EDSS, SCR, FRDC, ECS */ - sscr0 = SSCR0_MOD | SSCR0_PSP; - - /* sscr1 dynamic settings are TFT, RFT, SFRMDIR, SCLKDIR, SCFR */ - sscr1 = SSCR1_TTE | SSCR1_TTELP; - - /* enable Transmit underrun mode 1 */ - sscr2 = SSCR2_TURM1; - - /* sspsp dynamic settings are SCMODE, SFRMP, DMYSTRT, SFRMWDTH */ - sspsp = 0x0; - - /* sspsp2 no dynamic setting */ - sspsp2 = 0x0; - - ssp->config = *config; - ssp->params = config->ssp; - - switch (config->format & SOF_DAI_FMT_CLOCK_PROVIDER_MASK) { - case SOF_DAI_FMT_CBP_CFP: - sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR; -#ifdef ENABLE_SSRCR1_SCFR - sscr1 |= SSCR1_SCFR; -#endif - break; - case SOF_DAI_FMT_CBC_CFC: - break; - case SOF_DAI_FMT_CBP_CFC: - sscr1 |= SSCR1_SCLKDIR; -#ifdef ENABLE_SSRCR1_SCFR - sscr1 |= SSCR1_SCFR; -#endif - break; - case SOF_DAI_FMT_CBC_CFP: - sscr1 |= SSCR1_SFRMDIR; - break; - default: - dai_err(dai, "ssp_set_config(): format & PROVIDER_MASK EINVAL"); - ret = -EINVAL; - goto out; - } - - /* clock signal polarity */ - switch (config->format & SOF_DAI_FMT_INV_MASK) { - case SOF_DAI_FMT_NB_NF: - break; - case SOF_DAI_FMT_NB_IF: - inverted_frame = true; /* handled later with format */ - break; - case SOF_DAI_FMT_IB_IF: - sspsp |= SSPSP_SCMODE(2); - inverted_frame = true; /* handled later with format */ - break; - case SOF_DAI_FMT_IB_NF: - sspsp |= SSPSP_SCMODE(2); - break; - default: - dai_err(dai, "ssp_set_config(): format & INV_MASK EINVAL"); - ret = -EINVAL; - goto out; - } - - /* Additional hardware settings */ - - /* Receiver Time-out Interrupt Disabled/Enabled */ - sscr1 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_TINTE) ? - SSCR1_TINTE : 0; - - /* Peripheral Trailing Byte Interrupts Disable/Enable */ - sscr1 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_PINTE) ? - SSCR1_PINTE : 0; - - /* Enable/disable internal loopback. Output of transmit serial - * shifter connected to input of receive serial shifter, internally. - */ - sscr1 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_LBM) ? - SSCR1_LBM : 0; - - /* Transmit data are driven at the same/opposite clock edge specified - * in SSPSP.SCMODE[1:0] - */ - sscr2 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_SMTATF) ? - SSCR2_SMTATF : 0; - - /* Receive data are sampled at the same/opposite clock edge specified - * in SSPSP.SCMODE[1:0] - */ - sscr2 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_MMRATF) ? - SSCR2_MMRATF : 0; - - /* Enable/disable the fix for PSP consumer mode TXD wait for frame - * de-assertion before starting the second channel - */ - sscr2 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD) ? - SSCR2_PSPSTWFDFD : 0; - - /* Enable/disable the fix for PSP provider mode FSRT with dummy stop & - * frame end padding capability - */ - sscr2 |= (ssp->params.quirks & SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD) ? - SSCR2_PSPSRWFDFD : 0; - - /* BCLK is generated from MCLK - must be divisable */ - if (config->ssp.mclk_rate % config->ssp.bclk_rate) { - dai_err(dai, "ssp_set_config(): MCLK is not divisable"); - ret = -EINVAL; - goto out; - } - - /* divisor must be within SCR range */ - mdiv = (config->ssp.mclk_rate / config->ssp.bclk_rate) - 1; - if (mdiv > (SSCR0_SCR_MASK >> 8)) { - dai_err(dai, "ssp_set_config(): divisor is not within SCR range"); - ret = -EINVAL; - goto out; - } - - /* set the SCR divisor */ - sscr0 |= SSCR0_SCR(mdiv); - - /* calc frame width based on BCLK and rate - must be divisable */ - if (config->ssp.bclk_rate % config->ssp.fsync_rate) { - dai_err(dai, "ssp_set_config(): BLCK is not divisable"); - ret = -EINVAL; - goto out; - } - - /* must be enouch BCLKs for data */ - bdiv = config->ssp.bclk_rate / config->ssp.fsync_rate; - if (bdiv < config->ssp.tdm_slot_width * - config->ssp.tdm_slots) { - dai_err(dai, "ssp_set_config(): not enough BCLKs"); - ret = -EINVAL; - goto out; - } - - /* tdm_slot_width must be <= 38 for SSP */ - if (config->ssp.tdm_slot_width > 38) { - dai_err(dai, "ssp_set_config(): tdm_slot_width > 38"); - ret = -EINVAL; - goto out; - } - - bdiv_min = config->ssp.tdm_slots * config->ssp.sample_valid_bits; - if (bdiv < bdiv_min) { - dai_err(dai, "ssp_set_config(): bdiv < bdiv_min"); - ret = -EINVAL; - goto out; - } - - frame_end_padding = bdiv - bdiv_min; - if (frame_end_padding > SSPSP2_FEP_MASK) { - dai_err(dai, "ssp_set_config(): frame_end_padding > SSPSP2_FEP_MASK"); - ret = -EINVAL; - goto out; - } - - /* format */ - format = config->format & SOF_DAI_FMT_FORMAT_MASK; - switch (format) { - case SOF_DAI_FMT_I2S: - case SOF_DAI_FMT_LEFT_J: - - if (format == SOF_DAI_FMT_I2S) { - start_delay = 1; - - /* - * handle frame polarity, I2S default is falling/active low, - * non-inverted(inverted_frame=0) -- active low(SFRMP=0), - * inverted(inverted_frame=1) -- rising/active high(SFRMP=1), - * so, we should set SFRMP to inverted_frame. - */ - sspsp |= SSPSP_SFRMP(inverted_frame); - sspsp |= SSPSP_FSRT; - - } else { - start_delay = 0; - - /* - * handle frame polarity, LEFT_J default is rising/active high, - * non-inverted(inverted_frame=0) -- active high(SFRMP=1), - * inverted(inverted_frame=1) -- falling/active low(SFRMP=0), - * so, we should set SFRMP to !inverted_frame. - */ - sspsp |= SSPSP_SFRMP(!inverted_frame); - } - - sscr0 |= SSCR0_FRDC(config->ssp.tdm_slots); - - if (bdiv % 2) { - dai_err(dai, "ssp_set_config(): bdiv is not divisible by 2"); - ret = -EINVAL; - goto out; - } - - /* set asserted frame length to half frame length */ - frame_len = bdiv / 2; - - /* - * for I2S/LEFT_J, the padding has to happen at the end - * of each slot - */ - if (frame_end_padding % 2) { - dai_err(dai, "ssp_set_config(): frame_end_padding is not divisible by 2"); - ret = -EINVAL; - goto out; - } - - slot_end_padding = frame_end_padding / 2; - - if (slot_end_padding > 15) { - /* can't handle padding over 15 bits */ - dai_err(dai, "ssp_set_config(): slot_end_padding over 15 bits"); - ret = -EINVAL; - goto out; - } - - sspsp |= SSPSP_DMYSTOP(slot_end_padding); - slot_end_padding >>= SSPSP_DMYSTOP_BITS; - sspsp |= SSPSP_EDMYSTOP(slot_end_padding); - - break; - case SOF_DAI_FMT_DSP_A: - - start_delay = 1; - - sscr0 |= SSCR0_FRDC(config->ssp.tdm_slots); - - /* set asserted frame length */ - frame_len = 1; - - /* handle frame polarity, DSP_A default is rising/active high */ - sspsp |= SSPSP_SFRMP(!inverted_frame); - sspsp2 |= (frame_end_padding & SSPSP2_FEP_MASK); - - break; - case SOF_DAI_FMT_DSP_B: - - start_delay = 0; - - sscr0 |= SSCR0_FRDC(config->ssp.tdm_slots); - - /* set asserted frame length */ - frame_len = 1; - - /* handle frame polarity, DSP_B default is rising/active high */ - sspsp |= SSPSP_SFRMP(!inverted_frame); - sspsp2 |= (frame_end_padding & SSPSP2_FEP_MASK); - - break; - default: - dai_err(dai, "ssp_set_config(): invalid format"); - ret = -EINVAL; - goto out; - } - - if (start_delay) - sspsp |= SSPSP_FSRT; - - sspsp |= SSPSP_SFRMWDTH(frame_len); - - data_size = config->ssp.sample_valid_bits; - - if (data_size > 16) - sscr0 |= (SSCR0_EDSS | SSCR0_DSIZE(data_size - 16)); - else - sscr0 |= SSCR0_DSIZE(data_size); - - sscr1 |= SSCR1_TFT(0x8) | SSCR1_RFT(0x8); - - ssp_write(dai, SSCR0, sscr0); - ssp_write(dai, SSCR1, sscr1); - ssp_write(dai, SSCR2, sscr2); - ssp_write(dai, SSPSP, sspsp); - ssp_write(dai, SSTSA, SSTSA_SSTSA(config->ssp.tx_slots)); - ssp_write(dai, SSRSA, SSRSA_SSRSA(config->ssp.rx_slots)); - ssp_write(dai, SSPSP2, sspsp2); - - ssp->state[DAI_DIR_PLAYBACK] = COMP_STATE_PREPARE; - ssp->state[DAI_DIR_CAPTURE] = COMP_STATE_PREPARE; - - /* enable clock */ - shim_update_bits(SHIM_CLKCTL, SHIM_CLKCTL_EN_SSP(dai->index), - SHIM_CLKCTL_EN_SSP(dai->index)); - - /* enable free running clock */ - ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE); - ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0); - - dai_info(dai, "ssp_set_config(), done"); - -out: - k_spin_unlock(&dai->lock, key); - - return ret; -} - -/* get SSP hw params */ -static int ssp_get_hw_params(struct dai *dai, - struct sof_ipc_stream_params *params, int dir) -{ - struct ssp_pdata *ssp = dai_get_drvdata(dai); - - params->rate = ssp->params.fsync_rate; - params->buffer_fmt = 0; - - if (dir == SOF_IPC_STREAM_PLAYBACK) - params->channels = popcount(ssp->params.tx_slots); - else - params->channels = popcount(ssp->params.rx_slots); - - switch (ssp->params.sample_valid_bits) { - case 16: - params->frame_fmt = SOF_IPC_FRAME_S16_LE; - break; - case 24: - params->frame_fmt = SOF_IPC_FRAME_S24_4LE; - break; - case 32: - params->frame_fmt = SOF_IPC_FRAME_S32_LE; - break; - default: - dai_err(dai, "ssp_get_hw_params(): not supported format"); - return -EINVAL; - } - - return 0; -} - -/* start the SSP for either playback or capture */ -static void ssp_start(struct dai *dai, int direction) -{ - struct ssp_pdata *ssp = dai_get_drvdata(dai); - k_spinlock_key_t key; - - key = k_spin_lock(&dai->lock); - - dai_info(dai, "ssp_start()"); - - /* enable DMA */ - if (direction == DAI_DIR_PLAYBACK) { - ssp_update_bits(dai, SSCR1, SSCR1_TSRE | SSCR1_EBCEI, - SSCR1_TSRE | SSCR1_EBCEI); - ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE); - ssp_update_bits(dai, SSCR0, SSCR0_TIM, 0); - ssp_update_bits(dai, SSTSA, SSTSA_TSEN, SSTSA_TSEN); - } else { - ssp_update_bits(dai, SSCR1, SSCR1_RSRE | SSCR1_EBCEI, - SSCR1_RSRE | SSCR1_EBCEI); - ssp_update_bits(dai, SSCR0, SSCR0_SSE, SSCR0_SSE); - ssp_update_bits(dai, SSCR0, SSCR0_RIM, 0); - ssp_update_bits(dai, SSRSA, SSRSA_RSEN, SSRSA_RSEN); - } - - /* enable port */ - ssp->state[direction] = COMP_STATE_ACTIVE; - - k_spin_unlock(&dai->lock, key); -} - -/* stop the SSP for either playback or capture */ -static void ssp_stop(struct dai *dai, int direction) -{ - struct ssp_pdata *ssp = dai_get_drvdata(dai); - k_spinlock_key_t key; - - key = k_spin_lock(&dai->lock); - - /* stop Rx if neeed */ - if (direction == DAI_DIR_CAPTURE && - ssp->state[SOF_IPC_STREAM_CAPTURE] != COMP_STATE_PREPARE) { - ssp_update_bits(dai, SSCR1, SSCR1_RSRE, 0); - ssp_update_bits(dai, SSCR0, SSCR0_RIM, SSCR0_RIM); - ssp_update_bits(dai, SSRSA, SSRSA_RSEN, 0); - ssp->state[SOF_IPC_STREAM_CAPTURE] = COMP_STATE_PREPARE; - dai_info(dai, "ssp_stop(), RX stop"); - } - - /* stop Tx if needed */ - if (direction == DAI_DIR_PLAYBACK && - ssp->state[SOF_IPC_STREAM_PLAYBACK] != COMP_STATE_PREPARE) { - ssp_update_bits(dai, SSCR1, SSCR1_TSRE, 0); - ssp_update_bits(dai, SSCR0, SSCR0_TIM, SSCR0_TIM); - ssp_update_bits(dai, SSTSA, SSTSA_TSEN, 0); - ssp->state[SOF_IPC_STREAM_PLAYBACK] = COMP_STATE_PREPARE; - dai_info(dai, "ssp_stop(), TX stop"); - } - - /* disable SSP port if no users */ - if (ssp->state[SOF_IPC_STREAM_CAPTURE] == COMP_STATE_PREPARE && - ssp->state[SOF_IPC_STREAM_PLAYBACK] == COMP_STATE_PREPARE) { - ssp_update_bits(dai, SSCR0, SSCR0_SSE, 0); - dai_info(dai, "ssp_stop(), SSP port disabled"); - } - - k_spin_unlock(&dai->lock, key); -} - -static void ssp_pause(struct dai *dai, int direction) -{ - struct ssp_pdata *ssp = dai_get_drvdata(dai); - - if (direction == SOF_IPC_STREAM_CAPTURE) - dai_info(dai, "ssp_pause(), RX"); - else - dai_info(dai, "ssp_pause(), TX"); - - ssp->state[direction] = COMP_STATE_PAUSED; -} - -static int ssp_trigger(struct dai *dai, int cmd, int direction) -{ - struct ssp_pdata *ssp = dai_get_drvdata(dai); - - dai_info(dai, "ssp_trigger()"); - - switch (cmd) { - case COMP_TRIGGER_START: - case COMP_TRIGGER_RELEASE: - if (ssp->state[direction] == COMP_STATE_PAUSED || - ssp->state[direction] == COMP_STATE_PREPARE) - ssp_start(dai, direction); - break; - case COMP_TRIGGER_STOP: - ssp_stop(dai, direction); - break; - case COMP_TRIGGER_PAUSE: - ssp_pause(dai, direction); - break; - } - - return 0; -} - -static int ssp_probe(struct dai *dai) -{ - struct ssp_pdata *ssp; - - /* allocate private data */ - ssp = rzalloc(SOF_MEM_ZONE_SYS_SHARED, 0, SOF_MEM_CAPS_RAM, sizeof(*ssp)); - dai_set_drvdata(dai, ssp); - - ssp->state[DAI_DIR_PLAYBACK] = COMP_STATE_READY; - ssp->state[DAI_DIR_CAPTURE] = COMP_STATE_READY; - - return 0; -} - -static int ssp_get_handshake(struct dai *dai, int direction, int stream_id) -{ - return dai->plat_data.fifo[direction].handshake; -} - -static int ssp_get_fifo(struct dai *dai, int direction, int stream_id) -{ - return dai->plat_data.fifo[direction].offset; -} - -const struct dai_driver ssp_driver = { - .type = SOF_DAI_INTEL_SSP, - .dma_caps = DMA_CAP_GP_LP | DMA_CAP_GP_HP, - .dma_dev = DMA_DEV_SSP, - .ops = { - .trigger = ssp_trigger, - .set_config = ssp_set_config, - .get_hw_params = ssp_get_hw_params, - .get_handshake = ssp_get_handshake, - .get_fifo = ssp_get_fifo, - .probe = ssp_probe, - }, -}; diff --git a/src/drivers/intel/haswell/timer.c b/src/drivers/intel/haswell/timer.c deleted file mode 100644 index d205a9d65a4b..000000000000 --- a/src/drivers/intel/haswell/timer.c +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2016 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef __ZEPHYR__ - -void platform_timer_start(struct timer *timer) -{ - //nothing to do on BDW & HSW for cpu timer -} - -void platform_timer_stop(struct timer *timer) -{ - arch_timer_disable(timer); -} - -int64_t platform_timer_set(struct timer *timer, uint64_t ticks) -{ - return arch_timer_set(timer, ticks); -} - -void platform_timer_clear(struct timer *timer) -{ - arch_timer_clear(timer); -} - -uint64_t platform_timer_get(struct timer *timer) -{ - return arch_timer_get_system(timer); -} - -/* IRQs off in arch_timer_get_system() */ -uint64_t platform_timer_get_atomic(struct timer *timer) -{ - return arch_timer_get_system(timer); -} - -#endif /* __ZEPHYR__ */ - -/* get timestamp for host stream DMA position */ -void platform_host_timestamp(struct comp_dev *host, - struct sof_ipc_stream_posn *posn) -{ - int err; - - /* get host position */ - err = comp_position(host, posn); - if (err == 0) - posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64; -} - -/* get timestamp for DAI stream DMA position */ -void platform_dai_timestamp(struct comp_dev *dai, - struct sof_ipc_stream_posn *posn) -{ - int err; - - /* get DAI position */ - err = comp_position(dai, posn); - if (err == 0) - posn->flags |= SOF_TIME_DAI_VALID; - - /* get SSP wallclock - DAI sets this to stream start value */ - posn->wallclock = sof_cycle_get_64() - posn->wallclock; - posn->wallclock_hz = clock_get_freq(PLATFORM_DEFAULT_CLOCK); - posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64; -} - -/* get current wallclock for componnent */ -void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock) -{ - /* only 1 wallclock on HSW */ - *wallclock = sof_cycle_get_64(); -} - -#ifndef __ZEPHYR__ - -int timer_register(struct timer *timer, void (*handler)(void *arg), void *arg) -{ - int ret; - - switch (timer->id) { - case TIMER0: - case TIMER1: - case TIMER2: - ret = arch_timer_register(timer, handler, arg); - break; - default: - ret = -EINVAL; - break; - } - - return ret; -} - -void timer_unregister(struct timer *timer, void *arg) -{ - interrupt_unregister(timer->irq, arg); - -} - -void timer_enable(struct timer *timer, void *arg, int core) -{ - interrupt_enable(timer->irq, arg); - -} - -void timer_disable(struct timer *timer, void *arg, int core) -{ - interrupt_disable(timer->irq, arg); - -} - -#endif /* __ZEPHYR__ */ diff --git a/src/include/sof/drivers/ssp.h b/src/include/sof/drivers/ssp.h index 12bd50e4f1fd..f057e7147747 100644 --- a/src/include/sof/drivers/ssp.h +++ b/src/include/sof/drivers/ssp.h @@ -39,14 +39,6 @@ extern const uint32_t *ssp_freq_sources; #define SSTSS 0x38 #define SSCR2 0x40 -#if CONFIG_BROADWELL || CONFIG_HASWELL -#define SFIFOL 0x68 -#define SFIFOTT 0x6C -#define SSCR3 0x70 -#define SSCR4 0x74 -#define SSCR5 0x78 -#endif - extern const struct dai_driver ssp_driver; /* SSCR0 bits */ @@ -99,7 +91,7 @@ extern const struct dai_driver ssp_driver; #define SSCR1_TTE BIT(30) #define SSCR1_TTELP BIT(31) -#if CONFIG_CAVS || CONFIG_HASWELL || CONFIG_BROADWELL +#if CONFIG_CAVS #define SSCR2_TURM1 BIT(1) #define SSCR2_PSPSRWFDFD BIT(3) #define SSCR2_PSPSTWFDFD BIT(4) @@ -182,7 +174,7 @@ extern const struct dai_driver ssp_driver; #define SFIFOL_TFL(x) ((x) & 0xFFFF) #define SFIFOL_RFL(x) ((x) >> 16) -#if CONFIG_CAVS || CONFIG_HASWELL || CONFIG_BROADWELL +#if CONFIG_CAVS #define SSTSA_TSEN BIT(8) #define SSRSA_RSEN BIT(8) diff --git a/src/platform/CMakeLists.txt b/src/platform/CMakeLists.txt index 829ec9730884..e4196a331d22 100644 --- a/src/platform/CMakeLists.txt +++ b/src/platform/CMakeLists.txt @@ -5,9 +5,7 @@ if(CONFIG_LIBRARY) return() endif() -if(CONFIG_HASWELL OR CONFIG_BROADWELL) - add_subdirectory(haswell) -elseif(CONFIG_APOLLOLAKE) +if(CONFIG_APOLLOLAKE) add_subdirectory(apollolake) elseif(CONFIG_CANNONLAKE) add_subdirectory(cannonlake) diff --git a/src/platform/Kconfig b/src/platform/Kconfig index 36e49c8555b8..362db78862a1 100644 --- a/src/platform/Kconfig +++ b/src/platform/Kconfig @@ -7,36 +7,6 @@ choice default ZEPHYR_POSIX if ARCH_POSIX default TIGERLAKE -config HASWELL - bool "Build for Haswell" - select HOST_PTABLE - select DW_DMA_AGGREGATED_IRQ - select DW - select DW_DMA - select XT_HAVE_RESET_VECTOR_ROM - select XT_INTERRUPT_LEVEL_1 - select XT_INTERRUPT_LEVEL_2 - select XT_INTERRUPT_LEVEL_3 - select INTEL - select SCHEDULE_DMA_MULTI_CHANNEL - help - Select if your target platform is Haswell-compatible - -config BROADWELL - bool "Build for Broadwell" - select HOST_PTABLE - select DW_DMA_AGGREGATED_IRQ - select DW - select DW_DMA - select XT_HAVE_RESET_VECTOR_ROM - select XT_INTERRUPT_LEVEL_1 - select XT_INTERRUPT_LEVEL_2 - select XT_INTERRUPT_LEVEL_3 - select INTEL - select SCHEDULE_DMA_MULTI_CHANNEL - help - Select if your target platform is Broadwell-compatible - config APOLLOLAKE bool "Build for Apollolake" select XT_BOOT_LOADER @@ -486,8 +456,6 @@ config CAVS_IMR_D3_PERSISTENT # TODO: it should just take manifest version and offsets config RIMAGE_SIGNING_SCHEMA string "Rimage firmware signing schema name" - default "hsw" if HASWELL - default "bdw" if BROADWELL default "apl" if APOLLOLAKE default "cnl" if CANNONLAKE default "sue" if SUECREEK diff --git a/src/platform/haswell/CMakeLists.txt b/src/platform/haswell/CMakeLists.txt deleted file mode 100644 index ec909d60035f..000000000000 --- a/src/platform/haswell/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -add_subdirectory(lib) - -add_local_sources(sof platform.c) diff --git a/src/platform/haswell/haswell.x.in b/src/platform/haswell/haswell.x.in deleted file mode 100644 index 7312dfb1e8c1..000000000000 --- a/src/platform/haswell/haswell.x.in +++ /dev/null @@ -1,592 +0,0 @@ -/* - * Linker Script for Baytrail. - * - * This script is run through the GNU C preprocessor to align the memory - * offsets with headers. - * - * Use spaces for formatting as cpp ignore tab sizes. - */ - - -#include -#include - -OUTPUT_ARCH(xtensa) - -MEMORY -{ - vector_reset_text : - org = XCHAL_RESET_VECTOR_PADDR, - len = SOF_MEM_RESET_TEXT_SIZE - vector_reset_lit : - org = XCHAL_RESET_VECTOR_PADDR + SOF_MEM_RESET_TEXT_SIZE, - len = SOF_MEM_RESET_LIT_SIZE - vector_base_text : - org = SOF_MEM_VECBASE_TEXT_BASE, - len = SOF_MEM_VECBASE_LIT_SIZE - vector_int2_lit : - org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int2_text : - org = XCHAL_INTLEVEL2_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int3_lit : - org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int3_text : - org = XCHAL_INTLEVEL3_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int4_lit : - org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int4_text : - org = XCHAL_INTLEVEL4_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int5_lit : - org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int5_text : - org = XCHAL_INTLEVEL5_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int6_lit : - org = XCHAL_INTLEVEL6_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int6_text : - org = XCHAL_INTLEVEL6_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_int7_lit : - org = XCHAL_INTLEVEL7_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_int7_text : - org = XCHAL_INTLEVEL7_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_kernel_lit : - org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_kernel_text : - org = XCHAL_KERNEL_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_user_lit : - org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_user_text : - org = XCHAL_USER_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - vector_double_lit : - org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, - len = SOF_MEM_VECT_LIT_SIZE - vector_double_text : - org = XCHAL_DOUBLEEXC_VECTOR_PADDR, - len = SOF_MEM_VECT_TEXT_SIZE - sof_text_start : - org = XCHAL_NMI_VECTOR_VADDR + SOF_MEM_VECT_SIZE, - len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_NMI_VECTOR_VADDR + SOF_MEM_VECT_SIZE) - sof_data_ro : - org = DRAM0_BASE, - len = SOF_MEM_RO_SIZE - sof_data : - org = DRAM0_BASE + SOF_MEM_RO_SIZE, - len = HEAP_SYSTEM_BASE - (DRAM0_BASE + SOF_MEM_RO_SIZE) - system_heap : - org = HEAP_SYSTEM_BASE, - len = HEAP_SYSTEM_SIZE - system_runtime_heap : - org = HEAP_SYS_RUNTIME_BASE, - len = HEAP_SYS_RUNTIME_SIZE - runtime_heap : - org = HEAP_RUNTIME_BASE, - len = HEAP_RUNTIME_SIZE - buffer_heap : - org = HEAP_BUFFER_BASE, - len = HEAP_BUFFER_SIZE - sof_stack : - org = SOF_STACK_END, - len = SOF_STACK_BASE - SOF_STACK_END - mailbox : - org = MAILBOX_BASE, - len = MAILBOX_SIZE - virtual_thread : - org = SOF_VIRTUAL_THREAD_BASE, - len = SOF_VIRTUAL_THREAD_SIZE - static_uuid_entries_seg (!ari) : - org = UUID_ENTRY_ELF_BASE, - len = UUID_ENTRY_ELF_SIZE - static_log_entries_seg (!ari) : - org = LOG_ENTRY_ELF_BASE, - len = LOG_ENTRY_ELF_SIZE - fw_metadata_seg (!ari) : - org = EXT_MANIFEST_ELF_BASE, - len = EXT_MANIFEST_ELF_SIZE -} - -PHDRS -{ - vector_reset_text_phdr PT_LOAD; - vector_reset_lit_phdr PT_LOAD; - vector_base_text_phdr PT_LOAD; - vector_base_lit_phdr PT_LOAD; - vector_int2_text_phdr PT_LOAD; - vector_int2_lit_phdr PT_LOAD; - vector_int3_text_phdr PT_LOAD; - vector_int3_lit_phdr PT_LOAD; - vector_int4_text_phdr PT_LOAD; - vector_int4_lit_phdr PT_LOAD; - vector_int5_text_phdr PT_LOAD; - vector_int5_lit_phdr PT_LOAD; - vector_int6_text_phdr PT_LOAD; - vector_int6_lit_phdr PT_LOAD; - vector_int7_text_phdr PT_LOAD; - vector_int7_lit_phdr PT_LOAD; - vector_kernel_text_phdr PT_LOAD; - vector_kernel_lit_phdr PT_LOAD; - vector_user_text_phdr PT_LOAD; - vector_user_lit_phdr PT_LOAD; - vector_double_text_phdr PT_LOAD; - vector_double_lit_phdr PT_LOAD; - sof_text_start_phdr PT_LOAD; - sof_data_ro_phdr PT_LOAD; - sof_data_phdr PT_LOAD; - sof_data_bss_phdr PT_LOAD; - system_heap_phdr PT_LOAD; - system_runtime_heap_phdr PT_LOAD; - runtime_heap_phdr PT_LOAD; - buffer_heap_phdr PT_LOAD; - mailbox_phdr PT_LOAD; - virtual_thread_phdr PT_LOAD; - sof_stack_phdr PT_LOAD; - static_uuid_entries_phdr PT_NOTE; - static_log_entries_phdr PT_NOTE; - metadata_entries_phdr PT_NOTE; -} - -/* Default entry point: */ -ENTRY(_ResetVector) -_rom_store_table = 0; - -/* ABI0 does not use Window base */ -PROVIDE(_memmap_vecbase_reset = SOF_MEM_VECBASE_TEXT_BASE); - -/* Various memory-map dependent cache attribute settings: */ -_memmap_cacheattr_wb_base = 0x44024000; -_memmap_cacheattr_wt_base = 0x11021000; -_memmap_cacheattr_bp_base = 0x22022000; -_memmap_cacheattr_unused_mask = 0x00F00FFF; -_memmap_cacheattr_wb_trapnull = 0x4422422F; -_memmap_cacheattr_wba_trapnull = 0x4422422F; -_memmap_cacheattr_wbna_trapnull = 0x25222222; -_memmap_cacheattr_wt_trapnull = 0x1122122F; -_memmap_cacheattr_bp_trapnull = 0x2222222F; -_memmap_cacheattr_wb_strict = 0x44F24FFF; -_memmap_cacheattr_wt_strict = 0x11F21FFF; -_memmap_cacheattr_bp_strict = 0x22F22FFF; -_memmap_cacheattr_wb_allvalid = 0x44224222; -_memmap_cacheattr_wt_allvalid = 0x11221222; -_memmap_cacheattr_bp_allvalid = 0x22222222; -PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull); - -_EXT_MAN_ALIGN_ = 16; -EXTERN(ext_man_fw_ver) - -SECTIONS -{ - .ResetVector.text : ALIGN(4) - { - _ResetVector_text_start = ABSOLUTE(.); - KEEP (*(.ResetVector.text)) - _ResetVector_text_end = ABSOLUTE(.); - } >vector_reset_text :vector_reset_text_phdr - - .ResetVector.literal : ALIGN(4) - { - _ResetVector_literal_start = ABSOLUTE(.); - *(.ResetVector.literal) - _ResetVector_literal_end = ABSOLUTE(.); - } >vector_reset_lit :vector_reset_lit_phdr - - .WindowVectors.text : ALIGN(4) - { - _WindowVectors_text_start = ABSOLUTE(.); - KEEP (*(.WindowVectors.text)) - _WindowVectors_text_end = ABSOLUTE(.); - } >vector_base_text :vector_base_text_phdr - - .Level2InterruptVector.literal : ALIGN(4) - { - _Level2InterruptVector_literal_start = ABSOLUTE(.); - *(.Level2InterruptVector.literal) - _Level2InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int2_lit :vector_int2_lit_phdr - - .Level2InterruptVector.text : ALIGN(4) - { - _Level2InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level2InterruptVector.text)) - _Level2InterruptVector_text_end = ABSOLUTE(.); - } >vector_int2_text :vector_int2_text_phdr - - .Level3InterruptVector.literal : ALIGN(4) - { - _Level3InterruptVector_literal_start = ABSOLUTE(.); - *(.Level3InterruptVector.literal) - _Level3InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int3_lit :vector_int3_lit_phdr - - .Level3InterruptVector.text : ALIGN(4) - { - _Level3InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level3InterruptVector.text)) - _Level3InterruptVector_text_end = ABSOLUTE(.); - } >vector_int3_text :vector_int3_text_phdr - - .Level4InterruptVector.literal : ALIGN(4) - { - _Level4InterruptVector_literal_start = ABSOLUTE(.); - *(.Level4InterruptVector.literal) - _Level4InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int4_lit :vector_int4_lit_phdr - - .Level4InterruptVector.text : ALIGN(4) - { - _Level4InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level4InterruptVector.text)) - _Level4InterruptVector_text_end = ABSOLUTE(.); - } >vector_int4_text :vector_int4_text_phdr - - .Level5InterruptVector.literal : ALIGN(4) - { - _Level5InterruptVector_literal_start = ABSOLUTE(.); - *(.Level5InterruptVector.literal) - _Level5InterruptVector_literal_end = ABSOLUTE(.); - } >vector_int5_lit :vector_int5_lit_phdr - - .Level5InterruptVector.text : ALIGN(4) - { - _Level5InterruptVector_text_start = ABSOLUTE(.); - KEEP (*(.Level5InterruptVector.text)) - _Level5InterruptVector_text_end = ABSOLUTE(.); - } >vector_int5_text :vector_int5_text_phdr - - .DebugExceptionVector.literal : ALIGN(4) - { - _DebugExceptionVector_literal_start = ABSOLUTE(.); - *(.DebugExceptionVector.literal) - _DebugExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int6_lit :vector_int6_lit_phdr - - .DebugExceptionVector.text : ALIGN(4) - { - _DebugExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DebugExceptionVector.text)) - _DebugExceptionVector_text_end = ABSOLUTE(.); - } >vector_int6_text :vector_int6_text_phdr - - .NMIExceptionVector.literal : ALIGN(4) - { - _NMIExceptionVector_literal_start = ABSOLUTE(.); - *(.NMIExceptionVector.literal) - _NMIExceptionVector_literal_end = ABSOLUTE(.); - } >vector_int7_lit :vector_int7_lit_phdr - - .NMIExceptionVector.text : ALIGN(4) - { - _NMIExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.NMIExceptionVector.text)) - _NMIExceptionVector_text_end = ABSOLUTE(.); - } >vector_int7_text :vector_int7_text_phdr - - .KernelExceptionVector.literal : ALIGN(4) - { - _KernelExceptionVector_literal_start = ABSOLUTE(.); - *(.KernelExceptionVector.literal) - _KernelExceptionVector_literal_end = ABSOLUTE(.); - } >vector_kernel_lit :vector_kernel_lit_phdr - - .KernelExceptionVector.text : ALIGN(4) - { - _KernelExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.KernelExceptionVector.text)) - _KernelExceptionVector_text_end = ABSOLUTE(.); - } >vector_kernel_text :vector_kernel_text_phdr - - .UserExceptionVector.literal : ALIGN(4) - { - _UserExceptionVector_literal_start = ABSOLUTE(.); - *(.UserExceptionVector.literal) - _UserExceptionVector_literal_end = ABSOLUTE(.); - } >vector_user_lit :vector_user_lit_phdr - - .UserExceptionVector.text : ALIGN(4) - { - _UserExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.UserExceptionVector.text)) - _UserExceptionVector_text_end = ABSOLUTE(.); - } >vector_user_text :vector_user_text_phdr - - .DoubleExceptionVector.literal : ALIGN(4) - { - _DoubleExceptionVector_literal_start = ABSOLUTE(.); - *(.DoubleExceptionVector.literal) - _DoubleExceptionVector_literal_end = ABSOLUTE(.); - } >vector_double_lit :vector_double_lit_phdr - - .DoubleExceptionVector.text : ALIGN(4) - { - _DoubleExceptionVector_text_start = ABSOLUTE(.); - KEEP (*(.DoubleExceptionVector.text)) - _DoubleExceptionVector_text_end = ABSOLUTE(.); - } >vector_double_text :vector_double_text_phdr - - .text : ALIGN(4) - { - _stext = .; - _text_start = ABSOLUTE(.); - *(.entry.text) - *(.init.literal) - KEEP(*(.init)) - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.fini.literal) - KEEP(*(.fini)) - *(.gnu.version) - _text_end = ABSOLUTE(.); - _etext = .; - } >sof_text_start :sof_text_start_phdr - - .reset.rodata : ALIGN(4) - { - _reset_rodata_start = ABSOLUTE(.); - *(.reset.rodata) - _reset_rodata_end = ABSOLUTE(.); - } >sof_data_ro :sof_data_ro_phdr - - .rodata : ALIGN(4) - { - _rodata_start = ABSOLUTE(.); - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); - KEEP (*(.xt_except_table)) - KEEP (*(.gcc_except_table)) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - KEEP (*(.eh_frame)) - /* C++ constructor and destructor tables, properly ordered: */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); /* this table MUST be 4-byte aligned */ - _bss_table_start = ABSOLUTE(.); - LONG(_bss_start) - LONG(_bss_end) - _bss_table_end = ABSOLUTE(.); - _rodata_end = ABSOLUTE(.); - } >sof_data :sof_data_phdr - - .module_init : ALIGN(4) - { - _module_init_start = ABSOLUTE(.); - *(*.initcall) - _module_init_end = ABSOLUTE(.); - } >sof_data :sof_data_phdr - .data : ALIGN(4) - { - _data_start = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - KEEP(*(.gnu.linkonce.d.*personality*)) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - KEEP(*(.jcr)) - _data_end = ABSOLUTE(.); - _trace_ctx_start = ABSOLUTE(.); - *(.trace_ctx) - _trace_ctx_end = ABSOLUTE(.); - } >sof_data :sof_data_phdr - - .lit4 : ALIGN(4) - { - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - } >sof_data :sof_data_phdr - - .bss (NOLOAD) : ALIGN(8) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - _bss_end = ABSOLUTE(.); - } >sof_data :sof_data_bss_phdr - - /* stack */ - _end = SOF_STACK_END; - PROVIDE(end = SOF_STACK_END); - _stack_sentry = SOF_STACK_END; - __stack = SOF_STACK_BASE; - - _virtual_thread_ptr = _virtual_thread_start; - - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_info 0 : { *(.debug_info) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .xt.profile_range 0 : - { - KEEP (*(.xt.profile_range)) - KEEP (*(.gnu.linkonce.profile_range.*)) - } - .xt.profile_ranges 0 : - { - KEEP (*(.xt.profile_ranges)) - KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) - } - .xt.profile_files 0 : - { - KEEP (*(.xt.profile_files)) - KEEP (*(.gnu.linkonce.xt.profile_files.*)) - } - - .system_heap (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _system_heap_start = ABSOLUTE(.); - . = . + HEAP_SYSTEM_SIZE; - _system_heap_end = ABSOLUTE(.); - } >system_heap :system_heap_phdr - - .system_runtime_heap (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _system_runtime_heap_start = ABSOLUTE(.); - . = . + HEAP_SYS_RUNTIME_SIZE; - _system_runtime_heap_end = ABSOLUTE(.); - } >system_runtime_heap :system_runtime_heap_phdr - - .runtime_heap (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _runtime_heap_start = ABSOLUTE(.); - . = . + HEAP_RUNTIME_SIZE; - _runtime_heap_end = ABSOLUTE(.); - } >runtime_heap :runtime_heap_phdr - - .buffer_heap (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _buffer_heap_start = ABSOLUTE(.); - . = . + HEAP_BUFFER_SIZE; - _buffer_heap_end = ABSOLUTE(.); - } >buffer_heap :buffer_heap_phdr - - .mailbox (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _mailbox_start = ABSOLUTE(.); - . = . + MAILBOX_SIZE; - _mailbox_end = ABSOLUTE(.); - } >mailbox :mailbox_phdr - - .virtual_thread (NOLOAD) : ALIGN(8) - { - . = ALIGN (32); - _virtual_thread_start = ABSOLUTE(.); - . = . + SOF_VIRTUAL_THREAD_SIZE; - _virtual_thread_end = ABSOLUTE(.); - } >virtual_thread :virtual_thread_phdr - - .sof_stack (NOLOAD) : ALIGN(8) - { - . = ALIGN (4096); - _sof_stack_start = ABSOLUTE(.); - . = . + SOF_STACK_TOTAL_SIZE; - _sof_stack_end = ABSOLUTE(.); - } >sof_stack :sof_stack_phdr - - .static_uuid_entries (COPY) : ALIGN(1024) - { - *(*.static_uuids) - } > static_uuid_entries_seg :static_uuid_entries_phdr - - .static_log_entries (COPY) : ALIGN(1024) - { - *(*.static_log*) - } > static_log_entries_seg :static_log_entries_phdr - - .fw_ready : ALIGN(4) - { - KEEP (*(.fw_ready)) - KEEP (*(.fw_ready_metadata)) - } >sof_data :sof_data_phdr - - .fw_metadata (COPY) : ALIGN(1024) - { - KEEP (*(.fw_metadata)) - . = ALIGN(_EXT_MAN_ALIGN_); - } >fw_metadata_seg :metadata_entries_phdr -} diff --git a/src/platform/haswell/include/arch/xtensa/config/core-isa-bdw.h b/src/platform/haswell/include/arch/xtensa/config/core-isa-bdw.h deleted file mode 100644 index b7b2fbb6c671..000000000000 --- a/src/platform/haswell/include/arch/xtensa/config/core-isa-bdw.h +++ /dev/null @@ -1,616 +0,0 @@ -/* - * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa - * processor CORE configuration - * - * See , which includes this file, for more details. - */ - -/* Xtensa processor core configuration information. - - Customer ID=8198; Build=0x7550e; Copyright (c) 1999-2018 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#ifndef _XTENSA_CORE_CONFIGURATION_H -#define _XTENSA_CORE_CONFIGURATION_H - - -/**************************************************************************** - Parameters Useful for Any Code, USER or PRIVILEGED - ****************************************************************************/ - -/* - * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is - * configured, and a value of 0 otherwise. These macros are always defined. - */ - - -/*---------------------------------------------------------------------- - ISA - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ -#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ -#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ -#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ -#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ -#define XCHAL_HAVE_DEBUG 1 /* debug option */ -#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ -#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ -#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ -#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ -#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ -#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ -#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ -#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ -#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ -#define XCHAL_HAVE_MUL32 0 /* MULL instruction */ -#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ -#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */ -#define XCHAL_HAVE_L32R 1 /* L32R instruction */ -#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ -#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ -#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ -#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ -#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ -#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ -#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ -#define XCHAL_HAVE_ABS 1 /* ABS instruction */ -/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ -/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ -#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ -#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ -#define XCHAL_HAVE_SPECULATION 0 /* speculation */ -#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ -#define XCHAL_NUM_CONTEXTS 1 /* */ -#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ -#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ -#define XCHAL_HAVE_PRID 1 /* processor ID register */ -#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ -#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ -#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ -#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ -#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ -#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ -#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ -#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */ -#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ -#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ -#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ -#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ - -#define XCHAL_HAVE_FUSION 0 /* Fusion*/ -#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ -#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ -#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ -#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ -#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ -#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ -#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ -#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ -#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ -#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ -#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ -#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ -#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */ -#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */ -#define XCHAL_HAVE_HIFI_MINI 0 - - - -#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ -#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ -#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */ -#define XCHAL_HAVE_FP 0 /* single prec floating point */ -#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ -#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ -#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ -#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ -#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ -#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ -#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ -#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ -#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ -#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ -#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ - -#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ -#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ -#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ -#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ - -#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ -#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ -#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ -#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ -#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ -#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ - -#define XCHAL_HAVE_PDX 0 /* PDX */ -#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ -#define XCHAL_HAVE_PDX4 0 /* PDX4 */ -#define XCHAL_HAVE_PDX8 0 /* PDX8 */ -#define XCHAL_HAVE_PDX16 0 /* PDX16 */ - -#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ -#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ -#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ -#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ -#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ -#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ -#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ -#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ -#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ -#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ -#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ -#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ -#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ -#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ -#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ -#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ -#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ - -#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ -#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ -#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */ -#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ -#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ -#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */ -#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */ - -#define XCHAL_HAVE_VISIONC 0 /* Vision C */ - -/*---------------------------------------------------------------------- - MISC - ----------------------------------------------------------------------*/ - -#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ -#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ -#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ -#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ -#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay - (1 = 5-stage, 2 = 7-stage) */ -#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ -#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ -/* In T1050, applies to selected core load and store instructions (see ISA): */ -#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ -#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ -#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ -#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ - -#define XCHAL_SW_VERSION 1200008 /* sw version of this header */ - -#define XCHAL_CORE_ID "LX4_langwell_audio_17_8" /* alphanum core name - (CoreID) set in the Xtensa - Processor Generator */ - -#define XCHAL_BUILD_UNIQUE_ID 0x0007550E /* 22-bit sw build ID */ - -/* - * These definitions describe the hardware targeted by this software. - */ -#define XCHAL_HW_CONFIGID0 0xC2B0DBFE /* ConfigID hi 32 bits*/ -#define XCHAL_HW_CONFIGID1 0x15044668 /* ConfigID lo 32 bits*/ -#define XCHAL_HW_VERSION_NAME "LX4.0.4" /* full version name */ -#define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */ -#define XCHAL_HW_VERSION_MINOR 4 /* minor ver# of targeted hw */ -#define XCHAL_HW_VERSION 240004 /* major*100+minor */ -#define XCHAL_HW_REL_LX4 1 -#define XCHAL_HW_REL_LX4_0 1 -#define XCHAL_HW_REL_LX4_0_4 1 -#define XCHAL_HW_CONFIGID_RELIABLE 1 -/* If software targets a *range* of hardware versions, these are the bounds: */ -#define XCHAL_HW_MIN_VERSION_MAJOR 2400 /* major v of earliest tgt hw */ -#define XCHAL_HW_MIN_VERSION_MINOR 4 /* minor v of earliest tgt hw */ -#define XCHAL_HW_MIN_VERSION 240004 /* earliest targeted hw */ -#define XCHAL_HW_MAX_VERSION_MAJOR 2400 /* major v of latest tgt hw */ -#define XCHAL_HW_MAX_VERSION_MINOR 4 /* minor v of latest tgt hw */ -#define XCHAL_HW_MAX_VERSION 240004 /* latest targeted hw */ - - -/*---------------------------------------------------------------------- - CACHE - ----------------------------------------------------------------------*/ - -#define XCHAL_ICACHE_LINESIZE 8 /* I-cache line size in bytes */ -#define XCHAL_DCACHE_LINESIZE 8 /* D-cache line size in bytes */ -#define XCHAL_ICACHE_LINEWIDTH 3 /* log2(I line size in bytes) */ -#define XCHAL_DCACHE_LINEWIDTH 3 /* log2(D line size in bytes) */ - -#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ -#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ - -#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ -#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ - -#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ -#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ -#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ -#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ -#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ -#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ -#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ -#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ -#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ -#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ - - - - -/**************************************************************************** - Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code - ****************************************************************************/ - - -#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY - -/*---------------------------------------------------------------------- - CACHE - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ - -#define XCHAL_HAVE_AXI 0 /* AXI bus */ -#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ -#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ - -#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ -#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ - -/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ - -/* Number of cache sets in log2(lines per way): */ -#define XCHAL_ICACHE_SETWIDTH 0 -#define XCHAL_DCACHE_SETWIDTH 0 - -/* Cache set associativity (number of ways): */ -#define XCHAL_ICACHE_WAYS 1 -#define XCHAL_DCACHE_WAYS 1 - -/* Cache features: */ -#define XCHAL_ICACHE_LINE_LOCKABLE 0 -#define XCHAL_DCACHE_LINE_LOCKABLE 0 -#define XCHAL_ICACHE_ECC_PARITY 0 -#define XCHAL_DCACHE_ECC_PARITY 0 - -/* Cache access size in bytes (affects operation of SICW instruction): */ -#define XCHAL_ICACHE_ACCESS_SIZE 1 -#define XCHAL_DCACHE_ACCESS_SIZE 1 - -#define XCHAL_DCACHE_BANKS 0 /* number of banks */ - -/* Number of encoded cache attr bits (see for decoded bits): */ -#define XCHAL_CA_BITS 4 - - -/*---------------------------------------------------------------------- - INTERNAL I/D RAM/ROMs and XLMI - ----------------------------------------------------------------------*/ -#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ -#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ -#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ -#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ -#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ -#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ - -/* Instruction RAM 0: */ -#define XCHAL_INSTRAM0_VADDR 0x00000000 /* virtual address */ -#define XCHAL_INSTRAM0_PADDR 0x00000000 /* physical address */ -#define XCHAL_INSTRAM0_SIZE 0x50000 /* size in bytes */ -#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ -#define XCHAL_HAVE_INSTRAM0 1 -#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ - -/* Data RAM 0: */ -#define XCHAL_DATARAM0_VADDR 0x00400000 /* virtual address */ -#define XCHAL_DATARAM0_PADDR 0x00400000 /* physical address */ -#define XCHAL_DATARAM0_SIZE 0x50000 /* size in bytes */ -#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ -#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ -#define XCHAL_HAVE_DATARAM0 1 -#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ - -/* Data RAM 1: */ -#define XCHAL_DATARAM1_VADDR 0x00480000 /* virtual address */ -#define XCHAL_DATARAM1_PADDR 0x00480000 /* physical address */ -#define XCHAL_DATARAM1_SIZE 0x50000 /* size in bytes */ -#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ -#define XCHAL_DATARAM1_BANKS 1 /* number of banks */ -#define XCHAL_HAVE_DATARAM1 1 -#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */ - -#define XCHAL_HAVE_IDMA 0 -#define XCHAL_HAVE_IDMA_TRANSPOSE 0 - -#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ - - -/*---------------------------------------------------------------------- - INTERRUPTS and TIMERS - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ -#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ -#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ -#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ -#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ -#define XCHAL_NUM_INTERRUPTS 15 /* number of interrupts */ -#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */ -#define XCHAL_NUM_EXTINTERRUPTS 10 /* num of external interrupts */ -#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels - (not including level zero) */ -#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ - /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ - -/* Masks of interrupts at each interrupt level: */ -#define XCHAL_INTLEVEL1_MASK 0x000000FF -#define XCHAL_INTLEVEL2_MASK 0x00000100 -#define XCHAL_INTLEVEL3_MASK 0x00000E00 -#define XCHAL_INTLEVEL4_MASK 0x00001000 -#define XCHAL_INTLEVEL5_MASK 0x00002000 -#define XCHAL_INTLEVEL6_MASK 0x00000000 -#define XCHAL_INTLEVEL7_MASK 0x00004000 - -/* Masks of interrupts at each range 1..n of interrupt levels: */ -#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000000FF -#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000001FF -#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF -#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00001FFF -#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00003FFF -#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00003FFF -#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00007FFF - -/* Level of each interrupt: */ -#define XCHAL_INT0_LEVEL 1 -#define XCHAL_INT1_LEVEL 1 -#define XCHAL_INT2_LEVEL 1 -#define XCHAL_INT3_LEVEL 1 -#define XCHAL_INT4_LEVEL 1 -#define XCHAL_INT5_LEVEL 1 -#define XCHAL_INT6_LEVEL 1 -#define XCHAL_INT7_LEVEL 1 -#define XCHAL_INT8_LEVEL 2 -#define XCHAL_INT9_LEVEL 3 -#define XCHAL_INT10_LEVEL 3 -#define XCHAL_INT11_LEVEL 3 -#define XCHAL_INT12_LEVEL 4 -#define XCHAL_INT13_LEVEL 5 -#define XCHAL_INT14_LEVEL 7 -#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ -#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ -#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with - EXCSAVE/EPS/EPC_n, RFI n) */ - -/* Type of each interrupt: */ -#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI - -/* Masks of interrupts for each type of interrupt: */ -#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFF8000 -#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 -#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 -#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F -#define XCHAL_INTTYPE_MASK_TIMER 0x00002440 -#define XCHAL_INTTYPE_MASK_NMI 0x00004000 -#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 -#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 -#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 -#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 -#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 - -/* Interrupt numbers assigned to specific interrupt sources: */ -#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ -#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ -#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ -#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED -#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ - -/* Interrupt numbers for levels at which only one interrupt is configured: */ -#define XCHAL_INTLEVEL2_NUM 8 -#define XCHAL_INTLEVEL4_NUM 12 -#define XCHAL_INTLEVEL5_NUM 13 -#define XCHAL_INTLEVEL7_NUM 14 -/* (There are many interrupts each at level(s) 1, 3.) */ - - -/* - * External interrupt mapping. - * These macros describe how Xtensa processor interrupt numbers - * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) - * map to external BInterrupt pins, for those interrupts - * configured as external (level-triggered, edge-triggered, or NMI). - * See the Xtensa processor databook for more details. - */ - -/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ -#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ -#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ -#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ -#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ -#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ -#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ -#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ -#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ -#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ -#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ -/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ -#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ -#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ -#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ -#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ -#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ -#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ -#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ -#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ -#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */ -#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ - - -/*---------------------------------------------------------------------- - EXCEPTIONS and VECTORS - ----------------------------------------------------------------------*/ - -#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture - number: 1 == XEA1 (old) - 2 == XEA2 (new) - 0 == XEAX (extern) or TX */ -#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ -#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ -#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ -#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ -#define XCHAL_HAVE_HALT 0 /* halt architecture option */ -#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ -#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ -#define XCHAL_HAVE_VECTOR_SELECT 0 /* relocatable vectors */ -#define XCHAL_HAVE_VECBASE 0 /* relocatable vectors */ - -#define XCHAL_RESET_VECOFS 0x00000000 -#define XCHAL_RESET_VECTOR_VADDR 0x00000000 -#define XCHAL_RESET_VECTOR_PADDR 0x00000000 -#define XCHAL_USER_VECOFS 0x00000000 -#define XCHAL_USER_VECTOR_VADDR 0x000005C0 -#define XCHAL_USER_VECTOR_PADDR 0x000005C0 -#define XCHAL_KERNEL_VECOFS 0x00000000 -#define XCHAL_KERNEL_VECTOR_VADDR 0x00000584 -#define XCHAL_KERNEL_VECTOR_PADDR 0x00000584 -#define XCHAL_DOUBLEEXC_VECOFS 0x00000000 -#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000005FC -#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000005FC -#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 -#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 -#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 -#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 -#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 -#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 -#define XCHAL_WINDOW_VECTORS_VADDR 0x00000400 -#define XCHAL_WINDOW_VECTORS_PADDR 0x00000400 -#define XCHAL_INTLEVEL2_VECOFS 0x00000000 -#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00000640 -#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000640 -#define XCHAL_INTLEVEL3_VECOFS 0x00000000 -#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x0000067C -#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x0000067C -#define XCHAL_INTLEVEL4_VECOFS 0x00000000 -#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x000006B8 -#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x000006B8 -#define XCHAL_INTLEVEL5_VECOFS 0x00000000 -#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x000006F4 -#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x000006F4 -#define XCHAL_INTLEVEL6_VECOFS 0x00000000 -#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00000730 -#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00000730 -#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS -#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR -#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR -#define XCHAL_NMI_VECOFS 0x00000000 -#define XCHAL_NMI_VECTOR_VADDR 0x0000076C -#define XCHAL_NMI_VECTOR_PADDR 0x0000076C -#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS -#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR -#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR - - -/*---------------------------------------------------------------------- - DEBUG MODULE - ----------------------------------------------------------------------*/ - -/* Misc */ -#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ -#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ -#define XCHAL_HAVE_DEBUG_JTAG 0 /* JTAG to debug module */ - -/* On-Chip Debug (OCD) */ -#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ -#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ -#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ -#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option (to LX4) */ -#define XCHAL_HAVE_OCD_LS32DDR 0 /* L32DDR/S32DDR (faster OCD) */ - -/* TRAX (in core) */ -#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ -#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ -#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ -#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ -#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ - -/* Perf counters */ -#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ - - -/*---------------------------------------------------------------------- - MMU - ----------------------------------------------------------------------*/ - -/* See core-matmap.h header file for more details. */ - -#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ -#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ -#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ -#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ -#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ -#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ -#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ -#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table - [autorefill] and protection) - usable for an MMU-based OS */ - -/* If none of the above last 5 are set, it's a custom TLB configuration. */ - -#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ -#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ -#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ - -/*---------------------------------------------------------------------- - MPU - ----------------------------------------------------------------------*/ -#define XCHAL_HAVE_MPU 0 -#define XCHAL_MPU_ENTRIES 0 - -#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ -#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ -#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ - -#define XCHAL_MPU_ALIGN_BITS 0 -#define XCHAL_MPU_ALIGN 0 - -#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ - - -#endif /* _XTENSA_CORE_CONFIGURATION_H */ - diff --git a/src/platform/haswell/include/arch/xtensa/config/core-isa-hsw.h b/src/platform/haswell/include/arch/xtensa/config/core-isa-hsw.h deleted file mode 100644 index e8469b8d64f4..000000000000 --- a/src/platform/haswell/include/arch/xtensa/config/core-isa-hsw.h +++ /dev/null @@ -1,616 +0,0 @@ -/* - * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa - * processor CORE configuration - * - * See , which includes this file, for more details. - */ - -/* Xtensa processor core configuration information. - - Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#ifndef _XTENSA_CORE_CONFIGURATION_H -#define _XTENSA_CORE_CONFIGURATION_H - - -/**************************************************************************** - Parameters Useful for Any Code, USER or PRIVILEGED - ****************************************************************************/ - -/* - * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is - * configured, and a value of 0 otherwise. These macros are always defined. - */ - - -/*---------------------------------------------------------------------- - ISA - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ -#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ -#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ -#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ -#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */ -#define XCHAL_HAVE_DEBUG 1 /* debug option */ -#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ -#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ -#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ -#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ -#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ -#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ -#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ -#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ -#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ -#define XCHAL_HAVE_MUL32 0 /* MULL instruction */ -#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ -#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */ -#define XCHAL_HAVE_L32R 1 /* L32R instruction */ -#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ -#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ -#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ -#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ -#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ -#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ -#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ -#define XCHAL_HAVE_ABS 1 /* ABS instruction */ -/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ -/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ -#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ -#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ -#define XCHAL_HAVE_SPECULATION 0 /* speculation */ -#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ -#define XCHAL_NUM_CONTEXTS 1 /* */ -#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ -#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ -#define XCHAL_HAVE_PRID 1 /* processor ID register */ -#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ -#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ -#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ -#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ -#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ -#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ -#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ -#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */ -#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ -#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ -#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ -#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ - -#define XCHAL_HAVE_FUSION 0 /* Fusion*/ -#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ -#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ -#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ -#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ -#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ -#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ -#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ -#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ -#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ -#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ -#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ -#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ -#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ -#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */ -#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */ -#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */ -#define XCHAL_HAVE_HIFI_MINI 0 - - - -#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ -#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ -#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */ -#define XCHAL_HAVE_FP 0 /* single prec floating point */ -#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ -#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ -#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ -#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ -#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ -#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ -#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ -#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ -#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ -#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ -#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ - -#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ -#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ -#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ -#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ - -#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ -#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ -#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ -#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ -#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ -#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ - -#define XCHAL_HAVE_PDX 0 /* PDX */ -#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ -#define XCHAL_HAVE_PDX4 0 /* PDX4 */ -#define XCHAL_HAVE_PDX8 0 /* PDX8 */ -#define XCHAL_HAVE_PDX16 0 /* PDX16 */ - -#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ -#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ -#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ -#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ -#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ -#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ -#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ -#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ -#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ -#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ -#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ -#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ -#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ -#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ -#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ -#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ -#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ - -#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ -#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ -#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */ -#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ -#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ -#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */ -#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */ - -#define XCHAL_HAVE_VISIONC 0 /* Vision C */ - -/*---------------------------------------------------------------------- - MISC - ----------------------------------------------------------------------*/ - -#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ -#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ -#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */ -#define XCHAL_DATA_WIDTH 8 /* data width in bytes */ -#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay - (1 = 5-stage, 2 = 7-stage) */ -#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ -#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ -/* In T1050, applies to selected core load and store instructions (see ISA): */ -#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ -#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ -#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ -#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ - -#define XCHAL_SW_VERSION 1200008 /* sw version of this header */ - -#define XCHAL_CORE_ID "LX4_langwell_audio_17_8" /* alphanum core name - (CoreID) set in the Xtensa - Processor Generator */ - -#define XCHAL_BUILD_UNIQUE_ID 0x0005483B /* 22-bit sw build ID */ - -/* - * These definitions describe the hardware targeted by this software. - */ -#define XCHAL_HW_CONFIGID0 0xC2B0DBFE /* ConfigID hi 32 bits*/ -#define XCHAL_HW_CONFIGID1 0x15044668 /* ConfigID lo 32 bits*/ -#define XCHAL_HW_VERSION_NAME "LX4.0.4" /* full version name */ -#define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */ -#define XCHAL_HW_VERSION_MINOR 4 /* minor ver# of targeted hw */ -#define XCHAL_HW_VERSION 240004 /* major*100+minor */ -#define XCHAL_HW_REL_LX4 1 -#define XCHAL_HW_REL_LX4_0 1 -#define XCHAL_HW_REL_LX4_0_4 1 -#define XCHAL_HW_CONFIGID_RELIABLE 1 -/* If software targets a *range* of hardware versions, these are the bounds: */ -#define XCHAL_HW_MIN_VERSION_MAJOR 2400 /* major v of earliest tgt hw */ -#define XCHAL_HW_MIN_VERSION_MINOR 4 /* minor v of earliest tgt hw */ -#define XCHAL_HW_MIN_VERSION 240004 /* earliest targeted hw */ -#define XCHAL_HW_MAX_VERSION_MAJOR 2400 /* major v of latest tgt hw */ -#define XCHAL_HW_MAX_VERSION_MINOR 4 /* minor v of latest tgt hw */ -#define XCHAL_HW_MAX_VERSION 240004 /* latest targeted hw */ - - -/*---------------------------------------------------------------------- - CACHE - ----------------------------------------------------------------------*/ - -#define XCHAL_ICACHE_LINESIZE 8 /* I-cache line size in bytes */ -#define XCHAL_DCACHE_LINESIZE 8 /* D-cache line size in bytes */ -#define XCHAL_ICACHE_LINEWIDTH 3 /* log2(I line size in bytes) */ -#define XCHAL_DCACHE_LINEWIDTH 3 /* log2(D line size in bytes) */ - -#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ -#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ - -#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ -#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ - -#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ -#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ -#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ -#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ -#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ -#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ -#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ -#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ -#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ -#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ - - - - -/**************************************************************************** - Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code - ****************************************************************************/ - - -#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY - -/*---------------------------------------------------------------------- - CACHE - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ - -#define XCHAL_HAVE_AXI 0 /* AXI bus */ -#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ -#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ - -#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ -#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ - -/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ - -/* Number of cache sets in log2(lines per way): */ -#define XCHAL_ICACHE_SETWIDTH 0 -#define XCHAL_DCACHE_SETWIDTH 0 - -/* Cache set associativity (number of ways): */ -#define XCHAL_ICACHE_WAYS 1 -#define XCHAL_DCACHE_WAYS 1 - -/* Cache features: */ -#define XCHAL_ICACHE_LINE_LOCKABLE 0 -#define XCHAL_DCACHE_LINE_LOCKABLE 0 -#define XCHAL_ICACHE_ECC_PARITY 0 -#define XCHAL_DCACHE_ECC_PARITY 0 - -/* Cache access size in bytes (affects operation of SICW instruction): */ -#define XCHAL_ICACHE_ACCESS_SIZE 1 -#define XCHAL_DCACHE_ACCESS_SIZE 1 - -#define XCHAL_DCACHE_BANKS 0 /* number of banks */ - -/* Number of encoded cache attr bits (see for decoded bits): */ -#define XCHAL_CA_BITS 4 - - -/*---------------------------------------------------------------------- - INTERNAL I/D RAM/ROMs and XLMI - ----------------------------------------------------------------------*/ -#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ -#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ -#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ -#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ -#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ -#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ - -/* Instruction RAM 0: */ -#define XCHAL_INSTRAM0_VADDR 0x00000000 /* virtual address */ -#define XCHAL_INSTRAM0_PADDR 0x00000000 /* physical address */ -#define XCHAL_INSTRAM0_SIZE 0x50000 /* size in bytes */ -#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ -#define XCHAL_HAVE_INSTRAM0 1 -#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ - -/* Data RAM 0: */ -#define XCHAL_DATARAM0_VADDR 0x00400000 /* virtual address */ -#define XCHAL_DATARAM0_PADDR 0x00400000 /* physical address */ -#define XCHAL_DATARAM0_SIZE 0x50000 /* size in bytes */ -#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ -#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ -#define XCHAL_HAVE_DATARAM0 1 -#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ - -/* Data RAM 1: */ -#define XCHAL_DATARAM1_VADDR 0x00480000 /* virtual address */ -#define XCHAL_DATARAM1_PADDR 0x00480000 /* physical address */ -#define XCHAL_DATARAM1_SIZE 0x30000 /* size in bytes */ -#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ -#define XCHAL_DATARAM1_BANKS 1 /* number of banks */ -#define XCHAL_HAVE_DATARAM1 1 -#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */ - -#define XCHAL_HAVE_IDMA 0 -#define XCHAL_HAVE_IDMA_TRANSPOSE 0 - -#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ - - -/*---------------------------------------------------------------------- - INTERRUPTS and TIMERS - ----------------------------------------------------------------------*/ - -#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ -#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ -#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ -#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ -#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ -#define XCHAL_NUM_INTERRUPTS 15 /* number of interrupts */ -#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */ -#define XCHAL_NUM_EXTINTERRUPTS 10 /* num of external interrupts */ -#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels - (not including level zero) */ -#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ - /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ - -/* Masks of interrupts at each interrupt level: */ -#define XCHAL_INTLEVEL1_MASK 0x000000FF -#define XCHAL_INTLEVEL2_MASK 0x00000100 -#define XCHAL_INTLEVEL3_MASK 0x00000E00 -#define XCHAL_INTLEVEL4_MASK 0x00001000 -#define XCHAL_INTLEVEL5_MASK 0x00002000 -#define XCHAL_INTLEVEL6_MASK 0x00000000 -#define XCHAL_INTLEVEL7_MASK 0x00004000 - -/* Masks of interrupts at each range 1..n of interrupt levels: */ -#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000000FF -#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x000001FF -#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00000FFF -#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00001FFF -#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00003FFF -#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00003FFF -#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00007FFF - -/* Level of each interrupt: */ -#define XCHAL_INT0_LEVEL 1 -#define XCHAL_INT1_LEVEL 1 -#define XCHAL_INT2_LEVEL 1 -#define XCHAL_INT3_LEVEL 1 -#define XCHAL_INT4_LEVEL 1 -#define XCHAL_INT5_LEVEL 1 -#define XCHAL_INT6_LEVEL 1 -#define XCHAL_INT7_LEVEL 1 -#define XCHAL_INT8_LEVEL 2 -#define XCHAL_INT9_LEVEL 3 -#define XCHAL_INT10_LEVEL 3 -#define XCHAL_INT11_LEVEL 3 -#define XCHAL_INT12_LEVEL 4 -#define XCHAL_INT13_LEVEL 5 -#define XCHAL_INT14_LEVEL 7 -#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ -#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ -#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with - EXCSAVE/EPS/EPC_n, RFI n) */ - -/* Type of each interrupt: */ -#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE -#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER -#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI - -/* Masks of interrupts for each type of interrupt: */ -#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFF8000 -#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 -#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 -#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F -#define XCHAL_INTTYPE_MASK_TIMER 0x00002440 -#define XCHAL_INTTYPE_MASK_NMI 0x00004000 -#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 -#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 -#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 -#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 -#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 - -/* Interrupt numbers assigned to specific interrupt sources: */ -#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ -#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ -#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ -#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED -#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ - -/* Interrupt numbers for levels at which only one interrupt is configured: */ -#define XCHAL_INTLEVEL2_NUM 8 -#define XCHAL_INTLEVEL4_NUM 12 -#define XCHAL_INTLEVEL5_NUM 13 -#define XCHAL_INTLEVEL7_NUM 14 -/* (There are many interrupts each at level(s) 1, 3.) */ - - -/* - * External interrupt mapping. - * These macros describe how Xtensa processor interrupt numbers - * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) - * map to external BInterrupt pins, for those interrupts - * configured as external (level-triggered, edge-triggered, or NMI). - * See the Xtensa processor databook for more details. - */ - -/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ -#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ -#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ -#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ -#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ -#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ -#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ -#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ -#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ -#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ -#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ -/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ -#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ -#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ -#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ -#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ -#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ -#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ -#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ -#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ -#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */ -#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ - - -/*---------------------------------------------------------------------- - EXCEPTIONS and VECTORS - ----------------------------------------------------------------------*/ - -#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture - number: 1 == XEA1 (old) - 2 == XEA2 (new) - 0 == XEAX (extern) or TX */ -#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ -#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ -#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ -#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ -#define XCHAL_HAVE_HALT 0 /* halt architecture option */ -#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ -#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ -#define XCHAL_HAVE_VECTOR_SELECT 0 /* relocatable vectors */ -#define XCHAL_HAVE_VECBASE 0 /* relocatable vectors */ - -#define XCHAL_RESET_VECOFS 0x00000000 -#define XCHAL_RESET_VECTOR_VADDR 0x00000000 -#define XCHAL_RESET_VECTOR_PADDR 0x00000000 -#define XCHAL_USER_VECOFS 0x00000000 -#define XCHAL_USER_VECTOR_VADDR 0x000005C0 -#define XCHAL_USER_VECTOR_PADDR 0x000005C0 -#define XCHAL_KERNEL_VECOFS 0x00000000 -#define XCHAL_KERNEL_VECTOR_VADDR 0x00000584 -#define XCHAL_KERNEL_VECTOR_PADDR 0x00000584 -#define XCHAL_DOUBLEEXC_VECOFS 0x00000000 -#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000005FC -#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000005FC -#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 -#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 -#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 -#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 -#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 -#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 -#define XCHAL_WINDOW_VECTORS_VADDR 0x00000400 -#define XCHAL_WINDOW_VECTORS_PADDR 0x00000400 -#define XCHAL_INTLEVEL2_VECOFS 0x00000000 -#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00000640 -#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000640 -#define XCHAL_INTLEVEL3_VECOFS 0x00000000 -#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x0000067C -#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x0000067C -#define XCHAL_INTLEVEL4_VECOFS 0x00000000 -#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x000006B8 -#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x000006B8 -#define XCHAL_INTLEVEL5_VECOFS 0x00000000 -#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x000006F4 -#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x000006F4 -#define XCHAL_INTLEVEL6_VECOFS 0x00000000 -#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00000730 -#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00000730 -#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS -#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR -#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR -#define XCHAL_NMI_VECOFS 0x00000000 -#define XCHAL_NMI_VECTOR_VADDR 0x0000076C -#define XCHAL_NMI_VECTOR_PADDR 0x0000076C -#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS -#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR -#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR - - -/*---------------------------------------------------------------------- - DEBUG MODULE - ----------------------------------------------------------------------*/ - -/* Misc */ -#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */ -#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ -#define XCHAL_HAVE_DEBUG_JTAG 0 /* JTAG to debug module */ - -/* On-Chip Debug (OCD) */ -#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ -#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ -#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ -#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option (to LX4) */ -#define XCHAL_HAVE_OCD_LS32DDR 0 /* L32DDR/S32DDR (faster OCD) */ - -/* TRAX (in core) */ -#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */ -#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */ -#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ -#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ -#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ - -/* Perf counters */ -#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ - - -/*---------------------------------------------------------------------- - MMU - ----------------------------------------------------------------------*/ - -/* See core-matmap.h header file for more details. */ - -#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ -#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ -#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ -#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ -#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ -#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ -#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ -#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table - [autorefill] and protection) - usable for an MMU-based OS */ - -/* If none of the above last 5 are set, it's a custom TLB configuration. */ - -#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ -#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ -#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ - -/*---------------------------------------------------------------------- - MPU - ----------------------------------------------------------------------*/ -#define XCHAL_HAVE_MPU 0 -#define XCHAL_MPU_ENTRIES 0 - -#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ -#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ -#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ - -#define XCHAL_MPU_ALIGN_BITS 0 -#define XCHAL_MPU_ALIGN 0 - -#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ - - -#endif /* _XTENSA_CORE_CONFIGURATION_H */ - diff --git a/src/platform/haswell/include/arch/xtensa/config/core-isa.h b/src/platform/haswell/include/arch/xtensa/config/core-isa.h deleted file mode 100644 index afcaa8d020a7..000000000000 --- a/src/platform/haswell/include/arch/xtensa/config/core-isa.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ - -#if CONFIG_HASWELL -#include -#elif CONFIG_BROADWELL -#include -#else -#error "No ISA configuration selected" -#endif diff --git a/src/platform/haswell/include/arch/xtensa/config/core-matmap.h b/src/platform/haswell/include/arch/xtensa/config/core-matmap.h deleted file mode 100644 index 5c6fffeb7ddf..000000000000 --- a/src/platform/haswell/include/arch/xtensa/config/core-matmap.h +++ /dev/null @@ -1,314 +0,0 @@ -/* - * xtensa/config/core-matmap.h -- Memory access and translation mapping - * parameters (CHAL) of the Xtensa processor core configuration. - * - * If you are using Xtensa Tools, see (which includes - * this file) for more details. - * - * In the Xtensa processor products released to date, all parameters - * defined in this file are derivable (at least in theory) from - * information contained in the core-isa.h header file. - * In particular, the following core configuration parameters are relevant: - * XCHAL_HAVE_CACHEATTR - * XCHAL_HAVE_MIMIC_CACHEATTR - * XCHAL_HAVE_XLT_CACHEATTR - * XCHAL_HAVE_PTP_MMU - * XCHAL_ITLB_ARF_ENTRIES_LOG2 - * XCHAL_DTLB_ARF_ENTRIES_LOG2 - * XCHAL_DCACHE_IS_WRITEBACK - * XCHAL_ICACHE_SIZE (presence of I-cache) - * XCHAL_DCACHE_SIZE (presence of D-cache) - * XCHAL_HW_VERSION_MAJOR - * XCHAL_HW_VERSION_MINOR - */ - -/* Customer ID=4313; Build=0x5483b; Copyright (c) 1999-2015 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - - -#ifndef XTENSA_CONFIG_CORE_MATMAP_H -#define XTENSA_CONFIG_CORE_MATMAP_H - - -/*---------------------------------------------------------------------- - CACHE (MEMORY ACCESS) ATTRIBUTES - ----------------------------------------------------------------------*/ - - -/* Cache Attribute encodings -- lists of access modes for each cache attribute: */ -#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_CACHED XCHAL_SEP \ - XTHAL_FAM_BYPASS XCHAL_SEP \ - XTHAL_FAM_CACHED XCHAL_SEP \ - XTHAL_FAM_CACHED XCHAL_SEP \ - XTHAL_FAM_CACHED XCHAL_SEP \ - XTHAL_FAM_BYPASS XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION XCHAL_SEP \ - XTHAL_FAM_EXCEPTION -#define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \ - XTHAL_LAM_CACHED XCHAL_SEP \ - XTHAL_LAM_BYPASSG XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_CACHED XCHAL_SEP \ - XTHAL_LAM_CACHED XCHAL_SEP \ - XTHAL_LAM_BYPASSG XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_EXCEPTION XCHAL_SEP \ - XTHAL_LAM_ISOLATE XCHAL_SEP \ - XTHAL_LAM_EXCEPTION -#define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \ - XTHAL_SAM_WRITETHRU XCHAL_SEP \ - XTHAL_SAM_BYPASS XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_WRITEBACK XCHAL_SEP \ - XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \ - XTHAL_SAM_BYPASS XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_EXCEPTION XCHAL_SEP \ - XTHAL_SAM_ISOLATE XCHAL_SEP \ - XTHAL_SAM_EXCEPTION - - -/* - * Specific encoded cache attribute values of general interest. - * If a specific cache mode is not available, the closest available - * one is returned instead (eg. writethru instead of writeback, - * bypass instead of writethru). - */ -#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */ -#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */ -#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */ -#define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */ -#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 /* write-back no-allocate availability */ -#define XCHAL_CA_WRITEBACK_NOALLOC 5 /* cache enabled (write-back no-allocate) mode */ -#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */ -#define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */ - - -/*---------------------------------------------------------------------- - MMU - ----------------------------------------------------------------------*/ - -/* - * General notes on MMU parameters. - * - * Terminology: - * ASID = address-space ID (acts as an "extension" of virtual addresses) - * VPN = virtual page number - * PPN = physical page number - * CA = encoded cache attribute (access modes) - * TLB = translation look-aside buffer (term is stretched somewhat here) - * I = instruction (fetch accesses) - * D = data (load and store accesses) - * way = each TLB (ITLB and DTLB) consists of a number of "ways" - * that simultaneously match the virtual address of an access; - * a TLB successfully translates a virtual address if exactly - * one way matches the vaddr; if none match, it is a miss; - * if multiple match, one gets a "multihit" exception; - * each way can be independently configured in terms of number of - * entries, page sizes, which fields are writable or constant, etc. - * set = group of contiguous ways with exactly identical parameters - * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE - * from the page table and storing it in one of the auto-refill ways; - * if this PTE load also misses, a miss exception is posted for s/w. - * min-wired = a "min-wired" way can be used to map a single (minimum-sized) - * page arbitrarily under program control; it has a single entry, - * is non-auto-refill (some other way(s) must be auto-refill), - * all its fields (VPN, PPN, ASID, CA) are all writable, and it - * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current - * restriction is that this be the only page size it supports). - * - * TLB way entries are virtually indexed. - * TLB ways that support multiple page sizes: - * - must have all writable VPN and PPN fields; - * - can only use one page size at any given time (eg. setup at startup), - * selected by the respective ITLBCFG or DTLBCFG special register, - * whose bits n*4+3 .. n*4 index the list of page sizes for way n - * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); - * this list may be sparse for auto-refill ways because auto-refill - * ways have independent lists of supported page sizes sharing a - * common encoding with PTE entries; the encoding is the index into - * this list; unsupported sizes for a given way are zero in the list; - * selecting unsupported sizes results in undefined hardware behaviour; - * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). - */ - -#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ -#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */ -#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ -#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ -#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */ -#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */ - - -/*** Instruction TLB: ***/ - -#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */ -#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ -#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */ -#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */ - -/* Way set to which each way belongs: */ -#define XCHAL_ITLB_WAY0_SET 0 - -/* Ways sets that are used by hardware auto-refill (ARF): */ -#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */ - -/* Way sets that are "min-wired" (see terminology comment above): */ -#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ - - -/* ITLB way set 0 (group of ways 0 thru 0): */ -#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ -#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ -#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ -#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ -#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ -#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ -#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ -#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ -#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ -#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; - 2^PAGESZ_BITS entries in list, unsupported entries are zero */ -#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ -#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ -#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ -#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ -#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ -#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ -#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ -#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ -/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */ -#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000 -#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000 -#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000 -#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000 -#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000 -#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000 -#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000 -#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000 -/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */ -#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000 -#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000 -#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000 -#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000 -#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000 -#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000 -#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000 -#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000 -/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */ -#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02 -#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02 - - -/*** Data TLB: ***/ - -#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */ -#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ -#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */ -#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */ - -/* Way set to which each way belongs: */ -#define XCHAL_DTLB_WAY0_SET 0 - -/* Ways sets that are used by hardware auto-refill (ARF): */ -#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */ - -/* Way sets that are "min-wired" (see terminology comment above): */ -#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ - - -/* DTLB way set 0 (group of ways 0 thru 0): */ -#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ -#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ -#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ -#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ -#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ -#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ -#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ -#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ -#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ -#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; - 2^PAGESZ_BITS entries in list, unsupported entries are zero */ -#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ -#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ -#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ -#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ -#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ -#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ -#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ -#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ -/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */ -#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000 -#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000 -#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000 -#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000 -#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000 -#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000 -#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000 -#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000 -/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */ -#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000 -#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000 -#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000 -#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000 -#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000 -#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000 -#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000 -#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000 -/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */ -#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 -#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 - - - - -#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ - diff --git a/src/platform/haswell/include/arch/xtensa/config/defs.h b/src/platform/haswell/include/arch/xtensa/config/defs.h deleted file mode 100644 index b695e595135c..000000000000 --- a/src/platform/haswell/include/arch/xtensa/config/defs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Definitions for Xtensa instructions, types, and protos. */ - -/* Customer ID=4313; Build=0x5483b; Copyright (c) 2003-2004 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -/* NOTE: This file exists only for backward compatibility with T1050 - and earlier Xtensa releases. It includes only a subset of the - available header files. */ - -#ifndef _XTENSA_BASE_HEADER -#define _XTENSA_BASE_HEADER - -#ifdef __XTENSA__ - -#include -#include -#include - -#endif /* __XTENSA__ */ -#endif /* !_XTENSA_BASE_HEADER */ diff --git a/src/platform/haswell/include/arch/xtensa/config/specreg.h b/src/platform/haswell/include/arch/xtensa/config/specreg.h deleted file mode 100644 index 89bfe163eeb0..000000000000 --- a/src/platform/haswell/include/arch/xtensa/config/specreg.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Xtensa Special Register symbolic names - */ - -/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ - -/* Customer ID=4313; Build=0x5483b; Copyright (c) 1998-2002 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#ifndef XTENSA_SPECREG_H -#define XTENSA_SPECREG_H - -/* Include these special register bitfield definitions, for historical reasons: */ -#include - - -/* Special registers: */ -#define LBEG 0 -#define LEND 1 -#define LCOUNT 2 -#define SAR 3 -#define BR 4 -#define SCOMPARE1 12 -#define WINDOWBASE 72 -#define WINDOWSTART 73 -#define IBREAKENABLE 96 -#define ATOMCTL 99 -#define DDR 104 -#define IBREAKA_0 128 -#define IBREAKA_1 129 -#define DBREAKA_0 144 -#define DBREAKA_1 145 -#define DBREAKC_0 160 -#define DBREAKC_1 161 -#define EPC_1 177 -#define EPC_2 178 -#define EPC_3 179 -#define EPC_4 180 -#define EPC_5 181 -#define EPC_6 182 -#define EPC_7 183 -#define DEPC 192 -#define EPS_2 194 -#define EPS_3 195 -#define EPS_4 196 -#define EPS_5 197 -#define EPS_6 198 -#define EPS_7 199 -#define EXCSAVE_1 209 -#define EXCSAVE_2 210 -#define EXCSAVE_3 211 -#define EXCSAVE_4 212 -#define EXCSAVE_5 213 -#define EXCSAVE_6 214 -#define EXCSAVE_7 215 -#define CPENABLE 224 -#define INTERRUPT 226 -#define INTENABLE 228 -#define PS 230 -#define VECBASE 231 -#define EXCCAUSE 232 -#define DEBUGCAUSE 233 -#define CCOUNT 234 -#define PRID 235 -#define ICOUNT 236 -#define ICOUNTLEVEL 237 -#define EXCVADDR 238 -#define CCOMPARE_0 240 -#define CCOMPARE_1 241 -#define CCOMPARE_2 242 -#define MISC_REG_0 244 -#define MISC_REG_1 245 - -/* Special cases (bases of special register series): */ -#define IBREAKA 128 -#define DBREAKA 144 -#define DBREAKC 160 -#define EPC 176 -#define EPS 192 -#define EXCSAVE 208 -#define CCOMPARE 240 - -/* Special names for read-only and write-only interrupt registers: */ -#define INTREAD 226 -#define INTSET 226 -#define INTCLEAR 227 - -#endif /* XTENSA_SPECREG_H */ - diff --git a/src/platform/haswell/include/arch/xtensa/config/system.h b/src/platform/haswell/include/arch/xtensa/config/system.h deleted file mode 100644 index 147346a0c691..000000000000 --- a/src/platform/haswell/include/arch/xtensa/config/system.h +++ /dev/null @@ -1,272 +0,0 @@ -/* - * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration - * - * NOTE: The location and contents of this file are highly subject to change. - * - * Source for configuration-independent binaries (which link in a - * configuration-specific HAL library) must NEVER include this file. - * The HAL itself has historically included this file in some instances, - * but this is not appropriate either, because the HAL is meant to be - * core-specific but system independent. - */ - -/* Customer ID=4313; Build=0x5483b; Copyright (c) 2000-2010 Tensilica Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - - -#ifndef XTENSA_CONFIG_SYSTEM_H -#define XTENSA_CONFIG_SYSTEM_H - -/*#include */ - - - -/*---------------------------------------------------------------------- - CONFIGURED SOFTWARE OPTIONS - ----------------------------------------------------------------------*/ - -#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ -#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ - -#define XSHAL_ABI XTHAL_ABI_CALL0 /* (sw-only option, selected ABI) */ -/* The above maps to one of the following constants: */ -#define XTHAL_ABI_WINDOWED 0 -#define XTHAL_ABI_CALL0 1 -/* Alternatives: */ -/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */ -/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */ - -#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */ -/* The above maps to one of the following constants: */ -#define XTHAL_CLIB_NEWLIB 0 -#define XTHAL_CLIB_UCLIBC 1 -#define XTHAL_CLIB_XCLIB 2 -/* Alternatives: */ -/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */ -/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */ -/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */ - -#define XSHAL_USE_FLOATING_POINT 1 - -#define XSHAL_FLOATING_POINT_ABI 0 - -/*---------------------------------------------------------------------- - DEVICE ADDRESSES - ----------------------------------------------------------------------*/ - -/* - * Strange place to find these, but the configuration GUI - * allows moving these around to account for various core - * configurations. Specific boards (and their BSP software) - * will have specific meanings for these components. - */ - -/* I/O Block areas: */ -#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 -#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 -#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 - -#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000 -#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000 -#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 - -/* System ROM: */ -#define XSHAL_ROM_VADDR 0x50000000 -#define XSHAL_ROM_PADDR 0x50000000 -#define XSHAL_ROM_SIZE 0x01000000 -/* Largest available area (free of vectors): */ -#define XSHAL_ROM_AVAIL_VADDR 0x50000300 -#define XSHAL_ROM_AVAIL_VSIZE 0x00FFFD00 - -/* System RAM: */ -#define XSHAL_RAM_VADDR 0x60000000 -#define XSHAL_RAM_PADDR 0x60000000 -#define XSHAL_RAM_VSIZE 0x04000000 -#define XSHAL_RAM_PSIZE 0x04000000 -#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE -/* Largest available area (free of vectors): */ -#define XSHAL_RAM_AVAIL_VADDR 0x60000400 -#define XSHAL_RAM_AVAIL_VSIZE 0x03FFFC00 - -/* - * Shadow system RAM (same device as system RAM, at different address). - * (Emulation boards need this for the SONIC Ethernet driver - * when data caches are configured for writeback mode.) - * NOTE: on full MMU configs, this points to the BYPASS virtual address - * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual - * addresses are viewed through the BYPASS static map rather than - * the CACHED static map. - */ -#define XSHAL_RAM_BYPASS_VADDR 0xA0000000 -#define XSHAL_RAM_BYPASS_PADDR 0xA0000000 -#define XSHAL_RAM_BYPASS_PSIZE 0x04000000 - -/* Alternate system RAM (different device than system RAM): */ -/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/ -/*#define XSHAL_ALTRAM_SIZE ...not configured...*/ - -/* Some available location in which to place devices in a simulation (eg. XTMP): */ -#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000 -#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000 -#define XSHAL_SIMIO_PADDR 0xC0000000 -#define XSHAL_SIMIO_SIZE 0x20000000 - - -/*---------------------------------------------------------------------- - * For use by reference testbench exit and diagnostic routines. - */ -#define XSHAL_MAGIC_EXIT 0x0 - -/*---------------------------------------------------------------------- - * DEVICE-ADDRESS DEPENDENT... - * - * Values written to CACHEATTR special register (or its equivalent) - * to enable and disable caches in various modes. - *----------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------- - BACKWARD COMPATIBILITY ... - ----------------------------------------------------------------------*/ - -/* - * NOTE: the following two macros are DEPRECATED. Use the latter - * board-specific macros instead, which are specially tuned for the - * particular target environments' memory maps. - */ -#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ -#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ - -/*---------------------------------------------------------------------- - GENERIC - ----------------------------------------------------------------------*/ - -/* For the following, a 512MB region is used if it contains a system (PIF) RAM, - * system (PIF) ROM, local memory, or XLMI. */ - -/* These set any unused 512MB region to cache-BYPASS attribute: */ -#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22224442 /* enable caches in write-back mode */ -#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */ -#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */ -#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ -#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ - -/* These set any unused 512MB region to ILLEGAL attribute: */ -#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF444F /* enable caches in write-back mode */ -#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */ -#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */ -#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */ -#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ - -/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch - * NULL-pointer dereference bugs; all other unused 512MB regions are set - * to cache-BYPASS attribute: */ -#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222444F /* enable caches in write-back mode */ -#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */ -#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */ -#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */ -#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ - -/*---------------------------------------------------------------------- - ISS (Instruction Set Simulator) SPECIFIC ... - ----------------------------------------------------------------------*/ - -/* For now, ISS defaults to the TRAPNULL settings: */ -#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK -#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC -#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU -#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS -#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK - -#define XSHAL_ISS_PIPE_REGIONS 0 -#define XSHAL_ISS_SDRAM_REGIONS 0 - - -/*---------------------------------------------------------------------- - XT2000 BOARD SPECIFIC ... - ----------------------------------------------------------------------*/ - -/* For the following, a 512MB region is used if it contains any system RAM, - * system ROM, local memory, XLMI, or other XT2000 board device or memory. - * Regions containing devices are forced to cache-BYPASS mode regardless - * of whether the macro is _WRITEBACK vs. _BYPASS etc. */ - -/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ -#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22444F /* enable caches in write-back mode */ -#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */ -#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */ -#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ -#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ - -#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ -#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */ - - -/*---------------------------------------------------------------------- - VECTOR INFO AND SIZES - ----------------------------------------------------------------------*/ - -#define XSHAL_VECTORS_PACKED 0 -#define XSHAL_STATIC_VECTOR_SELECT 0 -#define XSHAL_RESET_VECTOR_VADDR 0x50000000 -#define XSHAL_RESET_VECTOR_PADDR 0x50000000 - -/* - * Sizes allocated to vectors by the system (memory map) configuration. - * These sizes are constrained by core configuration (eg. one vector's - * code cannot overflow into another vector) but are dependent on the - * system or board (or LSP) memory map configuration. - * - * Whether or not each vector happens to be in a system ROM is also - * a system configuration matter, sometimes useful, included here also: - */ -#define XSHAL_RESET_VECTOR_SIZE 0x00000300 -#define XSHAL_RESET_VECTOR_ISROM 1 -#define XSHAL_USER_VECTOR_SIZE 0x00000038 -#define XSHAL_USER_VECTOR_ISROM 0 -#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ -#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ -#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038 -#define XSHAL_KERNEL_VECTOR_ISROM 0 -#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ -#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ -#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040 -#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0 -#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 -#define XSHAL_WINDOW_VECTORS_ISROM 0 -#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL2_VECTOR_ISROM 0 -#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL3_VECTOR_ISROM 0 -#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL4_VECTOR_ISROM 0 -#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL5_VECTOR_ISROM 0 -#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038 -#define XSHAL_INTLEVEL6_VECTOR_ISROM 0 -#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE -#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM -#define XSHAL_NMI_VECTOR_SIZE 0x00000038 -#define XSHAL_NMI_VECTOR_ISROM 0 -#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE - - -#endif /*XTENSA_CONFIG_SYSTEM_H*/ - diff --git a/src/platform/haswell/include/arch/xtensa/config/tie-asm.h b/src/platform/haswell/include/arch/xtensa/config/tie-asm.h deleted file mode 100644 index d7140f87b71b..000000000000 --- a/src/platform/haswell/include/arch/xtensa/config/tie-asm.h +++ /dev/null @@ -1,240 +0,0 @@ -/* - * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE - * - * NOTE: This header file is not meant to be included directly. - */ - -/* This header file contains assembly-language definitions (assembly - macros, etc.) for this specific Xtensa processor's TIE extensions - and options. It is customized to this Xtensa processor configuration. - - Copyright (c) 1999-2015 Cadence Design Systems Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#ifndef _XTENSA_CORE_TIE_ASM_H -#define _XTENSA_CORE_TIE_ASM_H - -/* Selection parameter values for save-area save/restore macros: */ -/* Option vs. TIE: */ -#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ -#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ -#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ -/* Whether used automatically by compiler: */ -#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ -#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ -#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ -/* ABI handling across function calls: */ -#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ -#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ -#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ -#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ -/* Misc */ -#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ -#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ - | ((ccuse) & XTHAL_SAS_ANYCC) \ - | ((abi) & XTHAL_SAS_ANYABI) ) - - - /* - * Macro to store all non-coprocessor (extra) custom TIE and optional state - * (not including zero-overhead loop registers). - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 4 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters: - * continue If macro invoked as part of a larger store sequence, set to 1 - * if this is not the first in the sequence. Defaults to 0. - * ofs Offset from start of larger sequence (from value of first ptr - * in sequence) at which to store. Defaults to next available space - * (or 0 if is 0). - * select Select what category(ies) of registers to store, as a bitmask - * (see XTHAL_SAS_xxx constants). Defaults to all registers. - * alloc Select what category(ies) of registers to allocate; if any - * category is selected here that is not in , space for - * the corresponding registers is skipped without doing any load. - */ - .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Optional caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 1016, 4, 4 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wsr.BR \at1 // boolean option - l32i \at1, \ptr, .Lxchal_ofs_+4 - wsr.SCOMPARE1 \at1 // conditional store option - .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 - .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 1016, 4, 4 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 - .endif - .endm // xchal_ncp_load - - -#define XCHAL_NCP_NUM_ATMPS 1 - - /* - * Macro to store the state of TIE coprocessor AudioEngineLX. - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 8 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters are the same as for xchal_ncp_store. - */ -#define xchal_cp_AudioEngineLX_store xchal_cp1_store - .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Custom caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 0, 8, 8 - rur.AE_OVF_SAR \at1 // ureg 240 - s32i \at1, \ptr, .Lxchal_ofs_+0 - rur.AE_BITHEAD \at1 // ureg 241 - s32i \at1, \ptr, .Lxchal_ofs_+4 - rur.AE_TS_FTS_BU_BP \at1 // ureg 242 - s32i \at1, \ptr, .Lxchal_ofs_+8 - rur.AE_SD_NO \at1 // ureg 243 - s32i \at1, \ptr, .Lxchal_ofs_+12 - ae_sp24x2s.i aep0, \ptr, .Lxchal_ofs_+16 - ae_sp24x2s.i aep1, \ptr, .Lxchal_ofs_+24 - ae_sp24x2s.i aep2, \ptr, .Lxchal_ofs_+32 - ae_sp24x2s.i aep3, \ptr, .Lxchal_ofs_+40 - ae_sp24x2s.i aep4, \ptr, .Lxchal_ofs_+48 - ae_sp24x2s.i aep5, \ptr, .Lxchal_ofs_+56 - addi \ptr, \ptr, 64 - ae_sp24x2s.i aep6, \ptr, .Lxchal_ofs_+0 - ae_sp24x2s.i aep7, \ptr, .Lxchal_ofs_+8 - ae_sq56s.i aeq0, \ptr, .Lxchal_ofs_+16 - ae_sq56s.i aeq1, \ptr, .Lxchal_ofs_+24 - ae_sq56s.i aeq2, \ptr, .Lxchal_ofs_+32 - ae_sq56s.i aeq3, \ptr, .Lxchal_ofs_+40 - .set .Lxchal_pofs_, .Lxchal_pofs_ + 64 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 48 - .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 0, 8, 8 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 112 - .endif - .endm // xchal_cp1_store - - /* - * Macro to load the state of TIE coprocessor AudioEngineLX. - * Required parameters: - * ptr Save area pointer address register (clobbered) - * (register must contain a 8 byte aligned address). - * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS - * registers are clobbered, the remaining are unused). - * Optional parameters are the same as for xchal_ncp_load. - */ -#define xchal_cp_AudioEngineLX_load xchal_cp1_load - .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 - xchal_sa_start \continue, \ofs - // Custom caller-saved registers not used by default by the compiler: - .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) - xchal_sa_align \ptr, 0, 0, 8, 8 - l32i \at1, \ptr, .Lxchal_ofs_+0 - wur.AE_OVF_SAR \at1 // ureg 240 - l32i \at1, \ptr, .Lxchal_ofs_+4 - wur.AE_BITHEAD \at1 // ureg 241 - l32i \at1, \ptr, .Lxchal_ofs_+8 - wur.AE_TS_FTS_BU_BP \at1 // ureg 242 - l32i \at1, \ptr, .Lxchal_ofs_+12 - wur.AE_SD_NO \at1 // ureg 243 - ae_lp24x2.i aep0, \ptr, .Lxchal_ofs_+16 - ae_lp24x2.i aep1, \ptr, .Lxchal_ofs_+24 - ae_lp24x2.i aep2, \ptr, .Lxchal_ofs_+32 - ae_lp24x2.i aep3, \ptr, .Lxchal_ofs_+40 - ae_lp24x2.i aep4, \ptr, .Lxchal_ofs_+48 - ae_lp24x2.i aep5, \ptr, .Lxchal_ofs_+56 - addi \ptr, \ptr, 64 - ae_lp24x2.i aep6, \ptr, .Lxchal_ofs_+0 - ae_lp24x2.i aep7, \ptr, .Lxchal_ofs_+8 - addi \ptr, \ptr, 16 - ae_lq56.i aeq0, \ptr, .Lxchal_ofs_+0 - ae_lq56.i aeq1, \ptr, .Lxchal_ofs_+8 - ae_lq56.i aeq2, \ptr, .Lxchal_ofs_+16 - ae_lq56.i aeq3, \ptr, .Lxchal_ofs_+24 - .set .Lxchal_pofs_, .Lxchal_pofs_ + 80 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 - .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 - xchal_sa_align \ptr, 0, 0, 8, 8 - .set .Lxchal_ofs_, .Lxchal_ofs_ + 112 - .endif - .endm // xchal_cp1_load - -#define XCHAL_CP1_NUM_ATMPS 1 -#define XCHAL_SA_NUM_ATMPS 1 - - /* Empty macros for unconfigured coprocessors: */ - .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm - .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm - -#endif /*_XTENSA_CORE_TIE_ASM_H*/ - diff --git a/src/platform/haswell/include/arch/xtensa/config/tie.h b/src/platform/haswell/include/arch/xtensa/config/tie.h deleted file mode 100644 index 3c638122930a..000000000000 --- a/src/platform/haswell/include/arch/xtensa/config/tie.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration - * - * NOTE: This header file is not meant to be included directly. - */ - -/* This header file describes this specific Xtensa processor's TIE extensions - that extend basic Xtensa core functionality. It is customized to this - Xtensa processor configuration. - - Copyright (c) 1999-2015 Cadence Design Systems Inc. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice shall be included - in all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#ifndef _XTENSA_CORE_TIE_H -#define _XTENSA_CORE_TIE_H - -#define XCHAL_CP_NUM 1 /* number of coprocessors */ -#define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */ -#define XCHAL_CP_MASK 0x02 /* bitmask of all CPs by ID */ -#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ - -/* Basic parameters of each coprocessor: */ -#define XCHAL_CP1_NAME "AudioEngineLX" -#define XCHAL_CP1_IDENT AudioEngineLX -#define XCHAL_CP1_SA_SIZE 112 /* size of state save area */ -#define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */ -#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ - -/* Filler info for unassigned coprocessors, to simplify arrays etc: */ -#define XCHAL_CP0_SA_SIZE 0 -#define XCHAL_CP0_SA_ALIGN 1 -#define XCHAL_CP2_SA_SIZE 0 -#define XCHAL_CP2_SA_ALIGN 1 -#define XCHAL_CP3_SA_SIZE 0 -#define XCHAL_CP3_SA_ALIGN 1 -#define XCHAL_CP4_SA_SIZE 0 -#define XCHAL_CP4_SA_ALIGN 1 -#define XCHAL_CP5_SA_SIZE 0 -#define XCHAL_CP5_SA_ALIGN 1 -#define XCHAL_CP6_SA_SIZE 0 -#define XCHAL_CP6_SA_ALIGN 1 -#define XCHAL_CP7_SA_SIZE 0 -#define XCHAL_CP7_SA_ALIGN 1 - -/* Save area for non-coprocessor optional and custom (TIE) state: */ -#define XCHAL_NCP_SA_SIZE 8 -#define XCHAL_NCP_SA_ALIGN 4 - -/* Total save area for optional and custom state (NCP + CPn): */ -#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */ -#define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */ - -/* - * Detailed contents of save areas. - * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) - * before expanding the XCHAL_xxx_SA_LIST() macros. - * - * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, - * dbnum,base,regnum,bitsz,gapsz,reset,x...) - * - * s = passed from XCHAL_*_LIST(s), eg. to select how to expand - * ccused = set if used by compiler without special options or code - * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) - * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) - * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) - * name = lowercase reg name (no quotes) - * galign = group byte alignment (power of 2) (galign >= align) - * align = register byte alignment (power of 2) - * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) - * (not including any pad bytes required to galign this or next reg) - * dbnum = unique target number f/debug (see ) - * base = reg shortname w/o index (or sr=special, ur=TIE user reg) - * regnum = reg index in regfile, or special/TIE-user reg number - * bitsz = number of significant bits (regfile width, or ur/sr mask bits) - * gapsz = intervening bits, if bitsz bits not stored contiguously - * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) - * reset = register reset value (or 0 if undefined at reset) - * x = reserved for future use (0 until then) - * - * To filter out certain registers, e.g. to expand only the non-global - * registers used by the compiler, you can do something like this: - * - * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) - * #define SELCC0(p...) - * #define SELCC1(abikind,p...) SELAK##abikind(p) - * #define SELAK0(p...) REG(p) - * #define SELAK1(p...) REG(p) - * #define SELAK2(p...) - * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ - * ...what you want to expand... - */ - -#define XCHAL_NCP_SA_NUM 2 -#define XCHAL_NCP_SA_LIST(s) \ - XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ - XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) - -#define XCHAL_CP0_SA_NUM 0 -#define XCHAL_CP0_SA_LIST(s) /* empty */ - -#define XCHAL_CP1_SA_NUM 16 -#define XCHAL_CP1_SA_LIST(s) \ - XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \ - XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \ - XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0) - -#define XCHAL_CP2_SA_NUM 0 -#define XCHAL_CP2_SA_LIST(s) /* empty */ - -#define XCHAL_CP3_SA_NUM 0 -#define XCHAL_CP3_SA_LIST(s) /* empty */ - -#define XCHAL_CP4_SA_NUM 0 -#define XCHAL_CP4_SA_LIST(s) /* empty */ - -#define XCHAL_CP5_SA_NUM 0 -#define XCHAL_CP5_SA_LIST(s) /* empty */ - -#define XCHAL_CP6_SA_NUM 0 -#define XCHAL_CP6_SA_LIST(s) /* empty */ - -#define XCHAL_CP7_SA_NUM 0 -#define XCHAL_CP7_SA_LIST(s) /* empty */ - -/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ -#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8 -/* Byte length of instruction from its first byte, per FLIX. */ -#define XCHAL_BYTE0_FORMAT_LENGTHS \ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8,\ - 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8 - -#endif /*_XTENSA_CORE_TIE_H*/ - diff --git a/src/platform/haswell/include/platform/drivers/dw-dma.h b/src/platform/haswell/include/platform/drivers/dw-dma.h deleted file mode 100644 index 5789924f390d..000000000000 --- a/src/platform/haswell/include/platform/drivers/dw-dma.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -#ifdef __SOF_DRIVERS_DW_DMA_H__ - -#ifndef __PLATFORM_DRIVERS_DW_DMA_H__ -#define __PLATFORM_DRIVERS_DW_DMA_H__ - -#include -#include - -struct dma; -struct dma_chan_data; - -/* number of supported DW-DMACs (DMAC0 is not related with SSP)*/ -#define PLATFORM_NUM_DW_DMACS 1 - -/* index of the first DW-DMAC in the array (DMAC0 is not related with SSP)*/ -#define PLATFORM_DW_DMA_INDEX 1 - -/* DMA treats PHY addresses as host address unless within DSP region */ -#define PLATFORM_DW_DMA_HOST_MASK 0xFFF00000 - -/* CTL_HI */ -#define DW_CTLH_DONE(x) SET_BIT(12, x) -#define DW_CTLH_BLOCK_TS_MASK MASK(11, 0) - -/* CFG_LO */ -#define DW_CFGL_CLASS(x) SET_BITS(7, 5, x) - -/* CFG_HI */ -#define DW_CFGH_DST_PER(x) SET_BITS(14, 11, x) -#define DW_CFGH_SRC_PER(x) SET_BITS(10, 7, x) -#define DW_CFGH_DST(x) DW_CFGH_DST_PER(x) -#define DW_CFGH_SRC(x) DW_CFGH_SRC_PER(x) - -/* default initial setup register values */ -#define DW_CFG_LOW_DEF 0x0 -#define DW_CFG_HIGH_DEF 0x4 - -#define platform_dw_dma_set_class(chan, lli, class) \ - (chan->cfg_lo |= DW_CFGL_CLASS(class)) - -#define platform_dw_dma_set_transfer_size(chan, lli, size) \ - (lli->ctrl_hi |= ((size / (1 << ((lli->ctrl_lo & \ - DW_CTLL_SRC_WIDTH_MASK) >> DW_CTLL_SRC_WIDTH_SHIFT))) & \ - DW_CTLH_BLOCK_TS_MASK)) - -static inline void platform_dw_dma_llp_config(struct dma *dma, - struct dma_chan_data *chan, - uint32_t config) { } - -static inline void platform_dw_dma_llp_enable(struct dma *dma, - struct dma_chan_data *chan) { } - -static inline void platform_dw_dma_llp_disable(struct dma *dma, - struct dma_chan_data *chan) { } - -static inline void platform_dw_dma_llp_read(struct dma *dma, - struct dma_chan_data *chan, - uint32_t *llp_l, - uint32_t *llp_u) { } - -#endif /* __PLATFORM_DRIVERS_DW_DMA_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/drivers/dw-dma.h" - -#endif /* __SOF_DRIVERS_DW_DMA_H__ */ diff --git a/src/platform/haswell/include/platform/drivers/idc.h b/src/platform/haswell/include/platform/drivers/idc.h deleted file mode 100644 index 70a264d2dbc5..000000000000 --- a/src/platform/haswell/include/platform/drivers/idc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2018 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -#ifdef __SOF_DRIVERS_IDC_H__ - -#ifndef __PLATFORM_DRIVERS_IDC_H__ -#define __PLATFORM_DRIVERS_IDC_H__ - -#include - -struct idc_msg; - -static inline int idc_send_msg(struct idc_msg *msg, - uint32_t mode) { return 0; } - -static inline int idc_init(void) { return 0; } - -#endif /* __PLATFORM_DRIVERS_IDC_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/drivers/idc.h" - -#endif /* __SOF_DRIVERS_IDC_H__ */ diff --git a/src/platform/haswell/include/platform/drivers/interrupt.h b/src/platform/haswell/include/platform/drivers/interrupt.h deleted file mode 100644 index 5929da2f789a..000000000000 --- a/src/platform/haswell/include/platform/drivers/interrupt.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - */ - -#ifdef __SOF_DRIVERS_INTERRUPT_H__ - -#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__ -#define __PLATFORM_DRIVERS_INTERRUPT_H__ - -#include - -#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS -#define PLATFORM_IRQ_FIRST_CHILD PLATFORM_IRQ_HW_NUM -#define PLATFORM_IRQ_CHILDREN 0 - -/* IRQ numbers */ -#if CONFIG_XT_INTERRUPT_LEVEL_1 - -#define IRQ_NUM_EXT_SSP0 0 /* Level 1 */ -#define IRQ_NUM_EXT_SSP1 1 /* Level 1 */ -#define IRQ_NUM_EXT_OBFF 2 /* Level 1 */ -#define IRQ_NUM_EXT_IA 4 /* Level 1 */ -#define IRQ_NUM_TIMER1 6 /* Level 1 */ -#define IRQ_NUM_SOFTWARE1 7 /* Level 1 */ - -#define IRQ_MASK_EXT_SSP0 BIT(IRQ_NUM_EXT_SSP0) -#define IRQ_MASK_EXT_SSP1 BIT(IRQ_NUM_EXT_SSP1) -#define IRQ_MASK_EXT_OBFF BIT(IRQ_NUM_EXT_OBFF) -#define IRQ_MASK_EXT_IA BIT(IRQ_NUM_EXT_IA) -#define IRQ_MASK_TIMER1 BIT(IRQ_NUM_TIMER1) -#define IRQ_MASK_SOFTWARE1 BIT(IRQ_NUM_SOFTWARE1) - -#endif - -#if CONFIG_XT_INTERRUPT_LEVEL_2 - -#define IRQ_NUM_EXT_DMAC0 8 /* Level 2 */ - -#define IRQ_MASK_EXT_DMAC0 BIT(IRQ_NUM_EXT_DMAC0) - -#endif - -#if CONFIG_XT_INTERRUPT_LEVEL_3 - -#define IRQ_NUM_EXT_DMAC1 9 /* Level 3 */ -#define IRQ_NUM_TIMER2 10 /* Level 3 */ -#define IRQ_NUM_SOFTWARE2 11 /* Level 3 */ - -#define IRQ_MASK_EXT_DMAC1 BIT(IRQ_NUM_EXT_DMAC1) -#define IRQ_MASK_TIMER2 BIT(IRQ_NUM_TIMER2) -#define IRQ_MASK_SOFTWARE2 BIT(IRQ_NUM_SOFTWARE2) - -#endif - -#if CONFIG_XT_INTERRUPT_LEVEL_4 - -#define IRQ_NUM_EXT_PARITY 12 /* Level 4 */ - -#define IRQ_MASK_EXT_PARITY BIT(IRQ_NUM_EXT_PARITY) - -#endif - -#if CONFIG_XT_INTERRUPT_LEVEL_5 - -#define IRQ_NUM_TIMER3 13 /* Level 5 */ - -#define IRQ_MASK_TIMER3 BIT(IRQ_NUM_TIMER3) - -#endif - -#define IRQ_NUM_NMI 14 /* Level 7 */ - -#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/drivers/interrupt.h" - -#endif /* __SOF_DRIVERS_INTERRUPT_H__ */ diff --git a/src/platform/haswell/include/platform/lib/clk.h b/src/platform/haswell/include/platform/lib/clk.h deleted file mode 100644 index beb12c7d0415..000000000000 --- a/src/platform/haswell/include/platform/lib/clk.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - */ - -#ifdef __SOF_LIB_CLK_H__ - -#ifndef __PLATFORM_LIB_CLK_H__ -#define __PLATFORM_LIB_CLK_H__ - -#include -#include -#include - -struct sof; - -#define CLK_CPU(x) (x) -#define CLK_SSP 1 - -#define CPU_DEFAULT_IDX 3 -#define SSP_DEFAULT_IDX 0 - -#define CLK_DEFAULT_CPU_HZ 320000000 -#define CLK_MAX_CPU_HZ 320000000 - -#define NUM_CLOCKS 2 - -#define NUM_CPU_FREQ 6 -#define NUM_SSP_FREQ 1 - -void platform_clock_init(struct sof *sof); - -#endif /* __PLATFORM_LIB_CLK_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/clk.h" - -#endif /* __SOF_LIB_CLK_H__ */ diff --git a/src/platform/haswell/include/platform/lib/cpu.h b/src/platform/haswell/include/platform/lib/cpu.h deleted file mode 100644 index 2c7124c5b0dd..000000000000 --- a/src/platform/haswell/include/platform/lib/cpu.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -/** - * \file - * \brief DSP core parameters. - */ - -#ifdef __SOF_LIB_CPU_H__ - -#ifndef __PLATFORM_LIB_CPU_H__ -#define __PLATFORM_LIB_CPU_H__ - -/** \brief Id of primary DSP core */ -#define PLATFORM_PRIMARY_CORE_ID 0 - -#endif /* __PLATFORM_LIB_CPU_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/cpu.h" - -#endif /* __SOF_LIB_CPU_H__ */ diff --git a/src/platform/haswell/include/platform/lib/dai.h b/src/platform/haswell/include/platform/lib/dai.h deleted file mode 100644 index 0cfdf919d1bb..000000000000 --- a/src/platform/haswell/include/platform/lib/dai.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2018 Intel Corporation. All rights reserved. - * - * Author: Marcin Maka - */ - -#ifdef __SOF_LIB_DAI_H__ - -#ifndef __PLATFORM_LIB_DAI_H__ -#define __PLATFORM_LIB_DAI_H__ - -#endif /* __PLATFORM_LIB_DAI_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/dai.h" - -#endif /* __SOF_LIB_DAI_H__ */ diff --git a/src/platform/haswell/include/platform/lib/dma.h b/src/platform/haswell/include/platform/lib/dma.h deleted file mode 100644 index 434c397d573e..000000000000 --- a/src/platform/haswell/include/platform/lib/dma.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - */ - -#ifdef __SOF_LIB_DMA_H__ - -#ifndef __PLATFORM_LIB_DMA_H__ -#define __PLATFORM_LIB_DMA_H__ - -#define PLATFORM_NUM_DMACS 2 - -/* max number of supported DMA channels */ -#define PLATFORM_MAX_DMA_CHAN 8 - -#define DMA_ID_DMAC0 0 -#define DMA_ID_DMAC1 1 - -#define DMA_HANDSHAKE_SSP1_RX 0 -#define DMA_HANDSHAKE_SSP1_TX 1 -#define DMA_HANDSHAKE_SSP0_RX 2 -#define DMA_HANDSHAKE_SSP0_TX 3 -#define DMA_HANDSHAKE_OBFF_0 4 -#define DMA_HANDSHAKE_OBFF_1 5 -#define DMA_HANDSHAKE_OBFF_2 6 -#define DMA_HANDSHAKE_OBFF_3 7 -#define DMA_HANDSHAKE_OBFF_4 8 -#define DMA_HANDSHAKE_OBFF_5 9 -#define DMA_HANDSHAKE_OBFF_6 10 -#define DMA_HANDSHAKE_OBFF_7 11 -#define DMA_HANDSHAKE_OBFF_8 12 -#define DMA_HANDSHAKE_OBFF_9 13 -#define DMA_HANDSHAKE_OBFF_10 14 -#define DMA_HANDSHAKE_OBFF_11 15 - -#define dma_chan_irq(dma, chan) dma_irq(dma) -#define dma_chan_irq_name(dma, chan) dma_irq_name(dma) - -#endif /* __PLATFORM_LIB_DMA_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/dma.h" - -#endif /* __SOF_LIB_DMA_H__ */ diff --git a/src/platform/haswell/include/platform/lib/mailbox.h b/src/platform/haswell/include/platform/lib/mailbox.h deleted file mode 100644 index a06bdef98176..000000000000 --- a/src/platform/haswell/include/platform/lib/mailbox.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - */ - -#ifdef __SOF_LIB_MAILBOX_H__ - -#ifndef __PLATFORM_LIB_MAILBOX_H__ -#define __PLATFORM_LIB_MAILBOX_H__ - -#include - -#include -#include - -#if CONFIG_BROADWELL -#define MAILBOX_HOST_OFFSET 0x0009E000 -#else -#define MAILBOX_HOST_OFFSET 0x0007E000 -#endif - -#define MAILBOX_DSPBOX_OFFSET 0x0 -#define MAILBOX_DSPBOX_SIZE 0x400 -#define MAILBOX_DSPBOX_BASE \ - (MAILBOX_BASE + MAILBOX_DSPBOX_OFFSET) - -#define MAILBOX_HOSTBOX_OFFSET MAILBOX_DSPBOX_SIZE -#define MAILBOX_HOSTBOX_SIZE 0x400 -#define MAILBOX_HOSTBOX_BASE \ - (MAILBOX_BASE + MAILBOX_HOSTBOX_OFFSET) - -#define MAILBOX_EXCEPTION_OFFSET \ - (MAILBOX_HOSTBOX_SIZE + MAILBOX_DSPBOX_SIZE) -#define MAILBOX_EXCEPTION_SIZE 0x100 -#define MAILBOX_EXCEPTION_BASE \ - (MAILBOX_BASE + MAILBOX_EXCEPTION_OFFSET) - -#define MAILBOX_DEBUG_OFFSET \ - (MAILBOX_EXCEPTION_SIZE + MAILBOX_EXCEPTION_OFFSET) -#define MAILBOX_DEBUG_SIZE 0x100 -#define MAILBOX_DEBUG_BASE \ - (MAILBOX_BASE + MAILBOX_DEBUG_OFFSET) - -#define MAILBOX_STREAM_OFFSET \ - (MAILBOX_DEBUG_SIZE + MAILBOX_DEBUG_OFFSET) -#define MAILBOX_STREAM_SIZE 0x200 -#define MAILBOX_STREAM_BASE \ - (MAILBOX_BASE + MAILBOX_STREAM_OFFSET) - -#define MAILBOX_TRACE_OFFSET \ - (MAILBOX_STREAM_SIZE + MAILBOX_STREAM_OFFSET) - -#if CONFIG_TRACE -#define MAILBOX_TRACE_SIZE 0x380 -#else -#define MAILBOX_TRACE_SIZE 0x0 -#endif - -#define MAILBOX_TRACE_BASE \ - (MAILBOX_BASE + MAILBOX_TRACE_OFFSET) - -static inline void mailbox_sw_reg_write(size_t offset, uint32_t src) -{ - volatile uint32_t *ptr; - - ptr = (volatile uint32_t *)(MAILBOX_DEBUG_BASE + offset); - *ptr = src; -} - -#endif /* __PLATFORM_LIB_MAILBOX_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/mailbox.h" - -#endif /* __SOF_LIB_MAILBOX_H__ */ diff --git a/src/platform/haswell/include/platform/lib/memory.h b/src/platform/haswell/include/platform/lib/memory.h deleted file mode 100644 index 2eb5ac1a4266..000000000000 --- a/src/platform/haswell/include/platform/lib/memory.h +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - */ - -#ifdef __SOF_LIB_MEMORY_H__ - -#ifndef __PLATFORM_LIB_MEMORY_H__ -#define __PLATFORM_LIB_MEMORY_H__ - -#if !defined(__ASSEMBLER__) && !defined(LINKER) - -struct sof; - -/** - * \brief Data shared between different cores. - * Does nothing, since HSW doesn't support SMP. - */ -#define SHARED_DATA - -void platform_init_memmap(struct sof *sof); - -#define uncache_to_cache(address) address -#define cache_to_uncache(address) address -#define cache_to_uncache_init(address) address -#define is_uncached(address) 0 - -static inline void *platform_shared_get(void *ptr, int bytes) -{ - return ptr; -} - -/** - * \brief Function for keeping shared data synchronized. - * It's used after usage of data shared by different cores. - * Such data is either statically marked with SHARED_DATA - * or dynamically allocated with SOF_MEM_FLAG_SHARED flag. - * Does nothing, since HSW doesn't support SMP. - */ - -static inline void *platform_rfree_prepare(void *ptr) -{ - return ptr; -} - -#endif - -/* data cache line alignment */ -#define PLATFORM_DCACHE_ALIGN sizeof(void *) - -/** \brief EDF task's default stack size in bytes. */ -#define PLATFORM_TASK_DEFAULT_STACK_SIZE 2048 - -/* physical DSP addresses */ - -#define SHIM_SIZE 0x00001000 - -#define IRAM_BASE 0x00000000 -#define IRAM_SIZE 0x00050000 - -#define DRAM0_BASE 0x00400000 -#define DRAM0_VBASE 0x00400000 - -#define MAILBOX_SIZE (0x00001000 - SOF_VIRTUAL_THREAD_SIZE) -#define DMA0_SIZE 0x00001000 -#define DMA1_SIZE 0x00001000 -#define SSP0_SIZE 0x00001000 -#define SSP1_SIZE 0x00001000 - -#if CONFIG_BROADWELL -#define DRAM0_SIZE 0x000A0000 -#define SHIM_BASE 0xFFFFB000 -#define DMA0_BASE 0xFFFFE000 -#define DMA1_BASE 0xFFFFF000 -#define SSP0_BASE 0xFFFFC000 -#define SSP1_BASE 0xFFFFD000 - -#else /* HASWELL */ -#define DRAM0_SIZE 0x00080000 -#define SHIM_BASE 0xFFFE7000 -#define DMA0_BASE 0xFFFF0000 -#define DMA1_BASE 0xFFFF8000 -#define SSP0_BASE 0xFFFE8000 -#define SSP1_BASE 0xFFFE9000 - -#endif - -#define UUID_ENTRY_ELF_BASE 0x1FFFA000 -#define UUID_ENTRY_ELF_SIZE 0x6000 - -#define LOG_ENTRY_ELF_BASE 0x20000000 -#define LOG_ENTRY_ELF_SIZE 0x2000000 - -#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) -#define EXT_MANIFEST_ELF_SIZE 0x2000000 - -/* - * The Heap and Stack on Haswell/Broadwell are organised like this :- - * - * +--------------------------------------------------------------------------+ - * | Offset | Region | Size | - * +---------------------+----------------+-----------------------------------+ - * | DRAM0_BASE | RO Data | SOF_DATA_SIZE | - * | | Data | | - * | | BSS | | - * +---------------------+----------------+-----------------------------------+ - * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | MAILBOX_BASE | Mailbox | MAILBOX_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | VIRTUAL_THREAD_BASE | Vthread Ptr | SOF_VIRTUAL_THREAD_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SOF_STACK_END | Stack | SOF_STACK_SIZE | - * +---------------------+----------------+-----------------------------------+ - * | SOF_STACK_BASE | | | - * +---------------------+----------------+-----------------------------------+ - */ - -/* Heap section sizes for module pool */ -#define HEAP_RT_COUNT8 0 -#define HEAP_RT_COUNT16 192 -#define HEAP_RT_COUNT32 128 -#define HEAP_RT_COUNT64 64 -#define HEAP_RT_COUNT128 64 -#define HEAP_RT_COUNT256 64 -#define HEAP_RT_COUNT512 8 -#define HEAP_RT_COUNT1024 4 - -/* Heap section sizes for system runtime heap */ -#define HEAP_SYS_RT_COUNT64 64 -#define HEAP_SYS_RT_COUNT512 8 -#define HEAP_SYS_RT_COUNT1024 4 - -/* Heap configuration */ -#define SOF_DATA_SIZE 0xD000 - -#define HEAP_SYSTEM_BASE (DRAM0_BASE + SOF_DATA_SIZE) -#define HEAP_SYSTEM_SIZE 0x4000 - -#define HEAP_SYSTEM_0_BASE HEAP_SYSTEM_BASE - -#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE) -#define HEAP_SYS_RUNTIME_SIZE \ - (HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + \ - HEAP_SYS_RT_COUNT1024 * 1024) - -#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE) -#define HEAP_RUNTIME_SIZE \ - (HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + \ - HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \ - HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + \ - HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024) - -#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE) -#define HEAP_BUFFER_SIZE \ - (DRAM0_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE -\ - HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE - SOF_DATA_SIZE -\ - SOF_VIRTUAL_THREAD_SIZE - MAILBOX_SIZE) - -#define HEAP_BUFFER_BLOCK_SIZE 0x100 -#define HEAP_BUFFER_COUNT \ - (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE) - -#define PLATFORM_HEAP_SYSTEM 1 /* one per core */ -#define PLATFORM_HEAP_SYSTEM_RUNTIME 1 /* one per core */ -#define PLATFORM_HEAP_RUNTIME 1 -#define PLATFORM_HEAP_BUFFER 1 - -/* Stack configuration */ -#define SOF_STACK_SIZE (CONFIG_SOF_STACK_SIZE) -#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE -#define SOF_STACK_BASE (DRAM0_BASE + DRAM0_SIZE) -#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE) - -/* Virtual threadptr */ -#define SOF_VIRTUAL_THREAD_SIZE 0x20 -#define SOF_VIRTUAL_THREAD_BASE (SOF_STACK_END - SOF_VIRTUAL_THREAD_SIZE) - -#define MAILBOX_BASE (SOF_VIRTUAL_THREAD_BASE - MAILBOX_SIZE) - -/* Vector and literal sizes - not in core-isa.h */ -#define SOF_MEM_VECT_LIT_SIZE 0x4 -#define SOF_MEM_VECT_TEXT_SIZE 0x1c -#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + \ - SOF_MEM_VECT_LIT_SIZE) - -#define SOF_MEM_RESET_TEXT_SIZE 0x2e0 -#define SOF_MEM_RESET_LIT_SIZE 0x120 -#define SOF_MEM_VECBASE_TEXT_BASE 0x400 -#define SOF_MEM_VECBASE_LIT_SIZE 0x178 - -#define SOF_MEM_RO_SIZE 0x8 - -#define host_to_local(addr) (addr) -#define local_to_host(addr) (addr) - -#endif /* __PLATFORM_LIB_MEMORY_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/memory.h" - -#endif /* __SOF_LIB_MEMORY_H__ */ diff --git a/src/platform/haswell/include/platform/lib/pm_runtime.h b/src/platform/haswell/include/platform/lib/pm_runtime.h deleted file mode 100644 index ef1d0d676c7c..000000000000 --- a/src/platform/haswell/include/platform/lib/pm_runtime.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2018 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -/** - * \file platform/haswell/include/platform/lib/pm_runtime.h - * \brief Runtime power management header file for Haswell - * \author Tomasz Lauda - */ - -#ifdef __SOF_LIB_PM_RUNTIME_H__ - -#ifndef __PLATFORM_LIB_PM_RUNTIME_H__ -#define __PLATFORM_LIB_PM_RUNTIME_H__ - -#include -#include - -struct pm_runtime_data; - -/** - * \brief Initializes platform specific runtime power management. - * \param[in,out] prd Runtime power management data. - */ -static inline void platform_pm_runtime_init(struct pm_runtime_data *prd) { } - -/** - * \brief Retrieves platform specific power management resource. - * - * \param[in] context Type of power management context. - * \param[in] index Index of the device. - * \param[in] flags Flags, set of RPM_... - */ -static inline void platform_pm_runtime_get(uint32_t context, uint32_t index, - uint32_t flags) { } - -/** - * \brief Releases platform specific power management resource. - * - * \param[in] context Type of power management context. - * \param[in] index Index of the device. - * \param[in] flags Flags, set of RPM_... - */ -static inline void platform_pm_runtime_put(uint32_t context, uint32_t index, - uint32_t flags) { } - -static inline void platform_pm_runtime_enable(uint32_t context, - uint32_t index) {} - -static inline void platform_pm_runtime_disable(uint32_t context, - uint32_t index) {} - -static inline bool platform_pm_runtime_is_active(uint32_t context, - uint32_t index) -{ - return false; -} - -#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h" - -#endif /* __SOF_LIB_PM_RUNTIME_H__ */ diff --git a/src/platform/haswell/include/platform/lib/shim.h b/src/platform/haswell/include/platform/lib/shim.h deleted file mode 100644 index 954b86ed5f5c..000000000000 --- a/src/platform/haswell/include/platform/lib/shim.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - */ - -#ifdef __SOF_LIB_SHIM_H__ - -#ifndef __PLATFORM_LIB_SHIM_H__ -#define __PLATFORM_LIB_SHIM_H__ - -#include -#include -#include - -#define SHIM_CSR 0x00 -#define SHIM_ISRX 0x18 -#define SHIM_ISRD 0x20 -#define SHIM_IMRX 0x28 -#define SHIM_IMRD 0x30 -#define SHIM_IPCX 0x38 /* IPC IA -> SST */ -#define SHIM_IPCD 0x40 /* IPC SST -> IA */ - -#define SHIM_CLKCTL 0x78 - -#define SHIM_CSR2 0x80 -#define SHIM_LTRC 0xE0 -#define SHIM_HMDC 0xE8 - -#define SHIM_SHIM_BEGIN SHIM_CSR -#define SHIM_SHIM_END SHIM_HMDC - -/* CSR 0x0 */ -#define SHIM_CSR_RST (0x1 << 1) -#define SHIM_CSR_STALL (0x1 << 10) -#define SHIM_CSR_SDPM0 (0x1 << 11) -#define SHIM_CSR_SDPM1 (0x1 << 12) -#define SHIM_CSR_PCE (0x1 << 15) -#define SHIM_CSR_SFCR0 (0x1 << 27) -#define SHIM_CSR_SFCR1 (0x1 << 28) -#define SHIM_CSR_DCS(x) (x << 4) -#define SHIM_CSR_DCS_MASK (0x7 << 4) -#define SHIM_CSR_SFCR_SSP(x) (1 << (27 + x)) - -/* ISRX 0x18 */ -#define SHIM_ISRX_BUSY (0x1 << 1) -#define SHIM_ISRX_DONE (0x1 << 0) - -/* ISRD / ISD */ -#define SHIM_ISRD_BUSY (0x1 << 1) -#define SHIM_ISRD_DONE (0x1 << 0) - -/* IMRX / IMC */ -#define SHIM_IMRX_BUSY (0x1 << 1) -#define SHIM_IMRX_DONE (0x1 << 0) - -/* IMRD / IMD */ -#define SHIM_IMRD_DONE (0x1 << 0) -#define SHIM_IMRD_BUSY (0x1 << 1) -#define SHIM_IMRD_SSP0 (0x1 << 16) -#define SHIM_IMRD_SSP1 (0x1 << 17) -#define SHIM_IMRD_DMAC0 (0x1 << 21) -#define SHIM_IMRD_DMAC1 (0x1 << 22) -#define SHIM_IMRD_DMAC (SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1) - -/* IPCX / IPCCH */ -#define SHIM_IPCX_DONE (0x1 << 30) -#define SHIM_IPCX_BUSY (0x1 << 31) - -/* IPCDH */ -#define SHIM_IPCD_DONE (0x1 << 30) -#define SHIM_IPCD_BUSY (0x1 << 31) - -/* CLKCTL */ -#define SHIM_CLKCTL_SMOS(x) (x << 24) -#define SHIM_CLKCTL_MASK (3 << 24) -#define SHIM_CLKCTL_DCPLCG (1 << 18) -#define SHIM_CLKCTL_EN_SSP(x) (1 << (16 + x)) - -/* CSR2 / CS2 */ -#define SHIM_CSR2_SDFD_SSP0 (1 << 1) -#define SHIM_CSR2_SDFD_SSP1 (1 << 2) - -/* LTRC */ -#define SHIM_LTRC_VAL(x) (x << 0) - -/* HMDC */ -#define SHIM_HMDC_HDDA0(x) (x << 0) -#define SHIM_HMDC_HDDA1(x) (x << 8) -#define SHIM_HMDC_HDDA_CH_MASK 0xFF -#define SHIM_HMDC_HDDA_E0_ALLCH SHIM_HMDC_HDDA0(SHIM_HMDC_HDDA_CH_MASK) -#define SHIM_HMDC_HDDA_E1_ALLCH SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_CH_MASK) -#define SHIM_HMDC_HDDA_ALLCH (SHIM_HMDC_HDDA_E0_ALLCH | \ - SHIM_HMDC_HDDA_E1_ALLCH) - -/* PMCS */ -#define PCI_PMCS 0x84 -#define PCI_PMCS_PS_MASK 0x3 - -static inline uint32_t shim_read(uint32_t reg) -{ - return *((volatile uint32_t*)(SHIM_BASE + reg)); -} - -static inline void shim_write(uint32_t reg, uint32_t val) -{ - *((volatile uint32_t*)(SHIM_BASE + reg)) = val; -} - -static inline void shim_update_bits(uint32_t reg, uint32_t mask, - uint32_t value) -{ - io_reg_update_bits(SHIM_BASE + reg, mask, value); -} - -#endif /* __PLATFORM_LIB_SHIM_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/shim.h" - -#endif /* __SOF_LIB_SHIM_H__ */ diff --git a/src/platform/haswell/include/platform/platform.h b/src/platform/haswell/include/platform/platform.h deleted file mode 100644 index 375acbd6944c..000000000000 --- a/src/platform/haswell/include/platform/platform.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - */ - -#ifdef __SOF_PLATFORM_H__ - -#ifndef __PLATFORM_PLATFORM_H__ -#define __PLATFORM_PLATFORM_H__ - -#define PLATFORM_LPSRAM_EBB_COUNT 1 - -#define LPSRAM_BANK_SIZE (64 * 1024) - -#define LPSRAM_SIZE (PLATFORM_LPSRAM_EBB_COUNT * LPSRAM_BANK_SIZE) - -#if !defined(__ASSEMBLER__) && !defined(LINKER) - -#include -#include -#include -#include -#include -#include -#include - -struct ll_schedule_domain; -struct timer; - -/*! \def PLATFORM_DEFAULT_CLOCK - * \brief clock source for audio pipeline - * - * There are two types of clock: cpu clock which is a internal clock in - * xtensa core, and ssp clock which is provided by external HW IP. - * The choice depends on HW features on different platform - */ -#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0) - -/* IPC Interrupt */ -#define PLATFORM_IPC_INTERRUPT IRQ_NUM_EXT_IA -#define PLATFORM_IPC_INTERRUPT_NAME NULL - -/* Host page size */ -#define HOST_PAGE_SIZE 4096 -#define PLATFORM_PAGE_TABLE_SIZE 256 - -/* pipeline IRQ */ -#define PLATFORM_SCHEDULE_IRQ IRQ_NUM_SOFTWARE2 -#define PLATFORM_SCHEDULE_IRQ_NAME NULL - -/* Platform stream capabilities */ -#define PLATFORM_MAX_CHANNELS 4 -#define PLATFORM_MAX_STREAMS 5 - -/* local buffer size of DMA tracing */ -#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE - -/* trace bytes flushed during panic */ -#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2) - -/* the interval of DMA trace copying */ -#define DMA_TRACE_PERIOD 500000 - -/* - * the interval of reschedule DMA trace copying in special case like half - * fullness of local DMA trace buffer - */ -#define DMA_TRACE_RESCHEDULE_TIME 100 - -/* DSP default delay in cycles */ -#define PLATFORM_DEFAULT_DELAY 12 - -/* Platform defined panic code */ -static inline void platform_panic(uint32_t p) -{ - shim_write(SHIM_IPCX, MAILBOX_EXCEPTION_OFFSET & 0x3fffffff); - shim_write(SHIM_IPCD, (SHIM_IPCD_BUSY | p)); -} - -/** - * \brief Platform specific CPU entering idle. - * May be power-optimized using platform specific capabilities. - * @param level Interrupt level. - */ -void platform_wait_for_interrupt(int level); - -extern intptr_t _module_init_start; -extern intptr_t _module_init_end; - -#endif -#endif /* __PLATFORM_PLATFORM_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/platform.h" - -#endif /* __SOF_PLATFORM_H__ */ diff --git a/src/platform/haswell/include/platform/trace/trace.h b/src/platform/haswell/include/platform/trace/trace.h deleted file mode 100644 index 306e4fd5f40f..000000000000 --- a/src/platform/haswell/include/platform/trace/trace.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -#ifdef __SOF_TRACE_TRACE_H__ - -#ifndef __PLATFORM_TRACE_TRACE_H__ -#define __PLATFORM_TRACE_TRACE_H__ - -#include - -/* Platform defined trace code */ -#define platform_trace_point(__x) \ - shim_write(SHIM_IPCX, ((__x) & 0x3fffffff)) - -#endif /* __PLATFORM_TRACE_TRACE_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/trace/trace.h" - -#endif /* __SOF_TRACE_TRACE_H__ */ diff --git a/src/platform/haswell/lib/CMakeLists.txt b/src/platform/haswell/lib/CMakeLists.txt deleted file mode 100644 index 271a099cc6a9..000000000000 --- a/src/platform/haswell/lib/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: BSD-3-Clause - -add_local_sources(sof - clk.c - dai.c - dma.c - memory.c -) diff --git a/src/platform/haswell/lib/clk.c b/src/platform/haswell/lib/clk.c deleted file mode 100644 index 5cd82ee36a8d..000000000000 --- a/src/platform/haswell/lib/clk.c +++ /dev/null @@ -1,94 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2019 Intel Corporation. All rights reserved. -// -// Author: Tomasz Lauda -// Janusz Jankowski - -#include -#include -#include -#include -#include -#include -#include - -static const struct freq_table platform_cpu_freq[] = { - { 32000000, 32000 }, - { 80000000, 80000 }, - { 160000000, 160000 }, - { 320000000, 320000 }, - { 320000000, 320000 }, - { 160000000, 160000 }, -}; - -const uint32_t cpu_freq_enc[] = { - 0x6, - 0x2, - 0x1, - 0x4, - 0x0, - 0x5, -}; - -STATIC_ASSERT(NUM_CPU_FREQ == ARRAY_SIZE(platform_cpu_freq), - invalid_number_of_cpu_frequencies); - -static const struct freq_table platform_ssp_freq[] = { - { 24000000, 24000 }, -}; - -static const uint32_t platform_ssp_freq_sources[] = { - 0, -}; - -STATIC_ASSERT(NUM_SSP_FREQ == ARRAY_SIZE(platform_ssp_freq), - invalid_number_of_ssp_frequencies); - -const struct freq_table *ssp_freq = platform_ssp_freq; -const uint32_t *ssp_freq_sources = platform_ssp_freq_sources; - -static int clock_platform_set_cpu_freq(int clock, int freq_idx) -{ - uint32_t enc = cpu_freq_enc[freq_idx]; - - /* set CPU frequency request for CCU */ - io_reg_update_bits(SHIM_BASE + SHIM_CSR, SHIM_CSR_DCS_MASK, - enc); - - return 0; -} - -static SHARED_DATA struct clock_info platform_clocks_info[] = { - { - .freqs_num = NUM_CPU_FREQ, - .freqs = platform_cpu_freq, - .default_freq_idx = CPU_DEFAULT_IDX, - .current_freq_idx = CPU_DEFAULT_IDX, - .notification_id = NOTIFIER_ID_CPU_FREQ, - .notification_mask = NOTIFIER_TARGET_CORE_MASK(0), - .set_freq = clock_platform_set_cpu_freq, - }, - { - .freqs_num = NUM_SSP_FREQ, - .freqs = platform_ssp_freq, - .default_freq_idx = SSP_DEFAULT_IDX, - .current_freq_idx = SSP_DEFAULT_IDX, - .notification_id = NOTIFIER_ID_SSP_FREQ, - .notification_mask = NOTIFIER_TARGET_CORE_ALL_MASK, - .set_freq = NULL, - } -}; - -STATIC_ASSERT(ARRAY_SIZE(platform_clocks_info) == NUM_CLOCKS, - invalid_number_of_clocks); - -void platform_clock_init(struct sof *sof) -{ - int i; - - sof->clocks = platform_shared_get(platform_clocks_info, sizeof(platform_clocks_info)); - - for (i = 0; i < NUM_CLOCKS; i++) - k_spinlock_init(&sof->clocks[i].lock); -} diff --git a/src/platform/haswell/lib/dai.c b/src/platform/haswell/lib/dai.c deleted file mode 100644 index 3034da5a7899..000000000000 --- a/src/platform/haswell/lib/dai.c +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2016 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static SHARED_DATA struct dai ssp[2] = { -{ - .index = 0, - .plat_data = { - .base = SSP0_BASE, - .irq = IRQ_NUM_EXT_SSP0, - .fifo[SOF_IPC_STREAM_PLAYBACK] = { - .offset = SSP0_BASE + SSDR, - .handshake = DMA_HANDSHAKE_SSP0_TX, - }, - .fifo[SOF_IPC_STREAM_CAPTURE] = { - .offset = SSP0_BASE + SSDR, - .handshake = DMA_HANDSHAKE_SSP0_RX, - } - }, - .drv = &ssp_driver, -}, -{ - .index = 1, - .plat_data = { - .base = SSP1_BASE, - .irq = IRQ_NUM_EXT_SSP1, - .fifo[SOF_IPC_STREAM_PLAYBACK] = { - .offset = SSP1_BASE + SSDR, - .handshake = DMA_HANDSHAKE_SSP1_TX, - }, - .fifo[SOF_IPC_STREAM_CAPTURE] = { - .offset = SSP1_BASE + SSDR, - .handshake = DMA_HANDSHAKE_SSP1_RX, - } - }, - .drv = &ssp_driver, -}, -}; - -const struct dai_type_info dti[] = { - { - .type = SOF_DAI_INTEL_SSP, - .dai_array = cache_to_uncache_init((struct dai *)ssp), - .num_dais = ARRAY_SIZE(ssp) - } -}; - -const struct dai_info lib_dai = { - .dai_type_array = dti, - .num_dai_types = ARRAY_SIZE(dti) -}; - -int dai_init(struct sof *sof) -{ - int i; - - /* initialize spin locks early to enable ref counting */ - for (i = 0; i < ARRAY_SIZE(ssp); i++) - k_spinlock_init(&dti[0].dai_array[i].lock); - - sof->dai_info = &lib_dai; - - return 0; -} diff --git a/src/platform/haswell/lib/dma.c b/src/platform/haswell/lib/dma.c deleted file mode 100644 index 7687847bb17a..000000000000 --- a/src/platform/haswell/lib/dma.c +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2016 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static const struct dw_drv_plat_data dmac0 = { - .chan[0] = { - .class = 6, - .weight = 0, - }, - .chan[1] = { - .class = 6, - .weight = 0, - }, - .chan[2] = { - .class = 6, - .weight = 0, - }, - .chan[3] = { - .class = 6, - .weight = 0, - }, - .chan[4] = { - .class = 6, - .weight = 0, - }, - .chan[5] = { - .class = 6, - .weight = 0, - }, - .chan[6] = { - .class = 6, - .weight = 0, - }, - .chan[7] = { - .class = 6, - .weight = 0, - }, -}; - -static const struct dw_drv_plat_data dmac1 = { - .chan[0] = { - .class = 7, - .weight = 0, - }, - .chan[1] = { - .class = 7, - .weight = 0, - }, - .chan[2] = { - .class = 7, - .weight = 0, - }, - .chan[3] = { - .class = 7, - .weight = 0, - }, - .chan[4] = { - .class = 7, - .weight = 0, - }, - .chan[5] = { - .class = 7, - .weight = 0, - }, - .chan[6] = { - .class = 7, - .weight = 0, - }, - .chan[7] = { - .class = 7, - .weight = 0, - }, -}; - -static SHARED_DATA struct dma dma[PLATFORM_NUM_DMACS] = { -{ - .plat_data = { - .id = DMA_ID_DMAC0, - .base = DMA0_BASE, - .dir = DMA_DIR_MEM_TO_MEM, - .caps = DMA_CAP_GP_HP | DMA_CAP_GP_LP, - .devs = DMA_DEV_HOST, - .irq = IRQ_NUM_EXT_DMAC0, - .drv_plat_data = &dmac0, - .channels = 8, - }, - .ops = &dw_dma_ops, -}, -{ - .plat_data = { - .id = DMA_ID_DMAC1, - .base = DMA1_BASE, - .dir = DMA_DIR_MEM_TO_MEM | DMA_DIR_MEM_TO_DEV | - DMA_DIR_DEV_TO_MEM | DMA_DIR_DEV_TO_DEV | - DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM, - .caps = DMA_CAP_GP_HP | DMA_CAP_GP_LP, - .devs = DMA_DEV_SSP | DMA_DEV_HOST, - .irq = IRQ_NUM_EXT_DMAC1, - .drv_plat_data = &dmac1, - .channels = 8, - }, - .ops = &dw_dma_ops, -},}; - -static const struct dma_info lib_dma = { - .dma_array = cache_to_uncache_init((struct dma *)dma), - .num_dmas = ARRAY_SIZE(dma) -}; - -/* Initialize all platform DMAC's */ -int dmac_init(struct sof *sof) -{ - int i; - /* no probing before first use */ - - /* TODO: dynamic init based on platform settings */ - - /* early lock initialization for ref counting */ - for (i = 0; i < ARRAY_SIZE(dma); i++) - k_spinlock_init(&dma[i].lock); - - /* clear the masks for dsp of the dmacs */ - io_reg_update_bits(SHIM_BASE + SHIM_IMRD, - SHIM_IMRD_DMAC0, 0); - - io_reg_update_bits(SHIM_BASE + SHIM_IMRD, - SHIM_IMRD_DMAC1, 0); - - sof->dma_info = &lib_dma; - - return 0; -} diff --git a/src/platform/haswell/lib/memory.c b/src/platform/haswell/lib/memory.c deleted file mode 100644 index a4478e9d7f27..000000000000 --- a/src/platform/haswell/lib/memory.c +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2018 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood - -#include -#include -#include -#include -#include - -/* Heap blocks for system runtime */ -static SHARED_DATA struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64]; -static SHARED_DATA struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512]; -static SHARED_DATA struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024]; - -/* Heap memory for system runtime */ -static SHARED_DATA struct block_map sys_rt_heap_map[] = { - BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64), - BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512), - BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024), -}; - -/* Heap blocks for modules */ -static SHARED_DATA struct block_hdr mod_block16[HEAP_RT_COUNT16]; -static SHARED_DATA struct block_hdr mod_block32[HEAP_RT_COUNT32]; -static SHARED_DATA struct block_hdr mod_block64[HEAP_RT_COUNT64]; -static SHARED_DATA struct block_hdr mod_block128[HEAP_RT_COUNT128]; -static SHARED_DATA struct block_hdr mod_block256[HEAP_RT_COUNT256]; -static SHARED_DATA struct block_hdr mod_block512[HEAP_RT_COUNT512]; -static SHARED_DATA struct block_hdr mod_block1024[HEAP_RT_COUNT1024]; - -/* Heap memory map for modules */ -static SHARED_DATA struct block_map rt_heap_map[] = { - BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16), - BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32), - BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64), - BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128), - BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256), - BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512), - BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024), -}; - -/* Heap blocks for buffers */ -static SHARED_DATA struct block_hdr buf_block[HEAP_BUFFER_COUNT]; - -/* Heap memory map for buffers */ -static SHARED_DATA struct block_map buf_heap_map[] = { - BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block), -}; - -static SHARED_DATA struct mm memmap = { - .system[0] = { - .heap = HEAP_SYSTEM_BASE, - .size = HEAP_SYSTEM_SIZE, - .info = {.free = HEAP_SYSTEM_SIZE,}, - .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | - SOF_MEM_CAPS_DMA, - }, - .system_runtime[0] = { - .blocks = ARRAY_SIZE(sys_rt_heap_map), - .map = sys_rt_heap_map, - .heap = HEAP_SYS_RUNTIME_BASE, - .size = HEAP_SYS_RUNTIME_SIZE, - .info = {.free = HEAP_SYS_RUNTIME_SIZE,}, - .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | - SOF_MEM_CAPS_DMA, - }, - .runtime[0] = { - .blocks = ARRAY_SIZE(rt_heap_map), - .map = rt_heap_map, - .heap = HEAP_RUNTIME_BASE, - .size = HEAP_RUNTIME_SIZE, - .info = {.free = HEAP_RUNTIME_SIZE,}, - .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | - SOF_MEM_CAPS_DMA, - }, - .buffer[0] = { - .blocks = ARRAY_SIZE(buf_heap_map), - .map = buf_heap_map, - .heap = HEAP_BUFFER_BASE, - .size = HEAP_BUFFER_SIZE, - .info = {.free = HEAP_BUFFER_SIZE,}, - .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | - SOF_MEM_CAPS_DMA, - }, - .total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE + - HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,}, -}; - -void platform_init_memmap(struct sof *sof) -{ - /* memmap has been initialized statically as a part of .data */ - sof->memory_map = platform_shared_get(&memmap, sizeof(memmap)); -} diff --git a/src/platform/haswell/platform.c b/src/platform/haswell/platform.c deleted file mode 100644 index 495432a9db80..000000000000 --- a/src/platform/haswell/platform.c +++ /dev/null @@ -1,275 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2016 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static const struct sof_ipc_fw_ready ready - __section(".fw_ready") = { - .hdr = { - .cmd = SOF_IPC_FW_READY, - .size = sizeof(struct sof_ipc_fw_ready), - }, - /* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */ - .version = { - .hdr.size = sizeof(struct sof_ipc_fw_version), - .micro = SOF_MICRO, - .minor = SOF_MINOR, - .major = SOF_MAJOR, -/* opt-in; reproducible build by default */ -#if BLD_COUNTERS - .build = SOF_BUILD, /* See version-build-counter.cmake */ - .date = __DATE__, - .time = __TIME__, -#else - .build = -1, - .date = "dtermin.\0", - .time = "fwready.\0", -#endif - .tag = SOF_TAG, - .abi_version = SOF_ABI_VERSION, - .src_hash = SOF_SRC_HASH, - }, - .flags = DEBUG_SET_FW_READY_FLAGS, -}; - -#define NUM_HSW_WINDOWS 6 - -const struct ext_man_windows xsram_window - __aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = { - .hdr = { - .type = EXT_MAN_ELEM_WINDOW, - .elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN), - }, - .window = { - .ext_hdr = { - .hdr.cmd = SOF_IPC_FW_READY, - .hdr.size = sizeof(struct sof_ipc_window), - .type = SOF_IPC_EXT_WINDOW, - }, - .num_windows = NUM_HSW_WINDOWS, - .window = { - { - .type = SOF_IPC_REGION_UPBOX, - .id = 0, /* map to host window 0 */ - .flags = 0, // TODO: set later - .size = MAILBOX_DSPBOX_SIZE, - .offset = MAILBOX_DSPBOX_OFFSET, - }, - { - .type = SOF_IPC_REGION_DOWNBOX, - .id = 0, /* map to host window 0 */ - .flags = 0, // TODO: set later - .size = MAILBOX_HOSTBOX_SIZE, - .offset = MAILBOX_HOSTBOX_OFFSET, - }, - { - .type = SOF_IPC_REGION_DEBUG, - .id = 0, /* map to host window 0 */ - .flags = 0, // TODO: set later - .size = MAILBOX_DEBUG_SIZE, - .offset = MAILBOX_DEBUG_OFFSET, - }, - { - .type = SOF_IPC_REGION_TRACE, - .id = 0, /* map to host window 0 */ - .flags = 0, // TODO: set later - .size = MAILBOX_TRACE_SIZE, - .offset = MAILBOX_TRACE_OFFSET, - }, - { - .type = SOF_IPC_REGION_STREAM, - .id = 0, /* map to host window 0 */ - .flags = 0, // TODO: set later - .size = MAILBOX_STREAM_SIZE, - .offset = MAILBOX_STREAM_OFFSET, - }, - { - .type = SOF_IPC_REGION_EXCEPTION, - .id = 0, /* map to host window 0 */ - .flags = 0, // TODO: set later - .size = MAILBOX_EXCEPTION_SIZE, - .offset = MAILBOX_EXCEPTION_OFFSET, - }, - }, - }, -}; - -#ifndef __ZEPHYR__ -static SHARED_DATA struct timer timer_shared = { - .id = TIMER1, /* internal timer */ - .irq = IRQ_NUM_TIMER2, -}; -#endif - -int platform_boot_complete(uint32_t boot_message) -{ - uint32_t outbox = MAILBOX_HOST_OFFSET >> 3; - - mailbox_dspbox_write(0, &ready, sizeof(ready)); - - /* now interrupt host to tell it we are done booting */ - shim_write(SHIM_IPCD, outbox | SHIM_IPCD_BUSY); - - /* boot now complete so we can relax the CPU */ - clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ); - - return 0; -} - -/* init shim registers */ -static void platform_init_shim(void) -{ - /* disable power gate */ - io_reg_update_bits(SHIM_BASE + SHIM_CLKCTL, - SHIM_CLKCTL_DCPLCG, - SHIM_CLKCTL_DCPLCG); - - /* disable parity check */ - io_reg_update_bits(SHIM_BASE + SHIM_CSR, SHIM_CSR_PCE, 0); - - /* enable DMA finsh on ssp ports */ - io_reg_update_bits(SHIM_BASE + SHIM_CSR2, - SHIM_CSR2_SDFD_SSP0 | SHIM_CSR2_SDFD_SSP1, - SHIM_CSR2_SDFD_SSP0 | SHIM_CSR2_SDFD_SSP1); -} - -int platform_init(struct sof *sof) -{ - struct dai *ssp0; - struct dai *ssp1; - int ret; - -#ifndef __ZEPHYR__ - sof->platform_timer = platform_shared_get(&timer_shared, sizeof(timer_shared)); - sof->cpu_timers = sof->platform_timer; -#endif - - /* clear mailbox for early trace and debug */ - trace_point(TRACE_BOOT_PLATFORM_MBOX); - bzero((void *)MAILBOX_BASE, MAILBOX_SIZE); - - trace_point(TRACE_BOOT_PLATFORM_SHIM); - platform_init_shim(); - -#ifndef __ZEPHYR__ - /* init timers, clocks and schedulers */ - trace_point(TRACE_BOOT_PLATFORM_TIMER); - platform_timer_start(sof->platform_timer); -#endif - - trace_point(TRACE_BOOT_PLATFORM_CLOCK); - platform_clock_init(sof); - - trace_point(TRACE_BOOT_PLATFORM_SCHED); - scheduler_init_edf(); - - /* init low latency timer domain and scheduler */ - sof->platform_timer_domain = - timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK); - scheduler_init_ll(sof->platform_timer_domain); - - /* init the system agent */ - trace_point(TRACE_BOOT_PLATFORM_AGENT); - sa_init(sof, CONFIG_SYSTICK_PERIOD); - - /* Set CPU to default frequency for booting */ - trace_point(TRACE_BOOT_PLATFORM_CPU_FREQ); - clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ); - - /* set SSP clock to 24M */ - trace_point(TRACE_BOOT_PLATFORM_SSP_FREQ); - clock_set_freq(CLK_SSP, 24000000); - - /* init DMACs */ - trace_point(TRACE_BOOT_PLATFORM_DMA); - ret = dmac_init(sof); - if (ret < 0) - return -ENODEV; - - /* init low latency multi channel DW-DMA domain and scheduler */ - sof->platform_dma_domain = dma_multi_chan_domain_init - (&sof->dma_info->dma_array[PLATFORM_DW_DMA_INDEX], - PLATFORM_NUM_DW_DMACS, - PLATFORM_DEFAULT_CLOCK, true); - scheduler_init_ll(sof->platform_dma_domain); - - /* initialise the host IPC mechanisms */ - trace_point(TRACE_BOOT_PLATFORM_IPC); - ipc_init(sof); - - trace_point(TRACE_BOOT_PLATFORM_DAI); - ret = dai_init(sof); - if (ret < 0) - return -ENODEV; - - /* init SSP ports */ - trace_point(TRACE_BOOT_PLATFORM_SSP); - ssp0 = dai_get(SOF_DAI_INTEL_SSP, 0, DAI_CREAT); - if (!ssp0) - return -ENODEV; - - ssp1 = dai_get(SOF_DAI_INTEL_SSP, 1, DAI_CREAT); - if (!ssp1) - return -ENODEV; - -#ifndef __ZEPHYR__ -#if CONFIG_TRACE - /* Initialize DMA for Trace*/ - trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE); - dma_trace_init_complete(sof->dmat); -#endif - - /* show heap status */ - heap_trace_all(1); -#endif /* __ZEPHYR__ */ - - return 0; -} - -int platform_context_save(struct sof *sof) -{ - return 0; -} - -void platform_wait_for_interrupt(int level) -{ - if (arch_interrupt_get_level()) - sof_panic(SOF_IPC_PANIC_WFI); - - arch_wait_for_interrupt(level); -} diff --git a/src/platform/library/include/platform/lib/pm_runtime.h b/src/platform/library/include/platform/lib/pm_runtime.h index ef1d0d676c7c..9c4fb663fbf2 100644 --- a/src/platform/library/include/platform/lib/pm_runtime.h +++ b/src/platform/library/include/platform/lib/pm_runtime.h @@ -6,8 +6,8 @@ */ /** - * \file platform/haswell/include/platform/lib/pm_runtime.h - * \brief Runtime power management header file for Haswell + * \file platform/library/include/platform/lib/pm_runtime.h + * \brief Runtime power management header file for host-side testing * \author Tomasz Lauda */ diff --git a/tools/fuzzer/CMakeLists.txt b/tools/fuzzer/CMakeLists.txt index 6231dca05918..c00b40b6a313 100644 --- a/tools/fuzzer/CMakeLists.txt +++ b/tools/fuzzer/CMakeLists.txt @@ -23,7 +23,6 @@ add_executable(sof-fuzzer main.c qemu-bridge.c topology.c - platform/hsw-host.c platform/imx8-host.c ) diff --git a/tools/fuzzer/fuzzer.h b/tools/fuzzer/fuzzer.h index 9dfb4052e0b2..2ff006c8df51 100644 --- a/tools/fuzzer/fuzzer.h +++ b/tools/fuzzer/fuzzer.h @@ -157,8 +157,6 @@ static inline void fuzzer_fw_ready(struct fuzz *fuzzer) fuzzer->platform->fw_ready(fuzzer); } -extern struct fuzz_platform hsw_platform; -extern struct fuzz_platform bdw_platform; extern struct fuzz_platform imx8_platform; extern pthread_cond_t cond; diff --git a/tools/fuzzer/main.c b/tools/fuzzer/main.c index ab23919af2da..bc2a7349ca5e 100644 --- a/tools/fuzzer/main.c +++ b/tools/fuzzer/main.c @@ -73,8 +73,6 @@ uint32_t trace_cmd_types[] = {SOF_IPC_TRACE_DMA_PARAMS, /* list of supported target platforms */ static struct fuzz_platform *platform[] = { - &hsw_platform, - &bdw_platform, &imx8_platform, }; diff --git a/tools/fuzzer/platform/hsw-host.c b/tools/fuzzer/platform/hsw-host.c deleted file mode 100644 index b3ad5b9a60c2..000000000000 --- a/tools/fuzzer/platform/hsw-host.c +++ /dev/null @@ -1,552 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2019 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood -// Author: Ranjani Sridharan - -/* Core IA host SHIM support for Haswell audio DSP. */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "shim.h" -#include -#include -#include "../fuzzer.h" -#include "../qemu-bridge.h" - -#define MBOX_OFFSET 0x144000 - -/* taken from qemu value */ -#define ADSP_PCI_SIZE 0x00001000 - -/* Haswell and Broadwell */ -#define ADSP_HSW_PCI_BASE 0xF0200000 -#define ADSP_HSW_MMIO_BASE 0xF0400000 -#define ADSP_HSW_HOST_IRAM_OFFSET 0x00080000 -#define ADSP_HSW_HOST_DRAM_OFFSET 0x00000000 -#define ADSP_HSW_HOST_IRAM_BASE \ - (ADSP_HSW_MMIO_BASE + ADSP_HSW_HOST_IRAM_OFFSET) -#define ADSP_HSW_HOST_DRAM_BASE \ - (ADSP_HSW_MMIO_BASE + ADSP_HSW_HOST_DRAM_OFFSET) -#define ADSP_HSW_HOST_SHIM_BASE \ - (ADSP_HSW_MMIO_BASE + 0x000E7000) -#define ADSP_HSW_HOST_MAILBOX_BASE \ - (ADSP_HSW_HOST_DRAM_BASE + 0x0007E000) - -#define ADSP_BDW_PCI_BASE 0xF0600000 -#define ADSP_BDW_MMIO_BASE 0xF0800000 -#define ADSP_BDW_HOST_IRAM_OFFSET 0x000A0000 -#define ADSP_BDW_HOST_DRAM_OFFSET 0x00000000 -#define ADSP_BDW_HOST_IRAM_BASE \ - (ADSP_BDW_MMIO_BASE + ADSP_BDW_HOST_IRAM_OFFSET) -#define ADSP_BDW_HOST_DRAM_BASE \ - (ADSP_BDW_MMIO_BASE + ADSP_BDW_HOST_DRAM_OFFSET) -#define ADSP_BDW_HOST_SHIM_BASE \ - (ADSP_BDW_MMIO_BASE + 0x000FB000) -#define ADSP_BDW_HOST_MAILBOX_BASE \ - (ADSP_BDW_HOST_DRAM_BASE + 0x0009E000) - -#define ADSP_HSW_DSP_SHIM_BASE 0xFFFE7000 -#define ADSP_BDW_DSP_SHIM_BASE 0xFFFFB000 -#define ADSP_HSW_SHIM_SIZE 0x00001000 - -#define ADSP_BDW_DSP_MAILBOX_BASE (0x0049E000 - ADSP_HSW_DSP_DRAM_BASE) -#define ADSP_HSW_DSP_MAILBOX_BASE (0x0047E000 - ADSP_HSW_DSP_DRAM_BASE) - -#define ADSP_HSW_DSP_IRAM_BASE 0x00000000 -#define ADSP_HSW_DSP_DRAM_BASE 0x00400000 - -#define ADSP_HSW_IRAM_SIZE 0x50000 -#define ADSP_HSW_DRAM_SIZE 0x80000 - -#define ADSP_BDW_DSP_IRAM_BASE 0x00000000 -#define ADSP_BDW_DSP_DRAM_BASE 0x00400000 -#define ADSP_BDW_IRAM_SIZE 0x50000 -#define ADSP_BDW_DRAM_SIZE 0xA0000 - -#define ADSP_MAILBOX_SIZE 0x980 - -/* TODO get from driver. */ -#define HSW_PANIC_OFFSET(x) (x) - -struct hsw_data { - void *bar[MAX_BAR_COUNT]; - struct mailbox host_box; - struct mailbox dsp_box; - int boot_complete; - pthread_mutex_t mutex; -}; - -static struct fuzzer_mem_desc hsw_mem[] = { - {.name = "iram", .base = ADSP_HSW_HOST_IRAM_BASE, - .size = ADSP_HSW_IRAM_SIZE}, - {.name = "dram", .base = ADSP_HSW_HOST_DRAM_BASE, - .size = ADSP_HSW_DRAM_SIZE}, -}; - -static struct fuzzer_reg_space hsw_io[] = { - { .name = "shim", - .desc = {.base = ADSP_HSW_DSP_SHIM_BASE, - .size = ADSP_HSW_SHIM_SIZE},}, -}; - -static struct fuzzer_mem_desc bdw_mem[] = { - {.name = "iram", .base = ADSP_BDW_HOST_IRAM_BASE, - .size = ADSP_BDW_IRAM_SIZE}, - {.name = "dram", .base = ADSP_BDW_HOST_DRAM_BASE, - .size = ADSP_BDW_DRAM_SIZE}, -}; - -static struct fuzzer_reg_space bdw_io[] = { - { .name = "shim", - .desc = {.base = ADSP_BDW_DSP_SHIM_BASE, - .size = ADSP_HSW_SHIM_SIZE},}, -}; - -#define HSW_DSP_BAR 2 -#define HSW_MBOX_BAR 1 - -/* - * Platform support for HSW/BDW. - * - * The IPC portions below are copied and pasted from the SOF driver with some - * modification for data structure and printing. - * - * The "driver" code below no longer writes directly to the HW but writes - * to the virtual HW as exported by qemu as Posix SHM and message queues. - * - * Register IO and mailbox IO is performed using shared memory regions between - * fuzzer and qemu. - * - * IRQs are send using message queues between fuzzer and qemu. - * - * SHM and message queues can be inspected from the cmd line by using - * "less -C" on /dev/shm/name and /dev/mqueue/name - */ - -static uint32_t dsp_read(struct fuzz *fuzzer, unsigned int bar, - unsigned int reg) -{ - struct hsw_data *data = fuzzer->platform_data; - - return *((uint32_t *)(data->bar[bar] + reg)); -} - -static void dsp_write(struct fuzz *fuzzer, unsigned int bar, - unsigned int reg, uint32_t value) -{ - struct hsw_data *data = fuzzer->platform_data; - struct qemu_io_msg_irq irq; - uint32_t active, isrd; - - /* write value to SHM */ - *((uint32_t *)(data->bar[bar] + reg)) = value; - - /* most IO is handled by SHM, but there are some exceptions */ - switch (reg) { - case SHIM_IPCX: - /* now set/clear status bit */ - isrd = dsp_read(fuzzer, bar, SHIM_ISRD) & - ~(SHIM_ISRD_DONE | SHIM_ISRD_BUSY); - isrd |= value & SHIM_IPCX_BUSY ? SHIM_ISRD_BUSY : 0; - isrd |= value & SHIM_IPCX_DONE ? SHIM_ISRD_DONE : 0; - dsp_write(fuzzer, bar, SHIM_ISRD, isrd); - - /* do we need to send an IRQ ? */ - if (value & SHIM_IPCX_BUSY) { - - fprintf(stdout, "irq: send busy interrupt 0x%8.8x\n", - value); - - /* send IRQ to child */ - irq.hdr.type = QEMU_IO_TYPE_IRQ; - irq.hdr.msg = QEMU_IO_MSG_IRQ; - irq.hdr.size = sizeof(irq); - irq.irq = 0; - - qemu_io_send_msg(&irq.hdr); - } - break; - case SHIM_IPCD: - /* set/clear status bit */ - isrd = dsp_read(fuzzer, bar, SHIM_ISRD) & - ~(SHIM_ISRD_DONE | SHIM_ISRD_BUSY); - isrd |= value & SHIM_IPCD_BUSY ? SHIM_ISRD_BUSY : 0; - isrd |= value & SHIM_IPCD_DONE ? SHIM_ISRD_DONE : 0; - dsp_write(fuzzer, bar, SHIM_ISRD, isrd); - - /* do we need to send an IRQ ? */ - if (value & SHIM_IPCD_DONE) { - - fprintf(stdout, "irq: send done interrupt 0x%8.8x\n", - value); - - /* send IRQ to child */ - irq.hdr.type = QEMU_IO_TYPE_IRQ; - irq.hdr.msg = QEMU_IO_MSG_IRQ; - irq.hdr.size = sizeof(irq); - irq.irq = 0; - - qemu_io_send_msg(&irq.hdr); - } - break; - case SHIM_IMRX: - active = dsp_read(fuzzer, bar, SHIM_ISRX) & - ~(dsp_read(fuzzer, bar, SHIM_IMRX)); - - fprintf(stdout, "irq: masking %x mask %x active %x\n", - dsp_read(fuzzer, bar, SHIM_ISRD), - dsp_read(fuzzer, bar, SHIM_IMRD), active); - break; - default: - break; - } -} - -static uint64_t dsp_update_bits_unlocked(struct fuzz *fuzzer, - unsigned int bar, uint32_t offset, - uint32_t mask, uint32_t value) -{ - uint32_t old, new; - uint32_t ret; - - ret = dsp_read(fuzzer, bar, offset); - old = ret; - - new = (old & ~mask) | (value & mask); - - if (old == new) - return 0; - - dsp_write(fuzzer, bar, offset, new); - return 1; -} - -static void mailbox_read(struct fuzz *fuzzer, unsigned int offset, - void *mbox_data, unsigned int size) -{ - struct hsw_data *data = fuzzer->platform_data; - - memcpy(mbox_data, (void *)(data->bar[HSW_MBOX_BAR] + offset), size); -} - -static void mailbox_write(struct fuzz *fuzzer, unsigned int offset, - void *mbox_data, unsigned int size) -{ - struct hsw_data *data = fuzzer->platform_data; - - memcpy((void *)(data->bar[HSW_MBOX_BAR] + offset), mbox_data, size); -} - -static int hsw_cmd_done(struct fuzz *fuzzer, int dir) -{ - if (dir == SOF_IPC_HOST_REPLY) { - /* clear BUSY bit and set DONE bit - accept new messages */ - dsp_update_bits_unlocked(fuzzer, HSW_DSP_BAR, SHIM_IPCD, - SHIM_IPCD_BUSY | - SHIM_IPCD_DONE, - SHIM_IPCD_DONE); - - /* unmask busy interrupt */ - dsp_update_bits_unlocked(fuzzer, HSW_DSP_BAR, SHIM_IMRX, - SHIM_IMRX_BUSY, 0); - } else { - /* clear DONE bit - tell DSP we have completed */ - dsp_update_bits_unlocked(fuzzer, HSW_DSP_BAR, SHIM_IPCX, - SHIM_IPCX_DONE, 0); - - /* unmask Done interrupt */ - dsp_update_bits_unlocked(fuzzer, HSW_DSP_BAR, SHIM_IMRX, - SHIM_IMRX_DONE, 0); - } - - return 0; -} - -/* - * IPC Doorbell IRQ handler and thread. - */ - -static int hsw_irq_handler(int irq, void *context) -{ - struct fuzz *fuzzer = (struct fuzz *)context; - uint32_t isr; - int ret = IRQ_NONE; - - /* Interrupt arrived, check src */ - isr = dsp_read(fuzzer, HSW_DSP_BAR, SHIM_ISRX); - if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY)) - ret = IRQ_WAKE_THREAD; - - return ret; -} - -static int hsw_irq_thread(int irq, void *context) -{ - struct fuzz *fuzzer = (struct fuzz *)context; - struct hsw_data *data = fuzzer->platform_data; - uint32_t ipcx, ipcd; - uint32_t imrx; - - imrx = dsp_read(fuzzer, HSW_DSP_BAR, SHIM_IMRX); - ipcx = dsp_read(fuzzer, HSW_DSP_BAR, SHIM_IPCX); - - /* reply message from DSP */ - if ((ipcx & SHIM_IPCX_DONE) && - !(imrx & SHIM_IMRX_DONE)) { - /* Mask Done interrupt before first */ - dsp_update_bits_unlocked(fuzzer, HSW_DSP_BAR, - SHIM_IMRX, - SHIM_IMRX_DONE, - SHIM_IMRX_DONE); - - fprintf(stdout, "ipc: reply msg from DSP\n"); - /* - * handle immediate reply from DSP core. If the msg is - * found, set done bit in cmd_done which is called at the - * end of message processing function, else set it here - * because the done bit can't be set in cmd_done function - * which is triggered by msg - */ - - fuzzer_ipc_msg_reply(fuzzer, &data->host_box); - hsw_cmd_done(fuzzer, SOF_IPC_DSP_REPLY); - return IRQ_HANDLED; - } - - /* new message from DSP */ - ipcd = dsp_read(fuzzer, HSW_DSP_BAR, SHIM_IPCD); - if ((ipcd & SHIM_IPCD_BUSY) && - !(imrx & SHIM_IMRX_BUSY)) { - /* Mask Busy interrupt before return */ - dsp_update_bits_unlocked(fuzzer, HSW_DSP_BAR, - SHIM_IMRX, - SHIM_IMRX_BUSY, - SHIM_IMRX_BUSY); - - /* read mailbox */ - if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) { - fuzzer_ipc_crash(fuzzer, &data->dsp_box, - HSW_PANIC_OFFSET(ipcd) + MBOX_OFFSET); - } else { - fuzzer_ipc_msg_rx(fuzzer, &data->dsp_box); - } - - if (!data->boot_complete && fuzzer->boot_complete) { - data->boot_complete = 1; - hsw_cmd_done(fuzzer, SOF_IPC_HOST_REPLY); - pthread_cond_signal(&cond); - return IRQ_HANDLED; - } - } - - return IRQ_HANDLED; -} - -static int hsw_send_msg(struct fuzz *fuzzer, struct ipc_msg *msg) -{ - struct hsw_data *data = fuzzer->platform_data; - uint32_t cmd = msg->header; - - /* send the message */ - fuzzer_mailbox_write(fuzzer, &data->host_box, 0, msg->msg_data, - msg->msg_size); - - dsp_write(fuzzer, HSW_DSP_BAR, SHIM_IPCX, - cmd | SHIM_IPCX_BUSY); - - return 0; -} - -static int hsw_get_reply(struct fuzz *fuzzer, struct ipc_msg *msg) -{ - struct hsw_data *data = fuzzer->platform_data; - struct sof_ipc_reply reply; - int ret = 0; - uint32_t size; - - /* get reply */ - fuzzer_mailbox_read(fuzzer, &data->host_box, 0, &reply, sizeof(reply)); - - if (reply.error < 0) { - size = sizeof(reply); - ret = reply.error; - } else { - /* reply correct size ? */ - if (reply.hdr.size != msg->reply_size) { - fprintf(stderr, - "error: reply expected 0x%x got 0x%x bytes\n", - msg->reply_size, reply.hdr.size); - size = msg->reply_size; - ret = -EINVAL; - } else { - size = reply.hdr.size; - } - } - - /* read the message */ - if (msg->msg_data && size > 0) - fuzzer_mailbox_read(fuzzer, &data->host_box, 0, - msg->reply_data, size); - - return ret; -} - -/* called when we receive a message from qemu */ -static int bridge_cb(void *data, struct qemu_io_msg *msg) -{ - struct fuzz *fuzzer = (struct fuzz *)data; - - fprintf(stdout, "msg: id %d msg %d size %d type %d\n", - msg->id, msg->msg, msg->size, msg->type); - - switch (msg->type) { - case QEMU_IO_TYPE_IRQ: - /* IRQ from DSP */ - if (hsw_irq_handler(0, fuzzer) != IRQ_NONE) - hsw_irq_thread(0, fuzzer); - break; - default: - break; - } - - return 0; -} - -static int hsw_platform_init(struct fuzz *fuzzer, - struct fuzz_platform *platform) -{ - struct timespec timeout; - struct hsw_data *data; - struct timeval tp; - int i, bar; - int ret = 0; - - /* init private data */ - data = calloc(sizeof(*data), 1); - if (!data) - return -ENOMEM; - fuzzer->platform_data = data; - fuzzer->platform = platform; - - /* - * Hardcode offsets. - * TODO: read init host_box and dsp_box from fw_ready message - */ - data->host_box.offset = ADSP_BDW_DSP_MAILBOX_BASE + 0x400; - data->host_box.size = 0x400; - data->dsp_box.offset = ADSP_BDW_DSP_MAILBOX_BASE + 0x0; - data->dsp_box.size = 0x400; - - /* create SHM for memories and register regions */ - for (i = 0, bar = 0; i < platform->num_mem_regions; i++, bar++) { - data->bar[bar] = fuzzer_create_memory_region(fuzzer, bar, i); - if (!data->bar[bar]) { - fprintf(stderr, - "error: failed to create mem region %s\n", - platform->mem_region[i].name); - return -ENOMEM; - } - } - - for (i = 0; i < platform->num_reg_regions; i++, bar++) { - data->bar[bar] = fuzzer_create_io_region(fuzzer, bar, i); - if (!data->bar[bar]) { - fprintf(stderr, - "error: failed to create mem region %s\n", - platform->reg_region[i].name); - return -ENOMEM; - } - } - - /* initialise bridge to qemu */ - qemu_io_register_parent(platform->name, &bridge_cb, (void *)fuzzer); - - /* set boot wait timeout */ - gettimeofday(&tp, NULL); - timeout.tv_sec = tp.tv_sec; - timeout.tv_nsec = tp.tv_usec * 1000; - timeout.tv_sec += 5; - - /* first lock the boot wait mutex */ - pthread_mutex_lock(&data->mutex); - - /* now wait for mutex to be unlocked by boot ready message */ - while (!ret && !data->boot_complete) - ret = pthread_cond_timedwait(&cond, &data->mutex, &timeout); - - if (ret == ETIMEDOUT && !data->boot_complete) - fprintf(stderr, "error: DSP boot timeout\n"); - - pthread_mutex_unlock(&data->mutex); - - return ret; -} - -static void hsw_platform_free(struct fuzz *fuzzer) -{ - struct hsw_data *data = fuzzer->platform_data; - - fuzzer_free_regions(fuzzer); - free(data); -} - -static void hsw_fw_ready(struct fuzz *fuzzer) -{ - struct hsw_data *data = fuzzer->platform_data; - struct sof_ipc_fw_ready fw_ready; - struct sof_ipc_fw_version version; - - /* read fw_ready data from mailbox */ - fuzzer_mailbox_read(fuzzer, &data->dsp_box, 0, - &fw_ready, sizeof(fw_ready)); - - /* TODO read from FW */ - fprintf(stdout, "ipc: host box 0x%x size 0x%x\n", - data->host_box.offset, - data->host_box.size); - fprintf(stdout, "ipc: dsp box 0x%x size 0x%x\n", - data->dsp_box.offset, - data->dsp_box.size); - - version = fw_ready.version; - fprintf(stdout, "ipc: FW version major: %d minor: %d tag: %s\n", - version.major, version.minor, version.tag); -} - -struct fuzz_platform hsw_platform = { - .name = "hsw", - .send_msg = hsw_send_msg, - .get_reply = hsw_get_reply, - .init = hsw_platform_init, - .free = hsw_platform_free, - .mailbox_read = mailbox_read, - .mailbox_write = mailbox_write, - .fw_ready = hsw_fw_ready, - .num_mem_regions = ARRAY_SIZE(hsw_mem), - .mem_region = hsw_mem, - .num_reg_regions = ARRAY_SIZE(hsw_io), - .reg_region = hsw_io, -}; - -struct fuzz_platform bdw_platform = { - .name = "bdw", - .send_msg = hsw_send_msg, - .get_reply = hsw_get_reply, - .init = hsw_platform_init, - .free = hsw_platform_free, - .mailbox_read = mailbox_read, - .mailbox_write = mailbox_write, - .fw_ready = hsw_fw_ready, - .num_mem_regions = ARRAY_SIZE(bdw_mem), - .mem_region = bdw_mem, - .num_reg_regions = ARRAY_SIZE(bdw_io), - .reg_region = bdw_io, -}; diff --git a/tools/fuzzer/platform/shim.h b/tools/fuzzer/platform/shim.h deleted file mode 100644 index 5e8355606e60..000000000000 --- a/tools/fuzzer/platform/shim.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * SPDX-License-Identifier: (BSD-3-Clause) - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - */ - -#ifndef __SOF_INTEL_SHIM_H -#define __SOF_INTEL_SHIM_H - -#define BIT(x) (1 << x) -#define BIT_ULL(x) (1ULL << x) - -#define SHIM_OFFSET 0 - -/* - * SHIM registers for HSW, BDW - */ - -#define SHIM_CSR (SHIM_OFFSET + 0x00) -#define SHIM_PISR (SHIM_OFFSET + 0x08) -#define SHIM_PIMR (SHIM_OFFSET + 0x10) -#define SHIM_ISRX (SHIM_OFFSET + 0x18) -#define SHIM_ISRD (SHIM_OFFSET + 0x20) -#define SHIM_IMRX (SHIM_OFFSET + 0x28) -#define SHIM_IMRD (SHIM_OFFSET + 0x30) -#define SHIM_IPCX (SHIM_OFFSET + 0x38) -#define SHIM_IPCD (SHIM_OFFSET + 0x40) -#define SHIM_ISRSC (SHIM_OFFSET + 0x48) -#define SHIM_ISRLPESC (SHIM_OFFSET + 0x50) -#define SHIM_IMRSC (SHIM_OFFSET + 0x58) -#define SHIM_IMRLPESC (SHIM_OFFSET + 0x60) -#define SHIM_IPCSC (SHIM_OFFSET + 0x68) -#define SHIM_IPCLPESC (SHIM_OFFSET + 0x70) -#define SHIM_CLKCTL (SHIM_OFFSET + 0x78) -#define SHIM_CSR2 (SHIM_OFFSET + 0x80) -#define SHIM_LTRC (SHIM_OFFSET + 0xE0) -#define SHIM_HMDC (SHIM_OFFSET + 0xE8) - -#define SHIM_PWMCTRL 0x1000 - -/* - * SST SHIM register bits for HSW, BDW - * Register bit naming and functionality can differ between devices. - */ - -/* CSR / CS */ -#define SHIM_CSR_RST BIT(1) -#define SHIM_CSR_SBCS0 BIT(2) -#define SHIM_CSR_SBCS1 BIT(3) -#define SHIM_CSR_DCS(x) ((x) << 4) -#define SHIM_CSR_DCS_MASK (0x7 << 4) -#define SHIM_CSR_STALL BIT(10) -#define SHIM_CSR_S0IOCS BIT(21) -#define SHIM_CSR_S1IOCS BIT(23) -#define SHIM_CSR_LPCS BIT(31) -#define SHIM_CSR_24MHZ_LPCS \ - (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1 | SHIM_CSR_LPCS) -#define SHIM_CSR_24MHZ_NO_LPCS (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1) - -/* ISRX / ISC */ -#define SHIM_ISRX_BUSY BIT(1) -#define SHIM_ISRX_DONE BIT(0) - -/* ISRD / ISD */ -#define SHIM_ISRD_BUSY BIT(1) -#define SHIM_ISRD_DONE BIT(0) - -/* IMRX / IMC */ -#define SHIM_IMRX_BUSY BIT(1) -#define SHIM_IMRX_DONE BIT(0) - -/* IMRD / IMD */ -#define SHIM_IMRD_DONE BIT(0) -#define SHIM_IMRD_BUSY BIT(1) -#define SHIM_IMRD_SSP0 BIT(16) -#define SHIM_IMRD_DMAC0 BIT(21) -#define SHIM_IMRD_DMAC1 BIT(22) -#define SHIM_IMRD_DMAC (SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1) - -/* IPCX / IPCC */ -#define SHIM_IPCX_DONE BIT(30) -#define SHIM_IPCX_BUSY BIT(31) - -/* IPCD */ -#define SHIM_IPCD_DONE BIT(30) -#define SHIM_IPCD_BUSY BIT(31) - -/* CLKCTL */ -#define SHIM_CLKCTL_SMOS(x) ((x) << 24) -#define SHIM_CLKCTL_MASK (3 << 24) -#define SHIM_CLKCTL_DCPLCG BIT(18) -#define SHIM_CLKCTL_SCOE1 BIT(17) -#define SHIM_CLKCTL_SCOE0 BIT(16) - -/* CSR2 / CS2 */ -#define SHIM_CSR2_SDFD_SSP0 BIT(1) -#define SHIM_CSR2_SDFD_SSP1 BIT(2) - -/* LTRC */ -#define SHIM_LTRC_VAL(x) ((x) << 0) - -/* HMDC */ -#define SHIM_HMDC_HDDA0(x) ((x) << 0) -#define SHIM_HMDC_HDDA1(x) ((x) << 7) -#define SHIM_HMDC_HDDA_E0_CH0 1 -#define SHIM_HMDC_HDDA_E0_CH1 2 -#define SHIM_HMDC_HDDA_E0_CH2 4 -#define SHIM_HMDC_HDDA_E0_CH3 8 -#define SHIM_HMDC_HDDA_E1_CH0 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH0) -#define SHIM_HMDC_HDDA_E1_CH1 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH1) -#define SHIM_HMDC_HDDA_E1_CH2 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH2) -#define SHIM_HMDC_HDDA_E1_CH3 SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH3) -#define SHIM_HMDC_HDDA_E0_ALLCH \ - (SHIM_HMDC_HDDA_E0_CH0 | SHIM_HMDC_HDDA_E0_CH1 | \ - SHIM_HMDC_HDDA_E0_CH2 | SHIM_HMDC_HDDA_E0_CH3) -#define SHIM_HMDC_HDDA_E1_ALLCH \ - (SHIM_HMDC_HDDA_E1_CH0 | SHIM_HMDC_HDDA_E1_CH1 | \ - SHIM_HMDC_HDDA_E1_CH2 | SHIM_HMDC_HDDA_E1_CH3) - -/* Audio DSP PCI registers */ -#define PCI_VDRTCTL0 0xa0 -#define PCI_VDRTCTL1 0xa4 -#define PCI_VDRTCTL2 0xa8 -#define PCI_VDRTCTL3 0xaC - -/* VDRTCTL0 */ -#define PCI_VDRTCL0_D3PGD BIT(0) -#define PCI_VDRTCL0_D3SRAMPGD BIT(1) -#define PCI_VDRTCL0_DSRAMPGE_SHIFT 12 -#define PCI_VDRTCL0_DSRAMPGE_MASK GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\ - PCI_VDRTCL0_DSRAMPGE_SHIFT) -#define PCI_VDRTCL0_ISRAMPGE_SHIFT 2 -#define PCI_VDRTCL0_ISRAMPGE_MASK GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\ - PCI_VDRTCL0_ISRAMPGE_SHIFT) - -/* VDRTCTL2 */ -#define PCI_VDRTCL2_DCLCGE BIT(1) -#define PCI_VDRTCL2_DTCGE BIT(10) -#define PCI_VDRTCL2_APLLSE_MASK BIT(31) - -/* PMCS */ -#define PCI_PMCS 0x84 -#define PCI_PMCS_PS_MASK 0x3 - -#endif diff --git a/tools/topology/topology1/CMakeLists.txt b/tools/topology/topology1/CMakeLists.txt index 402e8e3caa1a..068c44c2d1f7 100644 --- a/tools/topology/topology1/CMakeLists.txt +++ b/tools/topology/topology1/CMakeLists.txt @@ -21,8 +21,6 @@ add_custom_command(OUTPUT abi.h ) set(TPLGS - "sof-bdw-nocodec\;sof-bdw-nocodec" - ## HDaudio codec topologies "sof-hda-generic\;sof-hda-generic\;-DCHANNELS=0\;-DHSPROC=volume\;-DDYNAMIC=1" "sof-hda-generic\;sof-hda-generic-1ch\;-DCHANNELS=2\;-DHSPROC=volume\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1" @@ -37,9 +35,6 @@ set(TPLGS "sof-hda-generic-idisp\;sof-hda-generic-idisp-2ch\;-DCHANNELS=2\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1" "sof-hda-generic-idisp\;sof-hda-generic-idisp-4ch\;-DCHANNELS=4\;-DDMICPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_48khz.m4\;-DDMIC16KPROC_FILTER1=eq_iir_coef_highpass_40hz_20db_16khz.m4\;-DDYNAMIC=1" "sof-apl-keyword-detect\;sof-apl-keyword-detect" - "sof-bdw-codec\;sof-bdw-rt286\;-DCODEC=RT286" - "sof-bdw-codec\;sof-bdw-rt5640\;-DCODEC=RT5640" - "sof-bdw-codec\;sof-bdw-rt5677\;-DCODEC=RT5677" "sof-cnl-rt274\;sof-cnl-rt274" "sof-apl-tdf8532\;sof-apl-tdf8532" "sof-apl-pcm512x\;sof-apl-pcm512x\;-DFSYNC=48000" diff --git a/tools/topology/topology1/platform/intel/bdw.m4 b/tools/topology/topology1/platform/intel/bdw.m4 deleted file mode 100644 index 1af669996969..000000000000 --- a/tools/topology/topology1/platform/intel/bdw.m4 +++ /dev/null @@ -1,31 +0,0 @@ -# -# Broadwell differentiation for pipelines and components -# - -include(`memory.m4') - -dnl Memory capabilities for diferent buffer types on Broadwell -define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) -define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) -define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) -define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) - -# Low Latency PCM Configuration -W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "50000"')) - -W_DATA(pipe_ll_schedule_plat, pipe_ll_schedule_plat_tokens) - -# Media PCM Configuration -W_VENDORTUPLES(pipe_media_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "100000"')) - -W_DATA(pipe_media_schedule_plat, pipe_media_schedule_plat_tokens) - -# Tone Signal Generator Configuration -W_VENDORTUPLES(pipe_tone_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "200000"')) - -W_DATA(pipe_tone_schedule_plat, pipe_tone_schedule_plat_tokens) - -# DAI schedule Configuration - scheduled by IRQ -W_VENDORTUPLES(pipe_dai_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "5000"')) - -W_DATA(pipe_dai_schedule_plat, pipe_dai_schedule_plat_tokens) diff --git a/tools/topology/topology1/platform/intel/hsw.m4 b/tools/topology/topology1/platform/intel/hsw.m4 deleted file mode 100644 index c096732a7cc5..000000000000 --- a/tools/topology/topology1/platform/intel/hsw.m4 +++ /dev/null @@ -1,31 +0,0 @@ -# -# Haswell differentiation for pipelines and components -# - -include(`memory.m4') - -dnl Memory capabilities for diferent buffer types on Haswell -define(`PLATFORM_DAI_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) -define(`PLATFORM_HOST_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) -define(`PLATFORM_PASS_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_DMA, MEM_CAP_CACHE)) -define(`PLATFORM_COMP_MEM_CAP', MEMCAPS(MEM_CAP_RAM, MEM_CAP_CACHE)) - -# Low Latency PCM Configuration -W_VENDORTUPLES(pipe_ll_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "50000"')) - -W_DATA(pipe_ll_schedule_plat, pipe_ll_schedule_plat_tokens) - -# Media PCM Configuration -W_VENDORTUPLES(pipe_media_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "100000"')) - -W_DATA(pipe_media_schedule_plat, pipe_media_schedule_plat_tokens) - -# Tone Signal Generator Configuration -W_VENDORTUPLES(pipe_tone_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "200000"')) - -W_DATA(pipe_tone_schedule_plat, pipe_tone_schedule_plat_tokens) - -# DAI schedule Configuration - scheduled by IRQ -W_VENDORTUPLES(pipe_dai_schedule_plat_tokens, sof_sched_tokens, LIST(` ', `SOF_TKN_SCHED_MIPS "5000"')) - -W_DATA(pipe_dai_schedule_plat, pipe_dai_schedule_plat_tokens) diff --git a/tools/topology/topology1/sof-bdw-codec.m4 b/tools/topology/topology1/sof-bdw-codec.m4 deleted file mode 100644 index c014cce7f3df..000000000000 --- a/tools/topology/topology1/sof-bdw-codec.m4 +++ /dev/null @@ -1,103 +0,0 @@ -# -`# Topology for generic bdw board with' CODEC -# - -# Include topology builder -include(`pipeline.m4') -include(`utils.m4') -include(`dai.m4') -include(`ssp.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include Broadwell DSP configuration -include(`platform/intel/bdw.m4') - - -define(PIPE_NAME, pipe-bdw-`'CODEC`') - -# -# Define the pipelines -# -# PCM0 ----> volume ---------------+ -# |--low latency mixer ----> volume ----> SSP0 -# PCM1 -----> volume -----> SRC ---+ -# -# PCM0 <---- Volume <---- SSP0 -# - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# 1000us deadline on core 0 with priority 1 -PIPELINE_PCM_ADD(sof/pipe-low-latency-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-low-latency-capture.m4, - 2, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# -# DAI configuration -# -# SSP port 0 is our only pipeline DAI -# - -# playback DAI is SSP0 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 0, Codec, - PIPELINE_SOURCE_1, 2, s24le, - 1000, 1, 0, SCHEDULE_TIME_DOMAIN_DMA) - -# PCM Media Playback pipeline 3 on PCM 1 using max 2 channels of s32le. -# 2000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-pcm-media.m4, - 3, 1, 2, s32le, - 2000, 0, 0, - 8000, 96000, 48000, - SCHEDULE_TIME_DOMAIN_DMA, - PIPELINE_PLAYBACK_SCHED_COMP_1) - -# Connect pipelines together -SectionGraph."PIPE_NAME" { - index "0" - - lines [ - # media 0 - dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_3) - ] -} - -# capture DAI is SSP0 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 2, SSP, 0, Codec, - PIPELINE_SINK_2, 2, s24le, - 1000, 0, 0, SCHEDULE_TIME_DOMAIN_DMA) - -# PCM Low Latency -PCM_DUPLEX_ADD(Low Latency, 0, PIPELINE_PCM_1, PIPELINE_PCM_2) - -# -# BE configurations - overrides config in ACPI if present -# -DAI_CONFIG(SSP, 0, 0, Codec, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24000000, codec_mclk_in), - SSP_CLOCK(bclk, 2400000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 25, 3, 3), - SSP_CONFIG_DATA(SSP, 0, 24))) - -dnl CODEC is defined and will be expanded, need to undefine it before use -undefine(`CODEC') -VIRTUAL_WIDGET(SSP0 CODEC OUT, output, 0) -VIRTUAL_WIDGET(SSP0 CODEC IN, input, 1) -VIRTUAL_WIDGET(DSP Capture, input, 2) diff --git a/tools/topology/topology1/sof-bdw-nocodec.m4 b/tools/topology/topology1/sof-bdw-nocodec.m4 deleted file mode 100644 index 84dbe14a8de0..000000000000 --- a/tools/topology/topology1/sof-bdw-nocodec.m4 +++ /dev/null @@ -1,93 +0,0 @@ -# -# Topology for generic Broadwell board with no codec. -# - -# Include topology builder -include(`pipeline.m4') -include(`utils.m4') -include(`dai.m4') -include(`ssp.m4') - -# Include TLV library -include(`common/tlv.m4') - -# Include Token library -include(`sof/tokens.m4') - -# Include DSP configuration -include(`platform/intel/bdw.m4') - -# -# Define the pipelines -# -# PCM0 ----> volume ---------------+ -# |--low latency mixer ----> volume ----> SSP0 (NoCodec) -# PCM1 -----> volume ----> SRC ----+ -# -# PCM0 <---- Volume <---- SSP0 (NoCodec) -# - -# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-low-latency-playback.m4, - 1, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# Volume switch capture pipeline 2 on PCM 0 using max 2 channels of s32le. -# 1000us deadline with priority 0 on core 0 -PIPELINE_PCM_ADD(sof/pipe-volume-switch-capture.m4, - 2, 0, 2, s32le, - 1000, 0, 0, - 48000, 48000, 48000) - -# -# DAI configuration -# -# SSP port 2 is our only pipeline DAI -# - -# playback DAI is SSP0 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-playback.m4, - 1, SSP, 0, NoCodec-0, - PIPELINE_SOURCE_1, 2, s24le, - 1000, 0, 0) - -# PCM Media Playback pipeline 3 on PCM 1 using max 2 channels of s32le. -# 1000us deadline on core 0 with priority 1 -PIPELINE_PCM_ADD(sof/pipe-pcm-media.m4, - 3, 1, 2, s32le, - 1000, 1, 0, - 8000, 48000, 48000, - 0, PIPELINE_PLAYBACK_SCHED_COMP_1) - -# Connect pipelines together -SectionGraph."media-pipe" { - index "0" - - lines [ - # media 0 - dapm(PIPELINE_MIXER_1, PIPELINE_SOURCE_3) - ] -} - -# capture DAI is SSP0 using 2 periods -# Buffers use s24le format, 1000us deadline with priority 0 on core 0 -DAI_ADD(sof/pipe-dai-capture.m4, - 2, SSP, 0, NoCodec-0, - PIPELINE_SINK_2, 2, s24le, - 1000, 0, 0) - -# PCM Low Latency -PCM_DUPLEX_ADD(Low Latency, 0, PIPELINE_PCM_1, PIPELINE_PCM_2) - -# -# BE configurations - overrides config in ACPI if present -# -DAI_CONFIG(SSP, 0, 0, NoCodec-0, - SSP_CONFIG(I2S, SSP_CLOCK(mclk, 24000000, codec_mclk_in), - SSP_CLOCK(bclk, 2400000, codec_slave), - SSP_CLOCK(fsync, 48000, codec_slave), - SSP_TDM(2, 25, 3, 3), - SSP_CONFIG_DATA(SSP, 0, 24, 0, SSP_QUIRK_LBM))) diff --git a/zephyr/include/rtos/interrupt.h b/zephyr/include/rtos/interrupt.h index dcd8805c6f42..6a8c9890e699 100644 --- a/zephyr/include/rtos/interrupt.h +++ b/zephyr/include/rtos/interrupt.h @@ -48,7 +48,7 @@ static inline void interrupt_unregister(uint32_t irq, const void *arg) } /* - * CAVS IRQs are multilevel whereas BDW is DSP level only. + * CAVS IRQs are multilevel */ static inline int interrupt_get_irq(unsigned int irq, const char *cascade) {