This project aims to convert the video output of old KC85/4 computer systems into a VGA signal for display on a modern monitor. The hosts video signals are sampled from the mainboard into an SRAM using an Xilinx Spartan 3A FPGA. The FPGA also generates the VGA video signal from the sampled image. A PIC32MX250F128B contains the FPGA bitstream and loads it during power-up. Additionally, the PIC32 serves as a USB bridge to the FPGA.
The input clock of 48 MHz is being fed into a DCM to generate the video clock of 108 MHz. This clock drives the states of all other modules inside the FPGA (KCVIDEO_INTERFACE, PIC32_INTERFACE, ROM, SRAM_INTERFACE, VGA_OUTPUT and the FIFOs).
The module KCVIDEO_INTERFACE FPGA has the purpose to pull the pixel data off the mainboard while the KC85 is generating its video signal. It taps into the color and brightness signals (R, G, B, EX, EZ) as well as the clock signals (KC_CLK, KC_HSYNC, KC_VSYNC).
To enhance the fault tolerance, the clock and synchronization signals are fed through glitch filters and edge detectors. A falling edge on KC_VSYNC starts a new frame which resets the current line number and SRAM address. A falling edge on KC_HSYNC resets the column counter. On every rising edge of the pixel clock KC_CLK all five pixel data bits are read into a temporary register and the SRAM address ist incremented. After three pixels have been read, these pixels are combined with the 16 bit SRAM address to form a 31 bit wide data word which is being fed into a FIFO. This FIFO buffers 512 words and serves as a synchronization object between the KCVIDEO_INTERFACE and the SRAM_INTERFACE.
This module checks the FIFOs connected to KCVIDEO_INTERFACE and VGA_OUTPUT while preferring the VGA_OUTPUT FIFO. The VGA_OUTPUT module initiates a data transfer by writing a new address into the SRAM_INTERFACE. In return, the SRAM_INTERFACE starts filling the FIFO with the content of one video line. If no VGA data transfer is active, the SRAM_INTERFACE module checks the other FIFO for new pixel data, which is then written into the SRAM.
The VGA_OUTPUT module generates the timing signals to create a valid VGA signal of 1280 by 1024 pixels. This mode was chosen because the pixels are integer divisible by the resolution of the KC85 (320 by 256). At the beginning of each line the module requests pixel data from the SRAM_INTERFACE by writing a new address. The FIFO is then starting to fill and at the end of the horizontal sync pulse the first pixels are available to be written to the outputs. The KC pixel data is being mapped to a fixed color space of 4 bit R, G and B values.
This module allows the PIC32 microcontroller to access the SRAM. Since the PIC32MX250F128B does not support USB High Speed, we're limited to approximately 1 megabyte per second which is close, but not enough to transport the 1.28 MB/s image stream (5 bits, 320 columns, 256 rows, 25 frames). An experimental video streaming implementation might be available later in the design process.
tbd