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Support for Many-Integrated-Core accelerators #313
Is there any thrust support in the works for Intel's MIC architectures? It seems like such an implementation would be possible (icpc for MIC can handle simultaneous x86_64 + MIC code compilation with full C++ template support) and even relatively simple (MIC supports TBB, so all thrust would need to add under the hood would be host<->device communication). On the other hand, the target audience would probably be much smaller than for the CUDA or plain-TBB backends; MIC cards are never going to be as popular as high-end video cards or multi-core CPUs.