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KabylakeOpenBoardPkg: Add TBT support.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Vishal P Adodariya <vishal.p.adodariya@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
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jyao1 committed Mar 26, 2018
1 parent 062cc36 commit 62f1e1e58965702030f722dcdf6de58998cf08a1
Showing with 9,817 additions and 4 deletions.
  1. +12 −1 Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl
  2. +358 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c
  3. +136 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h
  4. +66 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf
  5. +410 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3SptPcieTbt.asl
  6. +1,909 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl
  7. +66 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvs.asl
  8. +70 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvsAreaDef.h
  9. +53 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtPolicyLib.h
  10. +47 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtPolicyLib.h
  11. +247 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Include/Library/TbtCommonLib.h
  12. +36 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolicy.h
  13. +114 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiDTbtInitLib.h
  14. +47 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiTbtCommonInitLib.h
  15. +117 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbtPolicy.h
  16. +48 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvsArea.h
  17. +28 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h
  18. +84 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Include/TbtPolicyCommonDefinition.h
  19. +167 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.c
  20. +73 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf
  21. +28 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h
  22. +321 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.c
  23. +69 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf
  24. +210 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.c
  25. +62 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf
  26. +23 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h
  27. +572 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.c
  28. +48 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf
  29. +233 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c
  30. +54 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
  31. +216 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.c
  32. +50 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
  33. +1,615 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.c
  34. +185 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.h
  35. +1,771 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c
  36. +83 −0 Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
  37. +22 −0 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
  38. +82 −1 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
  39. +1 −0 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc
  40. +31 −0 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
  41. +53 −2 Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec
@@ -25,6 +25,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
External(\_SB.PCI0.PEG1.HPME, MethodObj)
External(\_SB.PCI0.PEG2.HPME, MethodObj)
External(\_GPE.AL6F, MethodObj)
External(\_SB.THDR, MethodObj)
External(\_GPE.P0L6, MethodObj)
External(\_GPE.P1L6, MethodObj)
External(\_GPE.P2L6, MethodObj)
@@ -34,6 +35,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
External(P0WK)
External(P1WK)
External(P2WK)
External(\CPG0)
External(\RPS0)
External(\RPT0)
External(\_PR.HWPI, IntObj)
External(\_PR.DTSI, IntObj)

@@ -841,5 +845,12 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
\_SB.PCI0.GFX0.GSCI() // Handle the SWSCI
}
}

//
// BIOS Needs to implement appropriate handler based on CIO_PLUG_EVENT GPIO
// This is generic 2-tier GPIO handler
//
Method(_L6F)
{
\_SB.THDR(\CPG0,\RPS0,\RPT0) // Check for TBT Hotplug Handler event (2-tier GPI GPE event architecture)
}
}
@@ -0,0 +1,358 @@
/** @file
Pci Hotplug Driver : This file will perform specific PCI-EXPRESS
Devics resource configuration.
Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php.
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/

//
// Statements that include other files
//
#include "PciHotPlug.h"
#include <Ppi/SiPolicy.h>
#include <TbtBoardInfo.h>
#include <Library/PchPcieRpLib.h>
#include <Library/TbtCommonLib.h>

#define PCIE_NUM (20)
#define PEG_NUM (3)
#define PADDING_BUS (1)
#define PADDING_NONPREFETCH_MEM (1)
#define PADDING_PREFETCH_MEM (1)
#define PADDING_IO (1)
#define PADDING_NUM (PADDING_BUS + PADDING_NONPREFETCH_MEM + PADDING_PREFETCH_MEM + PADDING_IO)

GLOBAL_REMOVE_IF_UNREFERENCED EFI_HPC_LOCATION mPcieLocation[PCIE_NUM + PEG_NUM];

GLOBAL_REMOVE_IF_UNREFERENCED UINTN mHpcCount = 0;

GLOBAL_REMOVE_IF_UNREFERENCED PCIE_HOT_PLUG_DEVICE_PATH mHotplugPcieDevicePathTemplate = {
ACPI,
PCI(0xFF, 0xFF), // Dummy Device no & Function no
END
};

/**
Entry point for the driver.
This routine reads the PlatformType GPI on FWH and produces a protocol
to be consumed by the chipset driver to effect those settings.
@param[in] ImageHandle An image handle.
@param[in] SystemTable A pointer to the system table.
@retval EFI_SUCCESS.
**/
EFI_STATUS
EFIAPI
PciHotPlug (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
PCI_HOT_PLUG_INSTANCE *PciHotPlug;
UINTN Index;
UINTN RpDev;
UINTN RpFunc;
PCIE_HOT_PLUG_DEVICE_PATH *HotplugPcieDevicePath;
UINT32 PcieRootPortHpeData = 0;

DEBUG ((DEBUG_INFO, "PciHotPlug Entry\n"));

PcieRootPortHpeData = PcdGet32 (PcdPchPcieRootPortHpe);
//
// PCH Rootports Hotplug device path creation
//
for (Index = 0; Index < PCIE_NUM; Index++) {
if (((PcieRootPortHpeData >> Index) & BIT0) == BIT0) { // Check the Rootport no's hotplug is set
Status = GetPchPcieRpDevFun (Index, &RpDev, &RpFunc); // Get the actual device/function no corresponding to the Rootport no provided
ASSERT_EFI_ERROR (Status);

HotplugPcieDevicePath = NULL;
HotplugPcieDevicePath = AllocatePool (sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
ASSERT (HotplugPcieDevicePath != NULL);
if (HotplugPcieDevicePath == NULL) {
return EFI_OUT_OF_RESOURCES;
}
CopyMem (HotplugPcieDevicePath, &mHotplugPcieDevicePathTemplate, sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
HotplugPcieDevicePath->PciRootPortNode.Device = (UINT8) RpDev; // Update real Device no
HotplugPcieDevicePath->PciRootPortNode.Function = (UINT8) RpFunc; // Update real Function no

mPcieLocation[mHpcCount].HpcDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
mPcieLocation[mHpcCount].HpbDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
mHpcCount++;

DEBUG ((DEBUG_INFO, "(%02d) PciHotPlug (PCH RP#) : Bus 0x00, Device 0x%x, Function 0x%x is added to the Hotplug Device Path list \n", mHpcCount, RpDev, RpFunc));
}
}


PciHotPlug = AllocatePool (sizeof (PCI_HOT_PLUG_INSTANCE));
ASSERT (PciHotPlug != NULL);
if (PciHotPlug == NULL) {
return EFI_OUT_OF_RESOURCES;
}

//
// Initialize driver private data.
//
ZeroMem (PciHotPlug, sizeof (PCI_HOT_PLUG_INSTANCE));

PciHotPlug->Signature = PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE;
PciHotPlug->HotPlugInitProtocol.GetRootHpcList = GetRootHpcList;
PciHotPlug->HotPlugInitProtocol.InitializeRootHpc = InitializeRootHpc;
PciHotPlug->HotPlugInitProtocol.GetResourcePadding = GetResourcePadding;

Status = gBS->InstallProtocolInterface (
&PciHotPlug->Handle,
&gEfiPciHotPlugInitProtocolGuid,
EFI_NATIVE_INTERFACE,
&PciHotPlug->HotPlugInitProtocol
);
ASSERT_EFI_ERROR (Status);

return EFI_SUCCESS;
}


/**
This procedure returns a list of Root Hot Plug controllers that require
initialization during boot process
@param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
@param[out] HpcCount The number of Root HPCs returned.
@param[out] HpcList The list of Root HPCs. HpcCount defines the number of elements in this list.
@retval EFI_SUCCESS.
**/
EFI_STATUS
EFIAPI
GetRootHpcList (
IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
OUT UINTN *HpcCount,
OUT EFI_HPC_LOCATION **HpcList
)
{
*HpcCount = mHpcCount;
*HpcList = mPcieLocation;

return EFI_SUCCESS;
}


/**
This procedure Initializes one Root Hot Plug Controller
This process may casue initialization of its subordinate buses
@param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
@param[in] HpcDevicePath The Device Path to the HPC that is being initialized.
@param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
@param[in] Event The event that should be signaled when the Hot Plug Controller initialization is complete. Set to NULL if the caller wants to wait until the entire initialization process is complete. The event must be of the type EFI_EVT_SIGNAL.
@param[out] HpcState The state of the Hot Plug Controller hardware. The type EFI_Hpc_STATE is defined in section 3.1.
@retval EFI_SUCCESS.
**/
EFI_STATUS
EFIAPI
InitializeRootHpc (
IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
IN UINT64 HpcPciAddress,
IN EFI_EVENT Event, OPTIONAL
OUT EFI_HPC_STATE *HpcState
)
{
if (Event) {
gBS->SignalEvent (Event);
}

*HpcState = EFI_HPC_STATE_INITIALIZED;

return EFI_SUCCESS;
}


/**
Returns the resource padding required by the PCI bus that is controlled by the specified Hot Plug Controller.
@param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol. initialized.
@param[in] HpcDevicePath The Device Path to the Hot Plug Controller.
@param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
@param[out] HpcState The state of the Hot Plug Controller hardware. The type EFI_HPC_STATE is defined in section 3.1.
@param[out] Padding This is the amount of resource padding required by the PCI bus under the control of the specified Hpc. Since the caller does not know the size of this buffer, this buffer is allocated by the callee and freed by the caller.
@param[out] Attribute Describes how padding is accounted for.
@retval EFI_SUCCESS.
**/
EFI_STATUS
EFIAPI
GetResourcePadding (
IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
IN UINT64 HpcPciAddress,
OUT EFI_HPC_STATE *HpcState,
OUT VOID **Padding,
OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes
)
{
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource;
EFI_STATUS Status;
UINT8 RsvdExtraBusNum = 0;
UINT16 RsvdPcieMegaMem = 10;
UINT8 PcieMemAddrRngMax = 0;
UINT16 RsvdPciePMegaMem = 10;
UINT8 PciePMemAddrRngMax = 0;
UINT8 RsvdTbtExtraBusNum = 0;
UINT16 RsvdTbtPcieMegaMem = 10;
UINT8 TbtPcieMemAddrRngMax = 0;
UINT16 RsvdTbtPciePMegaMem = 10;
UINT8 TbtPciePMemAddrRngMax = 0;
UINT8 RsvdPcieKiloIo = 4;
BOOLEAN SetResourceforTbt = FALSE;
UINTN RpIndex;
UINTN RpDev;
UINTN RpFunc;

DEBUG ((DEBUG_INFO, "GetResourcePadding : Start \n"));

PaddingResource = AllocatePool (PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
ASSERT (PaddingResource != NULL);
if (PaddingResource == NULL) {
return EFI_OUT_OF_RESOURCES;
}

*Padding = (VOID *) PaddingResource;

RpDev = (UINTN) ((HpcPciAddress >> 16) & 0xFF);
RpFunc = (UINTN) ((HpcPciAddress >> 8) & 0xFF);

// Get the actual Rootport no corresponding to the device/function no provided
if (RpDev == SA_PEG_DEV_NUM) {
// PEG
RpIndex = PCIE_NUM + RpFunc;
DEBUG ((DEBUG_INFO, "GetResourcePadding : PEG Rootport no %02d Bus 0x00, Device 0x%x, Function 0x%x \n", (RpIndex-PCIE_NUM), RpDev, RpFunc));
} else {
// PCH
Status = GetPchPcieRpNumber (RpDev, RpFunc, &RpIndex);
DEBUG ((DEBUG_INFO, "GetResourcePadding : PCH Rootport no %02d Bus 0x00, Device 0x%x, Function 0x%x \n", RpIndex, RpDev, RpFunc));
}

GetRootporttoSetResourcesforTbt(RpIndex, &RsvdTbtExtraBusNum, &RsvdTbtPcieMegaMem ,&TbtPcieMemAddrRngMax ,&RsvdTbtPciePMegaMem ,&TbtPciePMemAddrRngMax, &SetResourceforTbt);
if (SetResourceforTbt) {
RsvdExtraBusNum = RsvdTbtExtraBusNum;
RsvdPcieMegaMem = RsvdTbtPcieMegaMem;
PcieMemAddrRngMax = TbtPcieMemAddrRngMax;
RsvdPciePMegaMem = RsvdTbtPciePMegaMem;
PciePMemAddrRngMax = TbtPciePMemAddrRngMax;
}

//
// Padding for bus
//
ZeroMem (PaddingResource, PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
*Attributes = EfiPaddingPciBus;

PaddingResource->Desc = 0x8A;
PaddingResource->Len = 0x2B;
PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
PaddingResource->GenFlag = 0x0;
PaddingResource->SpecificFlag = 0;
PaddingResource->AddrRangeMin = 0;
PaddingResource->AddrRangeMax = 0;
PaddingResource->AddrLen = RsvdExtraBusNum;

//
// Padding for non-prefetchable memory
//
PaddingResource++;
PaddingResource->Desc = 0x8A;
PaddingResource->Len = 0x2B;
PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
PaddingResource->GenFlag = 0x0;
if (SetResourceforTbt) {
PaddingResource->AddrSpaceGranularity = 32;
} else {
PaddingResource->AddrSpaceGranularity = 32;
}
PaddingResource->SpecificFlag = 0;
//
// Pad non-prefetchable
//
PaddingResource->AddrRangeMin = 0;
PaddingResource->AddrLen = RsvdPcieMegaMem * 0x100000;
if (SetResourceforTbt) {
PaddingResource->AddrRangeMax = (1 << PcieMemAddrRngMax) - 1;
} else {
PaddingResource->AddrRangeMax = 1;
}

//
// Padding for prefetchable memory
//
PaddingResource++;
PaddingResource->Desc = 0x8A;
PaddingResource->Len = 0x2B;
PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
PaddingResource->GenFlag = 0x0;
if (SetResourceforTbt) {
PaddingResource->AddrSpaceGranularity = 32;
} else {
PaddingResource->AddrSpaceGranularity = 32;
}
PaddingResource->SpecificFlag = 06;
//
// Padding for prefetchable memory
//
PaddingResource->AddrRangeMin = 0;
if (SetResourceforTbt) {
PaddingResource->AddrLen = RsvdPciePMegaMem * 0x100000;
} else {
PaddingResource->AddrLen = RsvdPcieMegaMem * 0x100000;
}
//
// Pad 16 MB of MEM
//
if (SetResourceforTbt) {
PaddingResource->AddrRangeMax = (1 << PciePMemAddrRngMax) - 1;
} else {
PaddingResource->AddrRangeMax = 1;
}
//
// Alignment
//
// Padding for I/O
//
PaddingResource++;
PaddingResource->Desc = 0x8A;
PaddingResource->Len = 0x2B;
PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
PaddingResource->GenFlag = 0x0;
PaddingResource->SpecificFlag = 0;
PaddingResource->AddrRangeMin = 0;
PaddingResource->AddrLen = RsvdPcieKiloIo * 0x400;
//
// Pad 4K of IO
//
PaddingResource->AddrRangeMax = 1;
//
// Alignment
//
// Terminate the entries.
//
PaddingResource++;
((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Desc = ACPI_END_TAG_DESCRIPTOR;
((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Checksum = 0x0;

*HpcState = EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED;

return EFI_SUCCESS;
}

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