diff --git a/targets/atlys_base.py b/targets/atlys_base.py index 952776ea..577da564 100644 --- a/targets/atlys_base.py +++ b/targets/atlys_base.py @@ -19,7 +19,7 @@ from liteeth.core.mac import LiteEthMAC from gateware import dna - +from targets.common import * class _CRG(Module): def __init__(self, platform, clk_freq): @@ -110,22 +110,6 @@ def __init__(self, platform, clk_freq): platform.add_period_constraint(self.cd_base50.clk, 20) -def _get_firmware_data(firmware_filename): - data = [] - try: - with open(firmware_filename, "rb") as firmware_file: - while True: - w = firmware_file.read(4) - if not w: - break - data.append(struct.unpack(">I", w)[0]) - except: - pass - return data - -def csr_map_update(csr_map, csr_peripherals): - csr_map.update(dict((n, v) for v, n in enumerate(csr_peripherals, start=max(csr_map.values()) + 1))) - class BaseSoC(SDRAMSoC): default_platform = "atlys" @@ -153,7 +137,7 @@ def __init__(self, platform, self.submodules.crg = _CRG(platform, clk_freq) self.submodules.dna = dna.DNA() - self.submodules.firmware_ram = wishbone.SRAM(firmware_ram_size, init=_get_firmware_data(firmware_filename)) + self.submodules.firmware_ram = wishbone.SRAM(firmware_ram_size, init=get_firmware_data(firmware_filename)) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"]) diff --git a/targets/atlys_edid_debug.py b/targets/atlys_edid_debug.py index 86483731..873e1536 100644 --- a/targets/atlys_edid_debug.py +++ b/targets/atlys_edid_debug.py @@ -1,3 +1,4 @@ +from targets.common import * from targets.atlys_hdmi2usb import * from misoclib.com.uart.phy import UARTPHY diff --git a/targets/atlys_hdmi2eth.py b/targets/atlys_hdmi2eth.py index fa30c842..c9a86a11 100644 --- a/targets/atlys_hdmi2eth.py +++ b/targets/atlys_hdmi2eth.py @@ -1,3 +1,4 @@ +from targets.common import * from targets.atlys_base import * from liteeth.common import * diff --git a/targets/common.py b/targets/common.py new file mode 100644 index 00000000..cf4c2716 --- /dev/null +++ b/targets/common.py @@ -0,0 +1,18 @@ + +def get_firmware_data(firmware_filename): + data = [] + try: + with open(firmware_filename, "rb") as firmware_file: + while True: + w = firmware_file.read(4) + if not w: + break + data.append(struct.unpack(">I", w)[0]) + except: + pass + return data + + +def csr_map_update(csr_map, csr_peripherals): + csr_map.update(dict((n, v) for v, n in enumerate(csr_peripherals, start=max(csr_map.values()) + 1))) + diff --git a/targets/opsis_base.py b/targets/opsis_base.py index 77d23a2b..5b797771 100644 --- a/targets/opsis_base.py +++ b/targets/opsis_base.py @@ -21,18 +21,7 @@ from gateware import dna from gateware import i2c from gateware import i2c_hack - -class CSRMap(dict): - def __init__(self, offset, values): - dict.__init__(self) - self.offset = offset - for k, v in values.items(): - self[k] = v - - def __setitem__(self, k, v=None): - if v is None: - v = self.offset + len(self) - dict.__setitem__(self, k, v) +from targets.common import * class _CRG(Module): @@ -127,23 +116,6 @@ def __init__(self, platform, clk_freq): platform.add_period_constraint(self.cd_base50.clk, 20) -def _get_firmware_data(firmware_filename): - data = [] - try: - with open(firmware_filename, "rb") as firmware_file: - while True: - w = firmware_file.read(4) - if not w: - break - data.append(struct.unpack(">I", w)[0]) - except: - pass - return data - -def csr_map_update(csr_map, csr_peripherals): - csr_map.update(dict((n, v) for v, n in enumerate(csr_peripherals, start=max(csr_map.values()) + 1))) - - class BaseSoC(SDRAMSoC): default_platform = "opsis" @@ -180,7 +152,7 @@ def __init__(self, platform, self.submodules.tofe_eeprom_i2c = i2c.I2C(platform.request("tofe_eeprom")) - self.submodules.firmware_ram = wishbone.SRAM(firmware_ram_size, init=_get_firmware_data(firmware_filename)) + self.submodules.firmware_ram = wishbone.SRAM(firmware_ram_size, init=get_firmware_data(firmware_filename)) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"]) diff --git a/targets/opsis_hdmi2usb.py b/targets/opsis_hdmi2usb.py index b67bf16e..0cbb7d06 100644 --- a/targets/opsis_hdmi2usb.py +++ b/targets/opsis_hdmi2usb.py @@ -1,3 +1,4 @@ +from targets.common import * from targets.opsis_base import * from targets.opsis_base import default_subtarget as BaseSoC diff --git a/targets/pipistrello_base.py b/targets/pipistrello_base.py index 127e8880..a37759fe 100644 --- a/targets/pipistrello_base.py +++ b/targets/pipistrello_base.py @@ -1,5 +1,3 @@ -from gateware.hdmi_out import HDMIOut - from fractions import Fraction import struct @@ -16,6 +14,9 @@ from gateware import dna from gateware import i2c_hack +from gateware.hdmi_out import HDMIOut +from targets.common import * + class _CRG(Module): def __init__(self, platform, clk_freq): @@ -101,20 +102,6 @@ def __init__(self, platform, clk_freq): o_Q=clk.n) -def _get_firmware_data(firmware_filename): - data = [] - try: - with open(firmware_filename, "rb") as firmware_file: - while True: - w = firmware_file.read(4) - if not w: - break - data.append(struct.unpack(">I", w)[0]) - except: - pass - return data - - from mibuild.generic_platform import * PipistrelloCustom = [ ("fx2_hack", 0, @@ -125,9 +112,6 @@ def _get_firmware_data(firmware_filename): ("fx2_reset", 0, Pins("K13"), IOStandard("LVCMOS33")), #, Misc("PULLUP")), ] -def csr_map_update(csr_map, csr_peripherals): - csr_map.update(dict((n, v) for v, n in enumerate(csr_peripherals, start=max(csr_map.values()) + 1))) - class BaseSoC(SDRAMSoC): default_platform = "pipistrello" @@ -161,7 +145,7 @@ def __init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000*1000, self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset")) self.submodules.fx2_hack = i2c_hack.I2CShiftReg(platform.request("fx2_hack")) - self.submodules.firmware_ram = wishbone.SRAM(firmware_ram_size, init=_get_firmware_data(firmware_filename)) + self.submodules.firmware_ram = wishbone.SRAM(firmware_ram_size, init=get_firmware_data(firmware_filename)) self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size) self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])