From e1dc252fa568b2a314d731eda27aeb9115df169d Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <mithro@mithis.com>
Date: Sun, 29 Oct 2017 11:28:54 -0700
Subject: [PATCH] Updating for litex uart IRQ move from zero to 2.

(And fixing IRQ conflicts that reveals.)
---
 targets/opsis/base.py  | 5 +++++
 targets/opsis/video.py | 4 ++--
 third_party/litex      | 2 +-
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/targets/opsis/base.py b/targets/opsis/base.py
index 081d02d4..bdece491 100644
--- a/targets/opsis/base.py
+++ b/targets/opsis/base.py
@@ -223,6 +223,11 @@ class BaseSoC(SoCSDRAM):
     )
     csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
 
+    interrupt_map = {
+        "uart": 2,
+    }
+    interrupt_map.update(SoCSDRAM.interrupt_map)
+
     mem_map = {
         "spiflash":     0x20000000,  # (default shadow @0xa0000000)
     }
diff --git a/targets/opsis/video.py b/targets/opsis/video.py
index 911cea4e..a7ec6b94 100644
--- a/targets/opsis/video.py
+++ b/targets/opsis/video.py
@@ -22,8 +22,8 @@ class VideoSoC(BaseSoC):
     csr_map_update(BaseSoC.csr_map, csr_peripherals)
 
     interrupt_map = {
-        "hdmi_in0": 3,
-        "hdmi_in1": 4,
+        "hdmi_in0": 4,
+        "hdmi_in1": 5,
     }
     interrupt_map.update(BaseSoC.interrupt_map)
 
diff --git a/third_party/litex b/third_party/litex
index e07bd71b..56ef2290 160000
--- a/third_party/litex
+++ b/third_party/litex
@@ -1 +1 @@
-Subproject commit e07bd71b16932a504b7435a96901a3b0eb5a99cd
+Subproject commit 56ef22902926e5edfdb524a064804823fe449502