Permalink
Browse files

Adding LiteScope to USBStreamer.

  • Loading branch information...
mithro committed Aug 11, 2015
1 parent e300def commit f73fce7c9b4f3d3ab23da028d1930649b8e13cc0
Showing with 32 additions and 5 deletions.
  1. +16 −2 hdl/streamer/__init__.py
  2. +16 −3 targets/atlys_hdmi2usb.py
@@ -66,7 +66,7 @@ def __init__(self, ip_address, udp_port, fifo_depth=1024):


class USBStreamer(Module):
def __init__(self, platform, pads):
def __init__(self, platform, pads, debug_scope=False):
self.sink = sink = Sink([("data", 8)])

# # #
@@ -81,7 +81,6 @@ def __init__(self, platform, pads):
{"write": "sys", "read": "usb"})
self.comb += Record.connect(sink, fifo.sink)


self.specials += Instance("fx2_jpeg_streamer",
# clk, rst
i_rst=ResetSignal("usb"),
@@ -106,3 +105,18 @@ def __init__(self, platform, pads):

# add VHDL sources
platform.add_source_dir(os.path.join(platform.soc_ext_path, "hdl", "streamer", "vhdl"))

# Add a debugging litescope to the interface.
if debug_scope:
from misoclib.tools.litescope.frontend.la import LiteScopeLA
debug = (
pads.flagb,
pads.flagc,
pads.addr,
pads.cs_n,
pads.wr_n,
pads.rd_n,
pads.oe_n,
pads.pktend_n,
)
self.submodules.la = LiteScopeLA(debug, 4096)
@@ -10,7 +10,7 @@ class VideomixerSoC(BaseSoC):
csr_map = {
"fb": 19,
"dvisampler": 20,
"dvisampler_edid_mem": 21
"dvisampler_edid_mem": 21,
}
csr_map.update(BaseSoC.csr_map)

@@ -37,7 +37,8 @@ def __init__(self, platform, **kwargs):
class HDMI2USBSoC(VideomixerSoC):
csr_map = {
"encoder_reader": 22,
"encoder": 23
"encoder": 23,
"la": 24,
}
csr_map.update(VideomixerSoC.csr_map)
mem_map = {
@@ -48,9 +49,17 @@ class HDMI2USBSoC(VideomixerSoC):
def __init__(self, platform, **kwargs):
VideomixerSoC.__init__(self, platform, **kwargs)

debug_scope = ("fx2",)

self.submodules.encoder_reader = EncoderReader(self.sdram.crossbar.get_master())
self.submodules.encoder = Encoder(platform)
self.submodules.usb_streamer = USBStreamer(platform, platform.request("fx2"))
self.submodules.usb_streamer = USBStreamer(platform, platform.request("fx2"), debug_scope=("fx2" in debug_scope))

if debug_scope:
from misoclib.tools.litescope.core.port import LiteScopeTerm
if "fx2" in debug_scope:
la = self.usb_streamer.la
la.trigger.add_port(LiteScopeTerm(la.dw))

self.comb += [
platform.request("user_led", 0).eq(self.encoder_reader.source.stb),
@@ -67,4 +76,8 @@ def __init__(self, platform, **kwargs):
TIMESPEC "TSise_sucks10" = FROM "GRPsys_clk" TO "GRPusb_clk" TIG;
""", usb_clk=platform.lookup_request("fx2").ifclk)

def do_exit(self, vns):
print(vns)
self.usb_streamer.la.export(vns, "test/la.csv")

default_subtarget = HDMI2USBSoC

0 comments on commit f73fce7

Please sign in to comment.