Permalink
Commits on Dec 28, 2018
  1. Merge pull request #119 from cr1901/patch-1

    mithro committed Dec 28, 2018
    Install tinyprog from repo until new version is uploaded to PyPI.
  2. Merge pull request #462 from rohitk-singh/mmcm_fix

    mithro committed Dec 28, 2018
    firmware: fix MMCM multiplier & divisor calculation
  3. firmware: fix MMCM multiplier & divisor calculation

    rohitk-singh committed Dec 28, 2018
    Also warn if the calculated VCO frequency strays outside the
    datasheet specified range
    
    Signed-off-by: Rohit Singh <rohit91.2008@gmail.com>
Commits on Dec 25, 2018
  1. Merge pull request #118 from mithro/master

    mithro committed Dec 25, 2018
    Updating submodules.
  2. Updating submodules.

    mithro committed Dec 25, 2018
     * litedram changed from 81fa19e to 906edf1
        * 906edf1 - phy/gensdrphy: make cke/dm optional. <Florent Kermarrec>
    
     * litex changed from v0.1-677-g291843ee to v0.1-679-ga7378a72
        * a7378a72 - .gitmodules: use our copy of tapcfg since https://github.com/nizox/tapcfg no longer exists. <Florent Kermarrec>
        * 2deffd8c - build/sim/verilator: compile sim just before running and not when building. <Florent Kermarrec>
    
     * migen changed from 0.6.dev-228-g37db6bb to 0.6.dev-229-g5e7c71a
        * 5e7c71a - build/xilinx/vivado: use build_name instead of top in synth_design <Florent Kermarrec>
    
    Full submodule status
    --
     6def7bc83dfb0338632e06a8b14c93faa6af8879 edid-decode (remotes/origin/HEAD)
     a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (heads/master)
     906edf19177a55123f28f922e0b85700b7d191e5 litedram (remotes/origin/HEAD)
     d7fdcbb1dc17d07852b1c9957d62f68d2dde29b5 liteeth (remotes/origin/HEAD)
     b29c3a07bc5e4e7eb8c12b174446b85371ffb3a0 litepcie (remotes/origin/HEAD)
     b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (heads/master)
     1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (heads/master)
     0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
     0993a4e0422454e522e1d2b491837034b8dcccbe litevideo (remotes/origin/HEAD)
     a7378a721c039c89f6c339b9c0c50609f8769c0a litex (v0.1-679-ga7378a72)
     5e7c71acead518802c8ae1f27163e4f2a9218f36 migen (0.6.dev-229-g5e7c71a)
Commits on Dec 20, 2018
  1. Merge pull request #116 from mithro/update-submodules

    mithro committed Dec 20, 2018
    Update submodules
  2. Updating submodules.

    mithro committed Dec 20, 2018
     * litedram changed from da6fc8c to 81fa19e
        * 81fa19e - phy/usddrphy: fix DRC REQP-1665. <Florent Kermarrec>
        * c275755 - phy/usddrphy: add iodelay_clk_freq parameter <Florent Kermarrec>
        * 62a31de - phy: rename KUSDDRPHY to USDDRPHY since compatible with Kintex/Virtex Ultrascale <Florent Kermarrec>
        * e91366c - frontend/axi: use buffered SyncFIFO on datapath (reduce resource usage) <Florent Kermarrec>
    
     * liteeth changed from 52c2301 to d7fdcbb
        * d7fdcbb - phy: add Spartan6 RGMII PHY <Florent Kermarrec>
    
     * litex changed from v0.1-668-g1c1c1bd1 to v0.1-677-g291843ee
        *   291843ee - Merge pull request #144 from mithro/nextpnr-migen-update <Tim Ansell>
        |\
        | * 53731b79 - Integrate latest migen changes for lattice/icestorm. <Tim 'mithro' Ansell>
        * 180912a7 - build/sim: handle verilog $finish and if coverage is enabled, write report at the end of the simulation. <Florent Kermarrec>
        * b6c98cab - platforms/kcu105: change internal vref to 0.84v (recommended value for ddr4) <Florent Kermarrec>
        * ebe0d567 - bios/sdram: only show read delays when they are valid. <Florent Kermarrec>
        * 67a25902 - bios/sdram: reduce write leveling scan range <Florent Kermarrec>
        * fe5cef42 - soc/cores/clock: remove return on S7PLL.create_clkout <Florent Kermarrec>
        * eda1a83e - platforms/kcu105: set internal vref on ddr4 banks <Florent Kermarrec>
        * a27b5a3b - update Ultrascale DDRPHY <Florent Kermarrec>
    
    Full submodule status
    --
     6def7bc83dfb0338632e06a8b14c93faa6af8879 edid-decode (heads/master)
     a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (heads/master)
     81fa19e58d878a9d725086f3bb54aaed53cc6cde litedram (remotes/origin/HEAD)
     d7fdcbb1dc17d07852b1c9957d62f68d2dde29b5 liteeth (remotes/origin/HEAD)
     b29c3a07bc5e4e7eb8c12b174446b85371ffb3a0 litepcie (heads/master)
     b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (heads/master)
     1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (heads/master)
     0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
     0993a4e0422454e522e1d2b491837034b8dcccbe litevideo (heads/master)
     291843ee76b43f8308cfdba21aa8a99c07327855 litex (v0.1-677-g291843ee)
     37db6bb52532b6d1c6bc8b724c2e8c6a38546c2a migen (0.6.dev-228-g37db6bb)
Commits on Dec 18, 2018
  1. Merge pull request #115 from mithro/master

    mithro committed Dec 18, 2018
    Updating submodules.
  2. Updating submodules.

    mithro committed Dec 18, 2018
     * litedram changed from 0572006 to da6fc8c
        * da6fc8c - README: add Kintex Ultrascale PHY <Florent Kermarrec>
        * 8993e8b - core/refresher: fix refresh regression <Florent Kermarrec>
        * 83f763f - phy: replace wdly_dqs_taps with half_sys8x_taps (similar to what is implemented on 7-series) <Florent Kermarrec>
        * 28b7d32 - phy/kusddrphy: use rdly_dq_bitslip_rst CSR for bitslip reset <Florent Kermarrec>
        * 1ece2ca - phy/dfi: set act_n reset value to 1 <Florent Kermarrec>
    
     * litex changed from v0.1-664-g0ade06c0 to v0.1-668-g1c1c1bd1
        *   1c1c1bd1 - Merge pull request #141 from mithro/xst-fix <Tim Ansell>
        |\
        | * 8b2abc7e - Fix `-vlgincdir` for xst. <Tim 'mithro' Ansell>
        * f8f3683a - bios/sdram: reduce scans verbosity on ultrascale <Florent Kermarrec>
        * efce434a - bios/sdram: use ddrphy_half_sys8x_taps_read() for KUSDDRPHY <Florent Kermarrec>
    
    Full submodule status
    --
     6def7bc83dfb0338632e06a8b14c93faa6af8879 edid-decode (remotes/origin/HEAD)
     a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (heads/master)
     da6fc8c39b1376727c0184896ea494557500d645 litedram (remotes/origin/HEAD)
     52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (remotes/origin/HEAD)
     b29c3a07bc5e4e7eb8c12b174446b85371ffb3a0 litepcie (remotes/origin/HEAD)
     b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (heads/master)
     1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (heads/master)
     0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
     0993a4e0422454e522e1d2b491837034b8dcccbe litevideo (remotes/origin/HEAD)
     1c1c1bd122224dcd9ae22288c2660b0e70a283a8 litex (v0.1-668-g1c1c1bd1)
     37db6bb52532b6d1c6bc8b724c2e8c6a38546c2a migen (0.6.dev-228-g37db6bb)
  3. Merge pull request #103 from mithro/readme-fix

    mithro committed Dec 18, 2018
    docs: Fix missing s
  4. Merge pull request #104 from pgielda/fix-enter-env

    mithro committed Dec 18, 2018
    Fixes in enter-env.sh script.
  5. Merge pull request #114 from mithro/master

    mithro committed Dec 18, 2018
    Updating submodules.
Commits on Dec 16, 2018
  1. Updating submodules.

    mithro committed Dec 16, 2018
     * edid-decode changed from 5eeb151 to 6def7bc
        * 6def7bc - edid-decode: make it easier to find the out-of-range monitor values <Hans Verkuil>
    
     * litedram changed from bc6a3f2 to 0572006
        * 0572006 - phy/kusddrphy: remove ResetSignal on ODELAYE3/ISERDESE3 that are dynamically adjusted, reduce sys latency <Florent Kermarrec>
        * 57ebcc5 - sdram_init/ddr4: enable dll <Florent Kermarrec>
        * 7a2ff33 - sdram_init/get_sdram_phy_py_header: generate mr1 value, fix init_sequence identation <Florent Kermarrec>
        * 33ff34b - core/refresher: use self.sync to fix build (verilog wire vs reg...) <Florent Kermarrec>
        * 8419f28 - core: split refresher, expose it and allow it to be reloaded externally. <Florent Kermarrec>
        * 8ec0bc6 - modules: improve the way we define DDR4 banks/groups <Florent Kermarrec>
        * 1618a76 - phy: add KUSDDRPHY to __init__.py <Florent Kermarrec>
        * d6350d9 - test/test_axi: reduce rand_level on writes <Florent Kermarrec>
        * 282b60e - frontend/axi: simplify LiteDRAMAXI2NativeW logic <Florent Kermarrec>
        * 6778c72 - test/test_axi: cleanup, all tests passings. <Florent Kermarrec>
        * ebb1d3c - frontend/axi/LiteDRAMAXI2NativeW: be sure that we already have the data before sending the command to the controller <Florent Kermarrec>
        * 0d5e554 - frontend/axi: expose aw_burst2beat/ar_burst2beat <Florent Kermarrec>
        * da65a80 - frontend/axi: expose w_buffer/r_buffer (can be useful for debug) <Florent Kermarrec>
        * 7f5d749 - test: add missing +x <Florent Kermarrec>
        * 7ef4869 - test/test_axi: also add randomness on rdata.valid and wdata.ready <Florent Kermarrec>
        * 3db68cd - test/test_axi/axi2native: add tests for each randomness parameters (ease finding regressions issues) <Florent Kermarrec>
        * 190b1bd - test/test_axi/axi2native: add finer control on randomness <Florent Kermarrec>
        * 4f137b9 - test/test_axi/axi2native: add random on len, just use writes as reads <Florent Kermarrec>
        * 2a799e4 - test/test_axi: set size on axi2native test <Florent Kermarrec>
        * e70d77e - phy/s7dddrphy: fix nphases = 2 (same code can be shared between nphases = 2 and nphases = 4) <Florent Kermarrec>
        * 170b3dc - frontend/wishbone: set aw/ar size on LiteDRAMWishbone2AXI <Florent Kermarrec>
        * 9a25506 - frontend/wishbone: fix wishbone.err on LiteDRAMWishbone2AXI <Florent Kermarrec>
    
     * litepcie changed from dddd3b1 to b29c3a0
        * b29c3a0 - README: update PHY description <Florent Kermarrec>
        * 07501b8 - core: expose depacketizer/packetizer/controller (useful for debug) <Florent Kermarrec>
        * bfd2813 - frontend/dma: remove 64KB DMA buffer size limitation by increasing length to 24 bits. <Florent Kermarrec>
    
     * litex changed from v0.1-620-gab799f7b to v0.1-664-g0ade06c0
        *   0ade06c0 - Merge pull request #138 from mithro/mainram-hack <Tim Ansell>
        |\
        | * 22d454ef - Hack to fix #136. <Tim 'mithro' Ansell>
        |/
        *   fa6fef1e - Merge pull request #135 from mithro/icestorm-ice40up5k <Tim Ansell>
        |\
        | * 9481781d - Add uwg30 package and up3k part. <Tim 'mithro' Ansell>
        * | e9f10492 - soc/cores/cpu/vexriscv: add add_debug method for debug variants <Florent Kermarrec>
        * | 35155e51 - soc/cores/cpu/vexriscv: add support for the new variants. <Florent Kermarrec>
        * | 2ace45e6 - soc/cores/cpu/vexriscv: update submodule <Florent Kermarrec>
        * | 6d6c2b4c - soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v) <Florent Kermarrec>
        * | 584fd51c - build/sim/verilator: add support for plaform.sources, some cleanup <Florent Kermarrec>
        * | c9915f89 - build/microsemi/libero_soc: fix typos <Florent Kermarrec>
        * | 99578bc6 - gen/sim/core: add args support on Display <Florent Kermarrec>
        * | fa260f5b - gen/fhdl: add simulation Display, Finish support. <Florent Kermarrec>
        * | 92a6169d - build/sim: add coverage parameter to enable code coverage <Florent Kermarrec>
        * | 0c687bc2 - soc/interconnect/stream: add support for buffered async fifo <Florent Kermarrec>
        * | bf3b4eec - gen: integrate migen changes <Florent Kermarrec>
        |/
        * 96527b5a - soc/interconnect/stream/gearbox: remove bit reversing by changing words order <Florent Kermarrec>
        *   1c8c2426 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
        |\
        | *   cc4ba656 - Merge pull request #130 from jfng/master <enjoy-digital>
        | |\
        | | * 71398e01 - litex_sim: add --trace argument <Jean-François Nguyen>
        * | | 8887fc24 - build/xilinx/vivado: disable xpm by default (can be enabled by passing enable_xpm=True to build). <Florent Kermarrec>
        |/ /
        * | ec46beeb - targets/ulx3s, versa_ecp5: use ECP5PLL <Florent Kermarrec>
        * | 18048eb4 - cores/clock: test and fix ECP5PLL, phase still not implemented. <Florent Kermarrec>
        * | 20dd95c5 - boards/platforms/ulx3s: add gpios 0-3 <Florent Kermarrec>
        |/
        * 909cff19 - bios/sdram: flush l2 cache only when present <Florent Kermarrec>
        * 2ad83778 - bios: allow testing main_ram at init when using an external controller <Florent Kermarrec>
        * cdfe0454 - build/microsemi/libero_soc: small cleanup <Florent Kermarrec>
        *   4592e323 - Merge pull request #128 from mithro/small-fix <enjoy-digital>
        |\
        | * 4f565c51 - stream.Endpoint: Pass extra arguments to superclass. <Tim 'mithro' Ansell>
        | * 3b9e4c4d - wishbone.SRAM: Support non-32bit wishbone widths. <Tim 'mithro' Ansell>
        * 515c0621 - cores/clock: add ECP5PLL <Florent Kermarrec>
        * 7623b5dd - soc/interconnect/stream/gearbox: inverse bit order <Florent Kermarrec>
        * d32e3930 - soc/cores/spi_flash: add missing endianness parameter <Florent Kermarrec>
        * c954943e - platforms/avalanche: add IOStandard on ddram pins <Florent Kermarrec>
        * 09a1cda9 - build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification <Florent Kermarrec>
        * a98e1ad6 - build/microsemi/libero_soc: add additional_timing_constraints <Florent Kermarrec>
        * b1668823 - build/microsemi/libero_soc: use die/package/speed from platform.device and add tcl_name helper <Florent Kermarrec>
        * 9df75d7d - platforms/avalanche: add package/speed to platform.device <Florent Kermarrec>
        * 953b1f70 - build/microsemi/libero_soc: remove previous impl directory if exists <Florent Kermarrec>
        * 18d513a1 - build/microsemi/libero_soc: give better names to pdc files: io/fp <Florent Kermarrec>
        * 4f092dbe - build/microsemi/libero_soc: add additional_constraints <Florent Kermarrec>
        * 206c9a46 - platforms/avalanche: fix ddram dq7 <Florent Kermarrec>
        * f0034077 - build/microsemi/libero_soc: add {} around port name. <Florent Kermarrec>
        * beeca856 - utils/litex_read_verilog: fix generated indent on instance <Florent Kermarrec>
        * 1fe7d09f - soc/integration/soc_core: add csr_map_update function <Florent Kermarrec>
    
     * migen changed from 0.6.dev-211-g022721a to 0.6.dev-228-g37db6bb
        * 37db6bb - Add uwg30 package and up3k part. <Tim 'mithro' Ansell>
        * abc2802 - fhdl/tracer: support Python 3.7 (#167) <Pierre-Olivier Vauboin>
        * e6ff283 - examples/sim: add display example <Florent Kermarrec>
        * 6742210 - sim/core: add Display support <Florent Kermarrec>
        * f46f014 - fhdl: add simulation Display, Finish support. <Florent Kermarrec>
        * 3d8a580 - build/lattice/icestorm: allow passing options to synth_ice40. <whitequark>
        * be608f9 - Revert "lattice/common: no need to differentiate nbits==1 and nbits > 1" <whitequark>
        * ac0dd18 - fhdl: give names to storage locations in MemoryToArray. <whitequark>
        * 01d9055 - fhdl: fix mismatch between _can_lower() and _lower_specials_step(). <whitequark>
        * f5005b5 - fhdl: append lowered specials to the original fragment. <whitequark>
        * 29b4e65 - genlib/resetsync: add __all__. <whitequark>
        * f0cd29f - genlib/fifo: add __all__. <whitequark>
        * c05fc0c - build/lattice/icestorm: add fine grained clock constraint support. <whitequark>
        * 0c57a44 - build/lattice/icestorm: simplify. <whitequark>
        * 4eca436 - fhdl/specials: allow passing name hint to TSTriple. <whitequark>
        * b5d723b - build/lattice/trellis: update for newer ecppack. <whitequark>
        * 3fc11b5 - build/lattice/icestorm: update package list for iCE40-HX8K. <Adam Greig>
    
    Full submodule status
    --
     6def7bc83dfb0338632e06a8b14c93faa6af8879 edid-decode (heads/master)
     a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (heads/master)
     057200665f48fac184c46bbe6a82110f34ee01e4 litedram (heads/master)
     52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (heads/master)
     b29c3a07bc5e4e7eb8c12b174446b85371ffb3a0 litepcie (heads/master)
     b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (heads/master)
     1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (heads/master)
     0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
     0993a4e0422454e522e1d2b491837034b8dcccbe litevideo (heads/master)
     0ade06c0f0b3ba747ceee5e35ea0abc7bc20df77 litex (v0.1-664-g0ade06c0)
     37db6bb52532b6d1c6bc8b724c2e8c6a38546c2a migen (0.6.dev-228-g37db6bb)
Commits on Dec 9, 2018
  1. Fix `script` line in README

    mithro committed Dec 9, 2018
    Fixes #107.
Commits on Nov 21, 2018
  1. Merge pull request #106 from cr1901/picorv32-data

    mithro committed Nov 21, 2018
    Updating submodules.
  2. Updating submodules.

    cr1901 committed Nov 21, 2018
     * litedram changed from 30d9a3e to bc6a3f2
        * bc6a3f2 - examples/sim/sim/py: remove apb interface <Florent Kermarrec>
        * e7e4bc5 - examples/sim: add ddr3 micron model <Florent Kermarrec>
        * f219693 - examples: add simulation <Florent Kermarrec>
    
     * litepcie changed from 48f662e to dddd3b1
        * dddd3b1 - phy/s7pciephy: fix soft reset by reseting pcie on cd reset <Florent Kermarrec>
    
     * litevideo changed from 13d85a1 to 0993a4e
        * 0993a4e - Merge pull request #21 from felixheld/licensefix <Tim Ansell>
        * d8287db - LICENSE: use right project name <Felix Held>
    
     * litex changed from bc173380 to ab799f7b
        *   ab799f7b - Merge pull request #127 from cr1901/picorv32-data <Tim Ansell>
        |\
        | * 89c70218 - libbase/crt0-picorv32: Add support for .data sections. <William D. Jones>
        |/
        * 80bdae0e - build/sim/verilator: add trace parameter to enable tracer <Florent Kermarrec>
        * 7359a99b - soc_core: convert cpu_type="None" string to None <Florent Kermarrec>
        * 5805d630 - build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route <Florent Kermarrec>
        * 85f76662 - build/microsemi/common: add async reset synchronizer (using DFN1P0) <Florent Kermarrec>
        * e3c6bd58 - build/microsemi/libero_soc: pass timing constraints to synthesis, place & route and timing verification tools <Florent Kermarrec>
        * 4c966114 - build/microsemi/libero_soc: add timing constraints support <Florent Kermarrec>
        * 60faae49 - boards/platforms/avalanche: fix swapped serial pins <Florent Kermarrec>
        * 52396add - boards/platforms/avalanche: rename rst to rst_n (active low reset) <Florent Kermarrec>
        * 8e07e1a0 - build/microsemi/libero_soc: associate .pdc to place and route tool. <Florent Kermarrec>
        * 5137c2bf - test/test_targets: update <Florent Kermarrec>
        * a5ed42ec - soc/interconnect/stream: add Gearbox <Florent Kermarrec>
        * 11d536dc - test: remove test_bitslip (integrated in migen) <Florent Kermarrec>
        * a25645af - utils: add litex_read_verilog utility <Florent Kermarrec>
        * a538d362 - create utils directory and move the litex utils to it <Florent Kermarrec>
        * 45ec78e9 - build/microsemi/libero_soc: able to generate design script (tcl) and design constraint (pdc) for libero soc / avalanche board. <Florent Kermarrec>
        * 4cb6583b - build: add microsemi template for polarfire fpgas support <Florent Kermarrec>
    
     * migen changed from 0.6.dev-209-gc285c12 to 0.6.dev-211-g022721a
        * 022721a - lattice/diamond: Support sourcing by default. <William D. Jones>
        * 17e6d34 - fix yosys commands for build_names other than 'top' <Erin Moon>
    
    Full submodule status
    --
     5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
     a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
     bc6a3f220a16fbc1208cc23ab5cf072d2b81f62e litedram (remotes/origin/HEAD)
     52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (remotes/origin/HEAD)
     dddd3b16edfc9b345526f4106954b2c6b6f00933 litepcie (remotes/origin/HEAD)
     b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
     1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
     0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
     0993a4e0422454e522e1d2b491837034b8dcccbe litevideo (remotes/origin/HEAD)
     ab799f7bd7e0ad2063747dc6636de61225e648c4 litex (remotes/origin/HEAD)
     022721a81d274a08ccb1b1f7919d4940cce99a73 migen (0.6.dev-211-g022721a)
Commits on Nov 20, 2018
  1. Merge pull request #105 from cr1901/riscv32

    mithro committed Nov 20, 2018
    Riscv32 Support
  2. travis.yml: Fix formatting.

    cr1901 committed Nov 20, 2018
  3. Revert "scripts/build-micropython.sh: Fix detection of RISCV compilers."

    cr1901 committed Nov 20, 2018
    riscv32-elf-gcc is provided after all.
    
    This reverts commit afd259a.
Commits on Nov 18, 2018
  1. Do not try to execute enter-env.sh on anything other than bash.

    pgielda committed Nov 18, 2018
    Also try to use return first on two first errors
    as we do not know yet if we are being sourced or not.
Commits on Nov 17, 2018
  1. docs: Fix missing s

    mithro committed Nov 17, 2018
Commits on Nov 14, 2018
  1. Merge pull request #102 from mithro/update

    mithro committed Nov 14, 2018
    Updating submodules.
  2. Updating submodules.

    mithro committed Nov 14, 2018
     * litedram changed from f36bcff to 30d9a3e
        * 30d9a3e - modules: add MT40A1G8 DDR4 <Florent Kermarrec>
        * 4459bd2 - frontend/axi: same condition to connect connect wdata.we and wdata <Florent Kermarrec>
        * d10e2e9 - core: make address_mapping a controller setting <Florent Kermarrec>
        * 7973b7d - frontend/axi: emits the write command only if we have the write data <Florent Kermarrec>
        * 6fa891d - frontend/axi: fix write response for bursts <Florent Kermarrec>
        * 93e8510 - test/test_axi: add bursts to axi2native <Florent Kermarrec>
        * e27fbc2 - test/test_axi: move definitions to top and make Access herit from Burst <Florent Kermarrec>
        * 4470f32 - test/test_axi: change order of the tests <Florent Kermarrec>
        * 070cc26 - test/test_axi: use separate generator for writes cmd/data <Florent Kermarrec>
        * 127e928 - frontend/wishbone: simplify LiteDRAMWishbone2Native code (resource usage almost the same) <Florent Kermarrec>
        * ca82ac1 - frontend/wishbone: add LiteDRAMWishbone2AXI <Florent Kermarrec>
        * 3586e15 - frontend/axi: improve len/size comment (-1), set default id_width to 1 <Florent Kermarrec>
        * 71be616 - frontend/axi: be sure wdata is available before sending the command to the controller <Florent Kermarrec>
        * 55b5f40 - modules: add AS4C256M16D3A <Florent Kermarrec>
        *   69ea866 - Merge pull request #62 from daveshah1/AS4C32M16 <enjoy-digital>
        |\
        | * 3a5d45b - modules: Add AS4C32M16 32Mx16 SDRAM <David Shah>
        * | b41fe61 - phy/kusddrphy/ddr4: multiplexed address bits are always the same (14, 15, 16) and fix ba/bg ordering <Florent Kermarrec>
        * | 2e19787 - phy/kusddrphy: add dfi mux on address/control signals <Florent Kermarrec>
        * | a8c3d39 - sdram_init: fix compilation <Florent Kermarrec>
        * | af34489 - common: add DDR4 burst_length <Florent Kermarrec>
        * | 2a9fb11 - phy/kusddrphy: more genericity, initial DDR4 support <Florent Kermarrec>
        * | ae5dc9f - sdram_init: add initial DDR4 initialization <Florent Kermarrec>
        * | 8181fea - modules: add EDY4016A DDR4 <Florent Kermarrec>
        * | 346e64c - frontend/ecc: fix typo <Florent Kermarrec>
        |/
        * 82c08c7 - phy/gensdrphy: use tristate input <Florent Kermarrec>
        * 9ce84d9 - modules: add MT48LC16M16 (ulx3s) <Florent Kermarrec>
    
     * liteeth changed from 40b99ec to 52c2301
        * 52c2301 - frontend/etherbone: reduce default buffer_depth to 4 <Florent Kermarrec>
        * 602ddec - common: use reverse_bytes from litex.gen <Florent Kermarrec>
    
     * litepcie changed from a8b8048 to 48f662e
        * 48f662e - phy/s7pciephy: force user to use register_pll1 if pll1 is needed <Florent Kermarrec>
        * 33f4601 - phy/s7pciephy: add register_pll1 method <Florent Kermarrec>
        * 80f28b1 - common: use reverse_bits/reverse_bytes from litex.gen <Florent Kermarrec>
    
     * litex changed from v0.1-532-g98159209 to v0.1-602-gbc173380
        *   bc173380 - Merge pull request #126 from mithro/toolchain-fix <Tim Ansell>
        |\
        | * b1425ba8 - lattice/icestorm: Add toolchain_path so it doesn't end up kwargs. <Tim 'mithro' Ansell>
        |/
        * af25bf2b - soc_core: check for cpu before checking interrupt <Florent Kermarrec>
        * b4bdf2a0 - cores/clock/S7: just reset the generated clock, not the PLL/MMCM <Florent Kermarrec>
        * 86fd945b - bios/main: fix typo on mor1kx <Florent Kermarrec>
        * af950285 - cpu/mor1kx: use clang only for linux variant <Florent Kermarrec>
        * 04523bc2 - xilinx/vivado: fix migen merge <Florent Kermarrec>
        * f3343c46 - platforms: remove versaecp55g_sdram <Florent Kermarrec>
        * 58414b18 - build/xilinx/vivado: merge migen change <Florent Kermarrec>
        * a7f17f99 - build: use default toolchain_path on all backend when passed value is None <Florent Kermarrec>
        * eed1d5cb - generic_platform: use set for sources <Florent Kermarrec>
        * 665fff83 - build: merge more migen changes <Florent Kermarrec>
        * 70f48775 - platforms/versa_ecp5: import migen changes <Florent Kermarrec>
        * 4ff241b9 - targets/ulx3s,versa_ecp5: prjtrellis toolchain renamed to trellis <Florent Kermarrec>
        * cb86728a - build/lattice: import changes from migen <Florent Kermarrec>
        * 8574c62f - targets/versa_ecp5: increase sys_clk_freq to 50MHz <Florent Kermarrec>
        * a752dafb - targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll <Florent Kermarrec>
        * 87c7d23d - targets/ulx3s: for now revert to 25MHz clock/no pll <Florent Kermarrec>
        * d1baae36 - platforms/versa_ecp5: add ecp5 soc hat ios <Florent Kermarrec>
        *   b3bf1c95 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
        |\
        | *   1be6762d - Merge pull request #125 from daveshah1/trellis_sdram <enjoy-digital>
        | |\
        | | * f08f80be - working on Versa-5G dram <David Shah>
        | | * d78d5d3e - Debugging ULX3S SDRAM <David Shah>
        * | | 425ad755 - plarforms: rename versa/versaecp55g to versa_ecp3/versa_ecp5 <Florent Kermarrec>
        |/ /
        * | c57aa545 - targets/ulx3s: get memtest working by disabling sdram refresh <Florent Kermarrec>
        * | 9a644717 - soc/integration/soc_sdram: allow using axi interface with litedram <Florent Kermarrec>
        * | 416bdb64 - boards/platforms: add avalanche polarfire board ios definition <Florent Kermarrec>
        * | fc0d5c39 - bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients <Florent Kermarrec>
        * | 09f962fd - target/kcu105: add reset button <Florent Kermarrec>
        * | 169f8d8c - boards/platforms/kcu105: fix sdram/dq pin swap <Florent Kermarrec>
        * | 2624ba48 - bios/sdram: replace DDR3_MR1 constant with DDRX_MR1 <Florent Kermarrec>
        * | 6be74aa1 - boards/targets: add kcu105 <Florent Kermarrec>
        * |   93c62325 - Merge pull request #122 from daveshah1/trellis_ulx3s <enjoy-digital>
        |\ \
        | |/
        | * 0729b3a0 - ulx3s: Connect SDRAM clock <David Shah>
        | * 84044349 - Fix Trellis build; ULX3S demo boots to BIOS <David Shah>
        | * 0c1d8d59 - trellis: Switch to using LPF for constraints <David Shah>
        * |   00ef8240 - Merge pull request #124 from jfng/master <enjoy-digital>
        |\ \
        | * | dcbe759b - build/sim/verilator: don't use --threads when $(THREADS) is unset <Jean-François Nguyen>
        |/ /
        * | 6f38213a - boards/platforms/kc705: add user_sma_mgt_refclk <Florent Kermarrec>
        * |   4cdd6799 - Merge pull request #123 from cr1901/prv32-min <enjoy-digital>
        |\ \
        | * | e56f7182 - libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time). <William D. Jones>
        | * | f32121e0 - cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector. <William D. Jones>
        | * | 77389d27 - libbase/crt0-picorv32: Ensure BSS is cleared on boot. <William D. Jones>
        | * | f69bd877 - cpu/picorv32: Create minimal variant (disable mul/div insns, most speed optimizations). <William D. Jones>
        | * | d05fe673 - cpu/picorv32: Extract picorv32 parameters from Instance constructor to facilitate creating variant CPUs. <William D. Jones>
        * | | f7969b66 - cores/clock: add with_reset parameter (default to True) <Florent Kermarrec>
        | |/
        |/|
        * | 445c4940 - boards/platforms/kcu105: add sfp_tx/rx definition <Florent Kermarrec>
        |/
        * e9d4c882 - build/lattice/prjtrellis: fix default toolchain_path <Florent Kermarrec>
        * 468780c0 - soc/cores/spi_flash: add endianness parameter <Florent Kermarrec>
        * 6f3131e2 - soc/interconnect/stream_packet: use reverse_bytes from litex.gen <Florent Kermarrec>
        * b7968538 - gen: add common with reverse_bits/reverse_bytes functions <Florent Kermarrec>
        * 71fc34d7 - boards/targets/ulx3s: reduce l2_size <Florent Kermarrec>
        * 75d073f3 - build/lattice/prjtrellis: fix typo <Florent Kermarrec>
        * 6048a529 - build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper, handle inouts. <Florent Kermarrec>
        * 2243f628 - build/lattice/common: fix LatticeECPXPrjTrellisTristateImpl <Florent Kermarrec>
        *   3a8bb94a - Merge pull request #121 from cr1901/patch-3 <Tim Ansell>
        |\
        | * f3111e11 - Update vivado.py <William D. Jones>
        |/
        * 98fa8996 - boards/targets: add ulx3s <Florent Kermarrec>
        * 7d779473 - boards/platforms: add ulx3s <Florent Kermarrec>
        * d9dcad33 - build/lattice/prjtrellis: add inout support <Florent Kermarrec>
        * 091ad799 - build/lattice/common: add tristate support <Florent Kermarrec>
        * 23acefb1 - boards/targets/versaecp55g_prjtrellis: simple.py example working, specific target no longer needed <Florent Kermarrec>
        * 1097f822 - build/lattice/prjtrellis: set default toolchain_path to "/opt/prjtrellis" <Florent Kermarrec>
        * 52917a71 - boards/targets/simple: add gateware-toolchain parameter <Florent Kermarrec>
        * d84083f6 - boards/platforms/versaecp55g: use ftdi serial pins <Florent Kermarrec>
        * c05b9ef2 - build/lattice/prjtrellis: test and fix iowrapper multi-bit signals support <Florent Kermarrec>
        * a8f819fe - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
        * 4eb314a2 - boards/targets/versaecp55g: use new iowrapper support, basic led blink and ios working :) <Florent Kermarrec>
        * 27ec2a59 - build/lattice/prjtrellis: generate iowrapper to set constraints and TRELLIS_IO <Florent Kermarrec>
        * c506c975 - gen/fhdl/verilog: set direction to io signals <Florent Kermarrec>
    
     * migen changed from 0.6.dev-179-g657c0c7 to 0.6.dev-209-gc285c12
        * c285c12 - genlib/fsm: allow subclassing FSM and overriding control functionality. <whitequark>
        * dd78f38 - sim/core: fix typo breaking `yield x.part(...).eq(...)`. <whitequark>
        * f8bea17 - test/test_fsm: fix typo. <whitequark>
        * 319d3cd - build: use default toolchain_path on all backends when toolchain_path passed value is None <Florent Kermarrec>
        * e7c9ab0 - xilinx/vivado: fix missing **kwargs <Florent Kermarrec>
        * 8789575 - xilinx/vivado: fix edifs/ips import <Florent Kermarrec>
        * 5851076 - build: make sure build_name/kwargs are passed to platform.get_verilog on all backends <Florent Kermarrec>
        * ec40e98 - xilinx/vivado: enable xpm libraries <Florent Kermarrec>
        * 21bb0f7 - xilinx/vivado: add support for importing edifs for ips <Florent Kermarrec>
        * 263e729 - xilinx/programmer: add device parameter <Florent Kermarrec>
        * f71b4a8 - xilinx/ise: set build_name as top name <Florent Kermarrec>
        * 2dc085d - lattice/common: no need to differentiate nbits==1 and nbits > 1 <Florent Kermarrec>
        * 48023fa - lattice: fix Misc constraints <Florent Kermarrec>
        * 1fdf5db - lattice/diamond: use build_name as top name <Florent Kermarrec>
        * 28a5f32 - genlib/fsm: add basic FSM tests. <whitequark>
        * 9cd4e2c - remove asic_syntax and other cleanups <Sebastien Bourdeauducq>
        * cf4c3ef - build/lattice/diamond: translate `keep` and `no_retiming` attributes. <whitequark>
        * d5ac858 - build/lattice/diamond: save LDF project after creating it. <whitequark>
        * 2025071 - build/lattice/diamond: shorten pointlessly long paths. <whitequark>
        * 7303a8a - build/platforms/versaecp55g: add PCIe pins. <whitequark>
        * 0c5d42c - Add Project Trellis Backend (#156) <William D. Jones>
        * 37deff1 - build/platforms/versaecp55g: fix IOStandard for ext_clk. <whitequark>
        * c79d988 - build/platforms/versaecp55g: add X3 external connector. <whitequark>
        * d60cea0 - build/platforms/versaecp55g: add external clock input. <whitequark>
        * c51a064 - build/platforms/versaecp55g: allow programming without ispCLOCK in chain. <whitequark>
        * 34eeb3b - build/platforms/versaecp55g: import from litex. <whitequark>
        * 7bdc4ed - build/lattice/diamond: add Linux support. <whitequark>
        * 3a84a8b - build/lattice/diamond: only run Jedecgen for MachXO. <whitequark>
        * 966781b - class Tristate: add support for target parameter with oe, o and i subsignals. (#148) <Staf Verhaegen>
        * 907afd5 - platforms/icebreaker: Rename I/O w/ @esden's feedback. <William D. Jones>
    
    Full submodule status
    --
     5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD)
     a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
     30d9a3e2c22459470605b8d46f27d339b47f7987 litedram (remotes/origin/HEAD)
     52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (remotes/origin/HEAD)
     48f662e3928aa5af25aef932a8b1744d1f29c260 litepcie (remotes/origin/HEAD)
     b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (remotes/origin/HEAD)
     1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (remotes/origin/HEAD)
     0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD)
     13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD)
     bc173380f21f82a82fc41e9face61b0c33e7f8e4 litex (v0.1-602-gbc173380)
     c285c12905cca3d8db59ce9fba3bbcd7e781e3c3 migen (0.6.dev-209-gc285c12)
Commits on Nov 13, 2018
  1. Merge pull request #101 from mithro/master

    mithro committed Nov 13, 2018
    tinyfpga_bx: Actually use pins documented.
  2. tinyfpga_bx: Actually use pins documented.

    mithro committed Nov 13, 2018
     * Remove duplicate entry in `targets/tinyfpga_bx.py`.
     * Add useful comments.