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Branch: master
Commits on May 21, 2019
  1. Merge pull request #142 from TomKeddie/tomk_20190521_bootstrapfix

    mithro committed May 21, 2019
    bootstrap: fix logic inversion in platform detection
  2. bootstrap: fix logic inversion in platform detection

    Tom Keddie
    Tom Keddie committed May 21, 2019
Commits on May 15, 2019
  1. Merge pull request #136 from msloniewski/master

    mithro committed May 15, 2019
    platforms: add upduino_v1 platform
Commits on May 13, 2019
  1. platforms: add upduino_v1 platform

    msloniewski committed May 13, 2019
    Tested with micropython for vexriscv and lm32 lite.
Commits on May 12, 2019
  1. Merge pull request #135 from antmicro/fix_zephyr_litex_board

    mithro committed May 12, 2019
    zephyr: Change LiteX+VexRiscv board name
Commits on May 11, 2019
  1. Merge pull request #126 from antmicro/zephyr_firmware

    mithro committed May 11, 2019
    scripts: Add build-zephyr.sh script.
Commits on May 10, 2019
  1. Merge pull request #132 from mithro/remove-download-env-root

    mithro committed May 10, 2019
    scripts: Rework bootstrap.
Commits on May 9, 2019
  1. scripts: Rework bootstrap.

    mithro committed May 4, 2019
     * Check for the tools needed up `download-env.sh`.
     * Rename `download-env-root.sh` to `debian-setup.sh` (should stop
       people thinking we are Debian only).
  2. Merge pull request #133 from mithro/python-upgrade

    mithro committed May 9, 2019
    Upgrade version of Python
Commits on May 8, 2019
Commits on Apr 27, 2019
  1. Merge pull request #113 from CarlFK/repo-name

    mithro committed Apr 27, 2019
    Fix upstream repository detection.
Commits on Apr 26, 2019
  1. scripts: Fix upstream repository detection.

    CarlFK authored and mithro committed Dec 15, 2018
    Fixes #111.
  2. Merge pull request #130 from futaris/minerva

    mithro committed Apr 26, 2019
    minerva support
  3. minerva support

    futaris authored and mithro committed Apr 26, 2019
  4. Merge pull request #129 from mithro/conda-patch

    mithro committed Apr 26, 2019
    scripts: More aggressive patching of conda.
  5. scripts: More aggressive patching of conda.

    mithro committed Apr 25, 2019
    Patch conda to make expanduser return the `${CONDA_DIR}` rather than the
    user's home directory.
Commits on Feb 14, 2019
  1. Merge pull request #467 from mithro/update-submodules

    mithro committed Feb 14, 2019
    Updating submodules.
Commits on Feb 13, 2019
  1. Updating submodules.

    mithro committed Feb 13, 2019
     * litedram changed from 906edf1 to d89b171
        * d89b171 - modules/mt40a1g8: use _L (long) timings <Florent Kermarrec>
        * 2d4fdd1 - litedram/sdram_init/ddr4: disable data mask (not required) <Florent Kermarrec>
        *   0b49cbb - Merge pull request #74 from softerhardware/master <enjoy-digital>
        |\
        | * d65377f - Update to MT40A1G8 that Phillip was successful with <Steve Haynal - VSD Engineering>
        * | f207454 - sdram_init/ddr4: set data mask enable bit <Florent Kermarrec>
        * |   6d09a47 - Merge pull request #73 from softerhardware/master <enjoy-digital>
        |\ \
        | |/
        | * 8e6ad4c - Additional DDR3 and DDR4 SDRAMModules <Steve Haynal - VSD Engineering>
        * | 92df55f - travis: change tests order, comment test_examples for now (need to install the CPU toolchain to travis) <Florent Kermarrec>
        |/
        * 2d4b5ba - core/crossbar: cosmetic <Florent Kermarrec>
        * 429d3a8 - test/common: set rdata_valid_rand_level default value to 0 <Florent Kermarrec>
        * 9ddb3e2 - travis: set python version to 3.6 <Florent Kermarrec>
        *   cc38804 - Merge pull request #72 from EwoutH/master <enjoy-digital>
        |\
        | * 8e01cba - Add Travis CI (#1) <Ewout ter Hoeven>
        |/
        * 031746a - frontend/bist: fix for data_width < 31 (16 bits SDRAMs) <Florent Kermarrec>
        * b4c552a - core/multiplexer: fix command steering for nphases=1 (SDRAM), thanks jfng <Florent Kermarrec>
        * 224a423 - common: allow setting electrical settings with DDR4 <Florent Kermarrec>
        * fc3a192 - phy/gensdrphy: make CAS latency configurable <Florent Kermarrec>
        * b4ee95c - sdram_init: generate ddrx_mr1 only if mr1 is not None <Florent Kermarrec>
        * 2483d25 - test/test_ecc: update <Florent Kermarrec>
        * 6757a14 - frontend/ecc: add error injection capability <Florent Kermarrec>
        * 7eee80d - frontend/ecc: add description, rename dec signal to ded <Florent Kermarrec>
        * 14c6062 - core/crossbar: remove "ROW_COL_BANK" address_mapping (need to be simulated) <Florent Kermarrec>
        * 180b3d2 - modules: adjust MT48LC16M16 timings <Florent Kermarrec>
    
     * liteeth changed from d7fdcbb to 77fa4bf
        * 77fa4bf - phy: add Kintex7 1000BaseX PHY <Florent Kermarrec>
        * c2d8a46 - phy: add Kintex Ultrascale PHY (copyright M-Labs Ltd) <Florent Kermarrec>
    
     * litepcie changed from b29c3a0 to 3804c49
        * 3804c49 - frontend/dma: use max_request_size constant for DMAReader <Florent Kermarrec>
        * 3c4eb61 - core/msi: don't wait retransmit timer when irq vector changes <Florent Kermarrec>
        * 4196708 - core/tlp: expose tags/tlp_req/tlp_cmp <Florent Kermarrec>
        * 324ab72 - examples/targets: update crg with new phy (can't use pcie rst) <Florent Kermarrec>
        * 14acea3 - software/linux/kernel/main: fix compilation on 4.11.0 and > kernels (thanks nanortemis) <Florent Kermarrec>
        * b304a7a - software/linux/user: update dump_version <Florent Kermarrec>
    
     * litescope changed from 1634fa3 to c1d8bdf
        * c1d8bdf - core: fix Trigger flush when disabled <Florent Kermarrec>
    
     * litevideo changed from 0993a4e to 98e145f
        * 98e145f - Merge pull request #22 from rohitk-singh/regression-fix <enjoy-digital>
        * 411669b - input/clocking/S7Clocking: fix clock-domains when split_clocking=False <Rohit Singh>
        * 17ebc03 - output/hdmi: fix incorrect clock domain in S7HDMIOutEncoderSerializer <Rohit Singh>
        * 1e51823 - driver/hdmi: fix sink connection <Rohit Singh>
    
     * litex changed from v0.1-679-ga7378a72 to v0.1-710-gaf52842f
        * af52842f - soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches <Florent Kermarrec>
        * 32543430 - build/lattice/common/LatticeECXTrellisImpl: add support for nbits == 1 <Florent Kermarrec>
        * aabf042d - soc_sdram: don't generate sdram initialization error message when integrated_main_ram is used <Florent Kermarrec>
        * f51ad436 - build/lattice/common: add LatticeiCE40DDROutput <Florent Kermarrec>
        * 22ccf9dd - platforms/nexys_video: add LPC transceivers pins <Florent Kermarrec>
        * 1d9c5588 - build/sim: add jtagremote module (thanks LamdaConcept) <Florent Kermarrec>
        * 57b8bdd5 - soc/integration/soc_core: allow disabling wishbone timeout <Florent Kermarrec>
        * 05dcb5ca - soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles <Florent Kermarrec>
        * 02708d3b - boards/platform/kc705: add sfp pins (both tx and rx) <Florent Kermarrec>
        * 8344a6a4 - soc/cores/clock: add USIDELAYCTRL <Florent Kermarrec>
        * 7e0dd376 - soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case <Florent Kermarrec>
        * 871b958f - boards/targets: improve presentation <Florent Kermarrec>
        * a318343a - boards/platforms/kcu105: add si570_refclk <Florent Kermarrec>
        * 48312890 - boards/platforms/kc705: use vivado as default programmer <Florent Kermarrec>
        * 1b23890e - soc/cores/clock: allow ClockSignal to be used for clkin <Florent Kermarrec>
        * 387ee041 - build/sim/core: fix coverage <Florent Kermarrec>
        * 482abf9b - build/sim/core: set -Wno-BLKANDNBLK (prevent blocking/non-blocking assigns on a same structure in system verilog) <Florent Kermarrec>
        * 9c5f6547 - build/sim/core: set unroll-count to 256 to prevent Error-BLKLOOPINIT <Florent Kermarrec>
        * f132012d - build/sim: disable Warning-WIDTH <Florent Kermarrec>
        * 7c67bac7 - soc/cores/cpu/vexriscv: set default variant to None in add_sources <Florent Kermarrec>
        * 648015d7 - soc/cores/cpu/vexriscv: move verilog variant selection to add_sources <Florent Kermarrec>
        * 2b5a6f10 - targets/kcu105: use USMMCM <Florent Kermarrec>
        * 86e19e62 - targets: pass speedgrade to S7PLL/S7MMCM <Florent Kermarrec>
        * 2581a003 - soc/cores/clock: add Xilinx Ultrascale PLL/MMCM <Florent Kermarrec>
        * 68e1dfca - boards: avoid duplicating platforms that can be found in migen/litex-buildenv <Florent Kermarrec>
        * 041bf412 - soc/integration/cpu_interface: generate name for Memories in get_csr_header <Florent Kermarrec>
        * 9f5d0cef - utils/litex_server: allow specify uart_baudrate as float <Florent Kermarrec>
        * 2c43f6f7 - targets/ulx3s: use pll for phase shift, enable refresh, memtest ok <Florent Kermarrec>
        * 5ef4d09c - targets/versa_ecp5: use pll for phase shift, enable refresh, memtest ok <Florent Kermarrec>
        * 9c801fbe - soc/cores/clock/ECP5PLL: add basic phase support <Florent Kermarrec>
        * a7b5b9d2 - litex_sim: simplify, change sdram module and enable sdram refresh. <Florent Kermarrec>
    
     * migen changed from 0.6.dev-229-g5e7c71a to 0.6.dev-241-gafe4405
        * afe4405 - sayma_rtm: add si5324_clkout_fabric and rtm_master_aux_clk <Sebastien Bourdeauducq>
        * 3e6f39a - build/platforms: add upduino_v1 board initial support <msloniewski>
        * 6902e6f - sayma_amc: remove outdated and inaccurate comment <Sebastien Bourdeauducq>
        * 57c4467 - sayma_amc: add gth_clk200 pins <Sebastien Bourdeauducq>
        * 81ba8ca - Updating Pins of de0nanosoc.py Platform file <AlexanderKnapik>
        * 9da60e3 - sayma_rtm: offer 50T option <Sebastien Bourdeauducq>
        * fd23e4f - sayma_rtm: fix si5324_clkin IOSTANDARD <Sebastien Bourdeauducq>
        * ee0a827 - sayma_rtm: add DRTIO satellite signals <Sebastien Bourdeauducq>
        * 8bfbdcb - sayma_rtm: cleanup resource numbers <Sebastien Bourdeauducq>
        * 3d919dd - sayma_amc: add master SATA connector pins <Sebastien Bourdeauducq>
        * 27e65bf - test: use environment variables to determine FPGA toolchain presence <William D. Jones>
        * 5ab577e - Minor bugfix in docstring, missing comma at end of line. <Christian Vogel>
    
    Full submodule status
    --
     6def7bc83dfb0338632e06a8b14c93faa6af8879 edid-decode (heads/master)
     a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (heads/master)
     d89b17177ae675a493ae100de66f64a759f4b82c litedram (remotes/origin/HEAD)
     77fa4bfb1e452adb1fa34c1b0baede68c056763d liteeth (remotes/origin/HEAD)
     3804c4947adedc6c720e3041e518627b0bf57f78 litepcie (remotes/origin/HEAD)
     b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (heads/master)
     c1d8bdf6f23b1070b8bd2dd277a4708863474148 litescope (remotes/origin/HEAD)
     0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
     98e145fba8c25394e9958bad67e2a457d145127e litevideo (remotes/origin/HEAD)
     af52842fbb250d795d110d79fd2ac91442ad98b9 litex (v0.1-710-gaf52842f)
     afe4405becdbc76539f0195c319367187012b05e migen (0.6.dev-241-gafe4405)
Commits on Dec 28, 2018
  1. Merge pull request #119 from cr1901/patch-1

    mithro committed Dec 28, 2018
    Install tinyprog from repo until new version is uploaded to PyPI.
  2. Merge pull request #462 from rohitk-singh/mmcm_fix

    mithro committed Dec 28, 2018
    firmware: fix MMCM multiplier & divisor calculation
  3. firmware: fix MMCM multiplier & divisor calculation

    rohitk-singh committed Dec 28, 2018
    Also warn if the calculated VCO frequency strays outside the
    datasheet specified range
    
    Signed-off-by: Rohit Singh <rohit91.2008@gmail.com>
Commits on Dec 25, 2018
  1. Merge pull request #118 from mithro/master

    mithro committed Dec 25, 2018
    Updating submodules.
  2. Updating submodules.

    mithro committed Dec 25, 2018
     * litedram changed from 81fa19e to 906edf1
        * 906edf1 - phy/gensdrphy: make cke/dm optional. <Florent Kermarrec>
    
     * litex changed from v0.1-677-g291843ee to v0.1-679-ga7378a72
        * a7378a72 - .gitmodules: use our copy of tapcfg since https://github.com/nizox/tapcfg no longer exists. <Florent Kermarrec>
        * 2deffd8c - build/sim/verilator: compile sim just before running and not when building. <Florent Kermarrec>
    
     * migen changed from 0.6.dev-228-g37db6bb to 0.6.dev-229-g5e7c71a
        * 5e7c71a - build/xilinx/vivado: use build_name instead of top in synth_design <Florent Kermarrec>
    
    Full submodule status
    --
     6def7bc83dfb0338632e06a8b14c93faa6af8879 edid-decode (remotes/origin/HEAD)
     a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (heads/master)
     906edf19177a55123f28f922e0b85700b7d191e5 litedram (remotes/origin/HEAD)
     d7fdcbb1dc17d07852b1c9957d62f68d2dde29b5 liteeth (remotes/origin/HEAD)
     b29c3a07bc5e4e7eb8c12b174446b85371ffb3a0 litepcie (remotes/origin/HEAD)
     b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (heads/master)
     1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (heads/master)
     0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
     0993a4e0422454e522e1d2b491837034b8dcccbe litevideo (remotes/origin/HEAD)
     a7378a721c039c89f6c339b9c0c50609f8769c0a litex (v0.1-679-ga7378a72)
     5e7c71acead518802c8ae1f27163e4f2a9218f36 migen (0.6.dev-229-g5e7c71a)
Commits on Dec 20, 2018
  1. Merge pull request #116 from mithro/update-submodules

    mithro committed Dec 20, 2018
    Update submodules
  2. Updating submodules.

    mithro committed Dec 20, 2018
     * litedram changed from da6fc8c to 81fa19e
        * 81fa19e - phy/usddrphy: fix DRC REQP-1665. <Florent Kermarrec>
        * c275755 - phy/usddrphy: add iodelay_clk_freq parameter <Florent Kermarrec>
        * 62a31de - phy: rename KUSDDRPHY to USDDRPHY since compatible with Kintex/Virtex Ultrascale <Florent Kermarrec>
        * e91366c - frontend/axi: use buffered SyncFIFO on datapath (reduce resource usage) <Florent Kermarrec>
    
     * liteeth changed from 52c2301 to d7fdcbb
        * d7fdcbb - phy: add Spartan6 RGMII PHY <Florent Kermarrec>
    
     * litex changed from v0.1-668-g1c1c1bd1 to v0.1-677-g291843ee
        *   291843ee - Merge pull request #144 from mithro/nextpnr-migen-update <Tim Ansell>
        |\
        | * 53731b79 - Integrate latest migen changes for lattice/icestorm. <Tim 'mithro' Ansell>
        * 180912a7 - build/sim: handle verilog $finish and if coverage is enabled, write report at the end of the simulation. <Florent Kermarrec>
        * b6c98cab - platforms/kcu105: change internal vref to 0.84v (recommended value for ddr4) <Florent Kermarrec>
        * ebe0d567 - bios/sdram: only show read delays when they are valid. <Florent Kermarrec>
        * 67a25902 - bios/sdram: reduce write leveling scan range <Florent Kermarrec>
        * fe5cef42 - soc/cores/clock: remove return on S7PLL.create_clkout <Florent Kermarrec>
        * eda1a83e - platforms/kcu105: set internal vref on ddr4 banks <Florent Kermarrec>
        * a27b5a3b - update Ultrascale DDRPHY <Florent Kermarrec>
    
    Full submodule status
    --
     6def7bc83dfb0338632e06a8b14c93faa6af8879 edid-decode (heads/master)
     a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (heads/master)
     81fa19e58d878a9d725086f3bb54aaed53cc6cde litedram (remotes/origin/HEAD)
     d7fdcbb1dc17d07852b1c9957d62f68d2dde29b5 liteeth (remotes/origin/HEAD)
     b29c3a07bc5e4e7eb8c12b174446b85371ffb3a0 litepcie (heads/master)
     b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (heads/master)
     1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (heads/master)
     0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
     0993a4e0422454e522e1d2b491837034b8dcccbe litevideo (heads/master)
     291843ee76b43f8308cfdba21aa8a99c07327855 litex (v0.1-677-g291843ee)
     37db6bb52532b6d1c6bc8b724c2e8c6a38546c2a migen (0.6.dev-228-g37db6bb)
Commits on Dec 18, 2018
  1. Merge pull request #115 from mithro/master

    mithro committed Dec 18, 2018
    Updating submodules.
  2. Updating submodules.

    mithro committed Dec 18, 2018
     * litedram changed from 0572006 to da6fc8c
        * da6fc8c - README: add Kintex Ultrascale PHY <Florent Kermarrec>
        * 8993e8b - core/refresher: fix refresh regression <Florent Kermarrec>
        * 83f763f - phy: replace wdly_dqs_taps with half_sys8x_taps (similar to what is implemented on 7-series) <Florent Kermarrec>
        * 28b7d32 - phy/kusddrphy: use rdly_dq_bitslip_rst CSR for bitslip reset <Florent Kermarrec>
        * 1ece2ca - phy/dfi: set act_n reset value to 1 <Florent Kermarrec>
    
     * litex changed from v0.1-664-g0ade06c0 to v0.1-668-g1c1c1bd1
        *   1c1c1bd1 - Merge pull request #141 from mithro/xst-fix <Tim Ansell>
        |\
        | * 8b2abc7e - Fix `-vlgincdir` for xst. <Tim 'mithro' Ansell>
        * f8f3683a - bios/sdram: reduce scans verbosity on ultrascale <Florent Kermarrec>
        * efce434a - bios/sdram: use ddrphy_half_sys8x_taps_read() for KUSDDRPHY <Florent Kermarrec>
    
    Full submodule status
    --
     6def7bc83dfb0338632e06a8b14c93faa6af8879 edid-decode (remotes/origin/HEAD)
     a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (heads/master)
     da6fc8c39b1376727c0184896ea494557500d645 litedram (remotes/origin/HEAD)
     52c23015b052e40600a84ac73227fb5a0f0ce862 liteeth (remotes/origin/HEAD)
     b29c3a07bc5e4e7eb8c12b174446b85371ffb3a0 litepcie (remotes/origin/HEAD)
     b78a73110c0c26cf21bf1410329bf1e78286e929 litesata (heads/master)
     1634fa35bb9f2717ab355ca2e494e1d02fd489ec litescope (heads/master)
     0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
     0993a4e0422454e522e1d2b491837034b8dcccbe litevideo (remotes/origin/HEAD)
     1c1c1bd122224dcd9ae22288c2660b0e70a283a8 litex (v0.1-668-g1c1c1bd1)
     37db6bb52532b6d1c6bc8b724c2e8c6a38546c2a migen (0.6.dev-228-g37db6bb)
  3. Merge pull request #103 from mithro/readme-fix

    mithro committed Dec 18, 2018
    docs: Fix missing s
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