Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Adding Travis-CI which builds gateware #58

Closed
wants to merge 20 commits into from

Conversation

Projects
None yet
2 participants
@mithro
Copy link
Member

commented Sep 18, 2015

Fixes #8.

This stuff is based of the artiq stuff at https://github.com/m-labs/artiq and uses a similar method of making a cut back Xilinx ISE which is then encrypted and only made avaliable to the CI system. Because of the stripped back nature of the Xilinx ISE, changes can cause build failures if they make ISE require new files that were not previously touched. The .travis/package-xilinx.sh script can be used to recreate the package from a full ISE install.

Travis continues to use the same "quick setup scripts" we recommend people run to get up and running. It is important to keep things this way so that we have testing of the setup instructions.

As the gateware takes significantly longer than the previous firmware builds, each target now builds on a separate machine.

@landscape-bot

This comment has been minimized.

Copy link

commented Sep 18, 2015

Code Health
Code quality remained the same when pulling 5b70063 on timvideos:travis-xilinx-pretty into 70d371c on timvideos:master.

@mithro

This comment has been minimized.

Copy link
Member Author

commented Sep 19, 2015

Closing this PR in favor of #65 which runs the builds on the new Travis-CI container infrastructure and fixes issue #55 at the same time.

@mithro mithro closed this Sep 19, 2015

@mithro mithro deleted the travis-xilinx-pretty branch Sep 19, 2015

mithro added a commit that referenced this pull request Jan 26, 2018

Updating submodules.
 * flash_proxies changed from 070d8b2 to c506426
    * c506426 - Merge pull request #3 from cr1901/master <Robert Jördens>
    * bf63a40 - Add Spartan 7 (xc7s50) bitstream, plus corresponding logic to regenerate. <William D. Jones>

 * litedram changed from a09b7a0 to 13d41f6
    * 13d41f6 - Merge pull request #9 from felixheld/indentation-fixes <Tim Ansell>
    * 72b1b10 - Fix all remaining indentation issues in python code <Felix Held>

 * litepcie changed from 09dbd6d to 945963d
    * 945963d - phy/s7pciephy: set sys_rst_n to 1 if no rst_n pad <Florent Kermarrec>
    *   5590f11 - Merge pull request #7 from felixheld/indentation-fixes <Tim Ansell>
    |\
    | * d602010 - Fix all remaining indentation issues in python code <Felix Held>
    * 9469929 - Merge pull request #6 from felixheld/indentation-fixes <Tim Ansell>
    * 5376257 - fix code indentation <Felix Held>

 * litesata changed from a8bf0d4 to af00fa6
    * af00fa6 - Merge pull request #13 from felixheld/indentation-fixes <Tim Ansell>
    * 220b601 - Fix all indentation issues in python code <Felix Held>

 * litescope changed from 7757727 to aa44da3
    * aa44da3 - example_designs/make.py: fix typos <Florent Kermarrec>
    * 72e71e7 - core: simplify <Florent Kermarrec>
    * 7803591 - Merge pull request #9 from felixheld/indentation-fixes <Tim Ansell>
    * febb358 - Fix all remaining indentation issues in python code <Felix Held>

 * liteusb changed from 9a78586 to 0b05b6c
    * 0b05b6c - +x on scripts <Florent Kermarrec>

 * litevideo changed from c9770cc to 8d940dc
    * 8d940dc - output: add raw support (10 bits tmds in dram), untested <Florent Kermarrec>
    * 5c168aa - input: add capability to get raw 10 bits data when not using dram port <Florent Kermarrec>
    * dcd9624 - input/edid: simplify scl inversion <Florent Kermarrec>
    *   3b04d1b - Merge pull request #14 from bunnie/scl-merge <enjoy-digital>
    |\
    | * 7845c85 - add inverted attribute to SCL <bunnie>
    |/
    *   a7fd5f6 - Merge pull request #13 from felixheld/indentation-fixes <Tim Ansell>
    |\
    | * 34b1a0f - Fix all remaining indentation issues in python code <Felix Held>
    |/
    * 4d6bc46 - input/datacapture: simplify inverted data in S7DataCapture <Florent Kermarrec>
    * af096a5 - input/clocking/s7: use bufr and fix input connection to mmcm <Florent Kermarrec>
    * 9ebdd1b - output: use new inverted property of pads to invert polarity <Florent Kermarrec>
    * 218b708 - output: add assertion if inverted property is used (since not yet implemented) <Florent Kermarrec>
    * 113bdb7 - input: use new inverted property of pads to invert polarity <Florent Kermarrec>
    * 091c9ec - litevideo: add __init__.py, fix install <Florent Kermarrec>
    * 9aae319 - input: add clk_polarity parameter, rename data_polarities to datas_polarity <Florent Kermarrec>

 * litex changed from v0.1-251-gead88ed6 to v0.1-270-g4f272580
    * 4f272580 - software/common: revert PYTHON to python3 (since breaking things) <Florent Kermarrec>
    * 4e168221 - bios: fix riscv processor print <Florent Kermarrec>
    * d4488748 - sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation) <Florent Kermarrec>
    *   a3851437 - Merge pull request #59 from q3k/for-upstream/multiple-synthesis-directives <enjoy-digital>
    |\
    | * 21bd26dc - Allow for multiple synthesis directives in specials. <Sergiusz Bazanski>
    |/
    * 67f8718b - minor cleanup <Florent Kermarrec>
    *   d07ddd11 - Merge pull request #58 from q3k/for-upstream/picorv32-support <enjoy-digital>
    |\
    | * 6daf3eab - Implement IRQ software support for RISC-V. <Sergiusz Bazanski>
    | * 2108c97b - Import PicoRV32-specific instruction macros. <Sergiusz Bazanski>
    | * cf74c781 - Write init files that respect CPU's endianness. <Sergiusz Bazanski>
    | * 71764922 - Set the MABI and MArch of the riscv target. <Sergiusz Bazanski>
    | * 7ea5a267 - Enable hardware multiplier and divider in PicoRV32 <Sergiusz Bazanski>
    | * 75e230aa - Replace __riscv__ macros with __riscv. <Sergiusz Bazanski>
    | * 20ed2344 - Export trap signal from PicoRV32. <Sergiusz Bazanski>
    | * b0be5630 - Bump PicoRV32 version. <Sergiusz Bazanski>
    |/
    * 3a5f93db - software/bios: add litex logo <Florent Kermarrec>
    *   d6877300 - Merge pull request #56 from cr1901/mimasv2 <enjoy-digital>
    |\
    | * c553fe2b - Add mimasv2 platform (pulled from litex-buildenv). <William D. Jones>
    |/
    * d6f2f637 - Merge pull request #53 from mithro/allow-forcing-colorama <Tim Ansell>

Full submodule status
--
 f56f329ed23a25d002352dedba1e8f092a47286f edid-decode (heads/master)
 c5064269868396b2c7a78bff28f8e3cf421d1f6e flash_proxies (remotes/origin/HEAD)
 13d41f67ab3070f6af955aa8752c616d034f82f6 litedram (remotes/origin/HEAD)
 8fc716103670e703c7fe98c9bdf653b9b53ca12a liteeth (remotes/origin/HEAD)
 945963d186b3c0287426ef6655e00ad4e250d279 litepcie (remotes/origin/HEAD)
 af00fa613f1b6921e14788dd0ebf301e51009e74 litesata (remotes/origin/HEAD)
 aa44da35c6a232a9e39c43987a3afc9b025ab614 litescope (remotes/origin/HEAD)
 0b05b6c8f9279bb7e476b2c8ae4f39ea88534f08 liteusb (remotes/origin/HEAD)
 8d940dcaf21cffb18cd157e079ec94946878a5d7 litevideo (remotes/origin/HEAD)
 4f2725809e0b9b6cee94cb569c1878f48ab52a15 litex (v0.1-270-g4f272580)
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
You can’t perform that action at this time.