Cypress FX2 reset functionality needs fixing

[mithro]

The Cypress FX2 to used for JTAG programming of the FPGA, so it needs to come up no matter what the FPGA is currently programmed with. Currently if the FPGA doesn't pull Cypress-RST net high or float the FX2 won't boot.

Ported from http://redmine.numato.in/issues/1959

[mithro]

From Anoop;

The diode direction(D12,D13 should be reverse for providing external RESET( Need to change in the schematic).
Cypress is enumerating if the FPGA is in not configured condition ie., by default FPGA IOs will be weak pull up enabled condition( This is due to HSWAP pin state).
After configuring IO state will go low to avoid we should PULLUP the Cypress RESET pin in the UCF.

[mithro]

The desired behaviour is the following;

• Shorting the reset switch caused both the FX2 and the FPGA to undergo a reset.
• The FPGA is able to cause the FX2 to reset by toggling the IO pin connected to Cypress reset line.
• The FX2 will boot after a "fail safe delay" no matter the state of the FPGA. IE Even if the FPGA is actively pulling the line low.

As most people will be using the FX2 as a JTAG usb programmer, it is important that even if the SPI flash is loaded with bitstream that constantly pulls the Cypress RESET line permanently low, the FX2 will eventually boot in unconfigured mode.

[mithro]

We should also add a jumper which lets this line be totally disconnected.

[mithro]

#15

[mithro]

At the moment, the FX2 should come up as an unconfigured Cypress FX2 but only if the FPGA is correctly configured.

Pin G22 (the Cypress Reset line) must be pulled high or left floating.

For the moment we set all the unused pins to be floating - see https://github.com/timvideos/HDMI2USB-misoc-firmware/blob/master/platforms/opsis.py#L316

[mithro]

A friend suggested the following circuits;

from left to right - differentiator, (inverse) peak detector, ac coupler. I think you'll need to play with the values a bit to get the right timing and peak size.

reset.asc (ltspice file)

Version 4
SHEET 1 1120 680
WIRE 784 -80 720 -80
WIRE 816 -80 784 -80
WIRE 928 -80 896 -80
WIRE 80 64 80 32
WIRE 160 64 80 64
WIRE 288 64 224 64
WIRE 368 64 288 64
WIRE 496 64 432 64
WIRE 640 64 496 64
WIRE 672 64 640 64
WIRE 784 64 784 -80
WIRE 784 64 736 64
WIRE 784 112 784 64
WIRE 80 128 80 64
WIRE 288 128 288 64
WIRE 640 128 640 64
WIRE 928 128 928 -80
WIRE 496 144 496 64
WIRE 80 256 80 208
WIRE 288 256 288 208
WIRE 288 256 80 256
WIRE 496 256 496 208
WIRE 496 256 288 256
WIRE 640 256 640 208
WIRE 640 256 496 256
WIRE 784 256 784 192
WIRE 784 256 640 256
WIRE 928 256 928 208
WIRE 928 256 784 256
WIRE 80 304 80 256
FLAG 80 304 0
FLAG 80 32 FPGA
FLAG 720 -80 RST
SYMBOL voltage 80 112 R0
WINDOW 3 -413 53 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(3.3 0 20m 1u 1u 30m 50m)
SYMBOL res 272 112 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL cap 160 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value 10µ
SYMBOL diode 432 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL cap 480 144 R0
SYMATTR InstName C2
SYMATTR Value 10p
SYMBOL res 624 112 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL voltage 928 112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL res 768 96 R0
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL res 800 -64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL cap 672 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C3
SYMATTR Value 1µ
TEXT -146 328 Left 2 !.tran 200m

tim.asc (ltspice file)

Version 4
SHEET 1 1228 680
WIRE 96 0 0 0
WIRE 96 32 96 0
WIRE 384 64 368 64
WIRE 480 64 464 64
WIRE 0 112 0 0
WIRE 96 176 96 112
WIRE 192 176 96 176
WIRE 272 176 272 128
WIRE 272 176 192 176
WIRE 336 176 272 176
WIRE 368 176 368 64
WIRE 368 176 336 176
WIRE 384 176 368 176
WIRE 480 176 480 64
WIRE 480 176 448 176
WIRE 544 176 480 176
WIRE 720 176 720 128
WIRE 720 176 544 176
WIRE 96 192 96 176
WIRE 192 192 192 176
WIRE 336 192 336 176
WIRE 544 208 544 176
WIRE 720 208 720 176
WIRE 0 304 0 192
WIRE 96 304 96 272
WIRE 96 304 0 304
WIRE 192 304 192 256
WIRE 192 304 96 304
WIRE 336 304 336 256
WIRE 336 304 192 304
WIRE 544 304 544 288
WIRE 544 304 336 304
WIRE 720 304 720 288
WIRE 720 304 544 304
WIRE 720 336 720 304
FLAG 720 336 0
FLAG 720 128 FPGA
FLAG 272 128 RST
SYMBOL voltage 0 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 4.7
SYMBOL res 80 16 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 80 176 R0
SYMATTR InstName R2
SYMATTR Value 1000k
SYMBOL res 528 192 R0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL voltage 720 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(4.7 0 20m 1u 1u 15m 50m 100)
SYMBOL cap 384 192 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value 4.7µ
SYMBOL res 368 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL cap 176 192 R0
SYMATTR InstName C2
SYMATTR Value 1p
SYMBOL zener 352 256 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N750
TEXT -34 360 Left 2 !.tran 200ms

[mithro]

The specification for this circuit is;

• No matter the FPGA I/O pin state (high, low, high impedance or any voltage in between) - the Cypress RST pin must go high (2.0V), after at least 10 milliseconds, but no more than 250 milliseconds.
• Pulsing the FPGA I/O pin low should cause the Cypress pin to go low (below 0.8V) for 200 microseconds.