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liteeth: Fix for changes in LiteEth upstream.

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mithro committed Jan 4, 2018
1 parent d8ebfa9 commit dc90b3543ce0eb06814b7bccb391478621bf698f
Showing with 22 additions and 6 deletions.
  1. +22 −6 hw/net/liteeth.c
@@ -33,23 +33,39 @@
#define LITEETH_BUFFER_SIZE 0x800

enum {
R_ETHMAC_SRAM_WRITER_SLOT,
R_ETHMAC_SRAM_WRITER_LENGTH0,
R_ETHMAC_SRAM_WRITER_LENGTH1,
R_ETHMAC_SRAM_WRITER_LENGTH2,
R_ETHMAC_SRAM_WRITER_LENGTH3,
R_ETHMAC_SRAM_WRITER_SLOT, // 0

R_ETHMAC_SRAM_WRITER_LENGTH0, // 1 = 4
R_ETHMAC_SRAM_WRITER_LENGTH1, // 2 = 8
R_ETHMAC_SRAM_WRITER_LENGTH2, // 3 = 12 = 0x0c
R_ETHMAC_SRAM_WRITER_LENGTH3, // 4 = 16 = 0x10

R_ETHMAC_SRAM_WRITER_ERRORS0,
R_ETHMAC_SRAM_WRITER_ERRORS1,
R_ETHMAC_SRAM_WRITER_ERRORS2,
R_ETHMAC_SRAM_WRITER_ERRORS3,

R_ETHMAC_SRAM_WRITER_EV_STATUS,
R_ETHMAC_SRAM_WRITER_EV_PENDING,
R_ETHMAC_SRAM_WRITER_EV_ENABLE,

R_ETHMAC_SRAM_READER_START,
R_ETHMAC_SRAM_READER_READY,
R_ETHMAC_SRAM_READER_LEVEL,
R_ETHMAC_SRAM_READER_SLOT,
R_ETHMAC_SRAM_READER_LENGTH0,
R_ETHMAC_SRAM_READER_LENGTH1,
R_ETHMAC_SRAM_READER_EV_STATUS,
R_ETHMAC_SRAM_READER_EV_PENDING,
R_ETHMAC_SRAM_READER_EV_ENABLE,

R_ETHMAC_PREAMBLE_CRC,

R_ETHMAC_CRC_ERRORS0,
R_ETHMAC_CRC_ERRORS1,
R_ETHMAC_CRC_ERRORS2,
R_ETHMAC_CRC_ERRORS3,

R_MAX,
};

@@ -312,7 +328,7 @@ static uint64_t liteeth_reg_read(void *opaque, hwaddr addr, unsigned size)
uint32_t r = 0;
addr >>= 2;
r = s->regs[addr];
if (addr == 9)
if (addr == R_ETHMAC_SRAM_READER_READY)
r = 1;

//printf("Reading addr %08x value %08x\n", (unsigned int)addr, (unsigned int)r);

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