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Tracking: Support RISC-V #1135

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bradjc opened this issue Jul 26, 2018 · 4 comments

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@bradjc
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commented Jul 26, 2018

This RISC-V architecture continues to gain momentum, and having Tock support risc-v boards seems quite feasible. With the embedded version still in development, it seems like Tock could be a leading embedded OS for risc-v platforms. Also, supporting multiple architectures would demonstrate the Tock architecture flexibility.

  • Add support for risc-v (at least riscv32imac) in nightly rust. (rust-embedded/wg#36, rust-lang/rust#52787)
  • Simplify binutils for riscv32. Ideally the LLVM tools that ship with rust will work. But if not we need some way to distribute riscv32-ld and riscv32-objcopy that doesn't rely on users building from source.
  • Develop support for risc-v in Tock.
    • Add a RV32I arch crate. #1323
    • Create a HiFive1 board in /boards. PR: #1317
    • Create an arty-e21 board for running the E21 core on the ARTY FPGA. #1323
    • Implement a driver for the Physical Memory Protection (PMP) peripheral.
    • Implement a driver for the CLIC peripheral. #1323
    • Implement UserlandKernelBoundary for risc-v. This would enable context switches to userland. #1323
    • Implement a systick replacement for providing timeslices for apps.
    • Support the HiFive1(b) board.
    • Add better fault printing and debugging support.
  • Add support to Tockloader for loading code on risc-v boards. It seems like they use openocd, but unfortunately it seems to be a custom fork. https://github.com/riscv/riscv-wiki/wiki/RISC-V-Software-Status#openocd Status: this exists for arty-e21, pending for HiFive1.
  • Support userland c apps
    • Update crt0.c and tock.c to support risc-v. Branch: riscv
    • Get PIC working. This seems like it might be a ways off: riscv/riscv-gcc#158
    • Verify various more advanced apps work.

@bradjc bradjc added the tracking label Jul 26, 2018

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commented Aug 10, 2018

The development for this is happening in the https://github.com/tock/tock/tree/riscv branch.

So far:

  • riscvimac crate
  • basic e310x chip
  • basic hifive1 board
  • UART TX working
  • GPIO set working
  • GPIO interrupts (untested)
  • RTC implementation
  • alarm hil implementation
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commented Aug 17, 2018

I'm having trouble figuring out how to implement the context switch for Tock. Now the HiFive E310 chip only has M-mode, which means we won't have the application isolation we want, but it will serve as a proof of concept.

I think there are three primary operations to make context switching happen:

Switching to userland the first time

After the kernel is setup and the processes are loaded, the kernel must switch to the first process. I believe this can be done by setting the mepc register and calling the MRET instruction:

// Set mepc to the starting PC of the app.
// Here it is assuming the app entry point is at address 0x20c00000.
lui a0, %hi(0x20c00000)
addi a0, a0, %lo(0x20c00000)
csrw 0x341, a0

// Now go to what is in mepc.
mret

The mret instruction changes the privilege level before it executes code at the new location. This doesn't matter on a platform with only M mode, but it sets up an easier transition to a chip with user mode.

Returning from the app to the kernel.

To call a syscall the app has to return control to the kernel. I believe the app can do this with the ECALL instruction.

Handling the syscall and returning to the app

When the app calls the ECALL instruction that causes the trap handler to execute (which is configured by setting the mtvec register) with mcause set to "Environment call from M-mode". The trap handler can save the register state and handle whatever else it needs to, but it also needs to return execution to the instruction after the jump to the userland app. That is, the switch_to() function needs to be able to return. This is what I am unsure of how to do.

Using the MRET instruction at this point would, if I understand correctly, switch back to the app.

@anmolsahoo25

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commented Aug 27, 2018

ECALL and EBREAK cause the receiving privilege mode’s epc register to be set to the address of
the ECALL or EBREAK instruction itself, not the address of the following instruction.

So based on this, we would have to set mepc to mepc + 4 and then mret which will then return to the userland app, if that is what is required. Setting mepc to the next instruction address is necessary.

@DieracDelta

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commented Oct 12, 2018

Is this still in development on the riscv branch? If so, has anyone tried to test this on the riscv board? Did you manage to get openocd working well enough to actually load tock without userland/context switching onto the board?

@bradjc bradjc changed the title Tracking: Support RISC-V and HiFive1 Board Tracking: Support RISC-V Nov 26, 2018

@bradjc bradjc referenced this issue Jun 11, 2019

Merged

RISC-V: Add context switching #1323

2 of 2 tasks complete

bors bot added a commit that referenced this issue Aug 2, 2019

Merge #1323
1323: RISC-V: Add context switching r=bradjc a=bradjc

### Pull Request Overview

This pull request implements the `UserlandKernelBoundary` trait for RISC-V platforms.

This PR is towards tracking issue #1135.

This depends on #1318 so those commits have been included here. That PR should be merged first, and then I can update this one.

While I pulled things together for the PR, @sv2bb did much of this.

### Testing Strategy

This pull request was tested by running blink and c_hello on the the arty-e21 FPGA based board.


### TODO or Help Wanted

See inline comments.


### Documentation Updated

- [x] Updated the relevant files in `/docs`, or no updates are required.

### Formatting

- [x] Ran `make formatall`.


Co-authored-by: Brad Campbell <bradjc5@gmail.com>
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