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base: bf8bbc7180
...
compare: 9ca23a582e
  • 2 commits
  • 3 files changed
  • 0 commit comments
  • 1 contributor
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3  Language/Verilog/Lex.x
@@ -61,8 +61,11 @@ tokens :-
"always" { tok KW_always }
"assign" { tok KW_assign }
"begin" { tok KW_begin }
+ "case" { tok KW_case }
+ "default" { tok KW_default }
"else" { tok KW_else }
"end" { tok KW_end }
+ "endcase" { tok KW_endcase }
"endmodule" { tok KW_endmodule }
"for" { tok KW_for }
"if" { tok KW_if }
View
35 Language/Verilog/Parse.hs
@@ -72,13 +72,26 @@ modulePortList = oneOf
moduleItem :: Verilog ModuleItem
moduleItem = oneOf
- [ do { tok KW_parameter; commit $ do { a <- identifier; tok Sym_eq; b <- expr; tok Sym_semi; return $ Paremeter a b } }
+ [ do { tok KW_parameter; commit $ do { a <- optional range; b <- identifier; tok Sym_eq; c <- expr; tok Sym_semi; return $ Paremeter a b c } }
, do { a <- net; commit $ do { b <- optional range; c <- declarations; tok Sym_semi; return $ a b c } }
, do { tok KW_assign; commit $ do { a <- lhs; tok Sym_eq; b <- expr; tok Sym_semi; return $ Assign a b } }
, do { tok KW_initial; commit $ do { a <- stmt; return $ Initial a } }
, do { tok KW_always; commit $ do { tok Sym_at; tok Sym_paren_l; a <- sense; tok Sym_paren_r; b <- stmt; return $ Always a b } }
+ , do { a <- identifier; b <- parameterBindings; c <- identifier; d <- signalBindings; tok Sym_semi; return $ Instance a b c d }
]
+parameterBindings :: Verilog [(Identifier, Maybe Expr)]
+parameterBindings = oneOf
+ [ do { tok Sym_pound; signalBindings }
+ , return []
+ ]
+
+signalBindings :: Verilog [(Identifier, Maybe Expr)]
+signalBindings = do { tok Sym_paren_l; a <- commaList binding; tok Sym_paren_r; return a }
+
+binding :: Verilog (Identifier, Maybe Expr)
+binding = do { tok Sym_dot; a <- identifier; tok Sym_paren_l; b <- optional expr; tok Sym_paren_r; return (a, b) }
+
range :: Verilog Range
range = do { tok Sym_brack_l; a <- expr; tok Sym_colon; b <- expr; tok Sym_brack_r; return (a, b) }
@@ -148,9 +161,10 @@ chainl1 p op = do { x <- p; rest x }
exprTop :: Verilog Expr
exprTop = oneOf
- [ do { a <- string; return $ String a }
- , do { a <- number; return $ Number a }
- , do { a <- lhs; return $ ExprLHS a }
+ [ do { a <- call; return $ ExprCall a }
+ , do { a <- string; return $ String a }
+ , do { a <- number; return $ Number a }
+ , do { a <- lhs; return $ ExprLHS a }
, do { tok Sym_paren_l; a <- expr; tok Sym_paren_r; return a }
, do { tok Sym_bang; a <- expr; return $ Not a }
, do { tok Sym_tildy; a <- expr; return $ BWNot a }
@@ -167,10 +181,21 @@ stmt = oneOf
, do { tok KW_if; tok Sym_paren_l; a <- expr; tok Sym_paren_r; b <- stmt; return $ If a b Null }
, do { a <- lhs; tok Sym_eq; b <- expr; tok Sym_semi; return $ BlockingAssignment a b }
, do { a <- lhs; tok Sym_lt_eq; b <- expr; tok Sym_semi; return $ NonBlockingAssignment a b }
- , do { a <- identifier; tok Sym_paren_l; b <- commaList expr; tok Sym_paren_r; tok Sym_semi; return $ Call a b }
+ , do { a <- call; tok Sym_semi; return $ StmtCall a }
+ , do { tok KW_case; tok Sym_paren_l; a <- expr; tok Sym_paren_r; b <- many case_; c <- optional default_; tok KW_endcase; return $ Case a b c }
, do { tok Sym_semi; return Null }
+ , do { tok Sym_pound; a <- number; b <- stmt; return $ Delay a b }
]
+call :: Verilog Call
+call = do { a <- identifier; tok Sym_paren_l; b <- commaList expr; tok Sym_paren_r; return $ Call a b }
+
+case_ :: Verilog Case
+case_ = do { a <- commaList expr; tok Sym_colon; b <- stmt; return (a, b) }
+
+default_ :: Verilog Stmt
+default_ = do { tok KW_default; tok Sym_colon; stmt }
+
sense :: Verilog Sense
sense = oneOf
[ do { a <- sense'; tok KW_or; b <- sense; return $ SenseOr a b }
View
18 Language/Verilog/Types.hs
@@ -1,19 +1,18 @@
module Language.Verilog.Types
( Identifier
- , Range
, Module (..)
, ModuleItem (..)
, Stmt (..)
, Expr (..)
, Sense (..)
, LHS (..)
+ , Call (..)
, Case
+ , Range
) where
type Identifier = String
-type Range = (Expr, Expr)
-
data Module = Module Identifier [Identifier] [ModuleItem] deriving (Show, Eq)
{-
@@ -25,7 +24,7 @@ instance Show Module where
-}
data ModuleItem
- = Paremeter Identifier Expr
+ = Paremeter (Maybe Range) Identifier Expr
| Input (Maybe Range) [(Identifier, Maybe Range)]
| Output (Maybe Range) [(Identifier, Maybe Range)]
| Inout (Maybe Range) [(Identifier, Maybe Range)]
@@ -34,12 +33,14 @@ data ModuleItem
| Initial Stmt
| Always Sense Stmt
| Assign LHS Expr
+ | Instance Identifier [(Identifier, Maybe Expr)] Identifier [(Identifier, Maybe Expr)]
deriving (Show, Eq)
data Expr
= String String
| Number String
| ExprLHS LHS
+ | ExprCall Call
| Not Expr
| And Expr Expr
| Or Expr Expr
@@ -68,17 +69,20 @@ data Expr
data Stmt
= Block (Maybe Identifier) [Stmt]
| Integer Identifier
- | Case Expr [Case] Stmt
+ | Case Expr [Case] (Maybe Stmt)
| BlockingAssignment LHS Expr
| NonBlockingAssignment LHS Expr
| For (Identifier, Expr) Expr (Identifier, Expr) Stmt
| If Expr Stmt Stmt
- | Call Identifier [Expr]
+ | StmtCall Call
+ | Delay String Stmt
| Null
deriving (Show, Eq)
type Case = ([Expr], Stmt)
+data Call = Call Identifier [Expr] deriving (Show, Eq)
+
data Sense
= Sense LHS
| SenseOr Sense Sense
@@ -92,3 +96,5 @@ data LHS
| LHSRange Identifier Range
deriving (Show, Eq)
+type Range = (Expr, Expr)
+

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