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MR1

A hobby RISC-V CPU core to learn riscv-formal and SpinalHDL.

See my write-up here: A Bug Free RISC-V Core without Simulation.

While this core works and has passed the riscv-formal test suite, it's not nearly as good as the VexRiscv core, which is smaller, synthesizes with higher clocks, and has better IPC even in slow configurations.