MR1 formally verified RISC-V CPU
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Latest commit 801f043 Dec 17, 2018
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misc LED blinking program. Sep 4, 2018
project Init Aug 17, 2018
quartus_mr1 Liveness fix. Sep 14, 2018
quartus_pico Minor stuff. Sep 5, 2018
src/main/scala/mr1 Fix double-write. Dec 16, 2018
sw Ignore progmem intermediate files Sep 5, 2018
.gitignore Decoder WIP Aug 17, 2018
LICENSE Initial commit Aug 17, 2018 Copy files from WriteBack branch Nov 19, 2018 Comment about VexRiscv. Nov 19, 2018
build.sbt Remove non-MR1 stuff. Dec 16, 2018 Remove non-MR1 stuff. Dec 16, 2018


A hobby RISC-V CPU core to learn riscv-formal and SpinalHDL.

See my write-up here: A Bug Free RISC-V Core without Simulation.

While this core works and has passed the riscv-formal test suite, it's not nearly as good as the VexRiscv core, which is smaller, synthesizes with higher clocks, and has better IPC even in slow configurations.