Skip to content

tomverbeure/panologic

master
Switch branches/tags
Code

Latest commit

 

Git stats

Files

Permalink
Failed to load latest commit information.
Type
Name
Latest commit message
Commit time
 
 
doc
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Pano Logic Zero Client G1

Questions? Try the Pano Logic gitter chat room! https://gitter.im/panologic/community

Introduction

The project log can be found here.

This project starts with the work of The Cranky Sysadmin, and will build on top of that:

Related Projects

  • Pano Man implements the original PacMan on Pano G1

Main Board

Main Board PCB

FPGA Connections

The pin constraint file can be found here.

JTAG Connector

6 pin connector J8 is the JTAG connector. When the IO connectors are at the bottom, J8 is located at the top left of the Xilinx chip, and pin 1 is the one on the left.

The pin order does NOT follow the one of my Digilent clone.

Pinout is as follows:

  1. VCC
  2. TDI
  3. TMS
  4. TDO
  5. TCK
  6. GND

SPI Connector

  1. GND
  2. CS#
  3. DQ1 (MISO)
  4. CLK
  5. DQ0 (MOSI)
  6. VCC

The SPI pins are used to configure the bitstream at power-up. After that, they become user IO.

To program the SPI, use the "Short to Program" jumper and attach SPI programmer to the connector. The "Short to Program" jumper pulls the PROG_B pin of the FPGA to ground, which forces all FPGA IOs into Hi-Z.

During development, since the JTAG is already connected anyway, it's easier to program the SPI flash through JTAG.

The procedure is simply: Using Impact, create an 'mcs' file that contains the bitstream in SPI programming format. Then use Impact to program that file into the SPI flash through JTAG.

Detailed instructions are here:

Board to Board Connector

Board 2 Board Connector Footprint

A* = inward facing side of the connector

A'* = outward facing side of the connector

Pin Function FPGA Misc
A1 GND
A2 VGA SCL D4
A3 GND
A4 VGA SDA G3
A5 GND
A6 VGA B analog
A7 GND
A8 VGA G analog
A9 VGA VSYNC D1
A10 VGA R analog
A11 VGA HSYNC C2
A14 GND
A15 SMSC USB2513 USBDN2_DP pin 4
A16 SMSC USB2513 USBDN2_DM pin 3
A17 GND
A18 SMSC USB2513 USBDN3_DM pin 6 E5
A19 SMSC USB2513 USBDN3_DP pin 7
A20 GND
A'1 GND
A'2 FPGA VCCO 3.3V F3, K1, H7, ...
A'3 GND
A'4 ? 1.8V
A'5 GND
A'6 VGA PWR (5V)
A'7 GND
A'8 Button R7 (Pressed is 3.3V)
A'9 LED Green H1
A'10 LED Blue L1
A'11 LED Red L3 4.8V (but 3.3V at FPGA)
A'14 GND
A'15 ? 3.1V
A'16 ? B7 2.45V
A'17 GND
A'18 ? 1.2V
A'19 ? 2.75V
A'20 GND

Notes:

  • VGA/SDA: Connected to top right pin of U23
  • VGA/SCL: Connected to bottom right pin of U23
  • U23: level shifters?

Resources

About

PanoLogic Zero Client G1 reverse engineering info

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published