From 4cd2e57f362e58e3fe19f8e4f1771ec874c0c8db Mon Sep 17 00:00:00 2001 From: Mykola Hohsadze Date: Mon, 14 Aug 2023 00:04:05 +0300 Subject: [PATCH] arm64/disassem.c: add type01 instruction definitions Add disassembly support for the following instructions: adc, adcs, asr, cls, clz, lsl, lsr, rbit, rev, rev16, rev32, ror, ngc, sbc, ngcs, sbcs, sdiv, smulh, udiv, umulh. --- sys/arm64/arm64/disassem.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/sys/arm64/arm64/disassem.c b/sys/arm64/arm64/disassem.c index c7fd2564f095ca..790f3781e5881e 100644 --- a/sys/arm64/arm64/disassem.c +++ b/sys/arm64/arm64/disassem.c @@ -289,22 +289,6 @@ static struct arm64_insn arm64_i[] = { TYPE_01, 0 }, { "clz", "SF(1)|101101011000000000100|RN(5)|RD(5)", TYPE_01, 0 }, - { "crc32b", "00011010110|RM(5)|010000|RN(5)|RD(5)", - TYPE_01, 0 }, - { "crc32h", "00011010110|RM(5)|010001|RN(5)|RD(5)", - TYPE_01, 0 }, - { "crc32w", "00011010110|RM(5)|010010|RN(5)|RD(5)", - TYPE_01, 0 }, - { "crc32x", "10011010110|RM(5)|010011|RN(5)|RD(5)", - TYPE_01, 0 }, - { "crc32cb", "00011010110|RM(5)|010100|RN(5)|RD(5)", - TYPE_01, 0 }, - { "crc32ch", "00011010110|RM(5)|010101|RN(5)|RD(5)", - TYPE_01, 0 }, - { "crc32cw", "00011010110|RM(5)|010110|RN(5)|RD(5)", - TYPE_01, 0 }, - { "crc32cx", "10011010110|RM(5)|010111|RN(5)|RD(5)", - TYPE_01, 0 }, { "asr", "SF(1)|0011010110|RM(5)|001010|RN(5)|RD(5)", TYPE_01, 0 }, /* asr register */ { "lsl", "SF(1)|0011010110|RM(5)|001000|RN(5)|RD(5)",