pulp-platform / ariane

449

Ariane is a 6-stage RISC-V CPU capable of booting Linux

systemverilog-hdl cpu riscv asic fpga rv64gc ariane verilator questasim

SystemVerilog Updated May 1, 2019

ZhishengWang / Embedded-Neural-Network

358

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

neural-network deep-learning fpga asic compression

Updated Apr 11, 2019

VUnit / vunit

289

VUnit is a unit testing framework for VHDL/SystemVerilog

vhdl verification systemverilog-hdl unit-testing fpga asic testbench

Good first issues

SystemVerilog: Get current test name

good first issue enhancement

#307 opened over 1 year ago by alinaivanovaoff

8

VHDL Updated Apr 30, 2019

VLSI-EDA / PoC

243

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Com…

VHDL Updated Apr 13, 2019

esig / dss

233

Digital Signature Service : creation, extension and validation of advanced electronic signatures

xades cades pades asic signature esignature validation java

Java Updated Apr 25, 2019

tymonx / logic

75

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado

SystemVerilog Updated Jul 26, 2018

Juniper / open-register-design-tool

70

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

systemrdl jspec eda asic fpga registers uvm systemverilog register-descriptions systemrdl-compiler

Verilog Updated Apr 28, 2019

ultraembedded / cores

44

Various HDL (Verilog) IP Cores

verilog rtl verilog-hdl fpga verilator verilog-components asic sdram sram audio i2s spi uart usb

Verilog Updated Apr 23, 2019

masc-ucsc / lgraph

23

Live Graph infrastructure for Synthesis and Simulation

live synthesis fpga asic simulation hdl lgraph

Good first issues

Small patches on autocompletion

good first issue

#107 opened 7 months ago by rafaeltp

Add support to lgraphs in lgcheck

good first issue help wanted

#104 opened 7 months ago by rafaeltp

Verilog Updated May 4, 2019

MaynardMiner / SWARM

23

Profit Switching Mining Administrator For HiveOS/Unix & Windows: HiveOS Integrated

PowerShell Updated May 3, 2019

minershive / hiveos-asic

19

Hive OS client for ASICs

mining bitcoin litecoin asic

Shell Updated May 1, 2019

qwertycoin-org / qwertycoin

18

Qwertycoin is a decentralized peer-to-peer protocol for safe payments worldwide.

qwertycoin cryptocurrency cryptonight asic qwc altcoin

C++ Updated May 2, 2019

SystemRDL / systemrdl-compiler

15

SystemRDL 2.0 language compiler front-end

systemrdl-compiler hardware-description-language asic fpga registers register-descriptions eda design-automation

Good first issues

Document all RDL properties

documentation

#20 opened 3 months ago by amykyta3

Python Updated May 4, 2019

bogdanvuk / pygears

15

HW Design: A Functional Approach

hardware design python functional hdl simulator fpga asic

Python Updated May 4, 2019

WindowsNT / AdES

10

An Implementation of CAdES, XAdES, PAdES and ASiC for Windows in C++

pdf xml cades xades pades mime asic etsi eidas

C Updated Dec 8, 2018

lite-david / comet

7

RISC-V ISA based 32-bit processor written in HLS

hls fpga asic isa risc catapult vivado comet

C Updated Dec 18, 2017

andrsmllr / magic_vlsi_examples

7

Some simple examples for the Magic VLSI physical chip layout tool.

vlsi vlsi-physical-design asic

Updated Oct 9, 2017

minerstat / minerstat-asic-hub

5

Software what is installed on ASIC. No external computer/node required.

minerstat mining asic baikal antminer asic-monitor monitoring hub

Shell Updated Apr 28, 2019

neogeodev / NeoChips

5

Replacement "chips" for NeoGeo systems

neogeo clone chips asic snk preservation repair fix gerber electronics pcb layout verilog logic cpld fpga neo-geo arcade

Updated Mar 27, 2019

xver / Shunt

5

SystemVerilog DPI "TCP/IP Shunt" (TCP/IP system verilog socket library)

systemverilog verilog asic dpi open-source opensource system socket tcp-ip tcp library tcpip ip systemverilog-dpi tcp-socket systemverilog-simulation communication ip-shunt ip-socket

C Updated Mar 25, 2019

dfoderick / Mining Archived

4

Updated project at Full Cycle Mining https://github.com/dfoderick/fullcycle

bitcoin mining antminer asic privileged ssh

Python Updated May 6, 2018

hashrabbit / bitmain-spi

4

Linux SPI driver for Bitmain ASIC miners.

bitcoin mining spi devicetree asic linux-kernel-module device-driver

C Updated Jul 20, 2016

coinscrow / minerstat-airnode

4

OUTDATED! Project moved to: https://github.com/minerstat/minerstat-asic

antminer baikal asic mining mining-monitor mining-software-repositories bitmain minerstat

Updated Mar 2, 2018

pulp-platform / axi_node

4

AXI X-Bar

axi systemverilog asic fpga

SystemVerilog Updated Mar 7, 2019

YosysHQ / padring

3

A padring generator for ASICs

asic vlsi yosys chip eda

C++ Updated May 3, 2019

jiaobuzuji / jiaobuzuji.github.io

3

My Pages.

blog verilog rtl website life page asic

Batchfile Updated Mar 26, 2019

pulp-platform / axi_mem_if

3

Simple single-port AXI memory interface

axi systemverilog-hdl asic fpga

SystemVerilog Updated Mar 13, 2019

SystemRDL / RALBot-html

3

Generate address space documentation HTML from compiled SystemRDL input

asic fpga eda design-automation documentation documentation-generator registers

JavaScript Updated May 4, 2019

ghosh17 / DualCoreProcessor

2

ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor

systemverilog-hdl systemverilog asic rtl

SystemVerilog Updated Aug 23, 2017

RoaLogic / roalogic.github.io

2

Roa Logic GitHub Pages Site (Top Level)

roalogic ip fpga asic riscv ahb apb

HTML Updated Nov 3, 2017

asic

Repositories 57

Good first issues

Good first issues

Good first issues

dfoderick / Mining Archived