HLS for Networks-on-Chip
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Updated
Feb 18, 2021 - C++
HLS for Networks-on-Chip
Order matching engine
Simulator that simulates multiprocessor caches and involved cache coherence protocols
Repository for a predictable directory-based cache coherence for multicore safety-critical systems
VerC3: Verification Toolkit for C3
A cache coherence simulator for MESI, MOESI and Dragon Protocols.
Trace-based simulation for cache coherence in a multicore system
P_thread parallel programming task, cache coherency.
A cache-coherent stack allocated templated vector.
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