Here are
256 public repositories
matching this topic...
Updated
Mar 24, 2021
Verilog
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Updated
Jun 24, 2024
Verilog
A small, light weight, RISC CPU soft core
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Jun 7, 2024
Verilog
The Ultra-Low Power RISC-V Core
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Mar 27, 2023
Verilog
Updated
Sep 18, 2021
Verilog
32-bit Superscalar RISC-V CPU
Updated
Sep 18, 2021
Verilog
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Updated
Dec 21, 2023
Verilog
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
Updated
Jun 10, 2024
Verilog
Put WebAssembly in your washing machine
Updated
Nov 3, 2017
Verilog
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
Updated
Jun 28, 2021
Verilog
8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
Updated
Oct 9, 2019
Verilog
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
Updated
Jul 20, 2023
Verilog
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。
Updated
Jan 20, 2019
Verilog
Open source RISC-V microcontroller unit for FPGAs written in Verilog
Updated
Jun 10, 2024
Verilog
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…
Updated
Jul 17, 2022
Verilog
Naïve MIPS32 SoC implementation
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Jun 23, 2020
Verilog
Updated
Jun 18, 2024
Verilog
Parallel Array of Simple Cores. Multicore processor.
Updated
May 16, 2019
Verilog
XCrypto: a cryptographic ISE for RISC-V
Updated
Jan 5, 2023
Verilog
A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.
Updated
Sep 24, 2022
Verilog
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