The Ultra-Low Power RISC Core
Verilog
Updated Mar 13, 2019
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cpu
Repositories 667
A small, light weight, RISC CPU soft core
Verilog
Updated Apr 1, 2019
Put WebAssembly in your washing machine
Parallel Array of Simple Cores. Multicore processor.
Verilog
Updated Jan 7, 2019
ZAP is a pipelined ARMv4T architecture compatible processor with cache and MMU.
Verilog
Updated Dec 15, 2018
Naïve MIPS32 SoC implementation
Verilog
Updated Sep 28, 2018
Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
Verilog
Updated Apr 29, 2019
RISC-V CPU Core (RV32IM)
Verilog
Updated Mar 31, 2019
A MIPS CPU implemented in Verilog
Verilog
Updated Sep 12, 2017
Human Resource Machine - CPU Design #HRM
Verilog
Updated Apr 28, 2019
Riscv32 CPU Project
Verilog
Updated Jan 18, 2018
8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
Verilog
Updated Oct 20, 2018
MERA-400 in an FPGA
Verilog
Updated May 15, 2018
Pinky (8-bit CPU) written in Verilog and an Assembler written in Python 3
Verilog
Updated Oct 14, 2018
A custom 16-bit computer
Verilog
Updated Oct 17, 2018
FEWcore é um core RISC-V que segue as especificações RV32E com algumas leves modificações. Este projeto é o trabalho …
Verilog
Updated Dec 15, 2018
Uranus MIPS processor by MaxXing & USTB NSCSCC team
Verilog
Updated Apr 17, 2019
A single cycle CPU running MIPS instructions on Xilinx FPGA
Verilog
Updated Aug 27, 2017
SAP-1 CPU in Verilog for the Mojo FPGA board - has seperate address bus.
Verilog
Updated May 17, 2017
中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 S…
Verilog
Updated Jun 24, 2017
MyProc is a processor implemented in verilog for educational purposes.
Verilog
Updated Jul 22, 2017
This is Lou Sir's CPU =w=
Verilog
Updated Apr 3, 2018
32 bit Single Cycle CPU——Tsinghua computer principle homework
Verilog
Updated Nov 3, 2018
This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It h…
Verilog
Updated Oct 16, 2018
Verilog implementation of pipelined MIPS processor
Verilog
Updated Nov 18, 2017
Various verilog tests.
Verilog
Updated Nov 20, 2015
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
Verilog
Updated Jan 20, 2019
FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64
Verilog
Updated Oct 10, 2017
YA RI MA SU NE !
Verilog
Updated Feb 27, 2019
Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design …
Verilog
Updated Nov 29, 2018