Python module for hardware and system monitoring
Python
Updated May 4, 2019
CoreFreq is a CPU monitoring software designed for the 64-bits Processors.
C
Updated May 4, 2019
A Scala Commodore 64 & 128 emulator
Scala
Updated May 4, 2019
Cross-platform async library for system information fetching 🦀
Rust
Updated May 4, 2019
⌨️Repositório para Disciplina INE5411 - Organização de Computadores I - UFSC
Assembly
Updated May 4, 2019
A crazy small 8-bit CPU built with only seventeen 7400-series chips.
Perl
Updated May 4, 2019
Fork of Nigel's performance Monitor for Linux, adding cgroup-awareness. Makes it easy to monitor your LXC/Docker cont…
C++
Updated May 4, 2019
Ananicy - is Another auto nice daemon, with community rules support (Use pull request please)
Python
Updated May 3, 2019
A repository of plugins and extensions for AnyStatus
C#
Updated May 3, 2019
Performance monitoring tools for Linux
C
Updated May 3, 2019
Cycle-accurate pre-silicon simulator of MIPS and RISC-V CPUs
#918 opened about 2 months ago by pavelkryukov
1
#591 opened 7 months ago by pavelkryukov
#588 opened 7 months ago by pavelkryukov
1
C++
Updated May 4, 2019
A dashboard displaying the performance of any server.
Python
Updated May 3, 2019
Web Extension — A new tab page extension with material design and useful features 🆕 🎉
JavaScript
Updated May 3, 2019
Advanced multi-algo profit switching miner
H2Oai GPU Edition
#230 opened over 1 year ago by pseudotensor
1
Python
Updated May 2, 2019
A bit-serial CPU written in VHDL, with a simulator written in C.
VHDL
Updated May 2, 2019
Node.js sensor for Instana
JavaScript
Updated May 3, 2019
CPU-X is a Free software that gathers information on CPU, motherboard and more.
C
Updated May 2, 2019
Automatically set GOMAXPROCS to match Linux container CPU quota.
Go
Updated May 2, 2019
Cross-platform lib for process and system monitoring in Python
Python
Updated May 1, 2019
XCrypto: a cryptographic ISE for RISC-V
Updated May 1, 2019
Terminal based CPU stress and monitoring utility
Python
Updated May 1, 2019
A FPGA friendly 32 bit RISC-V CPU implementation
Assembly
Updated May 1, 2019
Ariane is a 6-stage RISC-V CPU capable of booting Linux
SystemVerilog
Updated May 1, 2019
A processor my partner (Nathan Ackermann) and I created in verilog for our computer organization class. It is compati…
Verilog
Updated May 1, 2019
A small RISC-V core (SystemVerilog)
SystemVerilog
Updated Apr 30, 2019
树莓派系统监控--CPU温度监控和内存使用监控
HTML
Updated Apr 30, 2019
Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink
Verilog
Updated Apr 29, 2019
FPGA implementation of vaxman's QNICE CPU as a fully fledged 16bit system-on-a-chip
C
Updated Apr 29, 2019
Experimental MIPS CPU plugin for the Hopper Disassembler
Objective-C
Updated Apr 29, 2019