RT-Thread is an open source IoT operating system from China.
C
Updated May 4, 2019
All CPU and MCU documentation in one place
HTML
Updated Sep 7, 2018
The Ultra-Low Power RISC Core
Verilog
Updated Mar 13, 2019
The GNU MCU Eclipse plug-ins for ARM & RISC-V C/C++ developers
C
Updated Jan 1, 2019
Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP…
Forth
Updated Dec 14, 2017
RARS -- RISC-V Assembler and Runtime Simulator
#21 opened 25 days ago by TheThirdOne
3
Java
Updated Apr 26, 2019
FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud (e.g. RISC-V Rocket …
#253 opened 2 months ago by sagark
#255 opened 2 months ago by sagark
2
good first issue
enhancement
#260 opened 2 months ago by sagark
Python
Updated May 3, 2019
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
SystemVerilog
Updated Apr 11, 2019
Mirror; Work-in-progress software-rendering Vulkan implementation
Rust
Updated Mar 8, 2019
为推广RISC-V尽些薄力
CSS
Updated Feb 3, 2019
32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs
C
Updated Feb 21, 2019
A graphical 5-stage RISC-V pipeline simulator & assembly editor
C++
Updated May 1, 2019
RISC-V CPU Core
SystemVerilog
Updated Oct 3, 2018
Renode - virtual development tool for multinode embedded networks
C#
Updated May 2, 2019
A simple RISC-V processor for use in FPGA designs.
VHDL
Updated Oct 20, 2018
RISC-V instruction set simulator built for education
Kotlin
Updated Jan 5, 2019
A port of FreeRTOS for the RISC-V ISA
C
Updated Apr 22, 2019
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
Verilog
Updated Jan 5, 2019
XCrypto: a cryptographic ISE for RISC-V
Updated May 1, 2019
Fast and compact Linux distribution which uses musl libc.
Shell
Updated May 4, 2019
LicheeTang 蜂鸟E203 Core
Verilog
Updated Dec 25, 2018
OpenEmbedded/Yocto layer for RISC-V Architecture
BitBake
Updated May 4, 2019
List of ideas for getting started with TimVideos projects
Shell
Updated May 4, 2019
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
SystemVerilog
Updated Nov 14, 2018
busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.
Shell
Updated Mar 28, 2019
Basic RISC-V CPU implementation in VHDL.
VHDL
Updated Dec 14, 2018
Yet Another RISC-V Implementation
Verilog
Updated Jul 10, 2016
SoftCPU/SoC engine-V
Verilog
Updated Mar 8, 2019
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the defau…
C
Updated Apr 24, 2019
Stack-based arbitrary-precision integers - Fast and portable with natural syntax for resource-restricted devices.
good first issue
ergonomics
#68 opened 6 months ago by arnetheduck
#67 opened 6 months ago by arnetheduck
1
Nim
Updated Mar 14, 2019