Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Spar…
C
Updated May 3, 2019
Rocket Chip Generator
Scala
Updated May 4, 2019
A FPGA friendly 32 bit RISC-V CPU implementation
Assembly
Updated May 1, 2019
Ariane is a 6-stage RISC-V CPU capable of booting Linux
SystemVerilog
Updated May 1, 2019
BOOM: Berkeley Out-of-Order Machine
#251 opened 16 days ago by jeehoonkang
1
good first issue
missing feature
#103 opened 9 months ago by hoangt
1
good first issue
help wanted
#36 opened over 1 year ago by ccelio
1
Scala
Updated May 4, 2019
RISC-V simulator for x86-64
C++
Updated Feb 9, 2019
A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
VHDL
Updated Apr 26, 2019
VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".
Verilog
Updated May 4, 2019
Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP…
Forth
Updated Dec 14, 2017
RARS -- RISC-V Assembler and Runtime Simulator
#21 opened 25 days ago by TheThirdOne
3
Java
Updated Apr 26, 2019
RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
SystemVerilog
Updated Apr 30, 2019
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
SystemVerilog
Updated Apr 11, 2019
Rust version of THU uCore OS. Linux compatible.
Rust
Updated May 4, 2019
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
Scala
Updated Mar 20, 2018
Simple RISC-V 3-stage Pipeline in Chisel
Scala
Updated Apr 24, 2019
CKB's vm
Rust
Updated May 1, 2019
Drink the kool-aid from a firehose
C
Updated May 3, 2019
Riscy Processors - Open-Sourced RISC-V Processors
Bluespec
Updated Apr 4, 2019
XCrypto: a cryptographic ISE for RISC-V
Updated May 1, 2019
OpenEmbedded/Yocto layer for RISC-V Architecture
BitBake
Updated May 4, 2019
Basic RISC-V CPU implementation in VHDL.
VHDL
Updated Dec 14, 2018
educational microarchitectures for risc-v isa
Yet Another RISC-V Implementation
Verilog
Updated Jul 10, 2016
Lightweight and secure multiprocessor microkernel written in Rust for RISC-V
Rust
Updated Apr 11, 2019
FPGA 101 - Workshop materials
C
Updated Mar 17, 2019
riscv资料、论文等
HTML
Updated Oct 24, 2018
Tests for example Rocket Custom Coprocessors
C
Updated Mar 26, 2018
A template for building new projects/platforms using the BOOM core.
RISC-V Instruction Set Metadata
Updated Oct 21, 2018
C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
C
Updated Feb 5, 2018