aquynh / capstone

3.5k

Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Spar…

C Updated May 3, 2019

freechipsproject / rocket-chip

1k

Rocket Chip Generator

scala rocket-chip chip-generator chisel riscv rtl

Scala Updated May 4, 2019

SpinalHDL / VexRiscv

499

A FPGA friendly 32 bit RISC-V CPU implementation

riscv soc cpu spinalhdl vhdl verilog fpga softcore

Assembly Updated May 1, 2019

pulp-platform / ariane

449

Ariane is a 6-stage RISC-V CPU capable of booting Linux

systemverilog-hdl cpu riscv asic fpga rv64gc ariane verilator questasim

SystemVerilog Updated May 1, 2019

riscv-boom / riscv-boom

422

BOOM: Berkeley Out-of-Order Machine

riscv boom chisel rtl rocket-chip scala

Good first issues

Documentation on load/store unit mentions non-existing variables

docs bug

#251 opened 16 days ago by jeehoonkang

1

Boom with RoCC

good first issue missing feature

#103 opened 9 months ago by hoangt

1

Add chicken-bit support to BOOM

good first issue help wanted

#36 opened over 1 year ago by ccelio

1

Scala Updated May 4, 2019

rv8-io / rv8

252

RISC-V simulator for x86-64

isa simulator disassembler emulator riscv binary-translation metadata histogram risc macro-op-fusion linux rv-sys rv-sim rv-meta rv-jit rv8

C++ Updated Feb 9, 2019

f32c / f32c

229

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

fpga altera lattice xilinx riscv mips arduino

VHDL Updated Apr 26, 2019

sergeykhbr / riscv_vhdl

212

VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

riscv soc vhdl fpga-soc simulator systemc qt5

Verilog Updated May 4, 2019

larsbrinkhoff / lbForth

204

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP…

forth compiler interpreter metacompiler pdp11 m68k self-hosted linux arm programming-language x86 asmjs risc-v riscv 6502 msp430 avr 8051 cortex-m

Forth Updated Dec 14, 2017

TheThirdOne / rars

199

RARS -- RISC-V Assembler and Runtime Simulator

mars risc-v riscv assembler simulator ide education

Good first issues

Improve InstructionCounter and InstructionStatistics

good first issue

#21 opened 25 days ago by TheThirdOne

3

Java Updated Apr 26, 2019

pulp-platform / riscv

190

RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

riscv riscv32imfc

SystemVerilog Updated Apr 30, 2019

syntacore / scr1

189

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

riscv risc-v rtl verilog rv32i rv32e rv32imc rv32emc ip core

SystemVerilog Updated Apr 11, 2019

rcore-os / rCore

136

Rust version of THU uCore OS. Linux compatible.

rust osdev riscv x86-64 aarch64 mips

Rust Updated May 4, 2019

bu-icsg / dana

114

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

neural-network rocket-chip hardware riscv rtl chisel rocc

Scala Updated Mar 20, 2018

ucb-bar / riscv-mini

95

Simple RISC-V 3-stage Pipeline in Chisel

chisel riscv rtl

Scala Updated Apr 24, 2019

nervosnetwork / ckb-vm

91

CKB's vm

nervos ckb blockchain rust riscv smart-contract

Rust Updated May 1, 2019

ucb-bar / project-template

69

Drink the kool-aid from a firehose

rocket-chip scala chip-generator chisel riscv rtl soc peripherals

C Updated May 3, 2019

csail-csg / riscy

41

Riscy Processors - Open-Sourced RISC-V Processors

riscv

Bluespec Updated Apr 4, 2019

scarv / xcrypto

40

XCrypto: a cryptographic ISE for RISC-V

risc-v riscv verilog formal-verification yosys icarus-verilog hardware hardware-acceleration cryptography instruction-set-architecture open-source mit-license crypto cpu ise

Updated May 1, 2019

riscv / meta-riscv

39

OpenEmbedded/Yocto layer for RISC-V Architecture

risc-v riscv yocto yocto-layer yocto-meta openembedded openembedded-layer

BitBake Updated May 4, 2019

Domipheus / RPU

34

Basic RISC-V CPU implementation in VHDL.

fpga cpu vhdl risc-v riscv apache2-license

VHDL Updated Dec 14, 2018

librecores / riscv-sodor

33

educational microarchitectures for risc-v isa

chisel3 pynq-z1 arty tilelink librecores riscv scala firrtl

Forked from ucb-bar/riscv-sodor Scala Updated Feb 18, 2019

tommythorn / yarvi

32

Yet Another RISC-V Implementation

riscv riscv32 fpga fpga-soc risc-v verilog

Verilog Updated Jul 10, 2016

diodesign / diosix

28

Lightweight and secure multiprocessor microkernel written in Rust for RISC-V

rust riscv kernel microkernel

Rust Updated Apr 11, 2019

mmicko / fpga101-workshop

27

FPGA 101 - Workshop materials

fpga verilog hackaday icestorm apio icestudio riscv micropython

C Updated Mar 17, 2019

l919898756 / RISC-V_article_paper_src

26

riscv资料、论文等

riscv

HTML Updated Oct 24, 2018

seldridge / rocket-rocc-examples

25

Tests for example Rocket Custom Coprocessors

riscv rocket-chip rocc

C Updated Mar 26, 2018

esperantotech / boom-template

24

A template for building new projects/platforms using the BOOM core.

riscv boom chisel rtl rocket-chip scala

Forked from ucb-bar/project-template Shell Updated Jan 14, 2019

michaeljclark / riscv-meta

21

RISC-V Instruction Set Metadata

risc-v riscv metadata risc

Updated Oct 21, 2018

IBM / rocc-software

19

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

riscv rocket-chip rocc

C Updated Feb 5, 2018

riscv

Repositories 114

aquynh / capstone

freechipsproject / rocket-chip

SpinalHDL / VexRiscv

pulp-platform / ariane

riscv-boom / riscv-boom

Good first issues

Documentation on load/store unit mentions non-existing variables

Boom with RoCC

Add chicken-bit support to BOOM

rv8-io / rv8

f32c / f32c

sergeykhbr / riscv_vhdl

larsbrinkhoff / lbForth

TheThirdOne / rars

Good first issues

Improve InstructionCounter and InstructionStatistics

pulp-platform / riscv

syntacore / scr1

rcore-os / rCore

bu-icsg / dana

ucb-bar / riscv-mini

nervosnetwork / ckb-vm

ucb-bar / project-template

csail-csg / riscy

scarv / xcrypto

riscv / meta-riscv

Domipheus / RPU

librecores / riscv-sodor

tommythorn / yarvi

diodesign / diosix

mmicko / fpga101-workshop

l919898756 / RISC-V_article_paper_src

seldridge / rocket-rocc-examples

esperantotech / boom-template

michaeljclark / riscv-meta

IBM / rocc-software

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