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spinalhdl

Repositories 6

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

riscv soc cpu spinalhdl vhdl verilog fpga softcore

Assembly Updated May 1, 2019

SteffenReith / J1Sc

A reimplementation of a tiny stack CPU

fpga spinalhdl forth cpu vhdl verilog hdl j1-cpu

Scala Updated Mar 20, 2019

ThorKn / J1-forth

Forth for the J1-CPU

j1-cpu spinal spinalhdl hdl forth aes j1sc fpga j1

Forth Updated Mar 13, 2017

SpinalHDL / SpinalCrypto

SpinalHDL - Cryptography libraries

spinalhdl fpga crypto cryptography vhdl verilog rtl scala aes des md5 sha hmac crc

Scala Updated Mar 8, 2019

plex1 / SpinalDev

Development Environment for SpinalHDL

spinalhdl vhdl verilog rtl scala fpga dockerfile

Dockerfile Updated Jan 2, 2019

jens-na / VexRiscv-CCOPI

Custom Coprocessor Interface for VexRiscv

processor-interface spinalhdl risc-v

C++ Updated Sep 19, 2018

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