pulp-platform / ariane

449

Ariane is a 6-stage RISC-V CPU capable of booting Linux

systemverilog-hdl cpu riscv asic fpga rv64gc ariane verilator questasim

SystemVerilog Updated May 1, 2019

VUnit / vunit

289

VUnit is a unit testing framework for VHDL/SystemVerilog

vhdl verification systemverilog-hdl unit-testing fpga asic testbench

Good first issues

SystemVerilog: Get current test name

good first issue enhancement

#307 opened over 1 year ago by alinaivanovaoff

8

VHDL Updated Apr 30, 2019

icglue / icglue

4

A Tcl-Library for scripted HDL generation

hdl verilog verilog-hdl systemverilog systemverilog-hdl tcl-applications

Tcl Updated Apr 25, 2019

pulp-platform / uvm-components

4

Contains commonly used UVM components (agents, environments and tests).

uvm systemverilog-hdl

SystemVerilog Updated Aug 17, 2018

nelsoncsc / ISP_UVM

3

A Framework for Design and Verification of Image Processing Applications using UVM

functional-verification systemverilog-hdl uvm systemc image-processing opencv hardware-designs

SystemVerilog Updated Nov 27, 2017

nelsoncsc / easyUVM

3

A simple UVM example with DPI

systemverilog-hdl uvm functional-verification

SystemVerilog Updated Aug 7, 2017

pulp-platform / axi_mem_if

3

Simple single-port AXI memory interface

axi systemverilog-hdl asic fpga

SystemVerilog Updated Mar 13, 2019

ghosh17 / DualCoreProcessor

2

ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor

systemverilog-hdl systemverilog asic rtl

SystemVerilog Updated Aug 23, 2017

vinodsake / Last-Level-Cache-Simulator

1

cache-simulator systemverilog-hdl

SystemVerilog Updated Apr 1, 2017

SvrAdityaReddy / Inter_Device_Communication_Protocols

1

Verilog Codes of various Inter Device Communication Protocols

systemverilog-hdl verilog-hdl

SystemVerilog Updated Apr 28, 2018

pulp-platform / apb_fll_if

1

Control interface for FLL

apb-fll systemverilog-hdl

SystemVerilog Updated Apr 24, 2019

himingway / Parallel_Multiplier

A Parallel Multiplier Using SystemVerilog HDL

systemverilog-hdl multiplier

SystemVerilog Updated Apr 21, 2018

nelsoncsc / basic_uvmc_oct

A simple UVM testbench using UVM Connect and Octave

systemc octave uvm functional-verification systemverilog-hdl

SystemVerilog Updated Aug 7, 2017

nelsoncsc / basicSV

Very basic SystemVerilog examples

basics systemverilog-hdl examples

SystemVerilog Updated Mar 27, 2017

NishadSaraf / Fibonacci-Sequence-Generator

Synthesizable hardware block that generated Fibonacci sequence based on the start value and order

systemverilog-hdl fibonacci-sequence

SystemVerilog Updated Sep 21, 2017

SalomeDevkule7 / Neural-Network-Layer-Generator

Application Specific Integrated Circuit(ASIC)

systemverilog-hdl vlsi neural-networks asic-verification

SystemVerilog Updated Jun 7, 2018

lorenzocugini / ES-AOS_MPU

Repository for the common project of Embedded Systems and Advanced Operating Systems courses. The chosen project is: …

systemverilog-hdl

Updated Nov 19, 2018

vinodsake / 8-Bit-5-Stage-Microprocessor-Design

microprocessor systemverilog-hdl

SystemVerilog Updated Jan 3, 2018

nelsoncsc / basic_uvmc

A simple testbench with two refmods using UVM Connect

systemverilog-hdl uvm functional-verification systemc

SystemVerilog Updated Aug 7, 2017

pulp-platform / axi2per

AXI to Peripheral Interconnect

axi systemverilog-hdl fpga asic

SystemVerilog Updated Mar 7, 2019

systemverilog-hdl

Repositories 20

Good first issues